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c186f0e1 IS |
1 | /* |
2 | * CARMA DATA-FPGA Access Driver | |
3 | * | |
4 | * Copyright (c) 2009-2011 Ira W. Snyder <iws@ovro.caltech.edu> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | */ | |
11 | ||
12 | /* | |
13 | * FPGA Memory Dump Format | |
14 | * | |
15 | * FPGA #0 control registers (32 x 32-bit words) | |
16 | * FPGA #1 control registers (32 x 32-bit words) | |
17 | * FPGA #2 control registers (32 x 32-bit words) | |
18 | * FPGA #3 control registers (32 x 32-bit words) | |
19 | * SYSFPGA control registers (32 x 32-bit words) | |
20 | * FPGA #0 correlation array (NUM_CORL0 correlation blocks) | |
21 | * FPGA #1 correlation array (NUM_CORL1 correlation blocks) | |
22 | * FPGA #2 correlation array (NUM_CORL2 correlation blocks) | |
23 | * FPGA #3 correlation array (NUM_CORL3 correlation blocks) | |
24 | * | |
25 | * Each correlation array consists of: | |
26 | * | |
27 | * Correlation Data (2 x NUM_LAGSn x 32-bit words) | |
28 | * Pipeline Metadata (2 x NUM_METAn x 32-bit words) | |
29 | * Quantization Counters (2 x NUM_QCNTn x 32-bit words) | |
30 | * | |
31 | * The NUM_CORLn, NUM_LAGSn, NUM_METAn, and NUM_QCNTn values come from | |
32 | * the FPGA configuration registers. They do not change once the FPGA's | |
33 | * have been programmed, they only change on re-programming. | |
34 | */ | |
35 | ||
36 | /* | |
37 | * Basic Description: | |
38 | * | |
39 | * This driver is used to capture correlation spectra off of the four data | |
40 | * processing FPGAs. The FPGAs are often reprogrammed at runtime, therefore | |
41 | * this driver supports dynamic enable/disable of capture while the device | |
42 | * remains open. | |
43 | * | |
44 | * The nominal capture rate is 64Hz (every 15.625ms). To facilitate this fast | |
45 | * capture rate, all buffers are pre-allocated to avoid any potentially long | |
46 | * running memory allocations while capturing. | |
47 | * | |
48 | * There are two lists and one pointer which are used to keep track of the | |
49 | * different states of data buffers. | |
50 | * | |
51 | * 1) free list | |
52 | * This list holds all empty data buffers which are ready to receive data. | |
53 | * | |
54 | * 2) inflight pointer | |
55 | * This pointer holds the currently inflight data buffer. This buffer is having | |
56 | * data copied into it by the DMA engine. | |
57 | * | |
58 | * 3) used list | |
59 | * This list holds data buffers which have been filled, and are waiting to be | |
60 | * read by userspace. | |
61 | * | |
62 | * All buffers start life on the free list, then move successively to the | |
63 | * inflight pointer, and then to the used list. After they have been read by | |
64 | * userspace, they are moved back to the free list. The cycle repeats as long | |
65 | * as necessary. | |
66 | * | |
67 | * It should be noted that all buffers are mapped and ready for DMA when they | |
68 | * are on any of the three lists. They are only unmapped when they are in the | |
69 | * process of being read by userspace. | |
70 | */ | |
71 | ||
72 | /* | |
73 | * Notes on the IRQ masking scheme: | |
74 | * | |
75 | * The IRQ masking scheme here is different than most other hardware. The only | |
76 | * way for the DATA-FPGAs to detect if the kernel has taken too long to copy | |
77 | * the data is if the status registers are not cleared before the next | |
78 | * correlation data dump is ready. | |
79 | * | |
80 | * The interrupt line is connected to the status registers, such that when they | |
81 | * are cleared, the interrupt is de-asserted. Therein lies our problem. We need | |
82 | * to schedule a long-running DMA operation and return from the interrupt | |
83 | * handler quickly, but we cannot clear the status registers. | |
84 | * | |
85 | * To handle this, the system controller FPGA has the capability to connect the | |
86 | * interrupt line to a user-controlled GPIO pin. This pin is driven high | |
87 | * (unasserted) and left that way. To mask the interrupt, we change the | |
88 | * interrupt source to the GPIO pin. Tada, we hid the interrupt. :) | |
89 | */ | |
90 | ||
5af50730 RH |
91 | #include <linux/of_address.h> |
92 | #include <linux/of_irq.h> | |
c186f0e1 IS |
93 | #include <linux/of_platform.h> |
94 | #include <linux/dma-mapping.h> | |
95 | #include <linux/miscdevice.h> | |
96 | #include <linux/interrupt.h> | |
97 | #include <linux/dmaengine.h> | |
98 | #include <linux/seq_file.h> | |
99 | #include <linux/highmem.h> | |
100 | #include <linux/debugfs.h> | |
101 | #include <linux/kernel.h> | |
102 | #include <linux/module.h> | |
103 | #include <linux/poll.h> | |
104 | #include <linux/init.h> | |
105 | #include <linux/slab.h> | |
106 | #include <linux/kref.h> | |
107 | #include <linux/io.h> | |
108 | ||
109 | #include <media/videobuf-dma-sg.h> | |
110 | ||
111 | /* system controller registers */ | |
112 | #define SYS_IRQ_SOURCE_CTL 0x24 | |
113 | #define SYS_IRQ_OUTPUT_EN 0x28 | |
114 | #define SYS_IRQ_OUTPUT_DATA 0x2C | |
115 | #define SYS_IRQ_INPUT_DATA 0x30 | |
116 | #define SYS_FPGA_CONFIG_STATUS 0x44 | |
117 | ||
118 | /* GPIO IRQ line assignment */ | |
119 | #define IRQ_CORL_DONE 0x10 | |
120 | ||
121 | /* FPGA registers */ | |
122 | #define MMAP_REG_VERSION 0x00 | |
123 | #define MMAP_REG_CORL_CONF1 0x08 | |
124 | #define MMAP_REG_CORL_CONF2 0x0C | |
125 | #define MMAP_REG_STATUS 0x48 | |
126 | ||
127 | #define SYS_FPGA_BLOCK 0xF0000000 | |
128 | ||
129 | #define DATA_FPGA_START 0x400000 | |
130 | #define DATA_FPGA_SIZE 0x80000 | |
131 | ||
132 | static const char drv_name[] = "carma-fpga"; | |
133 | ||
134 | #define NUM_FPGA 4 | |
135 | ||
136 | #define MIN_DATA_BUFS 8 | |
137 | #define MAX_DATA_BUFS 64 | |
138 | ||
139 | struct fpga_info { | |
140 | unsigned int num_lag_ram; | |
141 | unsigned int blk_size; | |
142 | }; | |
143 | ||
144 | struct data_buf { | |
145 | struct list_head entry; | |
146 | struct videobuf_dmabuf vb; | |
147 | size_t size; | |
148 | }; | |
149 | ||
150 | struct fpga_device { | |
151 | /* character device */ | |
152 | struct miscdevice miscdev; | |
153 | struct device *dev; | |
154 | struct mutex mutex; | |
155 | ||
156 | /* reference count */ | |
157 | struct kref ref; | |
158 | ||
159 | /* FPGA registers and information */ | |
160 | struct fpga_info info[NUM_FPGA]; | |
161 | void __iomem *regs; | |
162 | int irq; | |
163 | ||
164 | /* FPGA Physical Address/Size Information */ | |
165 | resource_size_t phys_addr; | |
166 | size_t phys_size; | |
167 | ||
168 | /* DMA structures */ | |
169 | struct sg_table corl_table; | |
170 | unsigned int corl_nents; | |
171 | struct dma_chan *chan; | |
172 | ||
173 | /* Protection for all members below */ | |
174 | spinlock_t lock; | |
175 | ||
176 | /* Device enable/disable flag */ | |
177 | bool enabled; | |
178 | ||
179 | /* Correlation data buffers */ | |
180 | wait_queue_head_t wait; | |
181 | struct list_head free; | |
182 | struct list_head used; | |
183 | struct data_buf *inflight; | |
184 | ||
185 | /* Information about data buffers */ | |
186 | unsigned int num_dropped; | |
187 | unsigned int num_buffers; | |
188 | size_t bufsize; | |
189 | struct dentry *dbg_entry; | |
190 | }; | |
191 | ||
192 | struct fpga_reader { | |
193 | struct fpga_device *priv; | |
194 | struct data_buf *buf; | |
195 | off_t buf_start; | |
196 | }; | |
197 | ||
198 | static void fpga_device_release(struct kref *ref) | |
199 | { | |
200 | struct fpga_device *priv = container_of(ref, struct fpga_device, ref); | |
201 | ||
202 | /* the last reader has exited, cleanup the last bits */ | |
203 | mutex_destroy(&priv->mutex); | |
204 | kfree(priv); | |
205 | } | |
206 | ||
207 | /* | |
208 | * Data Buffer Allocation Helpers | |
209 | */ | |
210 | ||
211 | /** | |
212 | * data_free_buffer() - free a single data buffer and all allocated memory | |
213 | * @buf: the buffer to free | |
214 | * | |
215 | * This will free all of the pages allocated to the given data buffer, and | |
216 | * then free the structure itself | |
217 | */ | |
218 | static void data_free_buffer(struct data_buf *buf) | |
219 | { | |
220 | /* It is ok to free a NULL buffer */ | |
221 | if (!buf) | |
222 | return; | |
223 | ||
224 | /* free all memory */ | |
225 | videobuf_dma_free(&buf->vb); | |
226 | kfree(buf); | |
227 | } | |
228 | ||
229 | /** | |
230 | * data_alloc_buffer() - allocate and fill a data buffer with pages | |
231 | * @bytes: the number of bytes required | |
232 | * | |
233 | * This allocates all space needed for a data buffer. It must be mapped before | |
234 | * use in a DMA transaction using videobuf_dma_map(). | |
235 | * | |
236 | * Returns NULL on failure | |
237 | */ | |
238 | static struct data_buf *data_alloc_buffer(const size_t bytes) | |
239 | { | |
240 | unsigned int nr_pages; | |
241 | struct data_buf *buf; | |
242 | int ret; | |
243 | ||
244 | /* calculate the number of pages necessary */ | |
245 | nr_pages = DIV_ROUND_UP(bytes, PAGE_SIZE); | |
246 | ||
247 | /* allocate the buffer structure */ | |
248 | buf = kzalloc(sizeof(*buf), GFP_KERNEL); | |
249 | if (!buf) | |
250 | goto out_return; | |
251 | ||
252 | /* initialize internal fields */ | |
253 | INIT_LIST_HEAD(&buf->entry); | |
254 | buf->size = bytes; | |
255 | ||
256 | /* allocate the videobuf */ | |
257 | videobuf_dma_init(&buf->vb); | |
258 | ret = videobuf_dma_init_kernel(&buf->vb, DMA_FROM_DEVICE, nr_pages); | |
259 | if (ret) | |
260 | goto out_free_buf; | |
261 | ||
262 | return buf; | |
263 | ||
264 | out_free_buf: | |
265 | kfree(buf); | |
266 | out_return: | |
267 | return NULL; | |
268 | } | |
269 | ||
270 | /** | |
271 | * data_free_buffers() - free all allocated buffers | |
272 | * @priv: the driver's private data structure | |
273 | * | |
274 | * Free all buffers allocated by the driver (except those currently in the | |
275 | * process of being read by userspace). | |
276 | * | |
277 | * LOCKING: must hold dev->mutex | |
278 | * CONTEXT: user | |
279 | */ | |
280 | static void data_free_buffers(struct fpga_device *priv) | |
281 | { | |
282 | struct data_buf *buf, *tmp; | |
283 | ||
284 | /* the device should be stopped, no DMA in progress */ | |
285 | BUG_ON(priv->inflight != NULL); | |
286 | ||
287 | list_for_each_entry_safe(buf, tmp, &priv->free, entry) { | |
288 | list_del_init(&buf->entry); | |
289 | videobuf_dma_unmap(priv->dev, &buf->vb); | |
290 | data_free_buffer(buf); | |
291 | } | |
292 | ||
293 | list_for_each_entry_safe(buf, tmp, &priv->used, entry) { | |
294 | list_del_init(&buf->entry); | |
295 | videobuf_dma_unmap(priv->dev, &buf->vb); | |
296 | data_free_buffer(buf); | |
297 | } | |
298 | ||
299 | priv->num_buffers = 0; | |
300 | priv->bufsize = 0; | |
301 | } | |
302 | ||
303 | /** | |
304 | * data_alloc_buffers() - allocate 1 seconds worth of data buffers | |
305 | * @priv: the driver's private data structure | |
306 | * | |
307 | * Allocate enough buffers for a whole second worth of data | |
308 | * | |
309 | * This routine will attempt to degrade nicely by succeeding even if a full | |
310 | * second worth of data buffers could not be allocated, as long as a minimum | |
311 | * number were allocated. In this case, it will print a message to the kernel | |
312 | * log. | |
313 | * | |
314 | * The device must not be modifying any lists when this is called. | |
315 | * | |
316 | * CONTEXT: user | |
317 | * LOCKING: must hold dev->mutex | |
318 | * | |
319 | * Returns 0 on success, -ERRNO otherwise | |
320 | */ | |
321 | static int data_alloc_buffers(struct fpga_device *priv) | |
322 | { | |
323 | struct data_buf *buf; | |
324 | int i, ret; | |
325 | ||
326 | for (i = 0; i < MAX_DATA_BUFS; i++) { | |
327 | ||
328 | /* allocate a buffer */ | |
329 | buf = data_alloc_buffer(priv->bufsize); | |
330 | if (!buf) | |
331 | break; | |
332 | ||
333 | /* map it for DMA */ | |
334 | ret = videobuf_dma_map(priv->dev, &buf->vb); | |
335 | if (ret) { | |
336 | data_free_buffer(buf); | |
337 | break; | |
338 | } | |
339 | ||
340 | /* add it to the list of free buffers */ | |
341 | list_add_tail(&buf->entry, &priv->free); | |
342 | priv->num_buffers++; | |
343 | } | |
344 | ||
345 | /* Make sure we allocated the minimum required number of buffers */ | |
346 | if (priv->num_buffers < MIN_DATA_BUFS) { | |
347 | dev_err(priv->dev, "Unable to allocate enough data buffers\n"); | |
348 | data_free_buffers(priv); | |
349 | return -ENOMEM; | |
350 | } | |
351 | ||
352 | /* Warn if we are running in a degraded state, but do not fail */ | |
353 | if (priv->num_buffers < MAX_DATA_BUFS) { | |
354 | dev_warn(priv->dev, | |
355 | "Unable to allocate %d buffers, using %d buffers instead\n", | |
356 | MAX_DATA_BUFS, i); | |
357 | } | |
358 | ||
359 | return 0; | |
360 | } | |
361 | ||
362 | /* | |
363 | * DMA Operations Helpers | |
364 | */ | |
365 | ||
366 | /** | |
367 | * fpga_start_addr() - get the physical address a DATA-FPGA | |
368 | * @priv: the driver's private data structure | |
369 | * @fpga: the DATA-FPGA number (zero based) | |
370 | */ | |
371 | static dma_addr_t fpga_start_addr(struct fpga_device *priv, unsigned int fpga) | |
372 | { | |
373 | return priv->phys_addr + 0x400000 + (0x80000 * fpga); | |
374 | } | |
375 | ||
376 | /** | |
377 | * fpga_block_addr() - get the physical address of a correlation data block | |
378 | * @priv: the driver's private data structure | |
379 | * @fpga: the DATA-FPGA number (zero based) | |
380 | * @blknum: the correlation block number (zero based) | |
381 | */ | |
382 | static dma_addr_t fpga_block_addr(struct fpga_device *priv, unsigned int fpga, | |
383 | unsigned int blknum) | |
384 | { | |
385 | return fpga_start_addr(priv, fpga) + (0x10000 * (1 + blknum)); | |
386 | } | |
387 | ||
388 | #define REG_BLOCK_SIZE (32 * 4) | |
389 | ||
390 | /** | |
391 | * data_setup_corl_table() - create the scatterlist for correlation dumps | |
392 | * @priv: the driver's private data structure | |
393 | * | |
394 | * Create the scatterlist for transferring a correlation dump from the | |
395 | * DATA FPGAs. This structure will be reused for each buffer than needs | |
396 | * to be filled with correlation data. | |
397 | * | |
398 | * Returns 0 on success, -ERRNO otherwise | |
399 | */ | |
400 | static int data_setup_corl_table(struct fpga_device *priv) | |
401 | { | |
402 | struct sg_table *table = &priv->corl_table; | |
403 | struct scatterlist *sg; | |
404 | struct fpga_info *info; | |
405 | int i, j, ret; | |
406 | ||
407 | /* Calculate the number of entries needed */ | |
408 | priv->corl_nents = (1 + NUM_FPGA) * REG_BLOCK_SIZE; | |
409 | for (i = 0; i < NUM_FPGA; i++) | |
410 | priv->corl_nents += priv->info[i].num_lag_ram; | |
411 | ||
412 | /* Allocate the scatterlist table */ | |
413 | ret = sg_alloc_table(table, priv->corl_nents, GFP_KERNEL); | |
414 | if (ret) { | |
415 | dev_err(priv->dev, "unable to allocate DMA table\n"); | |
416 | return ret; | |
417 | } | |
418 | ||
419 | /* Add the DATA FPGA registers to the scatterlist */ | |
420 | sg = table->sgl; | |
421 | for (i = 0; i < NUM_FPGA; i++) { | |
422 | sg_dma_address(sg) = fpga_start_addr(priv, i); | |
423 | sg_dma_len(sg) = REG_BLOCK_SIZE; | |
424 | sg = sg_next(sg); | |
425 | } | |
426 | ||
427 | /* Add the SYS-FPGA registers to the scatterlist */ | |
428 | sg_dma_address(sg) = SYS_FPGA_BLOCK; | |
429 | sg_dma_len(sg) = REG_BLOCK_SIZE; | |
430 | sg = sg_next(sg); | |
431 | ||
432 | /* Add the FPGA correlation data blocks to the scatterlist */ | |
433 | for (i = 0; i < NUM_FPGA; i++) { | |
434 | info = &priv->info[i]; | |
435 | for (j = 0; j < info->num_lag_ram; j++) { | |
436 | sg_dma_address(sg) = fpga_block_addr(priv, i, j); | |
437 | sg_dma_len(sg) = info->blk_size; | |
438 | sg = sg_next(sg); | |
439 | } | |
440 | } | |
441 | ||
442 | /* | |
443 | * All physical addresses and lengths are present in the structure | |
444 | * now. It can be reused for every FPGA DATA interrupt | |
445 | */ | |
446 | return 0; | |
447 | } | |
448 | ||
449 | /* | |
450 | * FPGA Register Access Helpers | |
451 | */ | |
452 | ||
453 | static void fpga_write_reg(struct fpga_device *priv, unsigned int fpga, | |
454 | unsigned int reg, u32 val) | |
455 | { | |
456 | const int fpga_start = DATA_FPGA_START + (fpga * DATA_FPGA_SIZE); | |
457 | iowrite32be(val, priv->regs + fpga_start + reg); | |
458 | } | |
459 | ||
460 | static u32 fpga_read_reg(struct fpga_device *priv, unsigned int fpga, | |
461 | unsigned int reg) | |
462 | { | |
463 | const int fpga_start = DATA_FPGA_START + (fpga * DATA_FPGA_SIZE); | |
464 | return ioread32be(priv->regs + fpga_start + reg); | |
465 | } | |
466 | ||
467 | /** | |
468 | * data_calculate_bufsize() - calculate the data buffer size required | |
469 | * @priv: the driver's private data structure | |
470 | * | |
471 | * Calculate the total buffer size needed to hold a single block | |
472 | * of correlation data | |
473 | * | |
474 | * CONTEXT: user | |
475 | * | |
476 | * Returns 0 on success, -ERRNO otherwise | |
477 | */ | |
478 | static int data_calculate_bufsize(struct fpga_device *priv) | |
479 | { | |
480 | u32 num_corl, num_lags, num_meta, num_qcnt, num_pack; | |
481 | u32 conf1, conf2, version; | |
482 | u32 num_lag_ram, blk_size; | |
483 | int i; | |
484 | ||
485 | /* Each buffer starts with the 5 FPGA register areas */ | |
486 | priv->bufsize = (1 + NUM_FPGA) * REG_BLOCK_SIZE; | |
487 | ||
488 | /* Read and store the configuration data for each FPGA */ | |
489 | for (i = 0; i < NUM_FPGA; i++) { | |
490 | version = fpga_read_reg(priv, i, MMAP_REG_VERSION); | |
491 | conf1 = fpga_read_reg(priv, i, MMAP_REG_CORL_CONF1); | |
492 | conf2 = fpga_read_reg(priv, i, MMAP_REG_CORL_CONF2); | |
493 | ||
494 | /* minor version 2 and later */ | |
495 | if ((version & 0x000000FF) >= 2) { | |
496 | num_corl = (conf1 & 0x000000F0) >> 4; | |
497 | num_pack = (conf1 & 0x00000F00) >> 8; | |
498 | num_lags = (conf1 & 0x00FFF000) >> 12; | |
499 | num_meta = (conf1 & 0x7F000000) >> 24; | |
500 | num_qcnt = (conf2 & 0x00000FFF) >> 0; | |
501 | } else { | |
502 | num_corl = (conf1 & 0x000000F0) >> 4; | |
503 | num_pack = 1; /* implied */ | |
504 | num_lags = (conf1 & 0x000FFF00) >> 8; | |
505 | num_meta = (conf1 & 0x7FF00000) >> 20; | |
506 | num_qcnt = (conf2 & 0x00000FFF) >> 0; | |
507 | } | |
508 | ||
509 | num_lag_ram = (num_corl + num_pack - 1) / num_pack; | |
510 | blk_size = ((num_pack * num_lags) + num_meta + num_qcnt) * 8; | |
511 | ||
512 | priv->info[i].num_lag_ram = num_lag_ram; | |
513 | priv->info[i].blk_size = blk_size; | |
514 | priv->bufsize += num_lag_ram * blk_size; | |
515 | ||
516 | dev_dbg(priv->dev, "FPGA %d NUM_CORL: %d\n", i, num_corl); | |
517 | dev_dbg(priv->dev, "FPGA %d NUM_PACK: %d\n", i, num_pack); | |
518 | dev_dbg(priv->dev, "FPGA %d NUM_LAGS: %d\n", i, num_lags); | |
519 | dev_dbg(priv->dev, "FPGA %d NUM_META: %d\n", i, num_meta); | |
520 | dev_dbg(priv->dev, "FPGA %d NUM_QCNT: %d\n", i, num_qcnt); | |
521 | dev_dbg(priv->dev, "FPGA %d BLK_SIZE: %d\n", i, blk_size); | |
522 | } | |
523 | ||
524 | dev_dbg(priv->dev, "TOTAL BUFFER SIZE: %zu bytes\n", priv->bufsize); | |
525 | return 0; | |
526 | } | |
527 | ||
528 | /* | |
529 | * Interrupt Handling | |
530 | */ | |
531 | ||
532 | /** | |
533 | * data_disable_interrupts() - stop the device from generating interrupts | |
534 | * @priv: the driver's private data structure | |
535 | * | |
536 | * Hide interrupts by switching to GPIO interrupt source | |
537 | * | |
538 | * LOCKING: must hold dev->lock | |
539 | */ | |
540 | static void data_disable_interrupts(struct fpga_device *priv) | |
541 | { | |
542 | /* hide the interrupt by switching the IRQ driver to GPIO */ | |
543 | iowrite32be(0x2F, priv->regs + SYS_IRQ_SOURCE_CTL); | |
544 | } | |
545 | ||
546 | /** | |
547 | * data_enable_interrupts() - allow the device to generate interrupts | |
548 | * @priv: the driver's private data structure | |
549 | * | |
550 | * Unhide interrupts by switching to the FPGA interrupt source. At the | |
551 | * same time, clear the DATA-FPGA status registers. | |
552 | * | |
553 | * LOCKING: must hold dev->lock | |
554 | */ | |
555 | static void data_enable_interrupts(struct fpga_device *priv) | |
556 | { | |
557 | /* clear the actual FPGA corl_done interrupt */ | |
558 | fpga_write_reg(priv, 0, MMAP_REG_STATUS, 0x0); | |
559 | fpga_write_reg(priv, 1, MMAP_REG_STATUS, 0x0); | |
560 | fpga_write_reg(priv, 2, MMAP_REG_STATUS, 0x0); | |
561 | fpga_write_reg(priv, 3, MMAP_REG_STATUS, 0x0); | |
562 | ||
563 | /* flush the writes */ | |
564 | fpga_read_reg(priv, 0, MMAP_REG_STATUS); | |
6c15d7af IS |
565 | fpga_read_reg(priv, 1, MMAP_REG_STATUS); |
566 | fpga_read_reg(priv, 2, MMAP_REG_STATUS); | |
567 | fpga_read_reg(priv, 3, MMAP_REG_STATUS); | |
c186f0e1 IS |
568 | |
569 | /* switch back to the external interrupt source */ | |
570 | iowrite32be(0x3F, priv->regs + SYS_IRQ_SOURCE_CTL); | |
571 | } | |
572 | ||
573 | /** | |
574 | * data_dma_cb() - DMAEngine callback for DMA completion | |
575 | * @data: the driver's private data structure | |
576 | * | |
577 | * Complete a DMA transfer from the DATA-FPGA's | |
578 | * | |
579 | * This is called via the DMA callback mechanism, and will handle moving the | |
580 | * completed DMA transaction to the used list, and then wake any processes | |
581 | * waiting for new data | |
582 | * | |
583 | * CONTEXT: any, softirq expected | |
584 | */ | |
585 | static void data_dma_cb(void *data) | |
586 | { | |
587 | struct fpga_device *priv = data; | |
588 | unsigned long flags; | |
589 | ||
590 | spin_lock_irqsave(&priv->lock, flags); | |
591 | ||
592 | /* If there is no inflight buffer, we've got a bug */ | |
593 | BUG_ON(priv->inflight == NULL); | |
594 | ||
595 | /* Move the inflight buffer onto the used list */ | |
596 | list_move_tail(&priv->inflight->entry, &priv->used); | |
597 | priv->inflight = NULL; | |
598 | ||
6c15d7af IS |
599 | /* |
600 | * If data dumping is still enabled, then clear the FPGA | |
601 | * status registers and re-enable FPGA interrupts | |
602 | */ | |
603 | if (priv->enabled) | |
604 | data_enable_interrupts(priv); | |
c186f0e1 IS |
605 | |
606 | spin_unlock_irqrestore(&priv->lock, flags); | |
607 | ||
608 | /* | |
609 | * We've changed both the inflight and used lists, so we need | |
610 | * to wake up any processes that are blocking for those events | |
611 | */ | |
612 | wake_up(&priv->wait); | |
613 | } | |
614 | ||
615 | /** | |
616 | * data_submit_dma() - prepare and submit the required DMA to fill a buffer | |
617 | * @priv: the driver's private data structure | |
618 | * @buf: the data buffer | |
619 | * | |
620 | * Prepare and submit the necessary DMA transactions to fill a correlation | |
621 | * data buffer. | |
622 | * | |
623 | * LOCKING: must hold dev->lock | |
624 | * CONTEXT: hardirq only | |
625 | * | |
626 | * Returns 0 on success, -ERRNO otherwise | |
627 | */ | |
628 | static int data_submit_dma(struct fpga_device *priv, struct data_buf *buf) | |
629 | { | |
630 | struct scatterlist *dst_sg, *src_sg; | |
631 | unsigned int dst_nents, src_nents; | |
632 | struct dma_chan *chan = priv->chan; | |
633 | struct dma_async_tx_descriptor *tx; | |
634 | dma_cookie_t cookie; | |
635 | dma_addr_t dst, src; | |
bfc191ea BZ |
636 | unsigned long dma_flags = DMA_COMPL_SKIP_DEST_UNMAP | |
637 | DMA_COMPL_SKIP_SRC_UNMAP; | |
c186f0e1 IS |
638 | |
639 | dst_sg = buf->vb.sglist; | |
640 | dst_nents = buf->vb.sglen; | |
641 | ||
642 | src_sg = priv->corl_table.sgl; | |
643 | src_nents = priv->corl_nents; | |
644 | ||
645 | /* | |
646 | * All buffers passed to this function should be ready and mapped | |
647 | * for DMA already. Therefore, we don't need to do anything except | |
648 | * submit it to the Freescale DMA Engine for processing | |
649 | */ | |
650 | ||
651 | /* setup the scatterlist to scatterlist transfer */ | |
652 | tx = chan->device->device_prep_dma_sg(chan, | |
653 | dst_sg, dst_nents, | |
654 | src_sg, src_nents, | |
655 | 0); | |
656 | if (!tx) { | |
657 | dev_err(priv->dev, "unable to prep scatterlist DMA\n"); | |
658 | return -ENOMEM; | |
659 | } | |
660 | ||
661 | /* submit the transaction to the DMA controller */ | |
662 | cookie = tx->tx_submit(tx); | |
663 | if (dma_submit_error(cookie)) { | |
664 | dev_err(priv->dev, "unable to submit scatterlist DMA\n"); | |
665 | return -ENOMEM; | |
666 | } | |
667 | ||
668 | /* Prepare the re-read of the SYS-FPGA block */ | |
669 | dst = sg_dma_address(dst_sg) + (NUM_FPGA * REG_BLOCK_SIZE); | |
670 | src = SYS_FPGA_BLOCK; | |
671 | tx = chan->device->device_prep_dma_memcpy(chan, dst, src, | |
672 | REG_BLOCK_SIZE, | |
bfc191ea | 673 | dma_flags); |
c186f0e1 IS |
674 | if (!tx) { |
675 | dev_err(priv->dev, "unable to prep SYS-FPGA DMA\n"); | |
676 | return -ENOMEM; | |
677 | } | |
678 | ||
679 | /* Setup the callback */ | |
680 | tx->callback = data_dma_cb; | |
681 | tx->callback_param = priv; | |
682 | ||
683 | /* submit the transaction to the DMA controller */ | |
684 | cookie = tx->tx_submit(tx); | |
685 | if (dma_submit_error(cookie)) { | |
686 | dev_err(priv->dev, "unable to submit SYS-FPGA DMA\n"); | |
687 | return -ENOMEM; | |
688 | } | |
689 | ||
690 | return 0; | |
691 | } | |
692 | ||
693 | #define CORL_DONE 0x1 | |
694 | #define CORL_ERR 0x2 | |
695 | ||
696 | static irqreturn_t data_irq(int irq, void *dev_id) | |
697 | { | |
698 | struct fpga_device *priv = dev_id; | |
699 | bool submitted = false; | |
700 | struct data_buf *buf; | |
701 | u32 status; | |
702 | int i; | |
703 | ||
704 | /* detect spurious interrupts via FPGA status */ | |
705 | for (i = 0; i < 4; i++) { | |
706 | status = fpga_read_reg(priv, i, MMAP_REG_STATUS); | |
707 | if (!(status & (CORL_DONE | CORL_ERR))) { | |
708 | dev_err(priv->dev, "spurious irq detected (FPGA)\n"); | |
709 | return IRQ_NONE; | |
710 | } | |
711 | } | |
712 | ||
713 | /* detect spurious interrupts via raw IRQ pin readback */ | |
714 | status = ioread32be(priv->regs + SYS_IRQ_INPUT_DATA); | |
715 | if (status & IRQ_CORL_DONE) { | |
716 | dev_err(priv->dev, "spurious irq detected (IRQ)\n"); | |
717 | return IRQ_NONE; | |
718 | } | |
719 | ||
720 | spin_lock(&priv->lock); | |
721 | ||
6c15d7af IS |
722 | /* |
723 | * This is an error case that should never happen. | |
724 | * | |
725 | * If this driver has a bug and manages to re-enable interrupts while | |
726 | * a DMA is in progress, then we will hit this statement and should | |
727 | * start paying attention immediately. | |
728 | */ | |
729 | BUG_ON(priv->inflight != NULL); | |
730 | ||
c186f0e1 IS |
731 | /* hide the interrupt by switching the IRQ driver to GPIO */ |
732 | data_disable_interrupts(priv); | |
733 | ||
734 | /* If there are no free buffers, drop this data */ | |
735 | if (list_empty(&priv->free)) { | |
736 | priv->num_dropped++; | |
737 | goto out; | |
738 | } | |
739 | ||
740 | buf = list_first_entry(&priv->free, struct data_buf, entry); | |
741 | list_del_init(&buf->entry); | |
742 | BUG_ON(buf->size != priv->bufsize); | |
743 | ||
744 | /* Submit a DMA transfer to get the correlation data */ | |
745 | if (data_submit_dma(priv, buf)) { | |
746 | dev_err(priv->dev, "Unable to setup DMA transfer\n"); | |
747 | list_move_tail(&buf->entry, &priv->free); | |
748 | goto out; | |
749 | } | |
750 | ||
751 | /* Save the buffer for the DMA callback */ | |
752 | priv->inflight = buf; | |
753 | submitted = true; | |
754 | ||
755 | /* Start the DMA Engine */ | |
b9ee8683 | 756 | dma_async_issue_pending(priv->chan); |
c186f0e1 IS |
757 | |
758 | out: | |
759 | /* If no DMA was submitted, re-enable interrupts */ | |
760 | if (!submitted) | |
761 | data_enable_interrupts(priv); | |
762 | ||
763 | spin_unlock(&priv->lock); | |
764 | return IRQ_HANDLED; | |
765 | } | |
766 | ||
767 | /* | |
768 | * Realtime Device Enable Helpers | |
769 | */ | |
770 | ||
771 | /** | |
772 | * data_device_enable() - enable the device for buffered dumping | |
773 | * @priv: the driver's private data structure | |
774 | * | |
775 | * Enable the device for buffered dumping. Allocates buffers and hooks up | |
776 | * the interrupt handler. When this finishes, data will come pouring in. | |
777 | * | |
778 | * LOCKING: must hold dev->mutex | |
779 | * CONTEXT: user context only | |
780 | * | |
781 | * Returns 0 on success, -ERRNO otherwise | |
782 | */ | |
783 | static int data_device_enable(struct fpga_device *priv) | |
784 | { | |
6c15d7af | 785 | bool enabled; |
c186f0e1 IS |
786 | u32 val; |
787 | int ret; | |
788 | ||
789 | /* multiple enables are safe: they do nothing */ | |
6c15d7af IS |
790 | spin_lock_irq(&priv->lock); |
791 | enabled = priv->enabled; | |
792 | spin_unlock_irq(&priv->lock); | |
793 | if (enabled) | |
c186f0e1 IS |
794 | return 0; |
795 | ||
796 | /* check that the FPGAs are programmed */ | |
797 | val = ioread32be(priv->regs + SYS_FPGA_CONFIG_STATUS); | |
798 | if (!(val & (1 << 18))) { | |
799 | dev_err(priv->dev, "DATA-FPGAs are not enabled\n"); | |
800 | return -ENODATA; | |
801 | } | |
802 | ||
803 | /* read the FPGAs to calculate the buffer size */ | |
804 | ret = data_calculate_bufsize(priv); | |
805 | if (ret) { | |
806 | dev_err(priv->dev, "unable to calculate buffer size\n"); | |
807 | goto out_error; | |
808 | } | |
809 | ||
810 | /* allocate the correlation data buffers */ | |
811 | ret = data_alloc_buffers(priv); | |
812 | if (ret) { | |
813 | dev_err(priv->dev, "unable to allocate buffers\n"); | |
814 | goto out_error; | |
815 | } | |
816 | ||
817 | /* setup the source scatterlist for dumping correlation data */ | |
818 | ret = data_setup_corl_table(priv); | |
819 | if (ret) { | |
820 | dev_err(priv->dev, "unable to setup correlation DMA table\n"); | |
821 | goto out_error; | |
822 | } | |
823 | ||
6c15d7af IS |
824 | /* prevent the FPGAs from generating interrupts */ |
825 | data_disable_interrupts(priv); | |
826 | ||
c186f0e1 IS |
827 | /* hookup the irq handler */ |
828 | ret = request_irq(priv->irq, data_irq, IRQF_SHARED, drv_name, priv); | |
829 | if (ret) { | |
830 | dev_err(priv->dev, "unable to request IRQ handler\n"); | |
831 | goto out_error; | |
832 | } | |
833 | ||
6c15d7af IS |
834 | /* allow the DMA callback to re-enable FPGA interrupts */ |
835 | spin_lock_irq(&priv->lock); | |
c186f0e1 | 836 | priv->enabled = true; |
6c15d7af IS |
837 | spin_unlock_irq(&priv->lock); |
838 | ||
839 | /* allow the FPGAs to generate interrupts */ | |
840 | data_enable_interrupts(priv); | |
c186f0e1 IS |
841 | return 0; |
842 | ||
843 | out_error: | |
844 | sg_free_table(&priv->corl_table); | |
845 | priv->corl_nents = 0; | |
846 | ||
847 | data_free_buffers(priv); | |
848 | return ret; | |
849 | } | |
850 | ||
851 | /** | |
852 | * data_device_disable() - disable the device for buffered dumping | |
853 | * @priv: the driver's private data structure | |
854 | * | |
855 | * Disable the device for buffered dumping. Stops new DMA transactions from | |
856 | * being generated, waits for all outstanding DMA to complete, and then frees | |
857 | * all buffers. | |
858 | * | |
859 | * LOCKING: must hold dev->mutex | |
860 | * CONTEXT: user only | |
861 | * | |
862 | * Returns 0 on success, -ERRNO otherwise | |
863 | */ | |
864 | static int data_device_disable(struct fpga_device *priv) | |
865 | { | |
6c15d7af | 866 | spin_lock_irq(&priv->lock); |
c186f0e1 IS |
867 | |
868 | /* allow multiple disable */ | |
6c15d7af IS |
869 | if (!priv->enabled) { |
870 | spin_unlock_irq(&priv->lock); | |
c186f0e1 | 871 | return 0; |
6c15d7af IS |
872 | } |
873 | ||
874 | /* | |
875 | * Mark the device disabled | |
876 | * | |
877 | * This stops DMA callbacks from re-enabling interrupts | |
878 | */ | |
879 | priv->enabled = false; | |
c186f0e1 | 880 | |
6c15d7af | 881 | /* prevent the FPGAs from generating interrupts */ |
c186f0e1 IS |
882 | data_disable_interrupts(priv); |
883 | ||
6c15d7af IS |
884 | /* wait until all ongoing DMA has finished */ |
885 | while (priv->inflight != NULL) { | |
886 | spin_unlock_irq(&priv->lock); | |
887 | wait_event(priv->wait, priv->inflight == NULL); | |
888 | spin_lock_irq(&priv->lock); | |
889 | } | |
890 | ||
891 | spin_unlock_irq(&priv->lock); | |
892 | ||
c186f0e1 IS |
893 | /* unhook the irq handler */ |
894 | free_irq(priv->irq, priv); | |
895 | ||
c186f0e1 IS |
896 | /* free the correlation table */ |
897 | sg_free_table(&priv->corl_table); | |
898 | priv->corl_nents = 0; | |
899 | ||
c186f0e1 IS |
900 | /* free all buffers: the free and used lists are not being changed */ |
901 | data_free_buffers(priv); | |
902 | return 0; | |
903 | } | |
904 | ||
905 | /* | |
906 | * DEBUGFS Interface | |
907 | */ | |
908 | #ifdef CONFIG_DEBUG_FS | |
909 | ||
910 | /* | |
911 | * Count the number of entries in the given list | |
912 | */ | |
913 | static unsigned int list_num_entries(struct list_head *list) | |
914 | { | |
915 | struct list_head *entry; | |
916 | unsigned int ret = 0; | |
917 | ||
918 | list_for_each(entry, list) | |
919 | ret++; | |
920 | ||
921 | return ret; | |
922 | } | |
923 | ||
924 | static int data_debug_show(struct seq_file *f, void *offset) | |
925 | { | |
926 | struct fpga_device *priv = f->private; | |
c186f0e1 IS |
927 | |
928 | spin_lock_irq(&priv->lock); | |
929 | ||
930 | seq_printf(f, "enabled: %d\n", priv->enabled); | |
931 | seq_printf(f, "bufsize: %d\n", priv->bufsize); | |
932 | seq_printf(f, "num_buffers: %d\n", priv->num_buffers); | |
933 | seq_printf(f, "num_free: %d\n", list_num_entries(&priv->free)); | |
934 | seq_printf(f, "inflight: %d\n", priv->inflight != NULL); | |
935 | seq_printf(f, "num_used: %d\n", list_num_entries(&priv->used)); | |
936 | seq_printf(f, "num_dropped: %d\n", priv->num_dropped); | |
937 | ||
938 | spin_unlock_irq(&priv->lock); | |
c186f0e1 IS |
939 | return 0; |
940 | } | |
941 | ||
942 | static int data_debug_open(struct inode *inode, struct file *file) | |
943 | { | |
944 | return single_open(file, data_debug_show, inode->i_private); | |
945 | } | |
946 | ||
947 | static const struct file_operations data_debug_fops = { | |
948 | .owner = THIS_MODULE, | |
949 | .open = data_debug_open, | |
950 | .read = seq_read, | |
951 | .llseek = seq_lseek, | |
952 | .release = single_release, | |
953 | }; | |
954 | ||
955 | static int data_debugfs_init(struct fpga_device *priv) | |
956 | { | |
957 | priv->dbg_entry = debugfs_create_file(drv_name, S_IRUGO, NULL, priv, | |
958 | &data_debug_fops); | |
959 | if (IS_ERR(priv->dbg_entry)) | |
960 | return PTR_ERR(priv->dbg_entry); | |
961 | ||
962 | return 0; | |
963 | } | |
964 | ||
965 | static void data_debugfs_exit(struct fpga_device *priv) | |
966 | { | |
967 | debugfs_remove(priv->dbg_entry); | |
968 | } | |
969 | ||
970 | #else | |
971 | ||
972 | static inline int data_debugfs_init(struct fpga_device *priv) | |
973 | { | |
974 | return 0; | |
975 | } | |
976 | ||
977 | static inline void data_debugfs_exit(struct fpga_device *priv) | |
978 | { | |
979 | } | |
980 | ||
981 | #endif /* CONFIG_DEBUG_FS */ | |
982 | ||
983 | /* | |
984 | * SYSFS Attributes | |
985 | */ | |
986 | ||
987 | static ssize_t data_en_show(struct device *dev, struct device_attribute *attr, | |
988 | char *buf) | |
989 | { | |
990 | struct fpga_device *priv = dev_get_drvdata(dev); | |
6c15d7af IS |
991 | int ret; |
992 | ||
993 | spin_lock_irq(&priv->lock); | |
994 | ret = snprintf(buf, PAGE_SIZE, "%u\n", priv->enabled); | |
995 | spin_unlock_irq(&priv->lock); | |
996 | ||
997 | return ret; | |
c186f0e1 IS |
998 | } |
999 | ||
1000 | static ssize_t data_en_set(struct device *dev, struct device_attribute *attr, | |
1001 | const char *buf, size_t count) | |
1002 | { | |
1003 | struct fpga_device *priv = dev_get_drvdata(dev); | |
1004 | unsigned long enable; | |
1005 | int ret; | |
1006 | ||
f7b41276 | 1007 | ret = kstrtoul(buf, 0, &enable); |
c186f0e1 IS |
1008 | if (ret) { |
1009 | dev_err(priv->dev, "unable to parse enable input\n"); | |
f7b41276 | 1010 | return ret; |
c186f0e1 IS |
1011 | } |
1012 | ||
6c15d7af | 1013 | /* protect against concurrent enable/disable */ |
c186f0e1 IS |
1014 | ret = mutex_lock_interruptible(&priv->mutex); |
1015 | if (ret) | |
1016 | return ret; | |
1017 | ||
1018 | if (enable) | |
1019 | ret = data_device_enable(priv); | |
1020 | else | |
1021 | ret = data_device_disable(priv); | |
1022 | ||
1023 | if (ret) { | |
1024 | dev_err(priv->dev, "device %s failed\n", | |
1025 | enable ? "enable" : "disable"); | |
1026 | count = ret; | |
1027 | goto out_unlock; | |
1028 | } | |
1029 | ||
1030 | out_unlock: | |
1031 | mutex_unlock(&priv->mutex); | |
1032 | return count; | |
1033 | } | |
1034 | ||
1035 | static DEVICE_ATTR(enable, S_IWUSR | S_IRUGO, data_en_show, data_en_set); | |
1036 | ||
1037 | static struct attribute *data_sysfs_attrs[] = { | |
1038 | &dev_attr_enable.attr, | |
1039 | NULL, | |
1040 | }; | |
1041 | ||
1042 | static const struct attribute_group rt_sysfs_attr_group = { | |
1043 | .attrs = data_sysfs_attrs, | |
1044 | }; | |
1045 | ||
1046 | /* | |
1047 | * FPGA Realtime Data Character Device | |
1048 | */ | |
1049 | ||
1050 | static int data_open(struct inode *inode, struct file *filp) | |
1051 | { | |
1052 | /* | |
1053 | * The miscdevice layer puts our struct miscdevice into the | |
1054 | * filp->private_data field. We use this to find our private | |
1055 | * data and then overwrite it with our own private structure. | |
1056 | */ | |
1057 | struct fpga_device *priv = container_of(filp->private_data, | |
1058 | struct fpga_device, miscdev); | |
1059 | struct fpga_reader *reader; | |
1060 | int ret; | |
1061 | ||
1062 | /* allocate private data */ | |
1063 | reader = kzalloc(sizeof(*reader), GFP_KERNEL); | |
1064 | if (!reader) | |
1065 | return -ENOMEM; | |
1066 | ||
1067 | reader->priv = priv; | |
1068 | reader->buf = NULL; | |
1069 | ||
1070 | filp->private_data = reader; | |
1071 | ret = nonseekable_open(inode, filp); | |
1072 | if (ret) { | |
1073 | dev_err(priv->dev, "nonseekable-open failed\n"); | |
1074 | kfree(reader); | |
1075 | return ret; | |
1076 | } | |
1077 | ||
1078 | /* | |
1079 | * success, increase the reference count of the private data structure | |
1080 | * so that it doesn't disappear if the device is unbound | |
1081 | */ | |
1082 | kref_get(&priv->ref); | |
1083 | return 0; | |
1084 | } | |
1085 | ||
1086 | static int data_release(struct inode *inode, struct file *filp) | |
1087 | { | |
1088 | struct fpga_reader *reader = filp->private_data; | |
1089 | struct fpga_device *priv = reader->priv; | |
1090 | ||
1091 | /* free the per-reader structure */ | |
1092 | data_free_buffer(reader->buf); | |
1093 | kfree(reader); | |
1094 | filp->private_data = NULL; | |
1095 | ||
1096 | /* decrement our reference count to the private data */ | |
1097 | kref_put(&priv->ref, fpga_device_release); | |
1098 | return 0; | |
1099 | } | |
1100 | ||
1101 | static ssize_t data_read(struct file *filp, char __user *ubuf, size_t count, | |
1102 | loff_t *f_pos) | |
1103 | { | |
1104 | struct fpga_reader *reader = filp->private_data; | |
1105 | struct fpga_device *priv = reader->priv; | |
1106 | struct list_head *used = &priv->used; | |
75ff85a8 | 1107 | bool drop_buffer = false; |
c186f0e1 IS |
1108 | struct data_buf *dbuf; |
1109 | size_t avail; | |
1110 | void *data; | |
1111 | int ret; | |
1112 | ||
1113 | /* check if we already have a partial buffer */ | |
1114 | if (reader->buf) { | |
1115 | dbuf = reader->buf; | |
1116 | goto have_buffer; | |
1117 | } | |
1118 | ||
1119 | spin_lock_irq(&priv->lock); | |
1120 | ||
1121 | /* Block until there is at least one buffer on the used list */ | |
1122 | while (list_empty(used)) { | |
1123 | spin_unlock_irq(&priv->lock); | |
1124 | ||
1125 | if (filp->f_flags & O_NONBLOCK) | |
1126 | return -EAGAIN; | |
1127 | ||
1128 | ret = wait_event_interruptible(priv->wait, !list_empty(used)); | |
1129 | if (ret) | |
1130 | return ret; | |
1131 | ||
1132 | spin_lock_irq(&priv->lock); | |
1133 | } | |
1134 | ||
1135 | /* Grab the first buffer off of the used list */ | |
1136 | dbuf = list_first_entry(used, struct data_buf, entry); | |
1137 | list_del_init(&dbuf->entry); | |
1138 | ||
1139 | spin_unlock_irq(&priv->lock); | |
1140 | ||
1141 | /* Buffers are always mapped: unmap it */ | |
1142 | videobuf_dma_unmap(priv->dev, &dbuf->vb); | |
1143 | ||
1144 | /* save the buffer for later */ | |
1145 | reader->buf = dbuf; | |
1146 | reader->buf_start = 0; | |
1147 | ||
1148 | have_buffer: | |
1149 | /* Get the number of bytes available */ | |
1150 | avail = dbuf->size - reader->buf_start; | |
1151 | data = dbuf->vb.vaddr + reader->buf_start; | |
1152 | ||
1153 | /* Get the number of bytes we can transfer */ | |
1154 | count = min(count, avail); | |
1155 | ||
1156 | /* Copy the data to the userspace buffer */ | |
1157 | if (copy_to_user(ubuf, data, count)) | |
1158 | return -EFAULT; | |
1159 | ||
1160 | /* Update the amount of available space */ | |
1161 | avail -= count; | |
1162 | ||
1163 | /* | |
1164 | * If there is still some data available, save the buffer for the | |
1165 | * next userspace call to read() and return | |
1166 | */ | |
1167 | if (avail > 0) { | |
1168 | reader->buf_start += count; | |
1169 | reader->buf = dbuf; | |
1170 | return count; | |
1171 | } | |
1172 | ||
1173 | /* | |
1174 | * Get the buffer ready to be reused for DMA | |
1175 | * | |
1176 | * If it fails, we pretend that the read never happed and return | |
1177 | * -EFAULT to userspace. The read will be retried. | |
1178 | */ | |
1179 | ret = videobuf_dma_map(priv->dev, &dbuf->vb); | |
1180 | if (ret) { | |
1181 | dev_err(priv->dev, "unable to remap buffer for DMA\n"); | |
1182 | return -EFAULT; | |
1183 | } | |
1184 | ||
1185 | /* Lock against concurrent enable/disable */ | |
1186 | spin_lock_irq(&priv->lock); | |
1187 | ||
1188 | /* the reader is finished with this buffer */ | |
1189 | reader->buf = NULL; | |
1190 | ||
1191 | /* | |
1192 | * One of two things has happened, the device is disabled, or the | |
1193 | * device has been reconfigured underneath us. In either case, we | |
1194 | * should just throw away the buffer. | |
75ff85a8 IS |
1195 | * |
1196 | * Lockdep complains if this is done under the spinlock, so we | |
1197 | * handle it during the unlock path. | |
c186f0e1 IS |
1198 | */ |
1199 | if (!priv->enabled || dbuf->size != priv->bufsize) { | |
75ff85a8 | 1200 | drop_buffer = true; |
c186f0e1 IS |
1201 | goto out_unlock; |
1202 | } | |
1203 | ||
1204 | /* The buffer is safe to reuse, so add it back to the free list */ | |
1205 | list_add_tail(&dbuf->entry, &priv->free); | |
1206 | ||
1207 | out_unlock: | |
1208 | spin_unlock_irq(&priv->lock); | |
75ff85a8 IS |
1209 | |
1210 | if (drop_buffer) { | |
1211 | videobuf_dma_unmap(priv->dev, &dbuf->vb); | |
1212 | data_free_buffer(dbuf); | |
1213 | } | |
1214 | ||
c186f0e1 IS |
1215 | return count; |
1216 | } | |
1217 | ||
1218 | static unsigned int data_poll(struct file *filp, struct poll_table_struct *tbl) | |
1219 | { | |
1220 | struct fpga_reader *reader = filp->private_data; | |
1221 | struct fpga_device *priv = reader->priv; | |
1222 | unsigned int mask = 0; | |
1223 | ||
1224 | poll_wait(filp, &priv->wait, tbl); | |
1225 | ||
1226 | if (!list_empty(&priv->used)) | |
1227 | mask |= POLLIN | POLLRDNORM; | |
1228 | ||
1229 | return mask; | |
1230 | } | |
1231 | ||
1232 | static int data_mmap(struct file *filp, struct vm_area_struct *vma) | |
1233 | { | |
1234 | struct fpga_reader *reader = filp->private_data; | |
1235 | struct fpga_device *priv = reader->priv; | |
1236 | unsigned long offset, vsize, psize, addr; | |
1237 | ||
1238 | /* VMA properties */ | |
1239 | offset = vma->vm_pgoff << PAGE_SHIFT; | |
1240 | vsize = vma->vm_end - vma->vm_start; | |
1241 | psize = priv->phys_size - offset; | |
1242 | addr = (priv->phys_addr + offset) >> PAGE_SHIFT; | |
1243 | ||
1244 | /* Check against the FPGA region's physical memory size */ | |
1245 | if (vsize > psize) { | |
1246 | dev_err(priv->dev, "requested mmap mapping too large\n"); | |
1247 | return -EINVAL; | |
1248 | } | |
1249 | ||
c186f0e1 IS |
1250 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
1251 | ||
1252 | return io_remap_pfn_range(vma, vma->vm_start, addr, vsize, | |
1253 | vma->vm_page_prot); | |
1254 | } | |
1255 | ||
1256 | static const struct file_operations data_fops = { | |
1257 | .owner = THIS_MODULE, | |
1258 | .open = data_open, | |
1259 | .release = data_release, | |
1260 | .read = data_read, | |
1261 | .poll = data_poll, | |
1262 | .mmap = data_mmap, | |
1263 | .llseek = no_llseek, | |
1264 | }; | |
1265 | ||
1266 | /* | |
1267 | * OpenFirmware Device Subsystem | |
1268 | */ | |
1269 | ||
1270 | static bool dma_filter(struct dma_chan *chan, void *data) | |
1271 | { | |
1272 | /* | |
1273 | * DMA Channel #0 is used for the FPGA Programmer, so ignore it | |
1274 | * | |
1275 | * This probably won't survive an unload/load cycle of the Freescale | |
1276 | * DMAEngine driver, but that won't be a problem | |
1277 | */ | |
1278 | if (chan->chan_id == 0 && chan->device->dev_id == 0) | |
1279 | return false; | |
1280 | ||
1281 | return true; | |
1282 | } | |
1283 | ||
49334020 | 1284 | static int data_of_probe(struct platform_device *op) |
c186f0e1 IS |
1285 | { |
1286 | struct device_node *of_node = op->dev.of_node; | |
1287 | struct device *this_device; | |
1288 | struct fpga_device *priv; | |
1289 | struct resource res; | |
1290 | dma_cap_mask_t mask; | |
1291 | int ret; | |
1292 | ||
1293 | /* Allocate private data */ | |
1294 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
1295 | if (!priv) { | |
1296 | dev_err(&op->dev, "Unable to allocate device private data\n"); | |
1297 | ret = -ENOMEM; | |
1298 | goto out_return; | |
1299 | } | |
1300 | ||
9093ca88 | 1301 | platform_set_drvdata(op, priv); |
c186f0e1 IS |
1302 | priv->dev = &op->dev; |
1303 | kref_init(&priv->ref); | |
1304 | mutex_init(&priv->mutex); | |
1305 | ||
1306 | dev_set_drvdata(priv->dev, priv); | |
1307 | spin_lock_init(&priv->lock); | |
1308 | INIT_LIST_HEAD(&priv->free); | |
1309 | INIT_LIST_HEAD(&priv->used); | |
1310 | init_waitqueue_head(&priv->wait); | |
1311 | ||
1312 | /* Setup the misc device */ | |
1313 | priv->miscdev.minor = MISC_DYNAMIC_MINOR; | |
1314 | priv->miscdev.name = drv_name; | |
1315 | priv->miscdev.fops = &data_fops; | |
1316 | ||
1317 | /* Get the physical address of the FPGA registers */ | |
1318 | ret = of_address_to_resource(of_node, 0, &res); | |
1319 | if (ret) { | |
1320 | dev_err(&op->dev, "Unable to find FPGA physical address\n"); | |
1321 | ret = -ENODEV; | |
1322 | goto out_free_priv; | |
1323 | } | |
1324 | ||
1325 | priv->phys_addr = res.start; | |
1326 | priv->phys_size = resource_size(&res); | |
1327 | ||
1328 | /* ioremap the registers for use */ | |
1329 | priv->regs = of_iomap(of_node, 0); | |
1330 | if (!priv->regs) { | |
1331 | dev_err(&op->dev, "Unable to ioremap registers\n"); | |
1332 | ret = -ENOMEM; | |
1333 | goto out_free_priv; | |
1334 | } | |
1335 | ||
1336 | dma_cap_zero(mask); | |
1337 | dma_cap_set(DMA_MEMCPY, mask); | |
1338 | dma_cap_set(DMA_INTERRUPT, mask); | |
1339 | dma_cap_set(DMA_SLAVE, mask); | |
1340 | dma_cap_set(DMA_SG, mask); | |
1341 | ||
1342 | /* Request a DMA channel */ | |
1343 | priv->chan = dma_request_channel(mask, dma_filter, NULL); | |
1344 | if (!priv->chan) { | |
1345 | dev_err(&op->dev, "Unable to request DMA channel\n"); | |
1346 | ret = -ENODEV; | |
1347 | goto out_unmap_regs; | |
1348 | } | |
1349 | ||
1350 | /* Find the correct IRQ number */ | |
1351 | priv->irq = irq_of_parse_and_map(of_node, 0); | |
1352 | if (priv->irq == NO_IRQ) { | |
1353 | dev_err(&op->dev, "Unable to find IRQ line\n"); | |
1354 | ret = -ENODEV; | |
1355 | goto out_release_dma; | |
1356 | } | |
1357 | ||
1358 | /* Drive the GPIO for FPGA IRQ high (no interrupt) */ | |
1359 | iowrite32be(IRQ_CORL_DONE, priv->regs + SYS_IRQ_OUTPUT_DATA); | |
1360 | ||
1361 | /* Register the miscdevice */ | |
1362 | ret = misc_register(&priv->miscdev); | |
1363 | if (ret) { | |
1364 | dev_err(&op->dev, "Unable to register miscdevice\n"); | |
1365 | goto out_irq_dispose_mapping; | |
1366 | } | |
1367 | ||
1368 | /* Create the debugfs files */ | |
1369 | ret = data_debugfs_init(priv); | |
1370 | if (ret) { | |
1371 | dev_err(&op->dev, "Unable to create debugfs files\n"); | |
1372 | goto out_misc_deregister; | |
1373 | } | |
1374 | ||
1375 | /* Create the sysfs files */ | |
1376 | this_device = priv->miscdev.this_device; | |
1377 | dev_set_drvdata(this_device, priv); | |
1378 | ret = sysfs_create_group(&this_device->kobj, &rt_sysfs_attr_group); | |
1379 | if (ret) { | |
1380 | dev_err(&op->dev, "Unable to create sysfs files\n"); | |
1381 | goto out_data_debugfs_exit; | |
1382 | } | |
1383 | ||
1384 | dev_info(&op->dev, "CARMA FPGA Realtime Data Driver Loaded\n"); | |
1385 | return 0; | |
1386 | ||
1387 | out_data_debugfs_exit: | |
1388 | data_debugfs_exit(priv); | |
1389 | out_misc_deregister: | |
1390 | misc_deregister(&priv->miscdev); | |
1391 | out_irq_dispose_mapping: | |
1392 | irq_dispose_mapping(priv->irq); | |
1393 | out_release_dma: | |
1394 | dma_release_channel(priv->chan); | |
1395 | out_unmap_regs: | |
1396 | iounmap(priv->regs); | |
1397 | out_free_priv: | |
1398 | kref_put(&priv->ref, fpga_device_release); | |
1399 | out_return: | |
1400 | return ret; | |
1401 | } | |
1402 | ||
1403 | static int data_of_remove(struct platform_device *op) | |
1404 | { | |
9093ca88 | 1405 | struct fpga_device *priv = platform_get_drvdata(op); |
c186f0e1 IS |
1406 | struct device *this_device = priv->miscdev.this_device; |
1407 | ||
1408 | /* remove all sysfs files, now the device cannot be re-enabled */ | |
1409 | sysfs_remove_group(&this_device->kobj, &rt_sysfs_attr_group); | |
1410 | ||
1411 | /* remove all debugfs files */ | |
1412 | data_debugfs_exit(priv); | |
1413 | ||
1414 | /* disable the device from generating data */ | |
1415 | data_device_disable(priv); | |
1416 | ||
1417 | /* remove the character device to stop new readers from appearing */ | |
1418 | misc_deregister(&priv->miscdev); | |
1419 | ||
1420 | /* cleanup everything not needed by readers */ | |
1421 | irq_dispose_mapping(priv->irq); | |
1422 | dma_release_channel(priv->chan); | |
1423 | iounmap(priv->regs); | |
1424 | ||
1425 | /* release our reference */ | |
1426 | kref_put(&priv->ref, fpga_device_release); | |
1427 | return 0; | |
1428 | } | |
1429 | ||
1430 | static struct of_device_id data_of_match[] = { | |
1431 | { .compatible = "carma,carma-fpga", }, | |
1432 | {}, | |
1433 | }; | |
1434 | ||
49334020 | 1435 | static struct platform_driver data_of_driver = { |
c186f0e1 IS |
1436 | .probe = data_of_probe, |
1437 | .remove = data_of_remove, | |
1438 | .driver = { | |
1439 | .name = drv_name, | |
1440 | .of_match_table = data_of_match, | |
1441 | .owner = THIS_MODULE, | |
1442 | }, | |
1443 | }; | |
1444 | ||
b00e126f | 1445 | module_platform_driver(data_of_driver); |
c186f0e1 IS |
1446 | |
1447 | MODULE_AUTHOR("Ira W. Snyder <iws@ovro.caltech.edu>"); | |
1448 | MODULE_DESCRIPTION("CARMA DATA-FPGA Access Driver"); | |
1449 | MODULE_LICENSE("GPL"); |