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cxl: Separate bare-metal fields in adapter and AFU data structures
[deliverable/linux.git] / drivers / misc / cxl / cxl.h
CommitLineData
f204e0b8
IM		 1/*
2 * Copyright 2014 IBM Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#ifndef _CXL_H_
11#define _CXL_H_
12
13#include <linux/interrupt.h>
14#include <linux/semaphore.h>
15#include <linux/device.h>
16#include <linux/types.h>
17#include <linux/cdev.h>
18#include <linux/pid.h>
19#include <linux/io.h>
20#include <linux/pci.h>
0520336a 21#include <linux/fs.h>
f204e0b8
IM		 22#include <asm/cputable.h>
23#include <asm/mmu.h>
24#include <asm/reg.h>
ec249dd8 25#include <misc/cxl-base.h>
f204e0b8
IM		 26
27#include <uapi/misc/cxl.h>
28
29extern uint cxl_verbose;
30
31#define CXL_TIMEOUT 5
32
33/*
34 * Bump version each time a user API change is made, whether it is
35 * backwards compatible ot not.
36 */
d9232a3d 37#define CXL_API_VERSION 2
f204e0b8
IM		 38#define CXL_API_VERSION_COMPATIBLE 1
39
40/*
41 * Opaque types to avoid accidentally passing registers for the wrong MMIO
42 *
43 * At the end of the day, I'm not married to using typedef here, but it might
44 * (and has!) help avoid bugs like mixing up CXL_PSL_CtxTime and
45 * CXL_PSL_CtxTime_An, or calling cxl_p1n_write instead of cxl_p1_write.
46 *
47 * I'm quite happy if these are changed back to #defines before upstreaming, it
48 * should be little more than a regexp search+replace operation in this file.
49 */
50typedef struct {
51 const int x;
52} cxl_p1_reg_t;
53typedef struct {
54 const int x;
55} cxl_p1n_reg_t;
56typedef struct {
57 const int x;
58} cxl_p2n_reg_t;
59#define cxl_reg_off(reg) \
60 (reg.x)
61
62/* Memory maps. Ref CXL Appendix A */
63
64/* PSL Privilege 1 Memory Map */
65/* Configuration and Control area */
66static const cxl_p1_reg_t CXL_PSL_CtxTime = {0x0000};
67static const cxl_p1_reg_t CXL_PSL_ErrIVTE = {0x0008};
68static const cxl_p1_reg_t CXL_PSL_KEY1 = {0x0010};
69static const cxl_p1_reg_t CXL_PSL_KEY2 = {0x0018};
70static const cxl_p1_reg_t CXL_PSL_Control = {0x0020};
71/* Downloading */
72static const cxl_p1_reg_t CXL_PSL_DLCNTL = {0x0060};
73static const cxl_p1_reg_t CXL_PSL_DLADDR = {0x0068};
74
75/* PSL Lookaside Buffer Management Area */
76static const cxl_p1_reg_t CXL_PSL_LBISEL = {0x0080};
77static const cxl_p1_reg_t CXL_PSL_SLBIE = {0x0088};
78static const cxl_p1_reg_t CXL_PSL_SLBIA = {0x0090};
79static const cxl_p1_reg_t CXL_PSL_TLBIE = {0x00A0};
80static const cxl_p1_reg_t CXL_PSL_TLBIA = {0x00A8};
81static const cxl_p1_reg_t CXL_PSL_AFUSEL = {0x00B0};
82
83/* 0x00C0:7EFF Implementation dependent area */
84static const cxl_p1_reg_t CXL_PSL_FIR1 = {0x0100};
85static const cxl_p1_reg_t CXL_PSL_FIR2 = {0x0108};
390fd592 86static const cxl_p1_reg_t CXL_PSL_Timebase = {0x0110};
f204e0b8
IM		 87static const cxl_p1_reg_t CXL_PSL_VERSION = {0x0118};
88static const cxl_p1_reg_t CXL_PSL_RESLCKTO = {0x0128};
390fd592 89static const cxl_p1_reg_t CXL_PSL_TB_CTLSTAT = {0x0140};
f204e0b8
IM		 90static const cxl_p1_reg_t CXL_PSL_FIR_CNTL = {0x0148};
91static const cxl_p1_reg_t CXL_PSL_DSNDCTL = {0x0150};
92static const cxl_p1_reg_t CXL_PSL_SNWRALLOC = {0x0158};
93static const cxl_p1_reg_t CXL_PSL_TRACE = {0x0170};
94/* 0x7F00:7FFF Reserved PCIe MSI-X Pending Bit Array area */
95/* 0x8000:FFFF Reserved PCIe MSI-X Table Area */
96
97/* PSL Slice Privilege 1 Memory Map */
98/* Configuration Area */
99static const cxl_p1n_reg_t CXL_PSL_SR_An = {0x00};
100static const cxl_p1n_reg_t CXL_PSL_LPID_An = {0x08};
101static const cxl_p1n_reg_t CXL_PSL_AMBAR_An = {0x10};
102static const cxl_p1n_reg_t CXL_PSL_SPOffset_An = {0x18};
103static const cxl_p1n_reg_t CXL_PSL_ID_An = {0x20};
104static const cxl_p1n_reg_t CXL_PSL_SERR_An = {0x28};
105/* Memory Management and Lookaside Buffer Management */
106static const cxl_p1n_reg_t CXL_PSL_SDR_An = {0x30};
107static const cxl_p1n_reg_t CXL_PSL_AMOR_An = {0x38};
108/* Pointer Area */
109static const cxl_p1n_reg_t CXL_HAURP_An = {0x80};
110static const cxl_p1n_reg_t CXL_PSL_SPAP_An = {0x88};
111static const cxl_p1n_reg_t CXL_PSL_LLCMD_An = {0x90};
112/* Control Area */
113static const cxl_p1n_reg_t CXL_PSL_SCNTL_An = {0xA0};
114static const cxl_p1n_reg_t CXL_PSL_CtxTime_An = {0xA8};
115static const cxl_p1n_reg_t CXL_PSL_IVTE_Offset_An = {0xB0};
116static const cxl_p1n_reg_t CXL_PSL_IVTE_Limit_An = {0xB8};
117/* 0xC0:FF Implementation Dependent Area */
118static const cxl_p1n_reg_t CXL_PSL_FIR_SLICE_An = {0xC0};
119static const cxl_p1n_reg_t CXL_AFU_DEBUG_An = {0xC8};
120static const cxl_p1n_reg_t CXL_PSL_APCALLOC_A = {0xD0};
121static const cxl_p1n_reg_t CXL_PSL_COALLOC_A = {0xD8};
122static const cxl_p1n_reg_t CXL_PSL_RXCTL_A = {0xE0};
123static const cxl_p1n_reg_t CXL_PSL_SLICE_TRACE = {0xE8};
124
125/* PSL Slice Privilege 2 Memory Map */
126/* Configuration and Control Area */
127static const cxl_p2n_reg_t CXL_PSL_PID_TID_An = {0x000};
128static const cxl_p2n_reg_t CXL_CSRP_An = {0x008};
129static const cxl_p2n_reg_t CXL_AURP0_An = {0x010};
130static const cxl_p2n_reg_t CXL_AURP1_An = {0x018};
131static const cxl_p2n_reg_t CXL_SSTP0_An = {0x020};
132static const cxl_p2n_reg_t CXL_SSTP1_An = {0x028};
133static const cxl_p2n_reg_t CXL_PSL_AMR_An = {0x030};
134/* Segment Lookaside Buffer Management */
135static const cxl_p2n_reg_t CXL_SLBIE_An = {0x040};
136static const cxl_p2n_reg_t CXL_SLBIA_An = {0x048};
137static const cxl_p2n_reg_t CXL_SLBI_Select_An = {0x050};
138/* Interrupt Registers */
139static const cxl_p2n_reg_t CXL_PSL_DSISR_An = {0x060};
140static const cxl_p2n_reg_t CXL_PSL_DAR_An = {0x068};
141static const cxl_p2n_reg_t CXL_PSL_DSR_An = {0x070};
142static const cxl_p2n_reg_t CXL_PSL_TFC_An = {0x078};
143static const cxl_p2n_reg_t CXL_PSL_PEHandle_An = {0x080};
144static const cxl_p2n_reg_t CXL_PSL_ErrStat_An = {0x088};
145/* AFU Registers */
146static const cxl_p2n_reg_t CXL_AFU_Cntl_An = {0x090};
147static const cxl_p2n_reg_t CXL_AFU_ERR_An = {0x098};
148/* Work Element Descriptor */
149static const cxl_p2n_reg_t CXL_PSL_WED_An = {0x0A0};
150/* 0x0C0:FFF Implementation Dependent Area */
151
152#define CXL_PSL_SPAP_Addr 0x0ffffffffffff000ULL
153#define CXL_PSL_SPAP_Size 0x0000000000000ff0ULL
154#define CXL_PSL_SPAP_Size_Shift 4
155#define CXL_PSL_SPAP_V 0x0000000000000001ULL
156
390fd592
PB		 157/****** CXL_PSL_Control ****************************************************/
158#define CXL_PSL_Control_tb 0x0000000000000001ULL
159
f204e0b8
IM		 160/****** CXL_PSL_DLCNTL *****************************************************/
161#define CXL_PSL_DLCNTL_D (0x1ull << (63-28))
162#define CXL_PSL_DLCNTL_C (0x1ull << (63-29))
163#define CXL_PSL_DLCNTL_E (0x1ull << (63-30))
164#define CXL_PSL_DLCNTL_S (0x1ull << (63-31))
165#define CXL_PSL_DLCNTL_CE (CXL_PSL_DLCNTL_C | CXL_PSL_DLCNTL_E)
166#define CXL_PSL_DLCNTL_DCES (CXL_PSL_DLCNTL_D | CXL_PSL_DLCNTL_CE | CXL_PSL_DLCNTL_S)
167
168/****** CXL_PSL_SR_An ******************************************************/
169#define CXL_PSL_SR_An_SF MSR_SF /* 64bit */
170#define CXL_PSL_SR_An_TA (1ull << (63-1)) /* Tags active, GA1: 0 */
171#define CXL_PSL_SR_An_HV MSR_HV /* Hypervisor, GA1: 0 */
172#define CXL_PSL_SR_An_PR MSR_PR /* Problem state, GA1: 1 */
173#define CXL_PSL_SR_An_ISL (1ull << (63-53)) /* Ignore Segment Large Page */
174#define CXL_PSL_SR_An_TC (1ull << (63-54)) /* Page Table secondary hash */
175#define CXL_PSL_SR_An_US (1ull << (63-56)) /* User state, GA1: X */
176#define CXL_PSL_SR_An_SC (1ull << (63-58)) /* Segment Table secondary hash */
177#define CXL_PSL_SR_An_R MSR_DR /* Relocate, GA1: 1 */
178#define CXL_PSL_SR_An_MP (1ull << (63-62)) /* Master Process */
179#define CXL_PSL_SR_An_LE (1ull << (63-63)) /* Little Endian */
180
181/****** CXL_PSL_LLCMD_An ****************************************************/
182#define CXL_LLCMD_TERMINATE 0x0001000000000000ULL
183#define CXL_LLCMD_REMOVE 0x0002000000000000ULL
184#define CXL_LLCMD_SUSPEND 0x0003000000000000ULL
185#define CXL_LLCMD_RESUME 0x0004000000000000ULL
186#define CXL_LLCMD_ADD 0x0005000000000000ULL
187#define CXL_LLCMD_UPDATE 0x0006000000000000ULL
188#define CXL_LLCMD_HANDLE_MASK 0x000000000000ffffULL
189
190/****** CXL_PSL_ID_An ****************************************************/
191#define CXL_PSL_ID_An_F (1ull << (63-31))
192#define CXL_PSL_ID_An_L (1ull << (63-30))
193
194/****** CXL_PSL_SCNTL_An ****************************************************/
195#define CXL_PSL_SCNTL_An_CR (0x1ull << (63-15))
196/* Programming Modes: */
197#define CXL_PSL_SCNTL_An_PM_MASK (0xffffull << (63-31))
198#define CXL_PSL_SCNTL_An_PM_Shared (0x0000ull << (63-31))
199#define CXL_PSL_SCNTL_An_PM_OS (0x0001ull << (63-31))
200#define CXL_PSL_SCNTL_An_PM_Process (0x0002ull << (63-31))
201#define CXL_PSL_SCNTL_An_PM_AFU (0x0004ull << (63-31))
202#define CXL_PSL_SCNTL_An_PM_AFU_PBT (0x0104ull << (63-31))
203/* Purge Status (ro) */
204#define CXL_PSL_SCNTL_An_Ps_MASK (0x3ull << (63-39))
205#define CXL_PSL_SCNTL_An_Ps_Pending (0x1ull << (63-39))
206#define CXL_PSL_SCNTL_An_Ps_Complete (0x3ull << (63-39))
207/* Purge */
208#define CXL_PSL_SCNTL_An_Pc (0x1ull << (63-48))
209/* Suspend Status (ro) */
210#define CXL_PSL_SCNTL_An_Ss_MASK (0x3ull << (63-55))
211#define CXL_PSL_SCNTL_An_Ss_Pending (0x1ull << (63-55))
212#define CXL_PSL_SCNTL_An_Ss_Complete (0x3ull << (63-55))
213/* Suspend Control */
214#define CXL_PSL_SCNTL_An_Sc (0x1ull << (63-63))
215
216/* AFU Slice Enable Status (ro) */
217#define CXL_AFU_Cntl_An_ES_MASK (0x7ull << (63-2))
218#define CXL_AFU_Cntl_An_ES_Disabled (0x0ull << (63-2))
219#define CXL_AFU_Cntl_An_ES_Enabled (0x4ull << (63-2))
220/* AFU Slice Enable */
221#define CXL_AFU_Cntl_An_E (0x1ull << (63-3))
222/* AFU Slice Reset status (ro) */
223#define CXL_AFU_Cntl_An_RS_MASK (0x3ull << (63-5))
224#define CXL_AFU_Cntl_An_RS_Pending (0x1ull << (63-5))
225#define CXL_AFU_Cntl_An_RS_Complete (0x2ull << (63-5))
226/* AFU Slice Reset */
227#define CXL_AFU_Cntl_An_RA (0x1ull << (63-7))
228
229/****** CXL_SSTP0/1_An ******************************************************/
230/* These top bits are for the segment that CONTAINS the segment table */
231#define CXL_SSTP0_An_B_SHIFT SLB_VSID_SSIZE_SHIFT
232#define CXL_SSTP0_An_KS (1ull << (63-2))
233#define CXL_SSTP0_An_KP (1ull << (63-3))
234#define CXL_SSTP0_An_N (1ull << (63-4))
235#define CXL_SSTP0_An_L (1ull << (63-5))
236#define CXL_SSTP0_An_C (1ull << (63-6))
237#define CXL_SSTP0_An_TA (1ull << (63-7))
238#define CXL_SSTP0_An_LP_SHIFT (63-9) /* 2 Bits */
239/* And finally, the virtual address & size of the segment table: */
240#define CXL_SSTP0_An_SegTableSize_SHIFT (63-31) /* 12 Bits */
241#define CXL_SSTP0_An_SegTableSize_MASK \
242 (((1ull << 12) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT)
243#define CXL_SSTP0_An_STVA_U_MASK ((1ull << (63-49))-1)
244#define CXL_SSTP1_An_STVA_L_MASK (~((1ull << (63-55))-1))
245#define CXL_SSTP1_An_V (1ull << (63-63))
246
247/****** CXL_PSL_SLBIE_[An] **************************************************/
248/* write: */
249#define CXL_SLBIE_C PPC_BIT(36) /* Class */
250#define CXL_SLBIE_SS PPC_BITMASK(37, 38) /* Segment Size */
251#define CXL_SLBIE_SS_SHIFT PPC_BITLSHIFT(38)
252#define CXL_SLBIE_TA PPC_BIT(38) /* Tags Active */
253/* read: */
254#define CXL_SLBIE_MAX PPC_BITMASK(24, 31)
255#define CXL_SLBIE_PENDING PPC_BITMASK(56, 63)
256
257/****** Common to all CXL_TLBIA/SLBIA_[An] **********************************/
258#define CXL_TLB_SLB_P (1ull) /* Pending (read) */
259
260/****** Common to all CXL_TLB/SLB_IA/IE_[An] registers **********************/
261#define CXL_TLB_SLB_IQ_ALL (0ull) /* Inv qualifier */
262#define CXL_TLB_SLB_IQ_LPID (1ull) /* Inv qualifier */
263#define CXL_TLB_SLB_IQ_LPIDPID (3ull) /* Inv qualifier */
264
265/****** CXL_PSL_AFUSEL ******************************************************/
266#define CXL_PSL_AFUSEL_A (1ull << (63-55)) /* Adapter wide invalidates affect all AFUs */
267
268/****** CXL_PSL_DSISR_An ****************************************************/
269#define CXL_PSL_DSISR_An_DS (1ull << (63-0)) /* Segment not found */
270#define CXL_PSL_DSISR_An_DM (1ull << (63-1)) /* PTE not found (See also: M) or protection fault */
271#define CXL_PSL_DSISR_An_ST (1ull << (63-2)) /* Segment Table PTE not found */
272#define CXL_PSL_DSISR_An_UR (1ull << (63-3)) /* AURP PTE not found */
273#define CXL_PSL_DSISR_TRANS (CXL_PSL_DSISR_An_DS | CXL_PSL_DSISR_An_DM | CXL_PSL_DSISR_An_ST | CXL_PSL_DSISR_An_UR)
274#define CXL_PSL_DSISR_An_PE (1ull << (63-4)) /* PSL Error (implementation specific) */
275#define CXL_PSL_DSISR_An_AE (1ull << (63-5)) /* AFU Error */
276#define CXL_PSL_DSISR_An_OC (1ull << (63-6)) /* OS Context Warning */
277/* NOTE: Bits 32:63 are undefined if DSISR[DS] = 1 */
278#define CXL_PSL_DSISR_An_M DSISR_NOHPTE /* PTE not found */
279#define CXL_PSL_DSISR_An_P DSISR_PROTFAULT /* Storage protection violation */
280#define CXL_PSL_DSISR_An_A (1ull << (63-37)) /* AFU lock access to write through or cache inhibited storage */
281#define CXL_PSL_DSISR_An_S DSISR_ISSTORE /* Access was afu_wr or afu_zero */
282#define CXL_PSL_DSISR_An_K DSISR_KEYFAULT /* Access not permitted by virtual page class key protection */
283
284/****** CXL_PSL_TFC_An ******************************************************/
285#define CXL_PSL_TFC_An_A (1ull << (63-28)) /* Acknowledge non-translation fault */
286#define CXL_PSL_TFC_An_C (1ull << (63-29)) /* Continue (abort transaction) */
287#define CXL_PSL_TFC_An_AE (1ull << (63-30)) /* Restart PSL with address error */
288#define CXL_PSL_TFC_An_R (1ull << (63-31)) /* Restart PSL transaction */
289
290/* cxl_process_element->software_status */
291#define CXL_PE_SOFTWARE_STATE_V (1ul << (31 - 0)) /* Valid */
292#define CXL_PE_SOFTWARE_STATE_C (1ul << (31 - 29)) /* Complete */
293#define CXL_PE_SOFTWARE_STATE_S (1ul << (31 - 30)) /* Suspend */
294#define CXL_PE_SOFTWARE_STATE_T (1ul << (31 - 31)) /* Terminate */
295
d6a6af2c
IM		 296/****** CXL_PSL_RXCTL_An (Implementation Specific) **************************
297 * Controls AFU Hang Pulse, which sets the timeout for the AFU to respond to
298 * the PSL for any response (except MMIO). Timeouts will occur between 1x to 2x
299 * of the hang pulse frequency.
300 */
301#define CXL_PSL_RXCTL_AFUHP_4S 0x7000000000000000ULL
302
f204e0b8
IM		 303/* SPA->sw_command_status */
304#define CXL_SPA_SW_CMD_MASK 0xffff000000000000ULL
305#define CXL_SPA_SW_CMD_TERMINATE 0x0001000000000000ULL
306#define CXL_SPA_SW_CMD_REMOVE 0x0002000000000000ULL
307#define CXL_SPA_SW_CMD_SUSPEND 0x0003000000000000ULL
308#define CXL_SPA_SW_CMD_RESUME 0x0004000000000000ULL
309#define CXL_SPA_SW_CMD_ADD 0x0005000000000000ULL
310#define CXL_SPA_SW_CMD_UPDATE 0x0006000000000000ULL
311#define CXL_SPA_SW_STATE_MASK 0x0000ffff00000000ULL
312#define CXL_SPA_SW_STATE_TERMINATED 0x0000000100000000ULL
313#define CXL_SPA_SW_STATE_REMOVED 0x0000000200000000ULL
314#define CXL_SPA_SW_STATE_SUSPENDED 0x0000000300000000ULL
315#define CXL_SPA_SW_STATE_RESUMED 0x0000000400000000ULL
316#define CXL_SPA_SW_STATE_ADDED 0x0000000500000000ULL
317#define CXL_SPA_SW_STATE_UPDATED 0x0000000600000000ULL
318#define CXL_SPA_SW_PSL_ID_MASK 0x00000000ffff0000ULL
319#define CXL_SPA_SW_LINK_MASK 0x000000000000ffffULL
320
321#define CXL_MAX_SLICES 4
322#define MAX_AFU_MMIO_REGS 3
323
f204e0b8
IM		 324#define CXL_MODE_TIME_SLICED 0x4
325#define CXL_SUPPORTED_MODES (CXL_MODE_DEDICATED | CXL_MODE_DIRECTED)
326
327enum cxl_context_status {
328 CLOSED,
329 OPENED,
330 STARTED
331};
332
333enum prefault_modes {
334 CXL_PREFAULT_NONE,
335 CXL_PREFAULT_WED,
336 CXL_PREFAULT_ALL,
337};
338
339struct cxl_sste {
340 __be64 esid_data;
341 __be64 vsid_data;
342};
343
344#define to_cxl_adapter(d) container_of(d, struct cxl, dev)
345#define to_cxl_afu(d) container_of(d, struct cxl_afu, dev)
346
cbffa3a5
CL		 347struct cxl_afu_native {
348 void __iomem *p1n_mmio;
349 void __iomem *afu_desc_mmio;
f204e0b8 350 irq_hw_number_t psl_hwirq;
cbffa3a5
CL		 351 unsigned int psl_virq;
352 struct mutex spa_mutex;
353 /*
354 * Only the first part of the SPA is used for the process element
355 * linked list. The only other part that software needs to worry about
356 * is sw_command_status, which we store a separate pointer to.
357 * Everything else in the SPA is only used by hardware
358 */
359 struct cxl_process_element *spa;
360 __be64 *sw_command_status;
361 unsigned int spa_size;
362 int spa_order;
363 int spa_max_procs;
364 u64 pp_offset;
365};
366
367struct cxl_afu_guest {
368 u64 handle;
369 phys_addr_t p2n_phys;
370 u64 p2n_size;
371 int max_ints;
372};
373
374struct cxl_afu {
375 struct cxl_afu_native *native;
376 struct cxl_afu_guest *guest;
f204e0b8
IM		 377 irq_hw_number_t serr_hwirq;
378 unsigned int serr_virq;
cbffa3a5
CL		 379 char *psl_irq_name;
380 char *err_irq_name;
f204e0b8
IM		 381 void __iomem *p2n_mmio;
382 phys_addr_t psn_phys;
f204e0b8 383 u64 pp_size;
cbffa3a5 384
f204e0b8
IM		 385 struct cxl *adapter;
386 struct device dev;
387 struct cdev afu_cdev_s, afu_cdev_m, afu_cdev_d;
388 struct device *chardev_s, *chardev_m, *chardev_d;
389 struct idr contexts_idr;
390 struct dentry *debugfs;
ee41d11d 391 struct mutex contexts_lock;
f204e0b8
IM		 392 spinlock_t afu_cntl_lock;
393
e36f6fe1
VJ		 394 /* AFU error buffer fields and bin attribute for sysfs */
395 u64 eb_len, eb_offset;
396 struct bin_attribute attr_eb;
397
6f7f0b3d
MN		 398 /* pointer to the vphb */
399 struct pci_controller *phb;
400
f204e0b8
IM		 401 int pp_irqs;
402 int irqs_max;
403 int num_procs;
404 int max_procs_virtualised;
405 int slice;
406 int modes_supported;
407 int current_mode;
b087e619
IM		 408 int crs_num;
409 u64 crs_len;
410 u64 crs_offset;
411 struct list_head crs;
f204e0b8
IM		 412 enum prefault_modes prefault_mode;
413 bool psa;
414 bool pp_psa;
415 bool enabled;
416};
417
1b5df59e
VJ		 418/* AFU refcount management */
419static inline struct cxl_afu *cxl_afu_get(struct cxl_afu *afu)
420{
421
422 return (get_device(&afu->dev) == NULL) ? NULL : afu;
423}
424
425static inline void cxl_afu_put(struct cxl_afu *afu)
426{
427 put_device(&afu->dev);
428}
429
80fa93fc
MN		 430
431struct cxl_irq_name {
432 struct list_head list;
433 char *name;
434};
435
f204e0b8
IM		 436/*
437 * This is a cxl context. If the PSL is in dedicated mode, there will be one
438 * of these per AFU. If in AFU directed there can be lots of these.
439 */
440struct cxl_context {
441 struct cxl_afu *afu;
442
443 /* Problem state MMIO */
444 phys_addr_t psn_phys;
445 u64 psn_size;
446
b123429e
IM		 447 /* Used to unmap any mmaps when force detaching */
448 struct address_space *mapping;
449 struct mutex mapping_lock;
d9232a3d
IM		 450 struct page *ff_page;
451 bool mmio_err_ff;
55e07668 452 bool kernelapi;
b123429e 453
f204e0b8
IM		 454 spinlock_t sste_lock; /* Protects segment table entries */
455 struct cxl_sste *sstp;
456 u64 sstp0, sstp1;
457 unsigned int sst_size, sst_lru;
458
459 wait_queue_head_t wq;
7b8ad495
VJ		 460 /* pid of the group leader associated with the pid */
461 struct pid *glpid;
462 /* use mm context associated with this pid for ds faults */
f204e0b8
IM		 463 struct pid *pid;
464 spinlock_t lock; /* Protects pending_irq_mask, pending_fault and fault_addr */
465 /* Only used in PR mode */
466 u64 process_token;
467
468 unsigned long *irq_bitmap; /* Accessed from IRQ context */
469 struct cxl_irq_ranges irqs;
80fa93fc 470 struct list_head irq_names;
f204e0b8
IM		 471 u64 fault_addr;
472 u64 fault_dsisr;
473 u64 afu_err;
474
475 /*
476 * This status and it's lock pretects start and detach context
477 * from racing. It also prevents detach from racing with
478 * itself
479 */
480 enum cxl_context_status status;
481 struct mutex status_mutex;
482
483
484 /* XXX: Is it possible to need multiple work items at once? */
485 struct work_struct fault_work;
486 u64 dsisr;
487 u64 dar;
488
489 struct cxl_process_element *elem;
490
491 int pe; /* process element handle */
492 u32 irq_count;
493 bool pe_inserted;
494 bool master;
495 bool kernel;
496 bool pending_irq;
497 bool pending_fault;
498 bool pending_afu_err;
8ac75b96
IM		 499
500 struct rcu_head rcu;
f204e0b8
IM		 501};
502
cbffa3a5
CL		 503struct cxl_native {
504 u64 afu_desc_off;
505 u64 afu_desc_size;
f204e0b8
IM		 506 void __iomem *p1_mmio;
507 void __iomem *p2_mmio;
508 irq_hw_number_t err_hwirq;
509 unsigned int err_virq;
cbffa3a5
CL		 510 u64 ps_off;
511};
512
513struct cxl_guest {
514 struct platform_device *pdev;
515 int irq_nranges;
516 struct cdev cdev;
517 irq_hw_number_t irq_base_offset;
518 struct irq_avail *irq_avail;
519 spinlock_t irq_alloc_lock;
520 u64 handle;
521 char *status;
522 u16 vendor;
523 u16 device;
524 u16 subsystem_vendor;
525 u16 subsystem;
526};
527
528struct cxl {
529 struct cxl_native *native;
530 struct cxl_guest *guest;
f204e0b8
IM		 531 spinlock_t afu_list_lock;
532 struct cxl_afu *afu[CXL_MAX_SLICES];
533 struct device dev;
534 struct dentry *trace;
535 struct dentry *psl_err_chk;
536 struct dentry *debugfs;
80fa93fc 537 char *irq_name;
f204e0b8
IM		 538 struct bin_attribute cxl_attr;
539 int adapter_num;
540 int user_irqs;
f204e0b8
IM		 541 u64 ps_size;
542 u16 psl_rev;
543 u16 base_image;
544 u8 vsec_status;
545 u8 caia_major;
546 u8 caia_minor;
547 u8 slices;
548 bool user_image_loaded;
549 bool perst_loads_image;
550 bool perst_select_user;
13e68d8b 551 bool perst_same_image;
f204e0b8
IM		 552};
553
2b04cf31
FB		 554int cxl_pci_alloc_one_irq(struct cxl *adapter);
555void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq);
556int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num);
557void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter);
558int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq, unsigned int virq);
4beb5421 559int cxl_update_image_control(struct cxl *adapter);
2b04cf31
FB		 560int cxl_pci_reset(struct cxl *adapter);
561void cxl_pci_release_afu(struct device *dev);
f204e0b8
IM		 562
563/* common == phyp + powernv */
564struct cxl_process_element_common {
565 __be32 tid;
566 __be32 pid;
567 __be64 csrp;
568 __be64 aurp0;
569 __be64 aurp1;
570 __be64 sstp0;
571 __be64 sstp1;
572 __be64 amr;
573 u8 reserved3[4];
574 __be64 wed;
575} __packed;
576
577/* just powernv */
578struct cxl_process_element {
579 __be64 sr;
580 __be64 SPOffset;
581 __be64 sdr;
582 __be64 haurp;
583 __be32 ctxtime;
584 __be16 ivte_offsets[4];
585 __be16 ivte_ranges[4];
586 __be32 lpid;
587 struct cxl_process_element_common common;
588 __be32 software_state;
589} __packed;
590
0b3f9c75
DA		 591static inline bool cxl_adapter_link_ok(struct cxl *cxl)
592{
593 struct pci_dev *pdev;
594
ea2d1f95
FB		 595 if (cpu_has_feature(CPU_FTR_HVMODE)) {
596 pdev = to_pci_dev(cxl->dev.parent);
597 return !pci_channel_offline(pdev);
598 }
599 return true;
0b3f9c75
DA		 600}
601
f204e0b8
IM		 602static inline void __iomem *_cxl_p1_addr(struct cxl *cxl, cxl_p1_reg_t reg)
603{
604 WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
cbffa3a5 605 return cxl->native->p1_mmio + cxl_reg_off(reg);
f204e0b8
IM		 606}
607
588b34be
DA		 608static inline void cxl_p1_write(struct cxl *cxl, cxl_p1_reg_t reg, u64 val)
609{
0b3f9c75
DA		 610 if (likely(cxl_adapter_link_ok(cxl)))
611 out_be64(_cxl_p1_addr(cxl, reg), val);
588b34be
DA		 612}
613
614static inline u64 cxl_p1_read(struct cxl *cxl, cxl_p1_reg_t reg)
615{
0b3f9c75
DA		 616 if (likely(cxl_adapter_link_ok(cxl)))
617 return in_be64(_cxl_p1_addr(cxl, reg));
618 else
619 return ~0ULL;
588b34be 620}
f204e0b8
IM		 621
622static inline void __iomem *_cxl_p1n_addr(struct cxl_afu *afu, cxl_p1n_reg_t reg)
623{
624 WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
cbffa3a5 625 return afu->native->p1n_mmio + cxl_reg_off(reg);
f204e0b8
IM		 626}
627
588b34be
DA		 628static inline void cxl_p1n_write(struct cxl_afu *afu, cxl_p1n_reg_t reg, u64 val)
629{
0b3f9c75
DA		 630 if (likely(cxl_adapter_link_ok(afu->adapter)))
631 out_be64(_cxl_p1n_addr(afu, reg), val);
588b34be
DA		 632}
633
634static inline u64 cxl_p1n_read(struct cxl_afu *afu, cxl_p1n_reg_t reg)
635{
0b3f9c75
DA		 636 if (likely(cxl_adapter_link_ok(afu->adapter)))
637 return in_be64(_cxl_p1n_addr(afu, reg));
638 else
639 return ~0ULL;
588b34be 640}
f204e0b8
IM		 641
642static inline void __iomem *_cxl_p2n_addr(struct cxl_afu *afu, cxl_p2n_reg_t reg)
643{
644 return afu->p2n_mmio + cxl_reg_off(reg);
645}
646
588b34be
DA		 647static inline void cxl_p2n_write(struct cxl_afu *afu, cxl_p2n_reg_t reg, u64 val)
648{
0b3f9c75
DA		 649 if (likely(cxl_adapter_link_ok(afu->adapter)))
650 out_be64(_cxl_p2n_addr(afu, reg), val);
588b34be 651}
f204e0b8 652
588b34be
DA		 653static inline u64 cxl_p2n_read(struct cxl_afu *afu, cxl_p2n_reg_t reg)
654{
0b3f9c75
DA		 655 if (likely(cxl_adapter_link_ok(afu->adapter)))
656 return in_be64(_cxl_p2n_addr(afu, reg));
657 else
658 return ~0ULL;
588b34be 659}
b087e619 660
2b04cf31 661ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
e36f6fe1
VJ		 662 loff_t off, size_t count);
663
b087e619 664
f204e0b8
IM		 665struct cxl_calls {
666 void (*cxl_slbia)(struct mm_struct *mm);
667 struct module *owner;
668};
669int register_cxl_calls(struct cxl_calls *calls);
670void unregister_cxl_calls(struct cxl_calls *calls);
671
f204e0b8
IM		 672void cxl_remove_adapter_nr(struct cxl *adapter);
673
05155772
DA		 674int cxl_alloc_spa(struct cxl_afu *afu);
675void cxl_release_spa(struct cxl_afu *afu);
676
f204e0b8
IM		 677int cxl_file_init(void);
678void cxl_file_exit(void);
679int cxl_register_adapter(struct cxl *adapter);
680int cxl_register_afu(struct cxl_afu *afu);
681int cxl_chardev_d_afu_add(struct cxl_afu *afu);
682int cxl_chardev_m_afu_add(struct cxl_afu *afu);
683int cxl_chardev_s_afu_add(struct cxl_afu *afu);
684void cxl_chardev_afu_remove(struct cxl_afu *afu);
685
686void cxl_context_detach_all(struct cxl_afu *afu);
687void cxl_context_free(struct cxl_context *ctx);
688void cxl_context_detach(struct cxl_context *ctx);
689
690int cxl_sysfs_adapter_add(struct cxl *adapter);
691void cxl_sysfs_adapter_remove(struct cxl *adapter);
692int cxl_sysfs_afu_add(struct cxl_afu *afu);
693void cxl_sysfs_afu_remove(struct cxl_afu *afu);
694int cxl_sysfs_afu_m_add(struct cxl_afu *afu);
695void cxl_sysfs_afu_m_remove(struct cxl_afu *afu);
696
86331862
CL		 697struct cxl *cxl_alloc_adapter(void);
698struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice);
f204e0b8
IM		 699int cxl_afu_select_best_mode(struct cxl_afu *afu);
700
2b04cf31
FB		 701int cxl_native_register_psl_irq(struct cxl_afu *afu);
702void cxl_native_release_psl_irq(struct cxl_afu *afu);
703int cxl_native_register_psl_err_irq(struct cxl *adapter);
704void cxl_native_release_psl_err_irq(struct cxl *adapter);
705int cxl_native_register_serr_irq(struct cxl_afu *afu);
706void cxl_native_release_serr_irq(struct cxl_afu *afu);
f204e0b8 707int afu_register_irqs(struct cxl_context *ctx, u32 count);
6428832a 708void afu_release_irqs(struct cxl_context *ctx, void *cookie);
8dde152e 709void afu_irq_name_free(struct cxl_context *ctx);
f204e0b8
IM		 710
711int cxl_debugfs_init(void);
712void cxl_debugfs_exit(void);
713int cxl_debugfs_adapter_add(struct cxl *adapter);
714void cxl_debugfs_adapter_remove(struct cxl *adapter);
715int cxl_debugfs_afu_add(struct cxl_afu *afu);
716void cxl_debugfs_afu_remove(struct cxl_afu *afu);
717
718void cxl_handle_fault(struct work_struct *work);
719void cxl_prefault(struct cxl_context *ctx, u64 wed);
720
721struct cxl *get_cxl_adapter(int num);
722int cxl_alloc_sst(struct cxl_context *ctx);
444c4ba4 723void cxl_dump_debug_buffer(void *addr, size_t size);
f204e0b8
IM		 724
725void init_cxl_native(void);
726
727struct cxl_context *cxl_context_alloc(void);
b123429e
IM		 728int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master,
729 struct address_space *mapping);
f204e0b8
IM		 730void cxl_context_free(struct cxl_context *ctx);
731int cxl_context_iomap(struct cxl_context *ctx, struct vm_area_struct *vma);
1a1a94b8
MN		 732unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq,
733 irq_handler_t handler, void *cookie, const char *name);
734void cxl_unmap_irq(unsigned int virq, void *cookie);
eda3693c 735int __detach_context(struct cxl_context *ctx);
f204e0b8 736
444c4ba4
CL		 737/*
738 * This must match the layout of the H_COLLECT_CA_INT_INFO retbuf defined
739 * in PAPR.
740 * A word about endianness: a pointer to this structure is passed when
741 * calling the hcall. However, it is not a block of memory filled up by
742 * the hypervisor. The return values are found in registers, and copied
743 * one by one when returning from the hcall. See the end of the call to
744 * plpar_hcall9() in hvCall.S
745 * As a consequence:
746 * - we don't need to do any endianness conversion
747 * - the pid and tid are an exception. They are 32-bit values returned in
748 * the same 64-bit register. So we do need to worry about byte ordering.
749 */
f204e0b8
IM		 750struct cxl_irq_info {
751 u64 dsisr;
752 u64 dar;
753 u64 dsr;
444c4ba4 754#ifndef CONFIG_CPU_LITTLE_ENDIAN
f204e0b8
IM		 755 u32 pid;
756 u32 tid;
444c4ba4
CL		 757#else
758 u32 tid;
759 u32 pid;
760#endif
f204e0b8
IM		 761 u64 afu_err;
762 u64 errstat;
444c4ba4
CL		 763 u64 proc_handle;
764 u64 padding[2]; /* to match the expected retbuf size for plpar_hcall9 */
f204e0b8
IM		 765};
766
1a1a94b8 767void cxl_assign_psn_space(struct cxl_context *ctx);
6d625ed9 768irqreturn_t cxl_irq(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
86331862
CL		 769int cxl_register_one_irq(struct cxl *adapter, irq_handler_t handler,
770 void *cookie, irq_hw_number_t *dest_hwirq,
771 unsigned int *dest_virq, const char *name);
772
f204e0b8
IM		 773int cxl_check_error(struct cxl_afu *afu);
774int cxl_afu_slbia(struct cxl_afu *afu);
775int cxl_tlb_slb_invalidate(struct cxl *adapter);
776int cxl_afu_disable(struct cxl_afu *afu);
f204e0b8
IM		 777int cxl_psl_purge(struct cxl_afu *afu);
778
779void cxl_stop_trace(struct cxl *cxl);
6f7f0b3d 780int cxl_pci_vphb_add(struct cxl_afu *afu);
9e8df8a2 781void cxl_pci_vphb_reconfigure(struct cxl_afu *afu);
6f7f0b3d 782void cxl_pci_vphb_remove(struct cxl_afu *afu);
f204e0b8
IM		 783
784extern struct pci_driver cxl_pci_driver;
c358d84b 785int afu_allocate_irqs(struct cxl_context *ctx, u32 count);
f204e0b8 786
0520336a
MN		 787int afu_open(struct inode *inode, struct file *file);
788int afu_release(struct inode *inode, struct file *file);
789long afu_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
790int afu_mmap(struct file *file, struct vm_area_struct *vm);
791unsigned int afu_poll(struct file *file, struct poll_table_struct *poll);
792ssize_t afu_read(struct file *file, char __user *buf, size_t count, loff_t *off);
793extern const struct file_operations afu_fops;
794
5be587b1
FB		 795struct cxl_backend_ops {
796 struct module *module;
797 int (*adapter_reset)(struct cxl *adapter);
798 int (*alloc_one_irq)(struct cxl *adapter);
799 void (*release_one_irq)(struct cxl *adapter, int hwirq);
800 int (*alloc_irq_ranges)(struct cxl_irq_ranges *irqs,
801 struct cxl *adapter, unsigned int num);
802 void (*release_irq_ranges)(struct cxl_irq_ranges *irqs,
803 struct cxl *adapter);
804 int (*setup_irq)(struct cxl *adapter, unsigned int hwirq,
805 unsigned int virq);
806 irqreturn_t (*handle_psl_slice_error)(struct cxl_context *ctx,
807 u64 dsisr, u64 errstat);
808 irqreturn_t (*psl_interrupt)(int irq, void *data);
809 int (*ack_irq)(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask);
810 int (*attach_process)(struct cxl_context *ctx, bool kernel,
811 u64 wed, u64 amr);
812 int (*detach_process)(struct cxl_context *ctx);
813 bool (*link_ok)(struct cxl *cxl);
814 void (*release_afu)(struct device *dev);
815 ssize_t (*afu_read_err_buffer)(struct cxl_afu *afu, char *buf,
816 loff_t off, size_t count);
817 int (*afu_check_and_enable)(struct cxl_afu *afu);
818 int (*afu_activate_mode)(struct cxl_afu *afu, int mode);
819 int (*afu_deactivate_mode)(struct cxl_afu *afu, int mode);
820 int (*afu_reset)(struct cxl_afu *afu);
821 int (*afu_cr_read8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 *val);
822 int (*afu_cr_read16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 *val);
823 int (*afu_cr_read32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 *val);
824 int (*afu_cr_read64)(struct cxl_afu *afu, int cr_idx, u64 offset, u64 *val);
825};
826extern const struct cxl_backend_ops cxl_native_ops;
827extern const struct cxl_backend_ops *cxl_ops;
828
f204e0b8 829#endif
Linux kernel - Deliverables
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