projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
cxl: Define process problem state area at attach time only
[deliverable/linux.git] / drivers / misc / cxl / pci.c
CommitLineData
f204e0b8
IM		 1/*
2 * Copyright 2014 IBM Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#include <linux/pci_regs.h>
11#include <linux/pci_ids.h>
12#include <linux/device.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/slab.h>
16#include <linux/sort.h>
17#include <linux/pci.h>
18#include <linux/of.h>
19#include <linux/delay.h>
20#include <asm/opal.h>
21#include <asm/msi_bitmap.h>
22#include <asm/pci-bridge.h> /* for struct pci_controller */
23#include <asm/pnv-pci.h>
62fa19d4 24#include <asm/io.h>
f204e0b8
IM		 25
26#include "cxl.h"
9e8df8a2 27#include <misc/cxl.h>
f204e0b8
IM		 28
29
30#define CXL_PCI_VSEC_ID 0x1280
31#define CXL_VSEC_MIN_SIZE 0x80
32
33#define CXL_READ_VSEC_LENGTH(dev, vsec, dest) \
34 { \
35 pci_read_config_word(dev, vsec + 0x6, dest); \
36 *dest >>= 4; \
37 }
38#define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \
39 pci_read_config_byte(dev, vsec + 0x8, dest)
40
41#define CXL_READ_VSEC_STATUS(dev, vsec, dest) \
42 pci_read_config_byte(dev, vsec + 0x9, dest)
43#define CXL_STATUS_SECOND_PORT 0x80
44#define CXL_STATUS_MSI_X_FULL 0x40
45#define CXL_STATUS_MSI_X_SINGLE 0x20
46#define CXL_STATUS_FLASH_RW 0x08
47#define CXL_STATUS_FLASH_RO 0x04
48#define CXL_STATUS_LOADABLE_AFU 0x02
49#define CXL_STATUS_LOADABLE_PSL 0x01
50/* If we see these features we won't try to use the card */
51#define CXL_UNSUPPORTED_FEATURES \
52 (CXL_STATUS_MSI_X_FULL | CXL_STATUS_MSI_X_SINGLE)
53
54#define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \
55 pci_read_config_byte(dev, vsec + 0xa, dest)
56#define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \
57 pci_write_config_byte(dev, vsec + 0xa, val)
58#define CXL_VSEC_PROTOCOL_MASK 0xe0
59#define CXL_VSEC_PROTOCOL_1024TB 0x80
60#define CXL_VSEC_PROTOCOL_512TB 0x40
61#define CXL_VSEC_PROTOCOL_256TB 0x20 /* Power 8 uses this */
62#define CXL_VSEC_PROTOCOL_ENABLE 0x01
63
64#define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \
65 pci_read_config_word(dev, vsec + 0xc, dest)
66#define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \
67 pci_read_config_byte(dev, vsec + 0xe, dest)
68#define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \
69 pci_read_config_byte(dev, vsec + 0xf, dest)
70#define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \
71 pci_read_config_word(dev, vsec + 0x10, dest)
72
73#define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \
74 pci_read_config_byte(dev, vsec + 0x13, dest)
75#define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \
76 pci_write_config_byte(dev, vsec + 0x13, val)
77#define CXL_VSEC_USER_IMAGE_LOADED 0x80 /* RO */
78#define CXL_VSEC_PERST_LOADS_IMAGE 0x20 /* RW */
79#define CXL_VSEC_PERST_SELECT_USER 0x10 /* RW */
80
81#define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \
82 pci_read_config_dword(dev, vsec + 0x20, dest)
83#define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \
84 pci_read_config_dword(dev, vsec + 0x24, dest)
85#define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \
86 pci_read_config_dword(dev, vsec + 0x28, dest)
87#define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \
88 pci_read_config_dword(dev, vsec + 0x2c, dest)
89
90
91/* This works a little different than the p1/p2 register accesses to make it
92 * easier to pull out individual fields */
93#define AFUD_READ(afu, off) in_be64(afu->afu_desc_mmio + off)
bfcdc8ff 94#define AFUD_READ_LE(afu, off) in_le64(afu->afu_desc_mmio + off)
f204e0b8
IM		 95#define EXTRACT_PPC_BIT(val, bit) (!!(val & PPC_BIT(bit)))
96#define EXTRACT_PPC_BITS(val, bs, be) ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be))
97
98#define AFUD_READ_INFO(afu) AFUD_READ(afu, 0x0)
99#define AFUD_NUM_INTS_PER_PROC(val) EXTRACT_PPC_BITS(val, 0, 15)
100#define AFUD_NUM_PROCS(val) EXTRACT_PPC_BITS(val, 16, 31)
101#define AFUD_NUM_CRS(val) EXTRACT_PPC_BITS(val, 32, 47)
102#define AFUD_MULTIMODE(val) EXTRACT_PPC_BIT(val, 48)
103#define AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55)
104#define AFUD_DEDICATED_PROCESS(val) EXTRACT_PPC_BIT(val, 59)
105#define AFUD_AFU_DIRECTED(val) EXTRACT_PPC_BIT(val, 61)
106#define AFUD_TIME_SLICED(val) EXTRACT_PPC_BIT(val, 63)
107#define AFUD_READ_CR(afu) AFUD_READ(afu, 0x20)
108#define AFUD_CR_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
109#define AFUD_READ_CR_OFF(afu) AFUD_READ(afu, 0x28)
110#define AFUD_READ_PPPSA(afu) AFUD_READ(afu, 0x30)
111#define AFUD_PPPSA_PP(val) EXTRACT_PPC_BIT(val, 6)
112#define AFUD_PPPSA_PSA(val) EXTRACT_PPC_BIT(val, 7)
113#define AFUD_PPPSA_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
114#define AFUD_READ_PPPSA_OFF(afu) AFUD_READ(afu, 0x38)
115#define AFUD_READ_EB(afu) AFUD_READ(afu, 0x40)
116#define AFUD_EB_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
117#define AFUD_READ_EB_OFF(afu) AFUD_READ(afu, 0x48)
118
f47f966f 119static const struct pci_device_id cxl_pci_tbl[] = {
f204e0b8
IM		 120 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), },
121 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), },
122 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), },
68adb7bf 123 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0601), },
f204e0b8
IM		 124 { PCI_DEVICE_CLASS(0x120000, ~0), },
125
126 { }
127};
128MODULE_DEVICE_TABLE(pci, cxl_pci_tbl);
129
130
131/*
132 * Mostly using these wrappers to avoid confusion:
133 * priv 1 is BAR2, while priv 2 is BAR0
134 */
135static inline resource_size_t p1_base(struct pci_dev *dev)
136{
137 return pci_resource_start(dev, 2);
138}
139
140static inline resource_size_t p1_size(struct pci_dev *dev)
141{
142 return pci_resource_len(dev, 2);
143}
144
145static inline resource_size_t p2_base(struct pci_dev *dev)
146{
147 return pci_resource_start(dev, 0);
148}
149
150static inline resource_size_t p2_size(struct pci_dev *dev)
151{
152 return pci_resource_len(dev, 0);
153}
154
155static int find_cxl_vsec(struct pci_dev *dev)
156{
157 int vsec = 0;
158 u16 val;
159
160 while ((vsec = pci_find_next_ext_capability(dev, vsec, PCI_EXT_CAP_ID_VNDR))) {
161 pci_read_config_word(dev, vsec + 0x4, &val);
162 if (val == CXL_PCI_VSEC_ID)
163 return vsec;
164 }
165 return 0;
166
167}
168
169static void dump_cxl_config_space(struct pci_dev *dev)
170{
171 int vsec;
172 u32 val;
173
174 dev_info(&dev->dev, "dump_cxl_config_space\n");
175
176 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val);
177 dev_info(&dev->dev, "BAR0: %#.8x\n", val);
178 pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val);
179 dev_info(&dev->dev, "BAR1: %#.8x\n", val);
180 pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val);
181 dev_info(&dev->dev, "BAR2: %#.8x\n", val);
182 pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val);
183 dev_info(&dev->dev, "BAR3: %#.8x\n", val);
184 pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val);
185 dev_info(&dev->dev, "BAR4: %#.8x\n", val);
186 pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val);
187 dev_info(&dev->dev, "BAR5: %#.8x\n", val);
188
189 dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n",
190 p1_base(dev), p1_size(dev));
191 dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n",
f2931069 192 p2_base(dev), p2_size(dev));
f204e0b8
IM		 193 dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n",
194 pci_resource_start(dev, 4), pci_resource_len(dev, 4));
195
196 if (!(vsec = find_cxl_vsec(dev)))
197 return;
198
199#define show_reg(name, what) \
200 dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what)
201
202 pci_read_config_dword(dev, vsec + 0x0, &val);
203 show_reg("Cap ID", (val >> 0) & 0xffff);
204 show_reg("Cap Ver", (val >> 16) & 0xf);
205 show_reg("Next Cap Ptr", (val >> 20) & 0xfff);
206 pci_read_config_dword(dev, vsec + 0x4, &val);
207 show_reg("VSEC ID", (val >> 0) & 0xffff);
208 show_reg("VSEC Rev", (val >> 16) & 0xf);
209 show_reg("VSEC Length", (val >> 20) & 0xfff);
210 pci_read_config_dword(dev, vsec + 0x8, &val);
211 show_reg("Num AFUs", (val >> 0) & 0xff);
212 show_reg("Status", (val >> 8) & 0xff);
213 show_reg("Mode Control", (val >> 16) & 0xff);
214 show_reg("Reserved", (val >> 24) & 0xff);
215 pci_read_config_dword(dev, vsec + 0xc, &val);
216 show_reg("PSL Rev", (val >> 0) & 0xffff);
217 show_reg("CAIA Ver", (val >> 16) & 0xffff);
218 pci_read_config_dword(dev, vsec + 0x10, &val);
219 show_reg("Base Image Rev", (val >> 0) & 0xffff);
220 show_reg("Reserved", (val >> 16) & 0x0fff);
221 show_reg("Image Control", (val >> 28) & 0x3);
222 show_reg("Reserved", (val >> 30) & 0x1);
223 show_reg("Image Loaded", (val >> 31) & 0x1);
224
225 pci_read_config_dword(dev, vsec + 0x14, &val);
226 show_reg("Reserved", val);
227 pci_read_config_dword(dev, vsec + 0x18, &val);
228 show_reg("Reserved", val);
229 pci_read_config_dword(dev, vsec + 0x1c, &val);
230 show_reg("Reserved", val);
231
232 pci_read_config_dword(dev, vsec + 0x20, &val);
233 show_reg("AFU Descriptor Offset", val);
234 pci_read_config_dword(dev, vsec + 0x24, &val);
235 show_reg("AFU Descriptor Size", val);
236 pci_read_config_dword(dev, vsec + 0x28, &val);
237 show_reg("Problem State Offset", val);
238 pci_read_config_dword(dev, vsec + 0x2c, &val);
239 show_reg("Problem State Size", val);
240
241 pci_read_config_dword(dev, vsec + 0x30, &val);
242 show_reg("Reserved", val);
243 pci_read_config_dword(dev, vsec + 0x34, &val);
244 show_reg("Reserved", val);
245 pci_read_config_dword(dev, vsec + 0x38, &val);
246 show_reg("Reserved", val);
247 pci_read_config_dword(dev, vsec + 0x3c, &val);
248 show_reg("Reserved", val);
249
250 pci_read_config_dword(dev, vsec + 0x40, &val);
251 show_reg("PSL Programming Port", val);
252 pci_read_config_dword(dev, vsec + 0x44, &val);
253 show_reg("PSL Programming Control", val);
254
255 pci_read_config_dword(dev, vsec + 0x48, &val);
256 show_reg("Reserved", val);
257 pci_read_config_dword(dev, vsec + 0x4c, &val);
258 show_reg("Reserved", val);
259
260 pci_read_config_dword(dev, vsec + 0x50, &val);
261 show_reg("Flash Address Register", val);
262 pci_read_config_dword(dev, vsec + 0x54, &val);
263 show_reg("Flash Size Register", val);
264 pci_read_config_dword(dev, vsec + 0x58, &val);
265 show_reg("Flash Status/Control Register", val);
266 pci_read_config_dword(dev, vsec + 0x58, &val);
267 show_reg("Flash Data Port", val);
268
269#undef show_reg
270}
271
272static void dump_afu_descriptor(struct cxl_afu *afu)
273{
bfcdc8ff
MN		 274 u64 val, afu_cr_num, afu_cr_off, afu_cr_len;
275 int i;
f204e0b8
IM		 276
277#define show_reg(name, what) \
278 dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what)
279
280 val = AFUD_READ_INFO(afu);
281 show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val));
282 show_reg("num_of_processes", AFUD_NUM_PROCS(val));
283 show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val));
284 show_reg("req_prog_mode", val & 0xffffULL);
bfcdc8ff 285 afu_cr_num = AFUD_NUM_CRS(val);
f204e0b8
IM		 286
287 val = AFUD_READ(afu, 0x8);
288 show_reg("Reserved", val);
289 val = AFUD_READ(afu, 0x10);
290 show_reg("Reserved", val);
291 val = AFUD_READ(afu, 0x18);
292 show_reg("Reserved", val);
293
294 val = AFUD_READ_CR(afu);
295 show_reg("Reserved", (val >> (63-7)) & 0xff);
296 show_reg("AFU_CR_len", AFUD_CR_LEN(val));
bfcdc8ff 297 afu_cr_len = AFUD_CR_LEN(val) * 256;
f204e0b8
IM		 298
299 val = AFUD_READ_CR_OFF(afu);
bfcdc8ff 300 afu_cr_off = val;
f204e0b8
IM		 301 show_reg("AFU_CR_offset", val);
302
303 val = AFUD_READ_PPPSA(afu);
304 show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff);
305 show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val));
306
307 val = AFUD_READ_PPPSA_OFF(afu);
308 show_reg("PerProcessPSA_offset", val);
309
310 val = AFUD_READ_EB(afu);
311 show_reg("Reserved", (val >> (63-7)) & 0xff);
312 show_reg("AFU_EB_len", AFUD_EB_LEN(val));
313
314 val = AFUD_READ_EB_OFF(afu);
315 show_reg("AFU_EB_offset", val);
316
bfcdc8ff
MN		 317 for (i = 0; i < afu_cr_num; i++) {
318 val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len);
319 show_reg("CR Vendor", val & 0xffff);
320 show_reg("CR Device", (val >> 16) & 0xffff);
321 }
f204e0b8
IM		 322#undef show_reg
323}
324
325static int init_implementation_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
326{
327 struct device_node *np;
328 const __be32 *prop;
329 u64 psl_dsnctl;
330 u64 chipid;
331
6f963ec2 332 if (!(np = pnv_pci_get_phb_node(dev)))
f204e0b8
IM		 333 return -ENODEV;
334
335 while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL)))
336 np = of_get_next_parent(np);
337 if (!np)
338 return -ENODEV;
339 chipid = be32_to_cpup(prop);
340 of_node_put(np);
341
342 /* Tell PSL where to route data to */
343 psl_dsnctl = 0x02E8900002000000ULL | (chipid << (63-5));
344 cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl);
345 cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL);
346 /* snoop write mask */
347 cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL);
348 /* set fir_accum */
349 cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, 0x0800000000000000ULL);
350 /* for debugging with trace arrays */
351 cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL);
352
353 return 0;
354}
355
390fd592
PB		 356#define TBSYNC_CNT(n) (((u64)n & 0x7) << (63-6))
357#define _2048_250MHZ_CYCLES 1
358
359static int cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)
360{
361 u64 psl_tb;
362 int delta;
363 unsigned int retry = 0;
364 struct device_node *np;
365
366 if (!(np = pnv_pci_get_phb_node(dev)))
367 return -ENODEV;
368
369 /* Do not fail when CAPP timebase sync is not supported by OPAL */
370 of_node_get(np);
371 if (! of_get_property(np, "ibm,capp-timebase-sync", NULL)) {
372 of_node_put(np);
373 pr_err("PSL: Timebase sync: OPAL support missing\n");
374 return 0;
375 }
376 of_node_put(np);
377
378 /*
379 * Setup PSL Timebase Control and Status register
380 * with the recommended Timebase Sync Count value
381 */
382 cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT,
383 TBSYNC_CNT(2 * _2048_250MHZ_CYCLES));
384
385 /* Enable PSL Timebase */
386 cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000);
387 cxl_p1_write(adapter, CXL_PSL_Control, CXL_PSL_Control_tb);
388
389 /* Wait until CORE TB and PSL TB difference <= 16usecs */
390 do {
391 msleep(1);
392 if (retry++ > 5) {
393 pr_err("PSL: Timebase sync: giving up!\n");
394 return -EIO;
395 }
396 psl_tb = cxl_p1_read(adapter, CXL_PSL_Timebase);
397 delta = mftb() - psl_tb;
398 if (delta < 0)
399 delta = -delta;
400 } while (cputime_to_usecs(delta) > 16);
401
402 return 0;
403}
404
f204e0b8
IM		 405static int init_implementation_afu_regs(struct cxl_afu *afu)
406{
407 /* read/write masks for this slice */
408 cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL);
409 /* APC read/write masks for this slice */
410 cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL);
411 /* for debugging with trace arrays */
412 cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL);
d6a6af2c 413 cxl_p1n_write(afu, CXL_PSL_RXCTL_A, CXL_PSL_RXCTL_AFUHP_4S);
f204e0b8
IM		 414
415 return 0;
416}
417
418int cxl_setup_irq(struct cxl *adapter, unsigned int hwirq,
419 unsigned int virq)
420{
421 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
422
423 return pnv_cxl_ioda_msi_setup(dev, hwirq, virq);
424}
425
4beb5421
RG		 426int cxl_update_image_control(struct cxl *adapter)
427{
428 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
429 int rc;
430 int vsec;
431 u8 image_state;
432
433 if (!(vsec = find_cxl_vsec(dev))) {
434 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
435 return -ENODEV;
436 }
437
438 if ((rc = CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state))) {
439 dev_err(&dev->dev, "failed to read image state: %i\n", rc);
440 return rc;
441 }
442
443 if (adapter->perst_loads_image)
444 image_state |= CXL_VSEC_PERST_LOADS_IMAGE;
445 else
446 image_state &= ~CXL_VSEC_PERST_LOADS_IMAGE;
447
448 if (adapter->perst_select_user)
449 image_state |= CXL_VSEC_PERST_SELECT_USER;
450 else
451 image_state &= ~CXL_VSEC_PERST_SELECT_USER;
452
453 if ((rc = CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, image_state))) {
454 dev_err(&dev->dev, "failed to update image control: %i\n", rc);
455 return rc;
456 }
457
458 return 0;
459}
460
f204e0b8
IM		 461int cxl_alloc_one_irq(struct cxl *adapter)
462{
463 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
464
465 return pnv_cxl_alloc_hwirqs(dev, 1);
466}
467
468void cxl_release_one_irq(struct cxl *adapter, int hwirq)
469{
470 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
471
472 return pnv_cxl_release_hwirqs(dev, hwirq, 1);
473}
474
475int cxl_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num)
476{
477 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
478
479 return pnv_cxl_alloc_hwirq_ranges(irqs, dev, num);
480}
481
482void cxl_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter)
483{
484 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
485
486 pnv_cxl_release_hwirq_ranges(irqs, dev);
487}
488
489static int setup_cxl_bars(struct pci_dev *dev)
490{
491 /* Safety check in case we get backported to < 3.17 without M64 */
492 if ((p1_base(dev) < 0x100000000ULL) ||
493 (p2_base(dev) < 0x100000000ULL)) {
494 dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n");
495 return -ENODEV;
496 }
497
498 /*
499 * BAR 4/5 has a special meaning for CXL and must be programmed with a
500 * special value corresponding to the CXL protocol address range.
501 * For POWER 8 that means bits 48:49 must be set to 10
502 */
503 pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0x00000000);
504 pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0x00020000);
505
506 return 0;
507}
508
509/* pciex node: ibm,opal-m64-window = <0x3d058 0x0 0x3d058 0x0 0x8 0x0>; */
510static int switch_card_to_cxl(struct pci_dev *dev)
511{
512 int vsec;
513 u8 val;
514 int rc;
515
516 dev_info(&dev->dev, "switch card to CXL\n");
517
518 if (!(vsec = find_cxl_vsec(dev))) {
519 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
520 return -ENODEV;
521 }
522
523 if ((rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val))) {
524 dev_err(&dev->dev, "failed to read current mode control: %i", rc);
525 return rc;
526 }
527 val &= ~CXL_VSEC_PROTOCOL_MASK;
528 val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE;
529 if ((rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val))) {
530 dev_err(&dev->dev, "failed to enable CXL protocol: %i", rc);
531 return rc;
532 }
533 /*
534 * The CAIA spec (v0.12 11.6 Bi-modal Device Support) states
535 * we must wait 100ms after this mode switch before touching
536 * PCIe config space.
537 */
538 msleep(100);
539
540 return 0;
541}
542
543static int cxl_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
544{
545 u64 p1n_base, p2n_base, afu_desc;
546 const u64 p1n_size = 0x100;
547 const u64 p2n_size = 0x1000;
548
549 p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size);
550 p2n_base = p2_base(dev) + (afu->slice * p2n_size);
551 afu->psn_phys = p2_base(dev) + (adapter->ps_off + (afu->slice * adapter->ps_size));
552 afu_desc = p2_base(dev) + adapter->afu_desc_off + (afu->slice * adapter->afu_desc_size);
553
554 if (!(afu->p1n_mmio = ioremap(p1n_base, p1n_size)))
555 goto err;
556 if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size)))
557 goto err1;
558 if (afu_desc) {
559 if (!(afu->afu_desc_mmio = ioremap(afu_desc, adapter->afu_desc_size)))
560 goto err2;
561 }
562
563 return 0;
564err2:
565 iounmap(afu->p2n_mmio);
566err1:
567 iounmap(afu->p1n_mmio);
568err:
569 dev_err(&afu->dev, "Error mapping AFU MMIO regions\n");
570 return -ENOMEM;
571}
572
573static void cxl_unmap_slice_regs(struct cxl_afu *afu)
574{
575e6986 575 if (afu->p2n_mmio) {
f204e0b8 576 iounmap(afu->p2n_mmio);
575e6986
DA		 577 afu->p2n_mmio = NULL;
578 }
579 if (afu->p1n_mmio) {
f204e0b8 580 iounmap(afu->p1n_mmio);
575e6986
DA		 581 afu->p1n_mmio = NULL;
582 }
583 if (afu->afu_desc_mmio) {
584 iounmap(afu->afu_desc_mmio);
585 afu->afu_desc_mmio = NULL;
586 }
f204e0b8
IM		 587}
588
86331862 589void cxl_release_afu(struct device *dev)
f204e0b8
IM		 590{
591 struct cxl_afu *afu = to_cxl_afu(dev);
592
593 pr_devel("cxl_release_afu\n");
594
bd664f89 595 idr_destroy(&afu->contexts_idr);
05155772
DA		 596 cxl_release_spa(afu);
597
f204e0b8
IM		 598 kfree(afu);
599}
600
f204e0b8
IM		 601/* Expects AFU struct to have recently been zeroed out */
602static int cxl_read_afu_descriptor(struct cxl_afu *afu)
603{
604 u64 val;
605
606 val = AFUD_READ_INFO(afu);
607 afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val);
608 afu->max_procs_virtualised = AFUD_NUM_PROCS(val);
b087e619 609 afu->crs_num = AFUD_NUM_CRS(val);
f204e0b8
IM		 610
611 if (AFUD_AFU_DIRECTED(val))
612 afu->modes_supported |= CXL_MODE_DIRECTED;
613 if (AFUD_DEDICATED_PROCESS(val))
614 afu->modes_supported |= CXL_MODE_DEDICATED;
615 if (AFUD_TIME_SLICED(val))
616 afu->modes_supported |= CXL_MODE_TIME_SLICED;
617
618 val = AFUD_READ_PPPSA(afu);
619 afu->pp_size = AFUD_PPPSA_LEN(val) * 4096;
620 afu->psa = AFUD_PPPSA_PSA(val);
621 if ((afu->pp_psa = AFUD_PPPSA_PP(val)))
622 afu->pp_offset = AFUD_READ_PPPSA_OFF(afu);
623
b087e619
IM		 624 val = AFUD_READ_CR(afu);
625 afu->crs_len = AFUD_CR_LEN(val) * 256;
626 afu->crs_offset = AFUD_READ_CR_OFF(afu);
627
e36f6fe1
VJ		 628
629 /* eb_len is in multiple of 4K */
630 afu->eb_len = AFUD_EB_LEN(AFUD_READ_EB(afu)) * 4096;
631 afu->eb_offset = AFUD_READ_EB_OFF(afu);
632
633 /* eb_off is 4K aligned so lower 12 bits are always zero */
634 if (EXTRACT_PPC_BITS(afu->eb_offset, 0, 11) != 0) {
635 dev_warn(&afu->dev,
636 "Invalid AFU error buffer offset %Lx\n",
637 afu->eb_offset);
638 dev_info(&afu->dev,
639 "Ignoring AFU error buffer in the descriptor\n");
640 /* indicate that no afu buffer exists */
641 afu->eb_len = 0;
642 }
643
f204e0b8
IM		 644 return 0;
645}
646
647static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu)
648{
3d5be039
IM		 649 int i;
650
f204e0b8
IM		 651 if (afu->psa && afu->adapter->ps_size <
652 (afu->pp_offset + afu->pp_size*afu->max_procs_virtualised)) {
653 dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n");
654 return -ENODEV;
655 }
656
657 if (afu->pp_psa && (afu->pp_size < PAGE_SIZE))
658 dev_warn(&afu->dev, "AFU uses < PAGE_SIZE per-process PSA!");
659
3d5be039
IM		 660 for (i = 0; i < afu->crs_num; i++) {
661 if ((cxl_afu_cr_read32(afu, i, 0) == 0)) {
662 dev_err(&afu->dev, "ABORTING: AFU configuration record %i is invalid\n", i);
663 return -EINVAL;
664 }
665 }
666
f204e0b8
IM		 667 return 0;
668}
669
670static int sanitise_afu_regs(struct cxl_afu *afu)
671{
672 u64 reg;
673
674 /*
675 * Clear out any regs that contain either an IVTE or address or may be
676 * waiting on an acknowledgement to try to be a bit safer as we bring
677 * it online
678 */
679 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
680 if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
de369538 681 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
b12994fb 682 if (__cxl_afu_reset(afu))
f204e0b8
IM		 683 return -EIO;
684 if (cxl_afu_disable(afu))
685 return -EIO;
686 if (cxl_psl_purge(afu))
687 return -EIO;
688 }
689 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
690 cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000);
691 cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000);
692 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
693 cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000);
694 cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000);
695 cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000);
696 cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000);
697 cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000);
698 cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000);
699 cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000);
700 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
701 if (reg) {
de369538 702 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
f204e0b8
IM		 703 if (reg & CXL_PSL_DSISR_TRANS)
704 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
705 else
706 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
707 }
708 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
709 if (reg) {
710 if (reg & ~0xffff)
de369538 711 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
f204e0b8
IM		 712 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
713 }
714 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
715 if (reg) {
de369538 716 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
f204e0b8
IM		 717 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
718 }
719
720 return 0;
721}
722
e36f6fe1
VJ		 723#define ERR_BUFF_MAX_COPY_SIZE PAGE_SIZE
724/*
725 * afu_eb_read:
726 * Called from sysfs and reads the afu error info buffer. The h/w only supports
727 * 4/8 bytes aligned access. So in case the requested offset/count arent 8 byte
728 * aligned the function uses a bounce buffer which can be max PAGE_SIZE.
729 */
730ssize_t cxl_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
731 loff_t off, size_t count)
732{
733 loff_t aligned_start, aligned_end;
734 size_t aligned_length;
735 void *tbuf;
736 const void __iomem *ebuf = afu->afu_desc_mmio + afu->eb_offset;
737
738 if (count == 0 || off < 0 || (size_t)off >= afu->eb_len)
739 return 0;
740
741 /* calculate aligned read window */
742 count = min((size_t)(afu->eb_len - off), count);
743 aligned_start = round_down(off, 8);
744 aligned_end = round_up(off + count, 8);
745 aligned_length = aligned_end - aligned_start;
746
747 /* max we can copy in one read is PAGE_SIZE */
748 if (aligned_length > ERR_BUFF_MAX_COPY_SIZE) {
749 aligned_length = ERR_BUFF_MAX_COPY_SIZE;
750 count = ERR_BUFF_MAX_COPY_SIZE - (off & 0x7);
751 }
752
753 /* use bounce buffer for copy */
754 tbuf = (void *)__get_free_page(GFP_TEMPORARY);
755 if (!tbuf)
756 return -ENOMEM;
757
758 /* perform aligned read from the mmio region */
759 memcpy_fromio(tbuf, ebuf + aligned_start, aligned_length);
760 memcpy(buf, tbuf + (off & 0x7), count);
761
762 free_page((unsigned long)tbuf);
763
764 return count;
765}
766
d76427b0 767static int cxl_configure_afu(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
f204e0b8 768{
f204e0b8
IM		 769 int rc;
770
f204e0b8 771 if ((rc = cxl_map_slice_regs(afu, adapter, dev)))
d76427b0 772 return rc;
f204e0b8
IM		 773
774 if ((rc = sanitise_afu_regs(afu)))
d76427b0 775 goto err1;
f204e0b8
IM		 776
777 /* We need to reset the AFU before we can read the AFU descriptor */
b12994fb 778 if ((rc = __cxl_afu_reset(afu)))
d76427b0 779 goto err1;
f204e0b8
IM		 780
781 if (cxl_verbose)
782 dump_afu_descriptor(afu);
783
784 if ((rc = cxl_read_afu_descriptor(afu)))
d76427b0 785 goto err1;
f204e0b8
IM		 786
787 if ((rc = cxl_afu_descriptor_looks_ok(afu)))
d76427b0 788 goto err1;
f204e0b8
IM		 789
790 if ((rc = init_implementation_afu_regs(afu)))
d76427b0 791 goto err1;
f204e0b8
IM		 792
793 if ((rc = cxl_register_serr_irq(afu)))
d76427b0 794 goto err1;
f204e0b8
IM		 795
796 if ((rc = cxl_register_psl_irq(afu)))
d76427b0
DA		 797 goto err2;
798
799 return 0;
800
801err2:
802 cxl_release_serr_irq(afu);
803err1:
804 cxl_unmap_slice_regs(afu);
805 return rc;
806}
807
808static void cxl_deconfigure_afu(struct cxl_afu *afu)
809{
810 cxl_release_psl_irq(afu);
811 cxl_release_serr_irq(afu);
812 cxl_unmap_slice_regs(afu);
813}
814
815static int cxl_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev)
816{
817 struct cxl_afu *afu;
818 int rc;
819
820 afu = cxl_alloc_afu(adapter, slice);
821 if (!afu)
822 return -ENOMEM;
823
824 rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice);
825 if (rc)
826 goto err_free;
827
828 rc = cxl_configure_afu(afu, adapter, dev);
829 if (rc)
830 goto err_free;
f204e0b8
IM		 831
832 /* Don't care if this fails */
833 cxl_debugfs_afu_add(afu);
834
835 /*
836 * After we call this function we must not free the afu directly, even
837 * if it returns an error!
838 */
839 if ((rc = cxl_register_afu(afu)))
840 goto err_put1;
841
842 if ((rc = cxl_sysfs_afu_add(afu)))
843 goto err_put1;
844
f204e0b8
IM		 845 adapter->afu[afu->slice] = afu;
846
6f7f0b3d
MN		 847 if ((rc = cxl_pci_vphb_add(afu)))
848 dev_info(&afu->dev, "Can't register vPHB\n");
849
f204e0b8
IM		 850 return 0;
851
f204e0b8 852err_put1:
d76427b0 853 cxl_deconfigure_afu(afu);
f204e0b8 854 cxl_debugfs_afu_remove(afu);
d76427b0 855 device_unregister(&afu->dev);
f204e0b8 856 return rc;
d76427b0
DA		 857
858err_free:
859 kfree(afu);
860 return rc;
861
f204e0b8
IM		 862}
863
864static void cxl_remove_afu(struct cxl_afu *afu)
865{
866 pr_devel("cxl_remove_afu\n");
867
868 if (!afu)
869 return;
870
871 cxl_sysfs_afu_remove(afu);
872 cxl_debugfs_afu_remove(afu);
873
874 spin_lock(&afu->adapter->afu_list_lock);
875 afu->adapter->afu[afu->slice] = NULL;
876 spin_unlock(&afu->adapter->afu_list_lock);
877
878 cxl_context_detach_all(afu);
879 cxl_afu_deactivate_mode(afu);
880
d76427b0 881 cxl_deconfigure_afu(afu);
f204e0b8
IM		 882 device_unregister(&afu->dev);
883}
884
62fa19d4
RG		 885int cxl_reset(struct cxl *adapter)
886{
887 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
888 int rc;
62fa19d4 889
13e68d8b
DA		 890 if (adapter->perst_same_image) {
891 dev_warn(&dev->dev,
892 "cxl: refusing to reset/reflash when perst_reloads_same_image is set.\n");
893 return -EINVAL;
894 }
895
62fa19d4
RG		 896 dev_info(&dev->dev, "CXL reset\n");
897
62fa19d4
RG		 898 /* pcie_warm_reset requests a fundamental pci reset which includes a
899 * PERST assert/deassert. PERST triggers a loading of the image
900 * if "user" or "factory" is selected in sysfs */
901 if ((rc = pci_set_pcie_reset_state(dev, pcie_warm_reset))) {
902 dev_err(&dev->dev, "cxl: pcie_warm_reset failed\n");
903 return rc;
904 }
905
62fa19d4
RG		 906 return rc;
907}
f204e0b8
IM		 908
909static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
910{
911 if (pci_request_region(dev, 2, "priv 2 regs"))
912 goto err1;
913 if (pci_request_region(dev, 0, "priv 1 regs"))
914 goto err2;
915
de369538 916 pr_devel("cxl_map_adapter_regs: p1: %#016llx %#llx, p2: %#016llx %#llx",
f204e0b8
IM		 917 p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev));
918
919 if (!(adapter->p1_mmio = ioremap(p1_base(dev), p1_size(dev))))
920 goto err3;
921
922 if (!(adapter->p2_mmio = ioremap(p2_base(dev), p2_size(dev))))
923 goto err4;
924
925 return 0;
926
927err4:
928 iounmap(adapter->p1_mmio);
929 adapter->p1_mmio = NULL;
930err3:
931 pci_release_region(dev, 0);
932err2:
933 pci_release_region(dev, 2);
934err1:
935 return -ENOMEM;
936}
937
938static void cxl_unmap_adapter_regs(struct cxl *adapter)
939{
575e6986 940 if (adapter->p1_mmio) {
f204e0b8 941 iounmap(adapter->p1_mmio);
575e6986
DA		 942 adapter->p1_mmio = NULL;
943 pci_release_region(to_pci_dev(adapter->dev.parent), 2);
944 }
945 if (adapter->p2_mmio) {
f204e0b8 946 iounmap(adapter->p2_mmio);
575e6986
DA		 947 adapter->p2_mmio = NULL;
948 pci_release_region(to_pci_dev(adapter->dev.parent), 0);
949 }
f204e0b8
IM		 950}
951
952static int cxl_read_vsec(struct cxl *adapter, struct pci_dev *dev)
953{
954 int vsec;
955 u32 afu_desc_off, afu_desc_size;
956 u32 ps_off, ps_size;
957 u16 vseclen;
958 u8 image_state;
959
960 if (!(vsec = find_cxl_vsec(dev))) {
bee30c70 961 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
f204e0b8
IM		 962 return -ENODEV;
963 }
964
965 CXL_READ_VSEC_LENGTH(dev, vsec, &vseclen);
966 if (vseclen < CXL_VSEC_MIN_SIZE) {
bee30c70 967 dev_err(&dev->dev, "ABORTING: CXL VSEC too short\n");
f204e0b8
IM		 968 return -EINVAL;
969 }
970
971 CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status);
972 CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev);
973 CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major);
974 CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor);
975 CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image);
976 CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state);
977 adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
4beb5421 978 adapter->perst_select_user = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
f204e0b8
IM		 979
980 CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices);
981 CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, &afu_desc_off);
982 CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, &afu_desc_size);
983 CXL_READ_VSEC_PS_OFF(dev, vsec, &ps_off);
984 CXL_READ_VSEC_PS_SIZE(dev, vsec, &ps_size);
985
986 /* Convert everything to bytes, because there is NO WAY I'd look at the
987 * code a month later and forget what units these are in ;-) */
988 adapter->ps_off = ps_off * 64 * 1024;
989 adapter->ps_size = ps_size * 64 * 1024;
990 adapter->afu_desc_off = afu_desc_off * 64 * 1024;
991 adapter->afu_desc_size = afu_desc_size *64 * 1024;
992
993 /* Total IRQs - 1 PSL ERROR - #AFU*(1 slice error + 1 DSI) */
994 adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices;
995
996 return 0;
997}
998
d79e6801
PB		 999/*
1000 * Workaround a PCIe Host Bridge defect on some cards, that can cause
1001 * malformed Transaction Layer Packet (TLP) errors to be erroneously
1002 * reported. Mask this error in the Uncorrectable Error Mask Register.
1003 *
1004 * The upper nibble of the PSL revision is used to distinguish between
1005 * different cards. The affected ones have it set to 0.
1006 */
1007static void cxl_fixup_malformed_tlp(struct cxl *adapter, struct pci_dev *dev)
1008{
1009 int aer;
1010 u32 data;
1011
1012 if (adapter->psl_rev & 0xf000)
1013 return;
1014 if (!(aer = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR)))
1015 return;
1016 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &data);
1017 if (data & PCI_ERR_UNC_MALF_TLP)
1018 if (data & PCI_ERR_UNC_INTN)
1019 return;
1020 data |= PCI_ERR_UNC_MALF_TLP;
1021 data |= PCI_ERR_UNC_INTN;
1022 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, data);
1023}
1024
f204e0b8
IM		 1025static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev)
1026{
1027 if (adapter->vsec_status & CXL_STATUS_SECOND_PORT)
1028 return -EBUSY;
1029
1030 if (adapter->vsec_status & CXL_UNSUPPORTED_FEATURES) {
bee30c70 1031 dev_err(&dev->dev, "ABORTING: CXL requires unsupported features\n");
f204e0b8
IM		 1032 return -EINVAL;
1033 }
1034
1035 if (!adapter->slices) {
1036 /* Once we support dynamic reprogramming we can use the card if
1037 * it supports loadable AFUs */
bee30c70 1038 dev_err(&dev->dev, "ABORTING: Device has no AFUs\n");
f204e0b8
IM		 1039 return -EINVAL;
1040 }
1041
1042 if (!adapter->afu_desc_off || !adapter->afu_desc_size) {
bee30c70 1043 dev_err(&dev->dev, "ABORTING: VSEC shows no AFU descriptors\n");
f204e0b8
IM		 1044 return -EINVAL;
1045 }
1046
1047 if (adapter->ps_size > p2_size(dev) - adapter->ps_off) {
bee30c70 1048 dev_err(&dev->dev, "ABORTING: Problem state size larger than "
f204e0b8
IM		 1049 "available in BAR2: 0x%llx > 0x%llx\n",
1050 adapter->ps_size, p2_size(dev) - adapter->ps_off);
1051 return -EINVAL;
1052 }
1053
1054 return 0;
1055}
1056
1057static void cxl_release_adapter(struct device *dev)
1058{
1059 struct cxl *adapter = to_cxl_adapter(dev);
1060
1061 pr_devel("cxl_release_adapter\n");
1062
c044c415
DA		 1063 cxl_remove_adapter_nr(adapter);
1064
f204e0b8
IM		 1065 kfree(adapter);
1066}
1067
390fd592
PB		 1068#define CXL_PSL_ErrIVTE_tberror (0x1ull << (63-31))
1069
f204e0b8
IM		 1070static int sanitise_adapter_regs(struct cxl *adapter)
1071{
390fd592
PB		 1072 /* Clear PSL tberror bit by writing 1 to it */
1073 cxl_p1_write(adapter, CXL_PSL_ErrIVTE, CXL_PSL_ErrIVTE_tberror);
f204e0b8
IM		 1074 return cxl_tlb_slb_invalidate(adapter);
1075}
1076
c044c415
DA		 1077/* This should contain *only* operations that can safely be done in
1078 * both creation and recovery.
1079 */
1080static int cxl_configure_adapter(struct cxl *adapter, struct pci_dev *dev)
f204e0b8 1081{
f204e0b8
IM		 1082 int rc;
1083
c044c415
DA		 1084 adapter->dev.parent = &dev->dev;
1085 adapter->dev.release = cxl_release_adapter;
1086 pci_set_drvdata(dev, adapter);
f204e0b8 1087
c044c415
DA		 1088 rc = pci_enable_device(dev);
1089 if (rc) {
1090 dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc);
1091 return rc;
1092 }
f204e0b8 1093
bee30c70 1094 if ((rc = cxl_read_vsec(adapter, dev)))
c044c415 1095 return rc;
bee30c70
IM		 1096
1097 if ((rc = cxl_vsec_looks_ok(adapter, dev)))
c044c415 1098 return rc;
bee30c70 1099
d79e6801
PB		 1100 cxl_fixup_malformed_tlp(adapter, dev);
1101
bee30c70 1102 if ((rc = setup_cxl_bars(dev)))
c044c415 1103 return rc;
bee30c70 1104
f204e0b8 1105 if ((rc = switch_card_to_cxl(dev)))
c044c415 1106 return rc;
f204e0b8 1107
4beb5421 1108 if ((rc = cxl_update_image_control(adapter)))
c044c415 1109 return rc;
4beb5421 1110
f204e0b8 1111 if ((rc = cxl_map_adapter_regs(adapter, dev)))
c044c415 1112 return rc;
f204e0b8
IM		 1113
1114 if ((rc = sanitise_adapter_regs(adapter)))
c044c415 1115 goto err;
f204e0b8
IM		 1116
1117 if ((rc = init_implementation_adapter_regs(adapter, dev)))
c044c415 1118 goto err;
f204e0b8 1119
1212aa1c 1120 if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_CAPI)))
c044c415 1121 goto err;
f204e0b8 1122
1212aa1c
RG		 1123 /* If recovery happened, the last step is to turn on snooping.
1124 * In the non-recovery case this has no effect */
c044c415
DA		 1125 if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON)))
1126 goto err;
1212aa1c 1127
390fd592
PB		 1128 if ((rc = cxl_setup_psl_timebase(adapter, dev)))
1129 goto err;
1130
f204e0b8 1131 if ((rc = cxl_register_psl_err_irq(adapter)))
c044c415
DA		 1132 goto err;
1133
1134 return 0;
1135
1136err:
1137 cxl_unmap_adapter_regs(adapter);
1138 return rc;
1139
1140}
1141
1142static void cxl_deconfigure_adapter(struct cxl *adapter)
1143{
1144 struct pci_dev *pdev = to_pci_dev(adapter->dev.parent);
1145
1146 cxl_release_psl_err_irq(adapter);
1147 cxl_unmap_adapter_regs(adapter);
1148
1149 pci_disable_device(pdev);
1150}
1151
1152static struct cxl *cxl_init_adapter(struct pci_dev *dev)
1153{
1154 struct cxl *adapter;
1155 int rc;
1156
1157 adapter = cxl_alloc_adapter();
1158 if (!adapter)
1159 return ERR_PTR(-ENOMEM);
1160
1161 /* Set defaults for parameters which need to persist over
1162 * configure/reconfigure
1163 */
1164 adapter->perst_loads_image = true;
13e68d8b 1165 adapter->perst_same_image = false;
c044c415
DA		 1166
1167 rc = cxl_configure_adapter(adapter, dev);
1168 if (rc) {
1169 pci_disable_device(dev);
1170 cxl_release_adapter(&adapter->dev);
1171 return ERR_PTR(rc);
1172 }
f204e0b8
IM		 1173
1174 /* Don't care if this one fails: */
1175 cxl_debugfs_adapter_add(adapter);
1176
1177 /*
1178 * After we call this function we must not free the adapter directly,
1179 * even if it returns an error!
1180 */
1181 if ((rc = cxl_register_adapter(adapter)))
1182 goto err_put1;
1183
1184 if ((rc = cxl_sysfs_adapter_add(adapter)))
1185 goto err_put1;
1186
1187 return adapter;
1188
1189err_put1:
c044c415
DA		 1190 /* This should mirror cxl_remove_adapter, except without the
1191 * sysfs parts
1192 */
f204e0b8 1193 cxl_debugfs_adapter_remove(adapter);
c044c415
DA		 1194 cxl_deconfigure_adapter(adapter);
1195 device_unregister(&adapter->dev);
f204e0b8
IM		 1196 return ERR_PTR(rc);
1197}
1198
1199static void cxl_remove_adapter(struct cxl *adapter)
1200{
c044c415 1201 pr_devel("cxl_remove_adapter\n");
f204e0b8
IM		 1202
1203 cxl_sysfs_adapter_remove(adapter);
1204 cxl_debugfs_adapter_remove(adapter);
f204e0b8 1205
c044c415 1206 cxl_deconfigure_adapter(adapter);
f204e0b8 1207
c044c415 1208 device_unregister(&adapter->dev);
f204e0b8
IM		 1209}
1210
1211static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id)
1212{
1213 struct cxl *adapter;
1214 int slice;
1215 int rc;
1216
f204e0b8
IM		 1217 if (cxl_verbose)
1218 dump_cxl_config_space(dev);
1219
f204e0b8
IM		 1220 adapter = cxl_init_adapter(dev);
1221 if (IS_ERR(adapter)) {
1222 dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter));
1223 return PTR_ERR(adapter);
1224 }
1225
1226 for (slice = 0; slice < adapter->slices; slice++) {
d76427b0 1227 if ((rc = cxl_init_afu(adapter, slice, dev))) {
f204e0b8 1228 dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc);
d76427b0
DA		 1229 continue;
1230 }
1231
1232 rc = cxl_afu_select_best_mode(adapter->afu[slice]);
1233 if (rc)
1234 dev_err(&dev->dev, "AFU %i failed to start: %i\n", slice, rc);
f204e0b8
IM		 1235 }
1236
1237 return 0;
1238}
1239
1240static void cxl_remove(struct pci_dev *dev)
1241{
1242 struct cxl *adapter = pci_get_drvdata(dev);
6f7f0b3d
MN		 1243 struct cxl_afu *afu;
1244 int i;
f204e0b8 1245
f204e0b8
IM		 1246 /*
1247 * Lock to prevent someone grabbing a ref through the adapter list as
1248 * we are removing it
1249 */
6f7f0b3d
MN		 1250 for (i = 0; i < adapter->slices; i++) {
1251 afu = adapter->afu[i];
1252 cxl_pci_vphb_remove(afu);
1253 cxl_remove_afu(afu);
1254 }
f204e0b8
IM		 1255 cxl_remove_adapter(adapter);
1256}
1257
9e8df8a2
DA		 1258static pci_ers_result_t cxl_vphb_error_detected(struct cxl_afu *afu,
1259 pci_channel_state_t state)
1260{
1261 struct pci_dev *afu_dev;
1262 pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET;
1263 pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET;
1264
1265 /* There should only be one entry, but go through the list
1266 * anyway
1267 */
1268 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
1269 if (!afu_dev->driver)
1270 continue;
1271
1272 afu_dev->error_state = state;
1273
1274 if (afu_dev->driver->err_handler)
1275 afu_result = afu_dev->driver->err_handler->error_detected(afu_dev,
1276 state);
1277 /* Disconnect trumps all, NONE trumps NEED_RESET */
1278 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
1279 result = PCI_ERS_RESULT_DISCONNECT;
1280 else if ((afu_result == PCI_ERS_RESULT_NONE) &&
1281 (result == PCI_ERS_RESULT_NEED_RESET))
1282 result = PCI_ERS_RESULT_NONE;
1283 }
1284 return result;
1285}
1286
1287static pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,
1288 pci_channel_state_t state)
1289{
1290 struct cxl *adapter = pci_get_drvdata(pdev);
1291 struct cxl_afu *afu;
1292 pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET;
1293 int i;
1294
1295 /* At this point, we could still have an interrupt pending.
1296 * Let's try to get them out of the way before they do
1297 * anything we don't like.
1298 */
1299 schedule();
1300
1301 /* If we're permanently dead, give up. */
1302 if (state == pci_channel_io_perm_failure) {
1303 /* Tell the AFU drivers; but we don't care what they
1304 * say, we're going away.
1305 */
1306 for (i = 0; i < adapter->slices; i++) {
1307 afu = adapter->afu[i];
1308 cxl_vphb_error_detected(afu, state);
1309 }
1310 return PCI_ERS_RESULT_DISCONNECT;
1311 }
1312
1313 /* Are we reflashing?
1314 *
1315 * If we reflash, we could come back as something entirely
1316 * different, including a non-CAPI card. As such, by default
1317 * we don't participate in the process. We'll be unbound and
1318 * the slot re-probed. (TODO: check EEH doesn't blindly rebind
1319 * us!)
1320 *
1321 * However, this isn't the entire story: for reliablity
1322 * reasons, we usually want to reflash the FPGA on PERST in
1323 * order to get back to a more reliable known-good state.
1324 *
1325 * This causes us a bit of a problem: if we reflash we can't
1326 * trust that we'll come back the same - we could have a new
1327 * image and been PERSTed in order to load that
1328 * image. However, most of the time we actually *will* come
1329 * back the same - for example a regular EEH event.
1330 *
1331 * Therefore, we allow the user to assert that the image is
1332 * indeed the same and that we should continue on into EEH
1333 * anyway.
1334 */
1335 if (adapter->perst_loads_image && !adapter->perst_same_image) {
1336 /* TODO take the PHB out of CXL mode */
1337 dev_info(&pdev->dev, "reflashing, so opting out of EEH!\n");
1338 return PCI_ERS_RESULT_NONE;
1339 }
1340
1341 /*
1342 * At this point, we want to try to recover. We'll always
1343 * need a complete slot reset: we don't trust any other reset.
1344 *
1345 * Now, we go through each AFU:
1346 * - We send the driver, if bound, an error_detected callback.
1347 * We expect it to clean up, but it can also tell us to give
1348 * up and permanently detach the card. To simplify things, if
1349 * any bound AFU driver doesn't support EEH, we give up on EEH.
1350 *
1351 * - We detach all contexts associated with the AFU. This
1352 * does not free them, but puts them into a CLOSED state
1353 * which causes any the associated files to return useful
1354 * errors to userland. It also unmaps, but does not free,
1355 * any IRQs.
1356 *
1357 * - We clean up our side: releasing and unmapping resources we hold
1358 * so we can wire them up again when the hardware comes back up.
1359 *
1360 * Driver authors should note:
1361 *
1362 * - Any contexts you create in your kernel driver (except
1363 * those associated with anonymous file descriptors) are
1364 * your responsibility to free and recreate. Likewise with
1365 * any attached resources.
1366 *
1367 * - We will take responsibility for re-initialising the
1368 * device context (the one set up for you in
1369 * cxl_pci_enable_device_hook and accessed through
1370 * cxl_get_context). If you've attached IRQs or other
1371 * resources to it, they remains yours to free.
1372 *
1373 * You can call the same functions to release resources as you
1374 * normally would: we make sure that these functions continue
1375 * to work when the hardware is down.
1376 *
1377 * Two examples:
1378 *
1379 * 1) If you normally free all your resources at the end of
1380 * each request, or if you use anonymous FDs, your
1381 * error_detected callback can simply set a flag to tell
1382 * your driver not to start any new calls. You can then
1383 * clear the flag in the resume callback.
1384 *
1385 * 2) If you normally allocate your resources on startup:
1386 * * Set a flag in error_detected as above.
1387 * * Let CXL detach your contexts.
1388 * * In slot_reset, free the old resources and allocate new ones.
1389 * * In resume, clear the flag to allow things to start.
1390 */
1391 for (i = 0; i < adapter->slices; i++) {
1392 afu = adapter->afu[i];
1393
1394 result = cxl_vphb_error_detected(afu, state);
1395
1396 /* Only continue if everyone agrees on NEED_RESET */
1397 if (result != PCI_ERS_RESULT_NEED_RESET)
1398 return result;
1399
1400 cxl_context_detach_all(afu);
1401 cxl_afu_deactivate_mode(afu);
1402 cxl_deconfigure_afu(afu);
1403 }
1404 cxl_deconfigure_adapter(adapter);
1405
1406 return result;
1407}
1408
1409static pci_ers_result_t cxl_pci_slot_reset(struct pci_dev *pdev)
1410{
1411 struct cxl *adapter = pci_get_drvdata(pdev);
1412 struct cxl_afu *afu;
1413 struct cxl_context *ctx;
1414 struct pci_dev *afu_dev;
1415 pci_ers_result_t afu_result = PCI_ERS_RESULT_RECOVERED;
1416 pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED;
1417 int i;
1418
1419 if (cxl_configure_adapter(adapter, pdev))
1420 goto err;
1421
1422 for (i = 0; i < adapter->slices; i++) {
1423 afu = adapter->afu[i];
1424
1425 if (cxl_configure_afu(afu, adapter, pdev))
1426 goto err;
1427
1428 if (cxl_afu_select_best_mode(afu))
1429 goto err;
1430
1431 cxl_pci_vphb_reconfigure(afu);
1432
1433 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
1434 /* Reset the device context.
1435 * TODO: make this less disruptive
1436 */
1437 ctx = cxl_get_context(afu_dev);
1438
1439 if (ctx && cxl_release_context(ctx))
1440 goto err;
1441
1442 ctx = cxl_dev_context_init(afu_dev);
1443 if (!ctx)
1444 goto err;
1445
1446 afu_dev->dev.archdata.cxl_ctx = ctx;
1447
1448 if (cxl_afu_check_and_enable(afu))
1449 goto err;
1450
1451 afu_dev->error_state = pci_channel_io_normal;
1452
1453 /* If there's a driver attached, allow it to
1454 * chime in on recovery. Drivers should check
1455 * if everything has come back OK, but
1456 * shouldn't start new work until we call
1457 * their resume function.
1458 */
1459 if (!afu_dev->driver)
1460 continue;
1461
1462 if (afu_dev->driver->err_handler &&
1463 afu_dev->driver->err_handler->slot_reset)
1464 afu_result = afu_dev->driver->err_handler->slot_reset(afu_dev);
1465
1466 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
1467 result = PCI_ERS_RESULT_DISCONNECT;
1468 }
1469 }
1470 return result;
1471
1472err:
1473 /* All the bits that happen in both error_detected and cxl_remove
1474 * should be idempotent, so we don't need to worry about leaving a mix
1475 * of unconfigured and reconfigured resources.
1476 */
1477 dev_err(&pdev->dev, "EEH recovery failed. Asking to be disconnected.\n");
1478 return PCI_ERS_RESULT_DISCONNECT;
1479}
1480
1481static void cxl_pci_resume(struct pci_dev *pdev)
1482{
1483 struct cxl *adapter = pci_get_drvdata(pdev);
1484 struct cxl_afu *afu;
1485 struct pci_dev *afu_dev;
1486 int i;
1487
1488 /* Everything is back now. Drivers should restart work now.
1489 * This is not the place to be checking if everything came back up
1490 * properly, because there's no return value: do that in slot_reset.
1491 */
1492 for (i = 0; i < adapter->slices; i++) {
1493 afu = adapter->afu[i];
1494
1495 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
1496 if (afu_dev->driver && afu_dev->driver->err_handler &&
1497 afu_dev->driver->err_handler->resume)
1498 afu_dev->driver->err_handler->resume(afu_dev);
1499 }
1500 }
1501}
1502
1503static const struct pci_error_handlers cxl_err_handler = {
1504 .error_detected = cxl_pci_error_detected,
1505 .slot_reset = cxl_pci_slot_reset,
1506 .resume = cxl_pci_resume,
1507};
1508
f204e0b8
IM		 1509struct pci_driver cxl_pci_driver = {
1510 .name = "cxl-pci",
1511 .id_table = cxl_pci_tbl,
1512 .probe = cxl_probe,
1513 .remove = cxl_remove,
aa70775e 1514 .shutdown = cxl_remove,
9e8df8a2 1515 .err_handler = &cxl_err_handler,
f204e0b8 1516};
Linux kernel - Deliverables
This page took 0.134553 seconds and 5 git commands to generate.