Commit | Line | Data |
---|---|---|
b587b13a DB |
1 | /* |
2 | * at25.c -- support most SPI EEPROMs, such as Atmel AT25 models | |
3 | * | |
4 | * Copyright (C) 2006 David Brownell | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
b587b13a DB |
13 | #include <linux/module.h> |
14 | #include <linux/slab.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/sched.h> | |
18 | ||
5a99f570 AL |
19 | #include <linux/nvmem-provider.h> |
20 | #include <linux/regmap.h> | |
b587b13a DB |
21 | #include <linux/spi/spi.h> |
22 | #include <linux/spi/eeprom.h> | |
f60e7074 | 23 | #include <linux/property.h> |
b587b13a | 24 | |
3f86f14c DB |
25 | /* |
26 | * NOTE: this is an *EEPROM* driver. The vagaries of product naming | |
27 | * mean that some AT25 products are EEPROMs, and others are FLASH. | |
28 | * Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver, | |
29 | * not this one! | |
30 | */ | |
31 | ||
b587b13a DB |
32 | struct at25_data { |
33 | struct spi_device *spi; | |
34 | struct mutex lock; | |
35 | struct spi_eeprom chip; | |
b587b13a | 36 | unsigned addrlen; |
5a99f570 AL |
37 | struct regmap_config regmap_config; |
38 | struct nvmem_config nvmem_config; | |
39 | struct nvmem_device *nvmem; | |
b587b13a DB |
40 | }; |
41 | ||
42 | #define AT25_WREN 0x06 /* latch the write enable */ | |
43 | #define AT25_WRDI 0x04 /* reset the write enable */ | |
44 | #define AT25_RDSR 0x05 /* read status register */ | |
45 | #define AT25_WRSR 0x01 /* write status register */ | |
46 | #define AT25_READ 0x03 /* read byte(s) */ | |
47 | #define AT25_WRITE 0x02 /* write byte(s)/sector */ | |
48 | ||
49 | #define AT25_SR_nRDY 0x01 /* nRDY = write-in-progress */ | |
50 | #define AT25_SR_WEN 0x02 /* write enable (latched) */ | |
51 | #define AT25_SR_BP0 0x04 /* BP for software writeprotect */ | |
52 | #define AT25_SR_BP1 0x08 | |
53 | #define AT25_SR_WPEN 0x80 /* writeprotect enable */ | |
54 | ||
b4161f0b | 55 | #define AT25_INSTR_BIT3 0x08 /* Additional address bit in instr */ |
b587b13a DB |
56 | |
57 | #define EE_MAXADDRLEN 3 /* 24 bit addresses, up to 2 MBytes */ | |
58 | ||
59 | /* Specs often allow 5 msec for a page write, sometimes 20 msec; | |
60 | * it's important to recover from write timeouts. | |
61 | */ | |
62 | #define EE_TIMEOUT 25 | |
63 | ||
64 | /*-------------------------------------------------------------------------*/ | |
65 | ||
66 | #define io_limit PAGE_SIZE /* bytes */ | |
67 | ||
68 | static ssize_t | |
69 | at25_ee_read( | |
70 | struct at25_data *at25, | |
71 | char *buf, | |
72 | unsigned offset, | |
73 | size_t count | |
74 | ) | |
75 | { | |
76 | u8 command[EE_MAXADDRLEN + 1]; | |
77 | u8 *cp; | |
78 | ssize_t status; | |
79 | struct spi_transfer t[2]; | |
80 | struct spi_message m; | |
b4161f0b | 81 | u8 instr; |
b587b13a | 82 | |
5a99f570 | 83 | if (unlikely(offset >= at25->chip.byte_len)) |
14dd1ff0 | 84 | return 0; |
5a99f570 AL |
85 | if ((offset + count) > at25->chip.byte_len) |
86 | count = at25->chip.byte_len - offset; | |
14dd1ff0 DB |
87 | if (unlikely(!count)) |
88 | return count; | |
89 | ||
b587b13a | 90 | cp = command; |
b4161f0b IS |
91 | |
92 | instr = AT25_READ; | |
93 | if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR) | |
94 | if (offset >= (1U << (at25->addrlen * 8))) | |
95 | instr |= AT25_INSTR_BIT3; | |
96 | *cp++ = instr; | |
b587b13a DB |
97 | |
98 | /* 8/16/24-bit address is written MSB first */ | |
99 | switch (at25->addrlen) { | |
100 | default: /* case 3 */ | |
101 | *cp++ = offset >> 16; | |
102 | case 2: | |
103 | *cp++ = offset >> 8; | |
104 | case 1: | |
105 | case 0: /* can't happen: for better codegen */ | |
106 | *cp++ = offset >> 0; | |
107 | } | |
108 | ||
109 | spi_message_init(&m); | |
110 | memset(t, 0, sizeof t); | |
111 | ||
112 | t[0].tx_buf = command; | |
113 | t[0].len = at25->addrlen + 1; | |
114 | spi_message_add_tail(&t[0], &m); | |
115 | ||
116 | t[1].rx_buf = buf; | |
117 | t[1].len = count; | |
118 | spi_message_add_tail(&t[1], &m); | |
119 | ||
120 | mutex_lock(&at25->lock); | |
121 | ||
122 | /* Read it all at once. | |
123 | * | |
124 | * REVISIT that's potentially a problem with large chips, if | |
125 | * other devices on the bus need to be accessed regularly or | |
126 | * this chip is clocked very slowly | |
127 | */ | |
128 | status = spi_sync(at25->spi, &m); | |
129 | dev_dbg(&at25->spi->dev, | |
130 | "read %Zd bytes at %d --> %d\n", | |
131 | count, offset, (int) status); | |
132 | ||
133 | mutex_unlock(&at25->lock); | |
134 | return status ? status : count; | |
135 | } | |
136 | ||
5a99f570 AL |
137 | static int at25_regmap_read(void *context, const void *reg, size_t reg_size, |
138 | void *val, size_t val_size) | |
b587b13a | 139 | { |
5a99f570 AL |
140 | struct at25_data *at25 = context; |
141 | off_t offset = *(u32 *)reg; | |
142 | int err; | |
b587b13a | 143 | |
5a99f570 AL |
144 | err = at25_ee_read(at25, val, offset, val_size); |
145 | if (err) | |
146 | return err; | |
147 | return 0; | |
b587b13a DB |
148 | } |
149 | ||
b587b13a | 150 | static ssize_t |
4cafbd0b GU |
151 | at25_ee_write(struct at25_data *at25, const char *buf, loff_t off, |
152 | size_t count) | |
b587b13a DB |
153 | { |
154 | ssize_t status = 0; | |
155 | unsigned written = 0; | |
156 | unsigned buf_size; | |
157 | u8 *bounce; | |
158 | ||
5a99f570 | 159 | if (unlikely(off >= at25->chip.byte_len)) |
14dd1ff0 | 160 | return -EFBIG; |
5a99f570 AL |
161 | if ((off + count) > at25->chip.byte_len) |
162 | count = at25->chip.byte_len - off; | |
14dd1ff0 DB |
163 | if (unlikely(!count)) |
164 | return count; | |
165 | ||
b587b13a DB |
166 | /* Temp buffer starts with command and address */ |
167 | buf_size = at25->chip.page_size; | |
168 | if (buf_size > io_limit) | |
169 | buf_size = io_limit; | |
170 | bounce = kmalloc(buf_size + at25->addrlen + 1, GFP_KERNEL); | |
171 | if (!bounce) | |
172 | return -ENOMEM; | |
173 | ||
174 | /* For write, rollover is within the page ... so we write at | |
175 | * most one page, then manually roll over to the next page. | |
176 | */ | |
b587b13a DB |
177 | mutex_lock(&at25->lock); |
178 | do { | |
179 | unsigned long timeout, retries; | |
180 | unsigned segment; | |
181 | unsigned offset = (unsigned) off; | |
b4161f0b | 182 | u8 *cp = bounce; |
f0d83679 | 183 | int sr; |
b4161f0b | 184 | u8 instr; |
b587b13a DB |
185 | |
186 | *cp = AT25_WREN; | |
187 | status = spi_write(at25->spi, cp, 1); | |
188 | if (status < 0) { | |
189 | dev_dbg(&at25->spi->dev, "WREN --> %d\n", | |
190 | (int) status); | |
191 | break; | |
192 | } | |
193 | ||
b4161f0b IS |
194 | instr = AT25_WRITE; |
195 | if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR) | |
196 | if (offset >= (1U << (at25->addrlen * 8))) | |
197 | instr |= AT25_INSTR_BIT3; | |
198 | *cp++ = instr; | |
199 | ||
b587b13a DB |
200 | /* 8/16/24-bit address is written MSB first */ |
201 | switch (at25->addrlen) { | |
202 | default: /* case 3 */ | |
203 | *cp++ = offset >> 16; | |
204 | case 2: | |
205 | *cp++ = offset >> 8; | |
206 | case 1: | |
207 | case 0: /* can't happen: for better codegen */ | |
208 | *cp++ = offset >> 0; | |
209 | } | |
210 | ||
211 | /* Write as much of a page as we can */ | |
212 | segment = buf_size - (offset % buf_size); | |
213 | if (segment > count) | |
214 | segment = count; | |
215 | memcpy(cp, buf, segment); | |
216 | status = spi_write(at25->spi, bounce, | |
217 | segment + at25->addrlen + 1); | |
218 | dev_dbg(&at25->spi->dev, | |
219 | "write %u bytes at %u --> %d\n", | |
220 | segment, offset, (int) status); | |
221 | if (status < 0) | |
222 | break; | |
223 | ||
224 | /* REVISIT this should detect (or prevent) failed writes | |
225 | * to readonly sections of the EEPROM... | |
226 | */ | |
227 | ||
228 | /* Wait for non-busy status */ | |
229 | timeout = jiffies + msecs_to_jiffies(EE_TIMEOUT); | |
230 | retries = 0; | |
231 | do { | |
b587b13a DB |
232 | |
233 | sr = spi_w8r8(at25->spi, AT25_RDSR); | |
234 | if (sr < 0 || (sr & AT25_SR_nRDY)) { | |
235 | dev_dbg(&at25->spi->dev, | |
236 | "rdsr --> %d (%02x)\n", sr, sr); | |
237 | /* at HZ=100, this is sloooow */ | |
238 | msleep(1); | |
239 | continue; | |
240 | } | |
241 | if (!(sr & AT25_SR_nRDY)) | |
242 | break; | |
243 | } while (retries++ < 3 || time_before_eq(jiffies, timeout)); | |
244 | ||
f0d83679 | 245 | if ((sr < 0) || (sr & AT25_SR_nRDY)) { |
b587b13a DB |
246 | dev_err(&at25->spi->dev, |
247 | "write %d bytes offset %d, " | |
248 | "timeout after %u msecs\n", | |
249 | segment, offset, | |
250 | jiffies_to_msecs(jiffies - | |
251 | (timeout - EE_TIMEOUT))); | |
252 | status = -ETIMEDOUT; | |
253 | break; | |
254 | } | |
255 | ||
256 | off += segment; | |
257 | buf += segment; | |
258 | count -= segment; | |
259 | written += segment; | |
260 | ||
261 | } while (count > 0); | |
262 | ||
263 | mutex_unlock(&at25->lock); | |
264 | ||
265 | kfree(bounce); | |
266 | return written ? written : status; | |
267 | } | |
268 | ||
5a99f570 | 269 | static int at25_regmap_write(void *context, const void *data, size_t count) |
b587b13a | 270 | { |
5a99f570 AL |
271 | struct at25_data *at25 = context; |
272 | const char *buf; | |
273 | u32 offset; | |
274 | size_t len; | |
275 | int err; | |
b587b13a | 276 | |
5a99f570 AL |
277 | memcpy(&offset, data, sizeof(offset)); |
278 | buf = (const char *)data + sizeof(offset); | |
279 | len = count - sizeof(offset); | |
b587b13a | 280 | |
5a99f570 AL |
281 | err = at25_ee_write(at25, buf, offset, len); |
282 | if (err) | |
283 | return err; | |
284 | return 0; | |
b587b13a DB |
285 | } |
286 | ||
5a99f570 AL |
287 | static const struct regmap_bus at25_regmap_bus = { |
288 | .read = at25_regmap_read, | |
289 | .write = at25_regmap_write, | |
290 | .reg_format_endian_default = REGMAP_ENDIAN_NATIVE, | |
291 | }; | |
292 | ||
b587b13a DB |
293 | /*-------------------------------------------------------------------------*/ |
294 | ||
f60e7074 | 295 | static int at25_fw_to_chip(struct device *dev, struct spi_eeprom *chip) |
d6ae0d57 DD |
296 | { |
297 | u32 val; | |
298 | ||
299 | memset(chip, 0, sizeof(*chip)); | |
f60e7074 | 300 | strncpy(chip->name, "at25", sizeof(chip->name)); |
d6ae0d57 | 301 | |
f60e7074 MW |
302 | if (device_property_read_u32(dev, "size", &val) == 0 || |
303 | device_property_read_u32(dev, "at25,byte-len", &val) == 0) { | |
d6ae0d57 DD |
304 | chip->byte_len = val; |
305 | } else { | |
306 | dev_err(dev, "Error: missing \"size\" property\n"); | |
307 | return -ENODEV; | |
308 | } | |
309 | ||
f60e7074 MW |
310 | if (device_property_read_u32(dev, "pagesize", &val) == 0 || |
311 | device_property_read_u32(dev, "at25,page-size", &val) == 0) { | |
d6ae0d57 DD |
312 | chip->page_size = (u16)val; |
313 | } else { | |
314 | dev_err(dev, "Error: missing \"pagesize\" property\n"); | |
315 | return -ENODEV; | |
316 | } | |
317 | ||
f60e7074 | 318 | if (device_property_read_u32(dev, "at25,addr-mode", &val) == 0) { |
d6ae0d57 DD |
319 | chip->flags = (u16)val; |
320 | } else { | |
f60e7074 | 321 | if (device_property_read_u32(dev, "address-width", &val)) { |
d6ae0d57 DD |
322 | dev_err(dev, |
323 | "Error: missing \"address-width\" property\n"); | |
324 | return -ENODEV; | |
325 | } | |
326 | switch (val) { | |
327 | case 8: | |
328 | chip->flags |= EE_ADDR1; | |
329 | break; | |
330 | case 16: | |
331 | chip->flags |= EE_ADDR2; | |
332 | break; | |
333 | case 24: | |
334 | chip->flags |= EE_ADDR3; | |
335 | break; | |
336 | default: | |
337 | dev_err(dev, | |
338 | "Error: bad \"address-width\" property: %u\n", | |
339 | val); | |
340 | return -ENODEV; | |
341 | } | |
f60e7074 | 342 | if (device_property_present(dev, "read-only")) |
d6ae0d57 DD |
343 | chip->flags |= EE_READONLY; |
344 | } | |
345 | return 0; | |
346 | } | |
347 | ||
b587b13a DB |
348 | static int at25_probe(struct spi_device *spi) |
349 | { | |
350 | struct at25_data *at25 = NULL; | |
002176db | 351 | struct spi_eeprom chip; |
5a99f570 | 352 | struct regmap *regmap; |
b587b13a DB |
353 | int err; |
354 | int sr; | |
355 | int addrlen; | |
356 | ||
357 | /* Chip description */ | |
002176db | 358 | if (!spi->dev.platform_data) { |
f60e7074 MW |
359 | err = at25_fw_to_chip(&spi->dev, &chip); |
360 | if (err) | |
361 | return err; | |
002176db APS |
362 | } else |
363 | chip = *(struct spi_eeprom *)spi->dev.platform_data; | |
b587b13a DB |
364 | |
365 | /* For now we only support 8/16/24 bit addressing */ | |
002176db | 366 | if (chip.flags & EE_ADDR1) |
b587b13a | 367 | addrlen = 1; |
002176db | 368 | else if (chip.flags & EE_ADDR2) |
b587b13a | 369 | addrlen = 2; |
002176db | 370 | else if (chip.flags & EE_ADDR3) |
b587b13a DB |
371 | addrlen = 3; |
372 | else { | |
373 | dev_dbg(&spi->dev, "unsupported address type\n"); | |
01fe7b43 | 374 | return -EINVAL; |
b587b13a DB |
375 | } |
376 | ||
377 | /* Ping the chip ... the status register is pretty portable, | |
378 | * unlike probing manufacturer IDs. We do expect that system | |
379 | * firmware didn't write it in the past few milliseconds! | |
380 | */ | |
381 | sr = spi_w8r8(spi, AT25_RDSR); | |
382 | if (sr < 0 || sr & AT25_SR_nRDY) { | |
c6ca97d2 | 383 | dev_dbg(&spi->dev, "rdsr --> %d (%02x)\n", sr, sr); |
01fe7b43 | 384 | return -ENXIO; |
b587b13a DB |
385 | } |
386 | ||
01fe7b43 NB |
387 | at25 = devm_kzalloc(&spi->dev, sizeof(struct at25_data), GFP_KERNEL); |
388 | if (!at25) | |
389 | return -ENOMEM; | |
b587b13a DB |
390 | |
391 | mutex_init(&at25->lock); | |
002176db | 392 | at25->chip = chip; |
b587b13a | 393 | at25->spi = spi_dev_get(spi); |
41ddcf67 | 394 | spi_set_drvdata(spi, at25); |
b587b13a DB |
395 | at25->addrlen = addrlen; |
396 | ||
5a99f570 AL |
397 | at25->regmap_config.reg_bits = 32; |
398 | at25->regmap_config.val_bits = 8; | |
399 | at25->regmap_config.reg_stride = 1; | |
400 | at25->regmap_config.max_register = chip.byte_len - 1; | |
b587b13a | 401 | |
5a99f570 AL |
402 | regmap = devm_regmap_init(&spi->dev, &at25_regmap_bus, at25, |
403 | &at25->regmap_config); | |
404 | if (IS_ERR(regmap)) { | |
405 | dev_err(&spi->dev, "regmap init failed\n"); | |
406 | return PTR_ERR(regmap); | |
407 | } | |
b587b13a | 408 | |
5a99f570 AL |
409 | at25->nvmem_config.name = dev_name(&spi->dev); |
410 | at25->nvmem_config.dev = &spi->dev; | |
411 | at25->nvmem_config.read_only = chip.flags & EE_READONLY; | |
412 | at25->nvmem_config.root_only = true; | |
413 | at25->nvmem_config.owner = THIS_MODULE; | |
414 | at25->nvmem_config.compat = true; | |
415 | at25->nvmem_config.base_dev = &spi->dev; | |
416 | ||
417 | at25->nvmem = nvmem_register(&at25->nvmem_config); | |
418 | if (IS_ERR(at25->nvmem)) | |
419 | return PTR_ERR(at25->nvmem); | |
420 | ||
421 | dev_info(&spi->dev, "%d %s %s eeprom%s, pagesize %u\n", | |
422 | (chip.byte_len < 1024) | |
423 | ? chip.byte_len | |
424 | : (chip.byte_len / 1024), | |
425 | (chip.byte_len < 1024) ? "Byte" : "KByte", | |
b587b13a | 426 | at25->chip.name, |
002176db | 427 | (chip.flags & EE_READONLY) ? " (readonly)" : "", |
b587b13a DB |
428 | at25->chip.page_size); |
429 | return 0; | |
b587b13a DB |
430 | } |
431 | ||
486a5c28 | 432 | static int at25_remove(struct spi_device *spi) |
b587b13a DB |
433 | { |
434 | struct at25_data *at25; | |
435 | ||
41ddcf67 | 436 | at25 = spi_get_drvdata(spi); |
5a99f570 AL |
437 | nvmem_unregister(at25->nvmem); |
438 | ||
b587b13a DB |
439 | return 0; |
440 | } | |
441 | ||
442 | /*-------------------------------------------------------------------------*/ | |
443 | ||
fbfdb6ed JL |
444 | static const struct of_device_id at25_of_match[] = { |
445 | { .compatible = "atmel,at25", }, | |
446 | { } | |
447 | }; | |
448 | MODULE_DEVICE_TABLE(of, at25_of_match); | |
449 | ||
b587b13a DB |
450 | static struct spi_driver at25_driver = { |
451 | .driver = { | |
452 | .name = "at25", | |
fbfdb6ed | 453 | .of_match_table = at25_of_match, |
b587b13a DB |
454 | }, |
455 | .probe = at25_probe, | |
2d6bed9c | 456 | .remove = at25_remove, |
b587b13a DB |
457 | }; |
458 | ||
a3dc3c9e | 459 | module_spi_driver(at25_driver); |
b587b13a DB |
460 | |
461 | MODULE_DESCRIPTION("Driver for most SPI EEPROMs"); | |
462 | MODULE_AUTHOR("David Brownell"); | |
463 | MODULE_LICENSE("GPL"); | |
e0626e38 | 464 | MODULE_ALIAS("spi:at25"); |