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32e2b59f TW |
1 | /* |
2 | * | |
3 | * Intel Management Engine Interface (Intel MEI) Linux driver | |
4 | * Copyright (c) 2013-2014, Intel Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | */ | |
16 | ||
17 | #include <linux/pci.h> | |
18 | #include <linux/jiffies.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/kthread.h> | |
4a22176a | 21 | #include <linux/irqreturn.h> |
32e2b59f TW |
22 | |
23 | #include <linux/mei.h> | |
24 | ||
25 | #include "mei_dev.h" | |
26 | #include "hw-txe.h" | |
27 | #include "client.h" | |
28 | #include "hbm.h" | |
29 | ||
30 | /** | |
ce23139c | 31 | * mei_txe_reg_read - Reads 32bit data from the txe device |
32e2b59f TW |
32 | * |
33 | * @base_addr: registers base address | |
34 | * @offset: register offset | |
35 | * | |
ce23139c | 36 | * Return: register value |
32e2b59f TW |
37 | */ |
38 | static inline u32 mei_txe_reg_read(void __iomem *base_addr, | |
39 | unsigned long offset) | |
40 | { | |
41 | return ioread32(base_addr + offset); | |
42 | } | |
43 | ||
44 | /** | |
ce23139c | 45 | * mei_txe_reg_write - Writes 32bit data to the txe device |
32e2b59f TW |
46 | * |
47 | * @base_addr: registers base address | |
48 | * @offset: register offset | |
49 | * @value: the value to write | |
50 | */ | |
51 | static inline void mei_txe_reg_write(void __iomem *base_addr, | |
52 | unsigned long offset, u32 value) | |
53 | { | |
54 | iowrite32(value, base_addr + offset); | |
55 | } | |
56 | ||
57 | /** | |
58 | * mei_txe_sec_reg_read_silent - Reads 32bit data from the SeC BAR | |
59 | * | |
ce23139c | 60 | * @hw: the txe hardware structure |
32e2b59f TW |
61 | * @offset: register offset |
62 | * | |
63 | * Doesn't check for aliveness while Reads 32bit data from the SeC BAR | |
ce23139c AU |
64 | * |
65 | * Return: register value | |
32e2b59f TW |
66 | */ |
67 | static inline u32 mei_txe_sec_reg_read_silent(struct mei_txe_hw *hw, | |
68 | unsigned long offset) | |
69 | { | |
70 | return mei_txe_reg_read(hw->mem_addr[SEC_BAR], offset); | |
71 | } | |
72 | ||
73 | /** | |
74 | * mei_txe_sec_reg_read - Reads 32bit data from the SeC BAR | |
75 | * | |
ce23139c | 76 | * @hw: the txe hardware structure |
32e2b59f TW |
77 | * @offset: register offset |
78 | * | |
79 | * Reads 32bit data from the SeC BAR and shout loud if aliveness is not set | |
ce23139c AU |
80 | * |
81 | * Return: register value | |
32e2b59f TW |
82 | */ |
83 | static inline u32 mei_txe_sec_reg_read(struct mei_txe_hw *hw, | |
84 | unsigned long offset) | |
85 | { | |
86 | WARN(!hw->aliveness, "sec read: aliveness not asserted\n"); | |
87 | return mei_txe_sec_reg_read_silent(hw, offset); | |
88 | } | |
89 | /** | |
90 | * mei_txe_sec_reg_write_silent - Writes 32bit data to the SeC BAR | |
91 | * doesn't check for aliveness | |
92 | * | |
a8605ea2 | 93 | * @hw: the txe hardware structure |
32e2b59f TW |
94 | * @offset: register offset |
95 | * @value: value to write | |
96 | * | |
97 | * Doesn't check for aliveness while writes 32bit data from to the SeC BAR | |
98 | */ | |
99 | static inline void mei_txe_sec_reg_write_silent(struct mei_txe_hw *hw, | |
100 | unsigned long offset, u32 value) | |
101 | { | |
102 | mei_txe_reg_write(hw->mem_addr[SEC_BAR], offset, value); | |
103 | } | |
104 | ||
105 | /** | |
106 | * mei_txe_sec_reg_write - Writes 32bit data to the SeC BAR | |
107 | * | |
a8605ea2 | 108 | * @hw: the txe hardware structure |
32e2b59f TW |
109 | * @offset: register offset |
110 | * @value: value to write | |
111 | * | |
112 | * Writes 32bit data from the SeC BAR and shout loud if aliveness is not set | |
113 | */ | |
114 | static inline void mei_txe_sec_reg_write(struct mei_txe_hw *hw, | |
115 | unsigned long offset, u32 value) | |
116 | { | |
117 | WARN(!hw->aliveness, "sec write: aliveness not asserted\n"); | |
118 | mei_txe_sec_reg_write_silent(hw, offset, value); | |
119 | } | |
120 | /** | |
121 | * mei_txe_br_reg_read - Reads 32bit data from the Bridge BAR | |
122 | * | |
ce23139c | 123 | * @hw: the txe hardware structure |
32e2b59f TW |
124 | * @offset: offset from which to read the data |
125 | * | |
ce23139c | 126 | * Return: the byte read. |
32e2b59f TW |
127 | */ |
128 | static inline u32 mei_txe_br_reg_read(struct mei_txe_hw *hw, | |
129 | unsigned long offset) | |
130 | { | |
131 | return mei_txe_reg_read(hw->mem_addr[BRIDGE_BAR], offset); | |
132 | } | |
133 | ||
134 | /** | |
135 | * mei_txe_br_reg_write - Writes 32bit data to the Bridge BAR | |
136 | * | |
a8605ea2 | 137 | * @hw: the txe hardware structure |
32e2b59f TW |
138 | * @offset: offset from which to write the data |
139 | * @value: the byte to write | |
140 | */ | |
141 | static inline void mei_txe_br_reg_write(struct mei_txe_hw *hw, | |
142 | unsigned long offset, u32 value) | |
143 | { | |
144 | mei_txe_reg_write(hw->mem_addr[BRIDGE_BAR], offset, value); | |
145 | } | |
146 | ||
147 | /** | |
148 | * mei_txe_aliveness_set - request for aliveness change | |
149 | * | |
150 | * @dev: the device structure | |
151 | * @req: requested aliveness value | |
152 | * | |
153 | * Request for aliveness change and returns true if the change is | |
154 | * really needed and false if aliveness is already | |
155 | * in the requested state | |
ce23139c AU |
156 | * |
157 | * Locking: called under "dev->device_lock" lock | |
158 | * | |
159 | * Return: true if request was send | |
32e2b59f TW |
160 | */ |
161 | static bool mei_txe_aliveness_set(struct mei_device *dev, u32 req) | |
162 | { | |
163 | ||
164 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
165 | bool do_req = hw->aliveness != req; | |
166 | ||
2bf94cab | 167 | dev_dbg(dev->dev, "Aliveness current=%d request=%d\n", |
32e2b59f TW |
168 | hw->aliveness, req); |
169 | if (do_req) { | |
964a2331 | 170 | dev->pg_event = MEI_PG_EVENT_WAIT; |
32e2b59f TW |
171 | mei_txe_br_reg_write(hw, SICR_HOST_ALIVENESS_REQ_REG, req); |
172 | } | |
173 | return do_req; | |
174 | } | |
175 | ||
176 | ||
177 | /** | |
178 | * mei_txe_aliveness_req_get - get aliveness requested register value | |
179 | * | |
180 | * @dev: the device structure | |
181 | * | |
182 | * Extract HICR_HOST_ALIVENESS_RESP_ACK bit from | |
183 | * from HICR_HOST_ALIVENESS_REQ register value | |
ce23139c AU |
184 | * |
185 | * Return: SICR_HOST_ALIVENESS_REQ_REQUESTED bit value | |
32e2b59f TW |
186 | */ |
187 | static u32 mei_txe_aliveness_req_get(struct mei_device *dev) | |
188 | { | |
189 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
190 | u32 reg; | |
92db1555 | 191 | |
32e2b59f TW |
192 | reg = mei_txe_br_reg_read(hw, SICR_HOST_ALIVENESS_REQ_REG); |
193 | return reg & SICR_HOST_ALIVENESS_REQ_REQUESTED; | |
194 | } | |
195 | ||
196 | /** | |
197 | * mei_txe_aliveness_get - get aliveness response register value | |
ce23139c | 198 | * |
32e2b59f TW |
199 | * @dev: the device structure |
200 | * | |
ce23139c AU |
201 | * Return: HICR_HOST_ALIVENESS_RESP_ACK bit from HICR_HOST_ALIVENESS_RESP |
202 | * register | |
32e2b59f TW |
203 | */ |
204 | static u32 mei_txe_aliveness_get(struct mei_device *dev) | |
205 | { | |
206 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
207 | u32 reg; | |
92db1555 | 208 | |
32e2b59f TW |
209 | reg = mei_txe_br_reg_read(hw, HICR_HOST_ALIVENESS_RESP_REG); |
210 | return reg & HICR_HOST_ALIVENESS_RESP_ACK; | |
211 | } | |
212 | ||
213 | /** | |
214 | * mei_txe_aliveness_poll - waits for aliveness to settle | |
215 | * | |
216 | * @dev: the device structure | |
217 | * @expected: expected aliveness value | |
218 | * | |
219 | * Polls for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set | |
a8605ea2 AU |
220 | * |
221 | * Return: > 0 if the expected value was received, -ETIME otherwise | |
32e2b59f TW |
222 | */ |
223 | static int mei_txe_aliveness_poll(struct mei_device *dev, u32 expected) | |
224 | { | |
225 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
226 | int t = 0; | |
227 | ||
228 | do { | |
229 | hw->aliveness = mei_txe_aliveness_get(dev); | |
230 | if (hw->aliveness == expected) { | |
964a2331 | 231 | dev->pg_event = MEI_PG_EVENT_IDLE; |
2bf94cab | 232 | dev_dbg(dev->dev, |
32e2b59f TW |
233 | "aliveness settled after %d msecs\n", t); |
234 | return t; | |
235 | } | |
236 | mutex_unlock(&dev->device_lock); | |
237 | msleep(MSEC_PER_SEC / 5); | |
238 | mutex_lock(&dev->device_lock); | |
239 | t += MSEC_PER_SEC / 5; | |
240 | } while (t < SEC_ALIVENESS_WAIT_TIMEOUT); | |
241 | ||
964a2331 | 242 | dev->pg_event = MEI_PG_EVENT_IDLE; |
2bf94cab | 243 | dev_err(dev->dev, "aliveness timed out\n"); |
32e2b59f TW |
244 | return -ETIME; |
245 | } | |
246 | ||
247 | /** | |
248 | * mei_txe_aliveness_wait - waits for aliveness to settle | |
249 | * | |
250 | * @dev: the device structure | |
251 | * @expected: expected aliveness value | |
252 | * | |
253 | * Waits for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set | |
a8605ea2 AU |
254 | * |
255 | * Return: 0 on success and < 0 otherwise | |
32e2b59f TW |
256 | */ |
257 | static int mei_txe_aliveness_wait(struct mei_device *dev, u32 expected) | |
258 | { | |
259 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
260 | const unsigned long timeout = | |
261 | msecs_to_jiffies(SEC_ALIVENESS_WAIT_TIMEOUT); | |
262 | long err; | |
263 | int ret; | |
264 | ||
265 | hw->aliveness = mei_txe_aliveness_get(dev); | |
266 | if (hw->aliveness == expected) | |
267 | return 0; | |
268 | ||
269 | mutex_unlock(&dev->device_lock); | |
964a2331 TW |
270 | err = wait_event_timeout(hw->wait_aliveness_resp, |
271 | dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); | |
32e2b59f TW |
272 | mutex_lock(&dev->device_lock); |
273 | ||
274 | hw->aliveness = mei_txe_aliveness_get(dev); | |
275 | ret = hw->aliveness == expected ? 0 : -ETIME; | |
276 | ||
277 | if (ret) | |
2bf94cab | 278 | dev_warn(dev->dev, "aliveness timed out = %ld aliveness = %d event = %d\n", |
964a2331 | 279 | err, hw->aliveness, dev->pg_event); |
32e2b59f | 280 | else |
2bf94cab | 281 | dev_dbg(dev->dev, "aliveness settled after = %d msec aliveness = %d event = %d\n", |
964a2331 TW |
282 | jiffies_to_msecs(timeout - err), |
283 | hw->aliveness, dev->pg_event); | |
284 | ||
285 | dev->pg_event = MEI_PG_EVENT_IDLE; | |
32e2b59f TW |
286 | return ret; |
287 | } | |
288 | ||
289 | /** | |
290 | * mei_txe_aliveness_set_sync - sets an wait for aliveness to complete | |
291 | * | |
292 | * @dev: the device structure | |
ce23139c | 293 | * @req: requested aliveness value |
32e2b59f | 294 | * |
a8605ea2 | 295 | * Return: 0 on success and < 0 otherwise |
32e2b59f TW |
296 | */ |
297 | int mei_txe_aliveness_set_sync(struct mei_device *dev, u32 req) | |
298 | { | |
299 | if (mei_txe_aliveness_set(dev, req)) | |
300 | return mei_txe_aliveness_wait(dev, req); | |
301 | return 0; | |
302 | } | |
303 | ||
ee7e5afd TW |
304 | /** |
305 | * mei_txe_pg_is_enabled - detect if PG is supported by HW | |
306 | * | |
307 | * @dev: the device structure | |
308 | * | |
a8605ea2 | 309 | * Return: true is pg supported, false otherwise |
ee7e5afd TW |
310 | */ |
311 | static bool mei_txe_pg_is_enabled(struct mei_device *dev) | |
312 | { | |
313 | return true; | |
314 | } | |
315 | ||
964a2331 TW |
316 | /** |
317 | * mei_txe_pg_state - translate aliveness register value | |
318 | * to the mei power gating state | |
319 | * | |
320 | * @dev: the device structure | |
321 | * | |
a8605ea2 | 322 | * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise |
964a2331 TW |
323 | */ |
324 | static inline enum mei_pg_state mei_txe_pg_state(struct mei_device *dev) | |
325 | { | |
326 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 327 | |
964a2331 TW |
328 | return hw->aliveness ? MEI_PG_OFF : MEI_PG_ON; |
329 | } | |
330 | ||
32e2b59f TW |
331 | /** |
332 | * mei_txe_input_ready_interrupt_enable - sets the Input Ready Interrupt | |
333 | * | |
334 | * @dev: the device structure | |
335 | */ | |
336 | static void mei_txe_input_ready_interrupt_enable(struct mei_device *dev) | |
337 | { | |
338 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
339 | u32 hintmsk; | |
340 | /* Enable the SEC_IPC_HOST_INT_MASK_IN_RDY interrupt */ | |
341 | hintmsk = mei_txe_sec_reg_read(hw, SEC_IPC_HOST_INT_MASK_REG); | |
342 | hintmsk |= SEC_IPC_HOST_INT_MASK_IN_RDY; | |
343 | mei_txe_sec_reg_write(hw, SEC_IPC_HOST_INT_MASK_REG, hintmsk); | |
344 | } | |
345 | ||
346 | /** | |
a8605ea2 AU |
347 | * mei_txe_input_doorbell_set - sets bit 0 in |
348 | * SEC_IPC_INPUT_DOORBELL.IPC_INPUT_DOORBELL. | |
349 | * | |
350 | * @hw: the txe hardware structure | |
32e2b59f TW |
351 | */ |
352 | static void mei_txe_input_doorbell_set(struct mei_txe_hw *hw) | |
353 | { | |
354 | /* Clear the interrupt cause */ | |
355 | clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause); | |
356 | mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_DOORBELL_REG, 1); | |
357 | } | |
358 | ||
359 | /** | |
360 | * mei_txe_output_ready_set - Sets the SICR_SEC_IPC_OUTPUT_STATUS bit to 1 | |
361 | * | |
a8605ea2 | 362 | * @hw: the txe hardware structure |
32e2b59f TW |
363 | */ |
364 | static void mei_txe_output_ready_set(struct mei_txe_hw *hw) | |
365 | { | |
366 | mei_txe_br_reg_write(hw, | |
367 | SICR_SEC_IPC_OUTPUT_STATUS_REG, | |
368 | SEC_IPC_OUTPUT_STATUS_RDY); | |
369 | } | |
370 | ||
371 | /** | |
372 | * mei_txe_is_input_ready - check if TXE is ready for receiving data | |
373 | * | |
374 | * @dev: the device structure | |
ce23139c AU |
375 | * |
376 | * Return: true if INPUT STATUS READY bit is set | |
32e2b59f TW |
377 | */ |
378 | static bool mei_txe_is_input_ready(struct mei_device *dev) | |
379 | { | |
380 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
381 | u32 status; | |
92db1555 | 382 | |
32e2b59f TW |
383 | status = mei_txe_sec_reg_read(hw, SEC_IPC_INPUT_STATUS_REG); |
384 | return !!(SEC_IPC_INPUT_STATUS_RDY & status); | |
385 | } | |
386 | ||
387 | /** | |
388 | * mei_txe_intr_clear - clear all interrupts | |
389 | * | |
390 | * @dev: the device structure | |
391 | */ | |
392 | static inline void mei_txe_intr_clear(struct mei_device *dev) | |
393 | { | |
394 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 395 | |
32e2b59f TW |
396 | mei_txe_sec_reg_write_silent(hw, SEC_IPC_HOST_INT_STATUS_REG, |
397 | SEC_IPC_HOST_INT_STATUS_PENDING); | |
398 | mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_STS_MSK); | |
399 | mei_txe_br_reg_write(hw, HHISR_REG, IPC_HHIER_MSK); | |
400 | } | |
401 | ||
402 | /** | |
403 | * mei_txe_intr_disable - disable all interrupts | |
404 | * | |
405 | * @dev: the device structure | |
406 | */ | |
407 | static void mei_txe_intr_disable(struct mei_device *dev) | |
408 | { | |
409 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 410 | |
32e2b59f TW |
411 | mei_txe_br_reg_write(hw, HHIER_REG, 0); |
412 | mei_txe_br_reg_write(hw, HIER_REG, 0); | |
413 | } | |
414 | /** | |
415 | * mei_txe_intr_disable - enable all interrupts | |
416 | * | |
417 | * @dev: the device structure | |
418 | */ | |
419 | static void mei_txe_intr_enable(struct mei_device *dev) | |
420 | { | |
421 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 422 | |
32e2b59f TW |
423 | mei_txe_br_reg_write(hw, HHIER_REG, IPC_HHIER_MSK); |
424 | mei_txe_br_reg_write(hw, HIER_REG, HIER_INT_EN_MSK); | |
425 | } | |
426 | ||
427 | /** | |
428 | * mei_txe_pending_interrupts - check if there are pending interrupts | |
429 | * only Aliveness, Input ready, and output doorbell are of relevance | |
430 | * | |
431 | * @dev: the device structure | |
432 | * | |
433 | * Checks if there are pending interrupts | |
434 | * only Aliveness, Readiness, Input ready, and Output doorbell are relevant | |
ce23139c AU |
435 | * |
436 | * Return: true if there are pending interrupts | |
32e2b59f TW |
437 | */ |
438 | static bool mei_txe_pending_interrupts(struct mei_device *dev) | |
439 | { | |
440 | ||
441 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
442 | bool ret = (hw->intr_cause & (TXE_INTR_READINESS | | |
443 | TXE_INTR_ALIVENESS | | |
444 | TXE_INTR_IN_READY | | |
445 | TXE_INTR_OUT_DB)); | |
446 | ||
447 | if (ret) { | |
2bf94cab | 448 | dev_dbg(dev->dev, |
32e2b59f TW |
449 | "Pending Interrupts InReady=%01d Readiness=%01d, Aliveness=%01d, OutDoor=%01d\n", |
450 | !!(hw->intr_cause & TXE_INTR_IN_READY), | |
451 | !!(hw->intr_cause & TXE_INTR_READINESS), | |
452 | !!(hw->intr_cause & TXE_INTR_ALIVENESS), | |
453 | !!(hw->intr_cause & TXE_INTR_OUT_DB)); | |
454 | } | |
455 | return ret; | |
456 | } | |
457 | ||
458 | /** | |
459 | * mei_txe_input_payload_write - write a dword to the host buffer | |
460 | * at offset idx | |
461 | * | |
462 | * @dev: the device structure | |
463 | * @idx: index in the host buffer | |
464 | * @value: value | |
465 | */ | |
466 | static void mei_txe_input_payload_write(struct mei_device *dev, | |
467 | unsigned long idx, u32 value) | |
468 | { | |
469 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 470 | |
32e2b59f TW |
471 | mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_PAYLOAD_REG + |
472 | (idx * sizeof(u32)), value); | |
473 | } | |
474 | ||
475 | /** | |
476 | * mei_txe_out_data_read - read dword from the device buffer | |
477 | * at offset idx | |
478 | * | |
479 | * @dev: the device structure | |
480 | * @idx: index in the device buffer | |
481 | * | |
a8605ea2 | 482 | * Return: register value at index |
32e2b59f TW |
483 | */ |
484 | static u32 mei_txe_out_data_read(const struct mei_device *dev, | |
485 | unsigned long idx) | |
486 | { | |
487 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 488 | |
32e2b59f TW |
489 | return mei_txe_br_reg_read(hw, |
490 | BRIDGE_IPC_OUTPUT_PAYLOAD_REG + (idx * sizeof(u32))); | |
491 | } | |
492 | ||
493 | /* Readiness */ | |
494 | ||
495 | /** | |
ce23139c | 496 | * mei_txe_readiness_set_host_rdy - set host readiness bit |
32e2b59f TW |
497 | * |
498 | * @dev: the device structure | |
499 | */ | |
500 | static void mei_txe_readiness_set_host_rdy(struct mei_device *dev) | |
501 | { | |
502 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 503 | |
32e2b59f TW |
504 | mei_txe_br_reg_write(hw, |
505 | SICR_HOST_IPC_READINESS_REQ_REG, | |
506 | SICR_HOST_IPC_READINESS_HOST_RDY); | |
507 | } | |
508 | ||
509 | /** | |
ce23139c | 510 | * mei_txe_readiness_clear - clear host readiness bit |
32e2b59f TW |
511 | * |
512 | * @dev: the device structure | |
513 | */ | |
514 | static void mei_txe_readiness_clear(struct mei_device *dev) | |
515 | { | |
516 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 517 | |
32e2b59f TW |
518 | mei_txe_br_reg_write(hw, SICR_HOST_IPC_READINESS_REQ_REG, |
519 | SICR_HOST_IPC_READINESS_RDY_CLR); | |
520 | } | |
521 | /** | |
522 | * mei_txe_readiness_get - Reads and returns | |
523 | * the HICR_SEC_IPC_READINESS register value | |
524 | * | |
525 | * @dev: the device structure | |
a8605ea2 AU |
526 | * |
527 | * Return: the HICR_SEC_IPC_READINESS register value | |
32e2b59f TW |
528 | */ |
529 | static u32 mei_txe_readiness_get(struct mei_device *dev) | |
530 | { | |
531 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 532 | |
32e2b59f TW |
533 | return mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG); |
534 | } | |
535 | ||
536 | ||
537 | /** | |
538 | * mei_txe_readiness_is_sec_rdy - check readiness | |
539 | * for HICR_SEC_IPC_READINESS_SEC_RDY | |
540 | * | |
ce23139c AU |
541 | * @readiness: cached readiness state |
542 | * | |
543 | * Return: true if readiness bit is set | |
32e2b59f TW |
544 | */ |
545 | static inline bool mei_txe_readiness_is_sec_rdy(u32 readiness) | |
546 | { | |
547 | return !!(readiness & HICR_SEC_IPC_READINESS_SEC_RDY); | |
548 | } | |
549 | ||
550 | /** | |
551 | * mei_txe_hw_is_ready - check if the hw is ready | |
552 | * | |
553 | * @dev: the device structure | |
ce23139c AU |
554 | * |
555 | * Return: true if sec is ready | |
32e2b59f TW |
556 | */ |
557 | static bool mei_txe_hw_is_ready(struct mei_device *dev) | |
558 | { | |
559 | u32 readiness = mei_txe_readiness_get(dev); | |
92db1555 | 560 | |
32e2b59f TW |
561 | return mei_txe_readiness_is_sec_rdy(readiness); |
562 | } | |
563 | ||
564 | /** | |
565 | * mei_txe_host_is_ready - check if the host is ready | |
566 | * | |
567 | * @dev: the device structure | |
ce23139c AU |
568 | * |
569 | * Return: true if host is ready | |
32e2b59f TW |
570 | */ |
571 | static inline bool mei_txe_host_is_ready(struct mei_device *dev) | |
572 | { | |
573 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
574 | u32 reg = mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG); | |
92db1555 | 575 | |
32e2b59f TW |
576 | return !!(reg & HICR_SEC_IPC_READINESS_HOST_RDY); |
577 | } | |
578 | ||
579 | /** | |
580 | * mei_txe_readiness_wait - wait till readiness settles | |
581 | * | |
582 | * @dev: the device structure | |
583 | * | |
a8605ea2 | 584 | * Return: 0 on success and -ETIME on timeout |
32e2b59f TW |
585 | */ |
586 | static int mei_txe_readiness_wait(struct mei_device *dev) | |
587 | { | |
588 | if (mei_txe_hw_is_ready(dev)) | |
589 | return 0; | |
590 | ||
591 | mutex_unlock(&dev->device_lock); | |
592 | wait_event_timeout(dev->wait_hw_ready, dev->recvd_hw_ready, | |
593 | msecs_to_jiffies(SEC_RESET_WAIT_TIMEOUT)); | |
594 | mutex_lock(&dev->device_lock); | |
595 | if (!dev->recvd_hw_ready) { | |
2bf94cab | 596 | dev_err(dev->dev, "wait for readiness failed\n"); |
32e2b59f TW |
597 | return -ETIME; |
598 | } | |
599 | ||
600 | dev->recvd_hw_ready = false; | |
601 | return 0; | |
602 | } | |
603 | ||
4ad96db6 TW |
604 | const struct mei_fw_status mei_txe_fw_sts = { |
605 | .count = 2, | |
606 | .status[0] = PCI_CFG_TXE_FW_STS0, | |
607 | .status[1] = PCI_CFG_TXE_FW_STS1 | |
608 | }; | |
1bd30b6a TW |
609 | |
610 | /** | |
611 | * mei_txe_fw_status - read fw status register from pci config space | |
612 | * | |
613 | * @dev: mei device | |
614 | * @fw_status: fw status register values | |
ce23139c AU |
615 | * |
616 | * Return: 0 on success, error otherwise | |
1bd30b6a TW |
617 | */ |
618 | static int mei_txe_fw_status(struct mei_device *dev, | |
619 | struct mei_fw_status *fw_status) | |
620 | { | |
4ad96db6 | 621 | const struct mei_fw_status *fw_src = &mei_txe_fw_sts; |
1bd30b6a TW |
622 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
623 | int ret; | |
624 | int i; | |
625 | ||
626 | if (!fw_status) | |
627 | return -EINVAL; | |
628 | ||
629 | fw_status->count = fw_src->count; | |
630 | for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) { | |
631 | ret = pci_read_config_dword(pdev, | |
632 | fw_src->status[i], &fw_status->status[i]); | |
633 | if (ret) | |
634 | return ret; | |
635 | } | |
636 | ||
637 | return 0; | |
638 | } | |
639 | ||
32e2b59f TW |
640 | /** |
641 | * mei_txe_hw_config - configure hardware at the start of the devices | |
642 | * | |
643 | * @dev: the device structure | |
644 | * | |
645 | * Configure hardware at the start of the device should be done only | |
646 | * once at the device probe time | |
647 | */ | |
648 | static void mei_txe_hw_config(struct mei_device *dev) | |
649 | { | |
650 | ||
651 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 652 | |
32e2b59f TW |
653 | /* Doesn't change in runtime */ |
654 | dev->hbuf_depth = PAYLOAD_SIZE / 4; | |
655 | ||
656 | hw->aliveness = mei_txe_aliveness_get(dev); | |
657 | hw->readiness = mei_txe_readiness_get(dev); | |
658 | ||
2bf94cab | 659 | dev_dbg(dev->dev, "aliveness_resp = 0x%08x, readiness = 0x%08x.\n", |
32e2b59f TW |
660 | hw->aliveness, hw->readiness); |
661 | } | |
662 | ||
663 | ||
664 | /** | |
665 | * mei_txe_write - writes a message to device. | |
666 | * | |
667 | * @dev: the device structure | |
668 | * @header: header of message | |
669 | * @buf: message buffer will be written | |
a8605ea2 | 670 | * |
ce23139c | 671 | * Return: 0 if success, <0 - otherwise. |
32e2b59f TW |
672 | */ |
673 | ||
674 | static int mei_txe_write(struct mei_device *dev, | |
675 | struct mei_msg_hdr *header, unsigned char *buf) | |
676 | { | |
677 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
678 | unsigned long rem; | |
679 | unsigned long length; | |
9d098192 | 680 | int slots = dev->hbuf_depth; |
32e2b59f | 681 | u32 *reg_buf = (u32 *)buf; |
9d098192 | 682 | u32 dw_cnt; |
32e2b59f TW |
683 | int i; |
684 | ||
685 | if (WARN_ON(!header || !buf)) | |
686 | return -EINVAL; | |
687 | ||
688 | length = header->length; | |
689 | ||
2bf94cab | 690 | dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header)); |
32e2b59f | 691 | |
9d098192 TW |
692 | dw_cnt = mei_data2slots(length); |
693 | if (dw_cnt > slots) | |
694 | return -EMSGSIZE; | |
32e2b59f TW |
695 | |
696 | if (WARN(!hw->aliveness, "txe write: aliveness not asserted\n")) | |
697 | return -EAGAIN; | |
698 | ||
699 | /* Enable Input Ready Interrupt. */ | |
700 | mei_txe_input_ready_interrupt_enable(dev); | |
701 | ||
702 | if (!mei_txe_is_input_ready(dev)) { | |
04dd3661 | 703 | struct mei_fw_status fw_status; |
92db1555 | 704 | |
04dd3661 | 705 | mei_fw_status(dev, &fw_status); |
2bf94cab | 706 | dev_err(dev->dev, "Input is not ready " FW_STS_FMT "\n", |
04dd3661 | 707 | FW_STS_PRM(fw_status)); |
32e2b59f TW |
708 | return -EAGAIN; |
709 | } | |
710 | ||
711 | mei_txe_input_payload_write(dev, 0, *((u32 *)header)); | |
712 | ||
713 | for (i = 0; i < length / 4; i++) | |
714 | mei_txe_input_payload_write(dev, i + 1, reg_buf[i]); | |
715 | ||
716 | rem = length & 0x3; | |
717 | if (rem > 0) { | |
718 | u32 reg = 0; | |
92db1555 | 719 | |
32e2b59f TW |
720 | memcpy(®, &buf[length - rem], rem); |
721 | mei_txe_input_payload_write(dev, i + 1, reg); | |
722 | } | |
723 | ||
9d098192 TW |
724 | /* after each write the whole buffer is consumed */ |
725 | hw->slots = 0; | |
726 | ||
32e2b59f TW |
727 | /* Set Input-Doorbell */ |
728 | mei_txe_input_doorbell_set(hw); | |
729 | ||
730 | return 0; | |
731 | } | |
732 | ||
733 | /** | |
734 | * mei_txe_hbuf_max_len - mimics the me hbuf circular buffer | |
735 | * | |
736 | * @dev: the device structure | |
737 | * | |
ce23139c | 738 | * Return: the PAYLOAD_SIZE - 4 |
32e2b59f TW |
739 | */ |
740 | static size_t mei_txe_hbuf_max_len(const struct mei_device *dev) | |
741 | { | |
742 | return PAYLOAD_SIZE - sizeof(struct mei_msg_hdr); | |
743 | } | |
744 | ||
745 | /** | |
746 | * mei_txe_hbuf_empty_slots - mimics the me hbuf circular buffer | |
747 | * | |
748 | * @dev: the device structure | |
749 | * | |
a8605ea2 | 750 | * Return: always hbuf_depth |
32e2b59f TW |
751 | */ |
752 | static int mei_txe_hbuf_empty_slots(struct mei_device *dev) | |
753 | { | |
9d098192 | 754 | struct mei_txe_hw *hw = to_txe_hw(dev); |
92db1555 | 755 | |
9d098192 | 756 | return hw->slots; |
32e2b59f TW |
757 | } |
758 | ||
759 | /** | |
760 | * mei_txe_count_full_read_slots - mimics the me device circular buffer | |
761 | * | |
762 | * @dev: the device structure | |
763 | * | |
a8605ea2 | 764 | * Return: always buffer size in dwords count |
32e2b59f TW |
765 | */ |
766 | static int mei_txe_count_full_read_slots(struct mei_device *dev) | |
767 | { | |
768 | /* read buffers has static size */ | |
769 | return PAYLOAD_SIZE / 4; | |
770 | } | |
771 | ||
772 | /** | |
773 | * mei_txe_read_hdr - read message header which is always in 4 first bytes | |
774 | * | |
775 | * @dev: the device structure | |
776 | * | |
a8605ea2 | 777 | * Return: mei message header |
32e2b59f TW |
778 | */ |
779 | ||
780 | static u32 mei_txe_read_hdr(const struct mei_device *dev) | |
781 | { | |
782 | return mei_txe_out_data_read(dev, 0); | |
783 | } | |
784 | /** | |
785 | * mei_txe_read - reads a message from the txe device. | |
786 | * | |
787 | * @dev: the device structure | |
788 | * @buf: message buffer will be written | |
789 | * @len: message size will be read | |
790 | * | |
a8605ea2 | 791 | * Return: -EINVAL on error wrong argument and 0 on success |
32e2b59f TW |
792 | */ |
793 | static int mei_txe_read(struct mei_device *dev, | |
794 | unsigned char *buf, unsigned long len) | |
795 | { | |
796 | ||
797 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 TW |
798 | u32 *reg_buf, reg; |
799 | u32 rem; | |
32e2b59f | 800 | u32 i; |
32e2b59f TW |
801 | |
802 | if (WARN_ON(!buf || !len)) | |
803 | return -EINVAL; | |
804 | ||
92db1555 TW |
805 | reg_buf = (u32 *)buf; |
806 | rem = len & 0x3; | |
807 | ||
2bf94cab | 808 | dev_dbg(dev->dev, "buffer-length = %lu buf[0]0x%08X\n", |
32e2b59f TW |
809 | len, mei_txe_out_data_read(dev, 0)); |
810 | ||
811 | for (i = 0; i < len / 4; i++) { | |
812 | /* skip header: index starts from 1 */ | |
92db1555 | 813 | reg = mei_txe_out_data_read(dev, i + 1); |
2bf94cab | 814 | dev_dbg(dev->dev, "buf[%d] = 0x%08X\n", i, reg); |
32e2b59f TW |
815 | *reg_buf++ = reg; |
816 | } | |
817 | ||
818 | if (rem) { | |
92db1555 | 819 | reg = mei_txe_out_data_read(dev, i + 1); |
32e2b59f TW |
820 | memcpy(reg_buf, ®, rem); |
821 | } | |
822 | ||
823 | mei_txe_output_ready_set(hw); | |
824 | return 0; | |
825 | } | |
826 | ||
827 | /** | |
828 | * mei_txe_hw_reset - resets host and fw. | |
829 | * | |
830 | * @dev: the device structure | |
831 | * @intr_enable: if interrupt should be enabled after reset. | |
832 | * | |
a8605ea2 | 833 | * Return: 0 on success and < 0 in case of error |
32e2b59f TW |
834 | */ |
835 | static int mei_txe_hw_reset(struct mei_device *dev, bool intr_enable) | |
836 | { | |
837 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
838 | ||
839 | u32 aliveness_req; | |
840 | /* | |
841 | * read input doorbell to ensure consistency between Bridge and SeC | |
842 | * return value might be garbage return | |
843 | */ | |
844 | (void)mei_txe_sec_reg_read_silent(hw, SEC_IPC_INPUT_DOORBELL_REG); | |
845 | ||
846 | aliveness_req = mei_txe_aliveness_req_get(dev); | |
847 | hw->aliveness = mei_txe_aliveness_get(dev); | |
848 | ||
849 | /* Disable interrupts in this stage we will poll */ | |
850 | mei_txe_intr_disable(dev); | |
851 | ||
852 | /* | |
853 | * If Aliveness Request and Aliveness Response are not equal then | |
854 | * wait for them to be equal | |
855 | * Since we might have interrupts disabled - poll for it | |
856 | */ | |
857 | if (aliveness_req != hw->aliveness) | |
858 | if (mei_txe_aliveness_poll(dev, aliveness_req) < 0) { | |
2bf94cab | 859 | dev_err(dev->dev, "wait for aliveness settle failed ... bailing out\n"); |
32e2b59f TW |
860 | return -EIO; |
861 | } | |
862 | ||
863 | /* | |
864 | * If Aliveness Request and Aliveness Response are set then clear them | |
865 | */ | |
866 | if (aliveness_req) { | |
867 | mei_txe_aliveness_set(dev, 0); | |
868 | if (mei_txe_aliveness_poll(dev, 0) < 0) { | |
2bf94cab | 869 | dev_err(dev->dev, "wait for aliveness failed ... bailing out\n"); |
32e2b59f TW |
870 | return -EIO; |
871 | } | |
872 | } | |
873 | ||
874 | /* | |
0a01e974 | 875 | * Set readiness RDY_CLR bit |
32e2b59f TW |
876 | */ |
877 | mei_txe_readiness_clear(dev); | |
878 | ||
879 | return 0; | |
880 | } | |
881 | ||
882 | /** | |
883 | * mei_txe_hw_start - start the hardware after reset | |
884 | * | |
885 | * @dev: the device structure | |
886 | * | |
ce23139c | 887 | * Return: 0 on success an error code otherwise |
32e2b59f TW |
888 | */ |
889 | static int mei_txe_hw_start(struct mei_device *dev) | |
890 | { | |
891 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
892 | int ret; | |
893 | ||
894 | u32 hisr; | |
895 | ||
896 | /* bring back interrupts */ | |
897 | mei_txe_intr_enable(dev); | |
898 | ||
899 | ret = mei_txe_readiness_wait(dev); | |
900 | if (ret < 0) { | |
0a01e974 | 901 | dev_err(dev->dev, "waiting for readiness failed\n"); |
32e2b59f TW |
902 | return ret; |
903 | } | |
904 | ||
905 | /* | |
906 | * If HISR.INT2_STS interrupt status bit is set then clear it. | |
907 | */ | |
908 | hisr = mei_txe_br_reg_read(hw, HISR_REG); | |
909 | if (hisr & HISR_INT_2_STS) | |
910 | mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_2_STS); | |
911 | ||
912 | /* Clear the interrupt cause of OutputDoorbell */ | |
913 | clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause); | |
914 | ||
915 | ret = mei_txe_aliveness_set_sync(dev, 1); | |
916 | if (ret < 0) { | |
2bf94cab | 917 | dev_err(dev->dev, "wait for aliveness failed ... bailing out\n"); |
32e2b59f TW |
918 | return ret; |
919 | } | |
920 | ||
921 | /* enable input ready interrupts: | |
922 | * SEC_IPC_HOST_INT_MASK.IPC_INPUT_READY_INT_MASK | |
923 | */ | |
924 | mei_txe_input_ready_interrupt_enable(dev); | |
925 | ||
926 | ||
927 | /* Set the SICR_SEC_IPC_OUTPUT_STATUS.IPC_OUTPUT_READY bit */ | |
928 | mei_txe_output_ready_set(hw); | |
929 | ||
930 | /* Set bit SICR_HOST_IPC_READINESS.HOST_RDY | |
931 | */ | |
932 | mei_txe_readiness_set_host_rdy(dev); | |
933 | ||
934 | return 0; | |
935 | } | |
936 | ||
937 | /** | |
938 | * mei_txe_check_and_ack_intrs - translate multi BAR interrupt into | |
939 | * single bit mask and acknowledge the interrupts | |
940 | * | |
941 | * @dev: the device structure | |
942 | * @do_ack: acknowledge interrupts | |
ce23139c AU |
943 | * |
944 | * Return: true if found interrupts to process. | |
32e2b59f TW |
945 | */ |
946 | static bool mei_txe_check_and_ack_intrs(struct mei_device *dev, bool do_ack) | |
947 | { | |
948 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
949 | u32 hisr; | |
950 | u32 hhisr; | |
951 | u32 ipc_isr; | |
952 | u32 aliveness; | |
953 | bool generated; | |
954 | ||
955 | /* read interrupt registers */ | |
956 | hhisr = mei_txe_br_reg_read(hw, HHISR_REG); | |
957 | generated = (hhisr & IPC_HHIER_MSK); | |
958 | if (!generated) | |
959 | goto out; | |
960 | ||
961 | hisr = mei_txe_br_reg_read(hw, HISR_REG); | |
962 | ||
963 | aliveness = mei_txe_aliveness_get(dev); | |
964 | if (hhisr & IPC_HHIER_SEC && aliveness) | |
965 | ipc_isr = mei_txe_sec_reg_read_silent(hw, | |
966 | SEC_IPC_HOST_INT_STATUS_REG); | |
967 | else | |
968 | ipc_isr = 0; | |
969 | ||
970 | generated = generated || | |
971 | (hisr & HISR_INT_STS_MSK) || | |
972 | (ipc_isr & SEC_IPC_HOST_INT_STATUS_PENDING); | |
973 | ||
974 | if (generated && do_ack) { | |
975 | /* Save the interrupt causes */ | |
976 | hw->intr_cause |= hisr & HISR_INT_STS_MSK; | |
977 | if (ipc_isr & SEC_IPC_HOST_INT_STATUS_IN_RDY) | |
978 | hw->intr_cause |= TXE_INTR_IN_READY; | |
979 | ||
980 | ||
981 | mei_txe_intr_disable(dev); | |
982 | /* Clear the interrupts in hierarchy: | |
983 | * IPC and Bridge, than the High Level */ | |
984 | mei_txe_sec_reg_write_silent(hw, | |
985 | SEC_IPC_HOST_INT_STATUS_REG, ipc_isr); | |
986 | mei_txe_br_reg_write(hw, HISR_REG, hisr); | |
987 | mei_txe_br_reg_write(hw, HHISR_REG, hhisr); | |
988 | } | |
989 | ||
990 | out: | |
991 | return generated; | |
992 | } | |
993 | ||
994 | /** | |
995 | * mei_txe_irq_quick_handler - The ISR of the MEI device | |
996 | * | |
997 | * @irq: The irq number | |
998 | * @dev_id: pointer to the device structure | |
999 | * | |
a8605ea2 AU |
1000 | * Return: IRQ_WAKE_THREAD if interrupt is designed for the device |
1001 | * IRQ_NONE otherwise | |
32e2b59f TW |
1002 | */ |
1003 | irqreturn_t mei_txe_irq_quick_handler(int irq, void *dev_id) | |
1004 | { | |
1005 | struct mei_device *dev = dev_id; | |
1006 | ||
1007 | if (mei_txe_check_and_ack_intrs(dev, true)) | |
1008 | return IRQ_WAKE_THREAD; | |
1009 | return IRQ_NONE; | |
1010 | } | |
1011 | ||
1012 | ||
1013 | /** | |
1014 | * mei_txe_irq_thread_handler - txe interrupt thread | |
1015 | * | |
1016 | * @irq: The irq number | |
1017 | * @dev_id: pointer to the device structure | |
1018 | * | |
a8605ea2 | 1019 | * Return: IRQ_HANDLED |
32e2b59f TW |
1020 | */ |
1021 | irqreturn_t mei_txe_irq_thread_handler(int irq, void *dev_id) | |
1022 | { | |
1023 | struct mei_device *dev = (struct mei_device *) dev_id; | |
1024 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
1025 | struct mei_cl_cb complete_list; | |
1026 | s32 slots; | |
1027 | int rets = 0; | |
1028 | ||
2bf94cab | 1029 | dev_dbg(dev->dev, "irq thread: Interrupt Registers HHISR|HISR|SEC=%02X|%04X|%02X\n", |
32e2b59f TW |
1030 | mei_txe_br_reg_read(hw, HHISR_REG), |
1031 | mei_txe_br_reg_read(hw, HISR_REG), | |
1032 | mei_txe_sec_reg_read_silent(hw, SEC_IPC_HOST_INT_STATUS_REG)); | |
1033 | ||
1034 | ||
1035 | /* initialize our complete list */ | |
1036 | mutex_lock(&dev->device_lock); | |
1037 | mei_io_list_init(&complete_list); | |
1038 | ||
d08b8fc0 | 1039 | if (pci_dev_msi_enabled(to_pci_dev(dev->dev))) |
32e2b59f TW |
1040 | mei_txe_check_and_ack_intrs(dev, true); |
1041 | ||
1042 | /* show irq events */ | |
1043 | mei_txe_pending_interrupts(dev); | |
1044 | ||
1045 | hw->aliveness = mei_txe_aliveness_get(dev); | |
1046 | hw->readiness = mei_txe_readiness_get(dev); | |
1047 | ||
1048 | /* Readiness: | |
1049 | * Detection of TXE driver going through reset | |
1050 | * or TXE driver resetting the HECI interface. | |
1051 | */ | |
1052 | if (test_and_clear_bit(TXE_INTR_READINESS_BIT, &hw->intr_cause)) { | |
2bf94cab | 1053 | dev_dbg(dev->dev, "Readiness Interrupt was received...\n"); |
32e2b59f TW |
1054 | |
1055 | /* Check if SeC is going through reset */ | |
1056 | if (mei_txe_readiness_is_sec_rdy(hw->readiness)) { | |
2bf94cab | 1057 | dev_dbg(dev->dev, "we need to start the dev.\n"); |
32e2b59f TW |
1058 | dev->recvd_hw_ready = true; |
1059 | } else { | |
1060 | dev->recvd_hw_ready = false; | |
1061 | if (dev->dev_state != MEI_DEV_RESETTING) { | |
1062 | ||
2bf94cab | 1063 | dev_warn(dev->dev, "FW not ready: resetting.\n"); |
32e2b59f TW |
1064 | schedule_work(&dev->reset_work); |
1065 | goto end; | |
1066 | ||
1067 | } | |
1068 | } | |
1069 | wake_up(&dev->wait_hw_ready); | |
1070 | } | |
1071 | ||
1072 | /************************************************************/ | |
1073 | /* Check interrupt cause: | |
1074 | * Aliveness: Detection of SeC acknowledge of host request that | |
1075 | * it remain alive or host cancellation of that request. | |
1076 | */ | |
1077 | ||
1078 | if (test_and_clear_bit(TXE_INTR_ALIVENESS_BIT, &hw->intr_cause)) { | |
1079 | /* Clear the interrupt cause */ | |
2bf94cab | 1080 | dev_dbg(dev->dev, |
32e2b59f | 1081 | "Aliveness Interrupt: Status: %d\n", hw->aliveness); |
964a2331 TW |
1082 | dev->pg_event = MEI_PG_EVENT_RECEIVED; |
1083 | if (waitqueue_active(&hw->wait_aliveness_resp)) | |
1084 | wake_up(&hw->wait_aliveness_resp); | |
32e2b59f TW |
1085 | } |
1086 | ||
1087 | ||
1088 | /* Output Doorbell: | |
1089 | * Detection of SeC having sent output to host | |
1090 | */ | |
1091 | slots = mei_count_full_read_slots(dev); | |
1092 | if (test_and_clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause)) { | |
1093 | /* Read from TXE */ | |
1094 | rets = mei_irq_read_handler(dev, &complete_list, &slots); | |
1095 | if (rets && dev->dev_state != MEI_DEV_RESETTING) { | |
2bf94cab | 1096 | dev_err(dev->dev, |
32e2b59f TW |
1097 | "mei_irq_read_handler ret = %d.\n", rets); |
1098 | ||
1099 | schedule_work(&dev->reset_work); | |
1100 | goto end; | |
1101 | } | |
1102 | } | |
1103 | /* Input Ready: Detection if host can write to SeC */ | |
9d098192 | 1104 | if (test_and_clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause)) { |
32e2b59f | 1105 | dev->hbuf_is_ready = true; |
9d098192 TW |
1106 | hw->slots = dev->hbuf_depth; |
1107 | } | |
32e2b59f TW |
1108 | |
1109 | if (hw->aliveness && dev->hbuf_is_ready) { | |
6aae48ff TW |
1110 | /* get the real register value */ |
1111 | dev->hbuf_is_ready = mei_hbuf_is_ready(dev); | |
32e2b59f | 1112 | rets = mei_irq_write_handler(dev, &complete_list); |
6aae48ff | 1113 | if (rets && rets != -EMSGSIZE) |
2bf94cab | 1114 | dev_err(dev->dev, "mei_irq_write_handler ret = %d.\n", |
6aae48ff TW |
1115 | rets); |
1116 | dev->hbuf_is_ready = mei_hbuf_is_ready(dev); | |
32e2b59f TW |
1117 | } |
1118 | ||
32e2b59f TW |
1119 | mei_irq_compl_handler(dev, &complete_list); |
1120 | ||
1121 | end: | |
2bf94cab | 1122 | dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets); |
32e2b59f TW |
1123 | |
1124 | mutex_unlock(&dev->device_lock); | |
1125 | ||
1126 | mei_enable_interrupts(dev); | |
1127 | return IRQ_HANDLED; | |
1128 | } | |
1129 | ||
1130 | static const struct mei_hw_ops mei_txe_hw_ops = { | |
1131 | ||
1132 | .host_is_ready = mei_txe_host_is_ready, | |
1133 | ||
1bd30b6a | 1134 | .fw_status = mei_txe_fw_status, |
964a2331 TW |
1135 | .pg_state = mei_txe_pg_state, |
1136 | ||
32e2b59f TW |
1137 | .hw_is_ready = mei_txe_hw_is_ready, |
1138 | .hw_reset = mei_txe_hw_reset, | |
1139 | .hw_config = mei_txe_hw_config, | |
1140 | .hw_start = mei_txe_hw_start, | |
1141 | ||
ee7e5afd TW |
1142 | .pg_is_enabled = mei_txe_pg_is_enabled, |
1143 | ||
32e2b59f TW |
1144 | .intr_clear = mei_txe_intr_clear, |
1145 | .intr_enable = mei_txe_intr_enable, | |
1146 | .intr_disable = mei_txe_intr_disable, | |
1147 | ||
1148 | .hbuf_free_slots = mei_txe_hbuf_empty_slots, | |
1149 | .hbuf_is_ready = mei_txe_is_input_ready, | |
1150 | .hbuf_max_len = mei_txe_hbuf_max_len, | |
1151 | ||
1152 | .write = mei_txe_write, | |
1153 | ||
1154 | .rdbuf_full_slots = mei_txe_count_full_read_slots, | |
1155 | .read_hdr = mei_txe_read_hdr, | |
1156 | ||
1157 | .read = mei_txe_read, | |
1158 | ||
1159 | }; | |
1160 | ||
1161 | /** | |
1162 | * mei_txe_dev_init - allocates and initializes txe hardware specific structure | |
1163 | * | |
ce23139c | 1164 | * @pdev: pci device |
32e2b59f | 1165 | * |
ce23139c | 1166 | * Return: struct mei_device * on success or NULL |
32e2b59f | 1167 | */ |
4ad96db6 | 1168 | struct mei_device *mei_txe_dev_init(struct pci_dev *pdev) |
32e2b59f TW |
1169 | { |
1170 | struct mei_device *dev; | |
1171 | struct mei_txe_hw *hw; | |
1172 | ||
1173 | dev = kzalloc(sizeof(struct mei_device) + | |
1174 | sizeof(struct mei_txe_hw), GFP_KERNEL); | |
1175 | if (!dev) | |
1176 | return NULL; | |
1177 | ||
3a7e9b6c | 1178 | mei_device_init(dev, &pdev->dev, &mei_txe_hw_ops); |
32e2b59f TW |
1179 | |
1180 | hw = to_txe_hw(dev); | |
1181 | ||
964a2331 | 1182 | init_waitqueue_head(&hw->wait_aliveness_resp); |
32e2b59f | 1183 | |
32e2b59f TW |
1184 | return dev; |
1185 | } | |
1186 | ||
1187 | /** | |
1188 | * mei_txe_setup_satt2 - SATT2 configuration for DMA support. | |
1189 | * | |
1190 | * @dev: the device structure | |
1191 | * @addr: physical address start of the range | |
1192 | * @range: physical range size | |
ce23139c AU |
1193 | * |
1194 | * Return: 0 on success an error code otherwise | |
32e2b59f TW |
1195 | */ |
1196 | int mei_txe_setup_satt2(struct mei_device *dev, phys_addr_t addr, u32 range) | |
1197 | { | |
1198 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
1199 | ||
1200 | u32 lo32 = lower_32_bits(addr); | |
1201 | u32 hi32 = upper_32_bits(addr); | |
1202 | u32 ctrl; | |
1203 | ||
1204 | /* SATT is limited to 36 Bits */ | |
1205 | if (hi32 & ~0xF) | |
1206 | return -EINVAL; | |
1207 | ||
1208 | /* SATT has to be 16Byte aligned */ | |
1209 | if (lo32 & 0xF) | |
1210 | return -EINVAL; | |
1211 | ||
1212 | /* SATT range has to be 4Bytes aligned */ | |
1213 | if (range & 0x4) | |
1214 | return -EINVAL; | |
1215 | ||
1216 | /* SATT is limited to 32 MB range*/ | |
1217 | if (range > SATT_RANGE_MAX) | |
1218 | return -EINVAL; | |
1219 | ||
1220 | ctrl = SATT2_CTRL_VALID_MSK; | |
1221 | ctrl |= hi32 << SATT2_CTRL_BR_BASE_ADDR_REG_SHIFT; | |
1222 | ||
1223 | mei_txe_br_reg_write(hw, SATT2_SAP_SIZE_REG, range); | |
1224 | mei_txe_br_reg_write(hw, SATT2_BRG_BA_LSB_REG, lo32); | |
1225 | mei_txe_br_reg_write(hw, SATT2_CTRL_REG, ctrl); | |
2bf94cab | 1226 | dev_dbg(dev->dev, "SATT2: SAP_SIZE_OFFSET=0x%08X, BRG_BA_LSB_OFFSET=0x%08X, CTRL_OFFSET=0x%08X\n", |
32e2b59f TW |
1227 | range, lo32, ctrl); |
1228 | ||
1229 | return 0; | |
1230 | } |