[deliverable/linux.git] / drivers / misc / mei / hw.h

/*
 *
 * Intel Management Engine Interface (Intel MEI) Linux driver
 * Copyright (c) 2003-2012, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 */

#ifndef _MEI_HW_TYPES_H_
#define _MEI_HW_TYPES_H_

#include <linux/uuid.h>

/*
 * Timeouts
 */
#define MEI_INTEROP_TIMEOUT    (HZ * 7)
#define MEI_CONNECT_TIMEOUT		3	/* at least 2 seconds */

#define CONNECT_TIMEOUT        15	/* HPS definition */
#define INIT_CLIENTS_TIMEOUT   15	/* HPS definition */

#define IAMTHIF_STALL_TIMER		12	/* seconds */
#define IAMTHIF_READ_TIMER		10000	/* ms */

/*
 * Internal Clients Number
 */
#define MEI_WD_HOST_CLIENT_ID          1
#define MEI_IAMTHIF_HOST_CLIENT_ID     2

/*
 * MEI device IDs
 */
#define MEI_DEV_ID_82946GZ    0x2974  /* 82946GZ/GL */
#define MEI_DEV_ID_82G35      0x2984  /* 82G35 Express */
#define MEI_DEV_ID_82Q965     0x2994  /* 82Q963/Q965 */
#define MEI_DEV_ID_82G965     0x29A4  /* 82P965/G965 */

#define MEI_DEV_ID_82GM965    0x2A04  /* Mobile PM965/GM965 */
#define MEI_DEV_ID_82GME965   0x2A14  /* Mobile GME965/GLE960 */

#define MEI_DEV_ID_ICH9_82Q35 0x29B4  /* 82Q35 Express */
#define MEI_DEV_ID_ICH9_82G33 0x29C4  /* 82G33/G31/P35/P31 Express */
#define MEI_DEV_ID_ICH9_82Q33 0x29D4  /* 82Q33 Express */
#define MEI_DEV_ID_ICH9_82X38 0x29E4  /* 82X38/X48 Express */
#define MEI_DEV_ID_ICH9_3200  0x29F4  /* 3200/3210 Server */

#define MEI_DEV_ID_ICH9_6     0x28B4  /* Bearlake */
#define MEI_DEV_ID_ICH9_7     0x28C4  /* Bearlake */
#define MEI_DEV_ID_ICH9_8     0x28D4  /* Bearlake */
#define MEI_DEV_ID_ICH9_9     0x28E4  /* Bearlake */
#define MEI_DEV_ID_ICH9_10    0x28F4  /* Bearlake */

#define MEI_DEV_ID_ICH9M_1    0x2A44  /* Cantiga */
#define MEI_DEV_ID_ICH9M_2    0x2A54  /* Cantiga */
#define MEI_DEV_ID_ICH9M_3    0x2A64  /* Cantiga */
#define MEI_DEV_ID_ICH9M_4    0x2A74  /* Cantiga */

#define MEI_DEV_ID_ICH10_1    0x2E04  /* Eaglelake */
#define MEI_DEV_ID_ICH10_2    0x2E14  /* Eaglelake */
#define MEI_DEV_ID_ICH10_3    0x2E24  /* Eaglelake */
#define MEI_DEV_ID_ICH10_4    0x2E34  /* Eaglelake */

#define MEI_DEV_ID_IBXPK_1    0x3B64  /* Calpella */
#define MEI_DEV_ID_IBXPK_2    0x3B65  /* Calpella */

#define MEI_DEV_ID_CPT_1      0x1C3A  /* Couger Point */
#define MEI_DEV_ID_PBG_1      0x1D3A  /* C600/X79 Patsburg */

#define MEI_DEV_ID_PPT_1      0x1E3A  /* Panther Point */
#define MEI_DEV_ID_PPT_2      0x1CBA  /* Panther Point */
#define MEI_DEV_ID_PPT_3      0x1DBA  /* Panther Point */

/*
 * MEI HW Section
 */

/* MEI registers */
/* H_CB_WW - Host Circular Buffer (CB) Write Window register */
#define H_CB_WW    0
/* H_CSR - Host Control Status register */
#define H_CSR      4
/* ME_CB_RW - ME Circular Buffer Read Window register (read only) */
#define ME_CB_RW   8
/* ME_CSR_HA - ME Control Status Host Access register (read only) */
#define ME_CSR_HA  0xC


/* register bits of H_CSR (Host Control Status register) */
/* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */
#define H_CBD             0xFF000000
/* Host Circular Buffer Write Pointer */
#define H_CBWP            0x00FF0000
/* Host Circular Buffer Read Pointer */
#define H_CBRP            0x0000FF00
/* Host Reset */
#define H_RST             0x00000010
/* Host Ready */
#define H_RDY             0x00000008
/* Host Interrupt Generate */
#define H_IG              0x00000004
/* Host Interrupt Status */
#define H_IS              0x00000002
/* Host Interrupt Enable */
#define H_IE              0x00000001


/* register bits of ME_CSR_HA (ME Control Status Host Access register) */
/* ME CB (Circular Buffer) Depth HRA (Host Read Access) - host read only
access to ME_CBD */
#define ME_CBD_HRA        0xFF000000
/* ME CB Write Pointer HRA - host read only access to ME_CBWP */
#define ME_CBWP_HRA       0x00FF0000
/* ME CB Read Pointer HRA - host read only access to ME_CBRP */
#define ME_CBRP_HRA       0x0000FF00
/* ME Reset HRA - host read only access to ME_RST */
#define ME_RST_HRA        0x00000010
/* ME Ready HRA - host read only access to ME_RDY */
#define ME_RDY_HRA        0x00000008
/* ME Interrupt Generate HRA - host read only access to ME_IG */
#define ME_IG_HRA         0x00000004
/* ME Interrupt Status HRA - host read only access to ME_IS */
#define ME_IS_HRA         0x00000002
/* ME Interrupt Enable HRA - host read only access to ME_IE */
#define ME_IE_HRA         0x00000001

/*
 * MEI Version
 */
#define HBM_MINOR_VERSION                   0
#define HBM_MAJOR_VERSION                   1
#define HBM_TIMEOUT                         1	/* 1 second */

/* Host bus message command opcode */
#define MEI_HBM_CMD_OP_MSK                  0x7f
/* Host bus message command RESPONSE */
#define MEI_HBM_CMD_RES_MSK                 0x80

/*
 * MEI Bus Message Command IDs
 */
#define HOST_START_REQ_CMD                  0x01
#define HOST_START_RES_CMD                  0x81

#define HOST_STOP_REQ_CMD                   0x02
#define HOST_STOP_RES_CMD                   0x82

#define ME_STOP_REQ_CMD                     0x03

#define HOST_ENUM_REQ_CMD                   0x04
#define HOST_ENUM_RES_CMD                   0x84

#define HOST_CLIENT_PROPERTIES_REQ_CMD      0x05
#define HOST_CLIENT_PROPERTIES_RES_CMD      0x85

#define CLIENT_CONNECT_REQ_CMD              0x06
#define CLIENT_CONNECT_RES_CMD              0x86

#define CLIENT_DISCONNECT_REQ_CMD           0x07
#define CLIENT_DISCONNECT_RES_CMD           0x87

#define MEI_FLOW_CONTROL_CMD                0x08

/*
 * MEI Stop Reason
 * used by hbm_host_stop_request.reason
 */
enum mei_stop_reason_types {
	DRIVER_STOP_REQUEST = 0x00,
	DEVICE_D1_ENTRY = 0x01,
	DEVICE_D2_ENTRY = 0x02,
	DEVICE_D3_ENTRY = 0x03,
	SYSTEM_S1_ENTRY = 0x04,
	SYSTEM_S2_ENTRY = 0x05,
	SYSTEM_S3_ENTRY = 0x06,
	SYSTEM_S4_ENTRY = 0x07,
	SYSTEM_S5_ENTRY = 0x08
};

/*
 * Client Connect Status
 * used by hbm_client_connect_response.status
 */
enum client_connect_status_types {
	CCS_SUCCESS = 0x00,
	CCS_NOT_FOUND = 0x01,
	CCS_ALREADY_STARTED = 0x02,
	CCS_OUT_OF_RESOURCES = 0x03,
	CCS_MESSAGE_SMALL = 0x04
};

/*
 * Client Disconnect Status
 */
enum client_disconnect_status_types {
	CDS_SUCCESS = 0x00
};

/*
 *  MEI BUS Interface Section
 */
struct mei_msg_hdr {
	u32 me_addr:8;
	u32 host_addr:8;
	u32 length:9;
	u32 reserved:6;
	u32 msg_complete:1;
} __packed;


struct mei_bus_message {
	u8 hbm_cmd;
	u8 data[0];
} __packed;

struct hbm_version {
	u8 minor_version;
	u8 major_version;
} __packed;

struct hbm_host_version_request {
	u8 hbm_cmd;
	u8 reserved;
	struct hbm_version host_version;
} __packed;

struct hbm_host_version_response {
	u8 hbm_cmd;
	u8 host_version_supported;
	struct hbm_version me_max_version;
} __packed;

struct hbm_host_stop_request {
	u8 hbm_cmd;
	u8 reason;
	u8 reserved[2];
} __packed;

struct hbm_host_stop_response {
	u8 hbm_cmd;
	u8 reserved[3];
} __packed;

struct hbm_me_stop_request {
	u8 hbm_cmd;
	u8 reason;
	u8 reserved[2];
} __packed;

struct hbm_host_enum_request {
	u8 hbm_cmd;
	u8 reserved[3];
} __packed;

struct hbm_host_enum_response {
	u8 hbm_cmd;
	u8 reserved[3];
	u8 valid_addresses[32];
} __packed;

struct mei_client_properties {
	uuid_le protocol_name;
	u8 protocol_version;
	u8 max_number_of_connections;
	u8 fixed_address;
	u8 single_recv_buf;
	u32 max_msg_length;
} __packed;

struct hbm_props_request {
	u8 hbm_cmd;
	u8 address;
	u8 reserved[2];
} __packed;


struct hbm_props_response {
	u8 hbm_cmd;
	u8 address;
	u8 status;
	u8 reserved[1];
	struct mei_client_properties client_properties;
} __packed;

struct hbm_client_connect_request {
	u8 hbm_cmd;
	u8 me_addr;
	u8 host_addr;
	u8 reserved;
} __packed;

struct hbm_client_connect_response {
	u8 hbm_cmd;
	u8 me_addr;
	u8 host_addr;
	u8 status;
} __packed;

struct hbm_client_disconnect_request {
	u8 hbm_cmd;
	u8 me_addr;
	u8 host_addr;
	u8 reserved[1];
} __packed;

#define MEI_FC_MESSAGE_RESERVED_LENGTH           5

struct hbm_flow_control {
	u8 hbm_cmd;
	u8 me_addr;
	u8 host_addr;
	u8 reserved[MEI_FC_MESSAGE_RESERVED_LENGTH];
} __packed;

struct mei_me_client {
	struct mei_client_properties props;
	u8 client_id;
	u8 mei_flow_ctrl_creds;
} __packed;


#endif
Commit	Line	Data
5a6003f2 OW	1	/*
	2	*
	3	* Intel Management Engine Interface (Intel MEI) Linux driver
733ba91c	4	* Copyright (c) 2003-2012, Intel Corporation.
5a6003f2 OW	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	*/
	16
	17	#ifndef _MEI_HW_TYPES_H_
	18	#define _MEI_HW_TYPES_H_
	19
	20	#include <linux/uuid.h>
	21
	22	/*
	23	* Timeouts
	24	*/
	25	#define MEI_INTEROP_TIMEOUT (HZ * 7)
	26	#define MEI_CONNECT_TIMEOUT 3 /* at least 2 seconds */
	27
	28	#define CONNECT_TIMEOUT 15 /* HPS definition */
	29	#define INIT_CLIENTS_TIMEOUT 15 /* HPS definition */
	30
	31	#define IAMTHIF_STALL_TIMER 12 /* seconds */
	32	#define IAMTHIF_READ_TIMER 10000 /* ms */
	33
	34	/*
	35	* Internal Clients Number
	36	*/
	37	#define MEI_WD_HOST_CLIENT_ID 1
	38	#define MEI_IAMTHIF_HOST_CLIENT_ID 2
	39
	40	/*
	41	* MEI device IDs
	42	*/
6ddf3aea TW	43	#define MEI_DEV_ID_82946GZ 0x2974 /* 82946GZ/GL */
	44	#define MEI_DEV_ID_82G35 0x2984 /* 82G35 Express */
	45	#define MEI_DEV_ID_82Q965 0x2994 /* 82Q963/Q965 */
	46	#define MEI_DEV_ID_82G965 0x29A4 /* 82P965/G965 */
	47
	48	#define MEI_DEV_ID_82GM965 0x2A04 /* Mobile PM965/GM965 */
	49	#define MEI_DEV_ID_82GME965 0x2A14 /* Mobile GME965/GLE960 */
	50
	51	#define MEI_DEV_ID_ICH9_82Q35 0x29B4 /* 82Q35 Express */
	52	#define MEI_DEV_ID_ICH9_82G33 0x29C4 /* 82G33/G31/P35/P31 Express */
	53	#define MEI_DEV_ID_ICH9_82Q33 0x29D4 /* 82Q33 Express */
	54	#define MEI_DEV_ID_ICH9_82X38 0x29E4 /* 82X38/X48 Express */
	55	#define MEI_DEV_ID_ICH9_3200 0x29F4 /* 3200/3210 Server */
	56
	57	#define MEI_DEV_ID_ICH9_6 0x28B4 /* Bearlake */
	58	#define MEI_DEV_ID_ICH9_7 0x28C4 /* Bearlake */
	59	#define MEI_DEV_ID_ICH9_8 0x28D4 /* Bearlake */
	60	#define MEI_DEV_ID_ICH9_9 0x28E4 /* Bearlake */
	61	#define MEI_DEV_ID_ICH9_10 0x28F4 /* Bearlake */
	62
	63	#define MEI_DEV_ID_ICH9M_1 0x2A44 /* Cantiga */
	64	#define MEI_DEV_ID_ICH9M_2 0x2A54 /* Cantiga */
	65	#define MEI_DEV_ID_ICH9M_3 0x2A64 /* Cantiga */
	66	#define MEI_DEV_ID_ICH9M_4 0x2A74 /* Cantiga */
	67
	68	#define MEI_DEV_ID_ICH10_1 0x2E04 /* Eaglelake */
	69	#define MEI_DEV_ID_ICH10_2 0x2E14 /* Eaglelake */
	70	#define MEI_DEV_ID_ICH10_3 0x2E24 /* Eaglelake */
	71	#define MEI_DEV_ID_ICH10_4 0x2E34 /* Eaglelake */
	72
	73	#define MEI_DEV_ID_IBXPK_1 0x3B64 /* Calpella */
	74	#define MEI_DEV_ID_IBXPK_2 0x3B65 /* Calpella */
	75
	76	#define MEI_DEV_ID_CPT_1 0x1C3A /* Couger Point */
	77	#define MEI_DEV_ID_PBG_1 0x1D3A /* C600/X79 Patsburg */
	78
	79	#define MEI_DEV_ID_PPT_1 0x1E3A /* Panther Point */
	80	#define MEI_DEV_ID_PPT_2 0x1CBA /* Panther Point */
	81	#define MEI_DEV_ID_PPT_3 0x1DBA /* Panther Point */
5a6003f2 OW	82
	83	/*
	84	* MEI HW Section
	85	*/
	86
	87	/* MEI registers */
	88	/* H_CB_WW - Host Circular Buffer (CB) Write Window register */
	89	#define H_CB_WW 0
	90	/* H_CSR - Host Control Status register */
	91	#define H_CSR 4
	92	/* ME_CB_RW - ME Circular Buffer Read Window register (read only) */
	93	#define ME_CB_RW 8
	94	/* ME_CSR_HA - ME Control Status Host Access register (read only) */
	95	#define ME_CSR_HA 0xC
	96
	97
	98	/* register bits of H_CSR (Host Control Status register) */
	99	/* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */
	100	#define H_CBD 0xFF000000
	101	/* Host Circular Buffer Write Pointer */
	102	#define H_CBWP 0x00FF0000
	103	/* Host Circular Buffer Read Pointer */
	104	#define H_CBRP 0x0000FF00
	105	/* Host Reset */
	106	#define H_RST 0x00000010
	107	/* Host Ready */
	108	#define H_RDY 0x00000008
	109	/* Host Interrupt Generate */
	110	#define H_IG 0x00000004
	111	/* Host Interrupt Status */
	112	#define H_IS 0x00000002
	113	/* Host Interrupt Enable */
	114	#define H_IE 0x00000001
	115
	116
	117	/* register bits of ME_CSR_HA (ME Control Status Host Access register) */
	118	/* ME CB (Circular Buffer) Depth HRA (Host Read Access) - host read only
	119	access to ME_CBD */
	120	#define ME_CBD_HRA 0xFF000000
	121	/* ME CB Write Pointer HRA - host read only access to ME_CBWP */
	122	#define ME_CBWP_HRA 0x00FF0000
	123	/* ME CB Read Pointer HRA - host read only access to ME_CBRP */
	124	#define ME_CBRP_HRA 0x0000FF00
	125	/* ME Reset HRA - host read only access to ME_RST */
	126	#define ME_RST_HRA 0x00000010
	127	/* ME Ready HRA - host read only access to ME_RDY */
	128	#define ME_RDY_HRA 0x00000008
	129	/* ME Interrupt Generate HRA - host read only access to ME_IG */
	130	#define ME_IG_HRA 0x00000004
	131	/* ME Interrupt Status HRA - host read only access to ME_IS */
	132	#define ME_IS_HRA 0x00000002
	133	/* ME Interrupt Enable HRA - host read only access to ME_IE */
	134	#define ME_IE_HRA 0x00000001
	135
	136	/*
	137	* MEI Version
	138	*/
	139	#define HBM_MINOR_VERSION 0
	140	#define HBM_MAJOR_VERSION 1
	141	#define HBM_TIMEOUT 1 /* 1 second */
	142
1ca7e782 TW	143	/* Host bus message command opcode */
	144	#define MEI_HBM_CMD_OP_MSK 0x7f
	145	/* Host bus message command RESPONSE */
	146	#define MEI_HBM_CMD_RES_MSK 0x80
	147
5a6003f2 OW	148	/*
	149	* MEI Bus Message Command IDs
	150	*/
	151	#define HOST_START_REQ_CMD 0x01
	152	#define HOST_START_RES_CMD 0x81
	153
	154	#define HOST_STOP_REQ_CMD 0x02
	155	#define HOST_STOP_RES_CMD 0x82
	156
	157	#define ME_STOP_REQ_CMD 0x03
	158
	159	#define HOST_ENUM_REQ_CMD 0x04
	160	#define HOST_ENUM_RES_CMD 0x84
	161
	162	#define HOST_CLIENT_PROPERTIES_REQ_CMD 0x05
	163	#define HOST_CLIENT_PROPERTIES_RES_CMD 0x85
	164
	165	#define CLIENT_CONNECT_REQ_CMD 0x06
	166	#define CLIENT_CONNECT_RES_CMD 0x86
	167
	168	#define CLIENT_DISCONNECT_REQ_CMD 0x07
	169	#define CLIENT_DISCONNECT_RES_CMD 0x87
	170
1ca7e782	171	#define MEI_FLOW_CONTROL_CMD 0x08
5a6003f2 OW	172
	173	/*
	174	* MEI Stop Reason
	175	* used by hbm_host_stop_request.reason
	176	*/
	177	enum mei_stop_reason_types {
	178	DRIVER_STOP_REQUEST = 0x00,
	179	DEVICE_D1_ENTRY = 0x01,
	180	DEVICE_D2_ENTRY = 0x02,
	181	DEVICE_D3_ENTRY = 0x03,
	182	SYSTEM_S1_ENTRY = 0x04,
	183	SYSTEM_S2_ENTRY = 0x05,
	184	SYSTEM_S3_ENTRY = 0x06,
	185	SYSTEM_S4_ENTRY = 0x07,
	186	SYSTEM_S5_ENTRY = 0x08
	187	};
	188
	189	/*
	190	* Client Connect Status
	191	* used by hbm_client_connect_response.status
	192	*/
	193	enum client_connect_status_types {
	194	CCS_SUCCESS = 0x00,
	195	CCS_NOT_FOUND = 0x01,
	196	CCS_ALREADY_STARTED = 0x02,
	197	CCS_OUT_OF_RESOURCES = 0x03,
	198	CCS_MESSAGE_SMALL = 0x04
	199	};
	200
	201	/*
	202	* Client Disconnect Status
	203	*/
	204	enum client_disconnect_status_types {
	205	CDS_SUCCESS = 0x00
	206	};
	207
	208	/*
	209	* MEI BUS Interface Section
	210	*/
	211	struct mei_msg_hdr {
	212	u32 me_addr:8;
	213	u32 host_addr:8;
	214	u32 length:9;
	215	u32 reserved:6;
	216	u32 msg_complete:1;
	217	} __packed;
	218
	219
5a6003f2	220	struct mei_bus_message {
1ca7e782 TW	221	u8 hbm_cmd;
1ca7e782 TW	222	u8 data[0];
5a6003f2 OW	223	} __packed;
	224
	225	struct hbm_version {
	226	u8 minor_version;
	227	u8 major_version;
	228	} __packed;
	229
	230	struct hbm_host_version_request {
1ca7e782	231	u8 hbm_cmd;
5a6003f2 OW	232	u8 reserved;
	233	struct hbm_version host_version;
	234	} __packed;
	235
	236	struct hbm_host_version_response {
1ca7e782	237	u8 hbm_cmd;
4b00706c	238	u8 host_version_supported;
5a6003f2 OW	239	struct hbm_version me_max_version;
	240	} __packed;
	241
	242	struct hbm_host_stop_request {
1ca7e782	243	u8 hbm_cmd;
5a6003f2 OW	244	u8 reason;
	245	u8 reserved[2];
	246	} __packed;
	247
	248	struct hbm_host_stop_response {
1ca7e782	249	u8 hbm_cmd;
5a6003f2 OW	250	u8 reserved[3];
	251	} __packed;
	252
	253	struct hbm_me_stop_request {
1ca7e782	254	u8 hbm_cmd;
5a6003f2 OW	255	u8 reason;
	256	u8 reserved[2];
	257	} __packed;
	258
	259	struct hbm_host_enum_request {
1ca7e782	260	u8 hbm_cmd;
5a6003f2 OW	261	u8 reserved[3];
	262	} __packed;
	263
	264	struct hbm_host_enum_response {
1ca7e782	265	u8 hbm_cmd;
5a6003f2 OW	266	u8 reserved[3];
	267	u8 valid_addresses[32];
	268	} __packed;
	269
	270	struct mei_client_properties {
	271	uuid_le protocol_name;
	272	u8 protocol_version;
	273	u8 max_number_of_connections;
	274	u8 fixed_address;
	275	u8 single_recv_buf;
	276	u32 max_msg_length;
	277	} __packed;
	278
	279	struct hbm_props_request {
1ca7e782	280	u8 hbm_cmd;
5a6003f2 OW	281	u8 address;
	282	u8 reserved[2];
	283	} __packed;
	284
	285
	286	struct hbm_props_response {
1ca7e782	287	u8 hbm_cmd;
5a6003f2 OW	288	u8 address;
	289	u8 status;
	290	u8 reserved[1];
	291	struct mei_client_properties client_properties;
	292	} __packed;
	293
	294	struct hbm_client_connect_request {
1ca7e782	295	u8 hbm_cmd;
5a6003f2 OW	296	u8 me_addr;
	297	u8 host_addr;
	298	u8 reserved;
	299	} __packed;
	300
	301	struct hbm_client_connect_response {
1ca7e782	302	u8 hbm_cmd;
5a6003f2 OW	303	u8 me_addr;
	304	u8 host_addr;
	305	u8 status;
	306	} __packed;
	307
	308	struct hbm_client_disconnect_request {
1ca7e782	309	u8 hbm_cmd;
5a6003f2 OW	310	u8 me_addr;
	311	u8 host_addr;
	312	u8 reserved[1];
	313	} __packed;
	314
	315	#define MEI_FC_MESSAGE_RESERVED_LENGTH 5
	316
	317	struct hbm_flow_control {
1ca7e782	318	u8 hbm_cmd;
5a6003f2 OW	319	u8 me_addr;
	320	u8 host_addr;
	321	u8 reserved[MEI_FC_MESSAGE_RESERVED_LENGTH];
	322	} __packed;
	323
	324	struct mei_me_client {
	325	struct mei_client_properties props;
	326	u8 client_id;
	327	u8 mei_flow_ctrl_creds;
	328	} __packed;
	329
	330
	331	#endif