projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| ba264b34 PP |
1 | #ifndef _AU1XMMC_H_ |
| 2 | #define _AU1XMMC_H_ | |
| 3 | ||
| 4 | /* Hardware definitions */ | |
| 5 | ||
| 6 | #define AU1XMMC_DESCRIPTOR_COUNT 1 | |
| 7 | #define AU1XMMC_DESCRIPTOR_SIZE 2048 | |
| 8 | ||
| 9 | #define AU1XMMC_OCR ( MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \ | |
| 10 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \ | |
| 11 | MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36) | |
| 12 | ||
| 13 | /* Easy access macros */ | |
| 14 | ||
| 15 | #define HOST_STATUS(h) ((h)->iobase + SD_STATUS) | |
| 16 | #define HOST_CONFIG(h) ((h)->iobase + SD_CONFIG) | |
| 17 | #define HOST_ENABLE(h) ((h)->iobase + SD_ENABLE) | |
| 18 | #define HOST_TXPORT(h) ((h)->iobase + SD_TXPORT) | |
| 19 | #define HOST_RXPORT(h) ((h)->iobase + SD_RXPORT) | |
| 20 | #define HOST_CMDARG(h) ((h)->iobase + SD_CMDARG) | |
| 21 | #define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE) | |
| 22 | #define HOST_CMD(h) ((h)->iobase + SD_CMD) | |
| 23 | #define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2) | |
| 24 | #define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT) | |
| 25 | #define HOST_DEBUG(h) ((h)->iobase + SD_DEBUG) | |
| 26 | ||
| 27 | #define DMA_CHANNEL(h) \ | |
| 28 | ( ((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan) | |
| 29 | ||
| 30 | /* This gives us a hard value for the stop command that we can write directly | |
| 31 | * to the command register | |
| 32 | */ | |
| 33 | ||
| 34 | #define STOP_CMD (SD_CMD_RT_1B|SD_CMD_CT_7|(0xC << SD_CMD_CI_SHIFT)|SD_CMD_GO) | |
| 35 | ||
| 36 | /* This is the set of interrupts that we configure by default */ | |
| 37 | ||
| 38 | #if 0 | |
| 39 | #define AU1XMMC_INTERRUPTS (SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_DD | \ | |
| 40 | SD_CONFIG_RAT | SD_CONFIG_CR | SD_CONFIG_I) | |
| 41 | #endif | |
| 42 | ||
| 43 | #define AU1XMMC_INTERRUPTS (SD_CONFIG_SC | SD_CONFIG_DT | \ | |
| 44 | SD_CONFIG_RAT | SD_CONFIG_CR | SD_CONFIG_I) | |
| 45 | /* The poll event (looking for insert/remove events runs twice a second */ | |
| 46 | #define AU1XMMC_DETECT_TIMEOUT (HZ/2) | |
| 47 | ||
| 48 | struct au1xmmc_host { | |
| 49 | struct mmc_host *mmc; | |
| 50 | struct mmc_request *mrq; | |
| 51 | ||
| 52 | u32 id; | |
| 53 | ||
| 54 | u32 flags; | |
| 55 | u32 iobase; | |
| 56 | u32 clock; | |
| 57 | u32 bus_width; | |
| 58 | u32 power_mode; | |
| 59 | ||
| 60 | int status; | |
| 61 | ||
| 62 | struct { | |
| 63 | int len; | |
| 64 | int dir; | |
| 65 | } dma; | |
| 66 | ||
| 67 | struct { | |
| 68 | int index; | |
| 69 | int offset; | |
| 70 | int len; | |
| 71 | } pio; | |
| 72 | ||
| 73 | u32 tx_chan; | |
| 74 | u32 rx_chan; | |
| 75 | ||
| 76 | struct timer_list timer; | |
| 77 | struct tasklet_struct finish_task; | |
| 78 | struct tasklet_struct data_task; | |
| 79 | ||
| 80 | spinlock_t lock; | |
| 81 | }; | |
| 82 | ||
| 83 | /* Status flags used by the host structure */ | |
| 84 | ||
| 85 | #define HOST_F_XMIT 0x0001 | |
| 86 | #define HOST_F_RECV 0x0002 | |
| 87 | #define HOST_F_DMA 0x0010 | |
| 88 | #define HOST_F_ACTIVE 0x0100 | |
| 89 | #define HOST_F_STOP 0x1000 | |
| 90 | ||
| 91 | #define HOST_S_IDLE 0x0001 | |
| 92 | #define HOST_S_CMD 0x0002 | |
| 93 | #define HOST_S_DATA 0x0003 | |
| 94 | #define HOST_S_STOP 0x0004 | |
| 95 | ||
| 96 | #endif |