Commit | Line | Data |
---|---|---|
7d2be074 HS |
1 | /* |
2 | * Atmel MultiMedia Card Interface driver | |
3 | * | |
4 | * Copyright (C) 2004-2008 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | #include <linux/blkdev.h> | |
11 | #include <linux/clk.h> | |
deec9ae3 | 12 | #include <linux/debugfs.h> |
7d2be074 | 13 | #include <linux/device.h> |
65e8b083 HS |
14 | #include <linux/dmaengine.h> |
15 | #include <linux/dma-mapping.h> | |
fbfca4b8 | 16 | #include <linux/err.h> |
3c26e170 | 17 | #include <linux/gpio.h> |
7d2be074 HS |
18 | #include <linux/init.h> |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/ioport.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/scatterlist.h> | |
deec9ae3 | 24 | #include <linux/seq_file.h> |
5a0e3ad6 | 25 | #include <linux/slab.h> |
deec9ae3 | 26 | #include <linux/stat.h> |
7d2be074 HS |
27 | |
28 | #include <linux/mmc/host.h> | |
2f1d7918 | 29 | #include <linux/mmc/sdio.h> |
2635d1ba NF |
30 | |
31 | #include <mach/atmel-mci.h> | |
c42aa775 | 32 | #include <linux/atmel-mci.h> |
796211b7 | 33 | #include <linux/atmel_pdc.h> |
7d2be074 | 34 | |
7d2be074 HS |
35 | #include <asm/io.h> |
36 | #include <asm/unaligned.h> | |
37 | ||
04d699c3 | 38 | #include <mach/cpu.h> |
3663b736 | 39 | #include <mach/board.h> |
7d2be074 HS |
40 | |
41 | #include "atmel-mci-regs.h" | |
42 | ||
2c96a293 | 43 | #define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE) |
65e8b083 | 44 | #define ATMCI_DMA_THRESHOLD 16 |
7d2be074 HS |
45 | |
46 | enum { | |
47 | EVENT_CMD_COMPLETE = 0, | |
7d2be074 | 48 | EVENT_XFER_COMPLETE, |
c06ad258 HS |
49 | EVENT_DATA_COMPLETE, |
50 | EVENT_DATA_ERROR, | |
51 | }; | |
52 | ||
53 | enum atmel_mci_state { | |
965ebf33 HS |
54 | STATE_IDLE = 0, |
55 | STATE_SENDING_CMD, | |
c06ad258 HS |
56 | STATE_SENDING_DATA, |
57 | STATE_DATA_BUSY, | |
58 | STATE_SENDING_STOP, | |
59 | STATE_DATA_ERROR, | |
7d2be074 HS |
60 | }; |
61 | ||
796211b7 LD |
62 | enum atmci_xfer_dir { |
63 | XFER_RECEIVE = 0, | |
64 | XFER_TRANSMIT, | |
65 | }; | |
66 | ||
67 | enum atmci_pdc_buf { | |
68 | PDC_FIRST_BUF = 0, | |
69 | PDC_SECOND_BUF, | |
70 | }; | |
71 | ||
72 | struct atmel_mci_caps { | |
73 | bool has_dma; | |
74 | bool has_pdc; | |
75 | bool has_cfg_reg; | |
76 | bool has_cstor_reg; | |
77 | bool has_highspeed; | |
78 | bool has_rwproof; | |
79 | }; | |
80 | ||
65e8b083 | 81 | struct atmel_mci_dma { |
65e8b083 HS |
82 | struct dma_chan *chan; |
83 | struct dma_async_tx_descriptor *data_desc; | |
65e8b083 HS |
84 | }; |
85 | ||
965ebf33 HS |
86 | /** |
87 | * struct atmel_mci - MMC controller state shared between all slots | |
88 | * @lock: Spinlock protecting the queue and associated data. | |
89 | * @regs: Pointer to MMIO registers. | |
796211b7 | 90 | * @sg: Scatterlist entry currently being processed by PIO or PDC code. |
965ebf33 HS |
91 | * @pio_offset: Offset into the current scatterlist entry. |
92 | * @cur_slot: The slot which is currently using the controller. | |
93 | * @mrq: The request currently being processed on @cur_slot, | |
94 | * or NULL if the controller is idle. | |
95 | * @cmd: The command currently being sent to the card, or NULL. | |
96 | * @data: The data currently being transferred, or NULL if no data | |
97 | * transfer is in progress. | |
796211b7 | 98 | * @data_size: just data->blocks * data->blksz. |
65e8b083 HS |
99 | * @dma: DMA client state. |
100 | * @data_chan: DMA channel being used for the current data transfer. | |
965ebf33 HS |
101 | * @cmd_status: Snapshot of SR taken upon completion of the current |
102 | * command. Only valid when EVENT_CMD_COMPLETE is pending. | |
103 | * @data_status: Snapshot of SR taken upon completion of the current | |
104 | * data transfer. Only valid when EVENT_DATA_COMPLETE or | |
105 | * EVENT_DATA_ERROR is pending. | |
106 | * @stop_cmdr: Value to be loaded into CMDR when the stop command is | |
107 | * to be sent. | |
108 | * @tasklet: Tasklet running the request state machine. | |
109 | * @pending_events: Bitmask of events flagged by the interrupt handler | |
110 | * to be processed by the tasklet. | |
111 | * @completed_events: Bitmask of events which the state machine has | |
112 | * processed. | |
113 | * @state: Tasklet state. | |
114 | * @queue: List of slots waiting for access to the controller. | |
115 | * @need_clock_update: Update the clock rate before the next request. | |
116 | * @need_reset: Reset controller before next request. | |
117 | * @mode_reg: Value of the MR register. | |
74791a2d | 118 | * @cfg_reg: Value of the CFG register. |
965ebf33 HS |
119 | * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus |
120 | * rate and timeout calculations. | |
121 | * @mapbase: Physical address of the MMIO registers. | |
122 | * @mck: The peripheral bus clock hooked up to the MMC controller. | |
123 | * @pdev: Platform device associated with the MMC controller. | |
124 | * @slot: Slots sharing this MMC controller. | |
796211b7 LD |
125 | * @caps: MCI capabilities depending on MCI version. |
126 | * @prepare_data: function to setup MCI before data transfer which | |
127 | * depends on MCI capabilities. | |
128 | * @submit_data: function to start data transfer which depends on MCI | |
129 | * capabilities. | |
130 | * @stop_transfer: function to stop data transfer which depends on MCI | |
131 | * capabilities. | |
965ebf33 HS |
132 | * |
133 | * Locking | |
134 | * ======= | |
135 | * | |
136 | * @lock is a softirq-safe spinlock protecting @queue as well as | |
137 | * @cur_slot, @mrq and @state. These must always be updated | |
138 | * at the same time while holding @lock. | |
139 | * | |
140 | * @lock also protects mode_reg and need_clock_update since these are | |
141 | * used to synchronize mode register updates with the queue | |
142 | * processing. | |
143 | * | |
144 | * The @mrq field of struct atmel_mci_slot is also protected by @lock, | |
145 | * and must always be written at the same time as the slot is added to | |
146 | * @queue. | |
147 | * | |
148 | * @pending_events and @completed_events are accessed using atomic bit | |
149 | * operations, so they don't need any locking. | |
150 | * | |
151 | * None of the fields touched by the interrupt handler need any | |
152 | * locking. However, ordering is important: Before EVENT_DATA_ERROR or | |
153 | * EVENT_DATA_COMPLETE is set in @pending_events, all data-related | |
154 | * interrupts must be disabled and @data_status updated with a | |
155 | * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the | |
25985edc | 156 | * CMDRDY interrupt must be disabled and @cmd_status updated with a |
965ebf33 HS |
157 | * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the |
158 | * bytes_xfered field of @data must be written. This is ensured by | |
159 | * using barriers. | |
160 | */ | |
7d2be074 | 161 | struct atmel_mci { |
965ebf33 | 162 | spinlock_t lock; |
7d2be074 HS |
163 | void __iomem *regs; |
164 | ||
165 | struct scatterlist *sg; | |
166 | unsigned int pio_offset; | |
167 | ||
965ebf33 | 168 | struct atmel_mci_slot *cur_slot; |
7d2be074 HS |
169 | struct mmc_request *mrq; |
170 | struct mmc_command *cmd; | |
171 | struct mmc_data *data; | |
796211b7 | 172 | unsigned int data_size; |
7d2be074 | 173 | |
65e8b083 HS |
174 | struct atmel_mci_dma dma; |
175 | struct dma_chan *data_chan; | |
176 | ||
7d2be074 HS |
177 | u32 cmd_status; |
178 | u32 data_status; | |
7d2be074 HS |
179 | u32 stop_cmdr; |
180 | ||
7d2be074 HS |
181 | struct tasklet_struct tasklet; |
182 | unsigned long pending_events; | |
183 | unsigned long completed_events; | |
c06ad258 | 184 | enum atmel_mci_state state; |
965ebf33 | 185 | struct list_head queue; |
7d2be074 | 186 | |
965ebf33 HS |
187 | bool need_clock_update; |
188 | bool need_reset; | |
189 | u32 mode_reg; | |
74791a2d | 190 | u32 cfg_reg; |
7d2be074 HS |
191 | unsigned long bus_hz; |
192 | unsigned long mapbase; | |
193 | struct clk *mck; | |
194 | struct platform_device *pdev; | |
965ebf33 | 195 | |
2c96a293 | 196 | struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS]; |
796211b7 LD |
197 | |
198 | struct atmel_mci_caps caps; | |
199 | ||
200 | u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data); | |
201 | void (*submit_data)(struct atmel_mci *host, struct mmc_data *data); | |
202 | void (*stop_transfer)(struct atmel_mci *host); | |
965ebf33 HS |
203 | }; |
204 | ||
205 | /** | |
206 | * struct atmel_mci_slot - MMC slot state | |
207 | * @mmc: The mmc_host representing this slot. | |
208 | * @host: The MMC controller this slot is using. | |
209 | * @sdc_reg: Value of SDCR to be written before using this slot. | |
88ff82ed | 210 | * @sdio_irq: SDIO irq mask for this slot. |
965ebf33 HS |
211 | * @mrq: mmc_request currently being processed or waiting to be |
212 | * processed, or NULL when the slot is idle. | |
213 | * @queue_node: List node for placing this node in the @queue list of | |
214 | * &struct atmel_mci. | |
215 | * @clock: Clock rate configured by set_ios(). Protected by host->lock. | |
216 | * @flags: Random state bits associated with the slot. | |
217 | * @detect_pin: GPIO pin used for card detection, or negative if not | |
218 | * available. | |
219 | * @wp_pin: GPIO pin used for card write protect sending, or negative | |
220 | * if not available. | |
1c1452be | 221 | * @detect_is_active_high: The state of the detect pin when it is active. |
965ebf33 HS |
222 | * @detect_timer: Timer used for debouncing @detect_pin interrupts. |
223 | */ | |
224 | struct atmel_mci_slot { | |
225 | struct mmc_host *mmc; | |
226 | struct atmel_mci *host; | |
227 | ||
228 | u32 sdc_reg; | |
88ff82ed | 229 | u32 sdio_irq; |
965ebf33 HS |
230 | |
231 | struct mmc_request *mrq; | |
232 | struct list_head queue_node; | |
233 | ||
234 | unsigned int clock; | |
235 | unsigned long flags; | |
236 | #define ATMCI_CARD_PRESENT 0 | |
237 | #define ATMCI_CARD_NEED_INIT 1 | |
238 | #define ATMCI_SHUTDOWN 2 | |
5c2f2b9b | 239 | #define ATMCI_SUSPENDED 3 |
965ebf33 HS |
240 | |
241 | int detect_pin; | |
242 | int wp_pin; | |
1c1452be | 243 | bool detect_is_active_high; |
965ebf33 HS |
244 | |
245 | struct timer_list detect_timer; | |
7d2be074 HS |
246 | }; |
247 | ||
7d2be074 HS |
248 | #define atmci_test_and_clear_pending(host, event) \ |
249 | test_and_clear_bit(event, &host->pending_events) | |
7d2be074 HS |
250 | #define atmci_set_completed(host, event) \ |
251 | set_bit(event, &host->completed_events) | |
252 | #define atmci_set_pending(host, event) \ | |
253 | set_bit(event, &host->pending_events) | |
7d2be074 | 254 | |
deec9ae3 HS |
255 | /* |
256 | * The debugfs stuff below is mostly optimized away when | |
257 | * CONFIG_DEBUG_FS is not set. | |
258 | */ | |
259 | static int atmci_req_show(struct seq_file *s, void *v) | |
260 | { | |
965ebf33 HS |
261 | struct atmel_mci_slot *slot = s->private; |
262 | struct mmc_request *mrq; | |
deec9ae3 HS |
263 | struct mmc_command *cmd; |
264 | struct mmc_command *stop; | |
265 | struct mmc_data *data; | |
266 | ||
267 | /* Make sure we get a consistent snapshot */ | |
965ebf33 HS |
268 | spin_lock_bh(&slot->host->lock); |
269 | mrq = slot->mrq; | |
deec9ae3 HS |
270 | |
271 | if (mrq) { | |
272 | cmd = mrq->cmd; | |
273 | data = mrq->data; | |
274 | stop = mrq->stop; | |
275 | ||
276 | if (cmd) | |
277 | seq_printf(s, | |
278 | "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", | |
279 | cmd->opcode, cmd->arg, cmd->flags, | |
280 | cmd->resp[0], cmd->resp[1], cmd->resp[2], | |
d586ebbb | 281 | cmd->resp[3], cmd->error); |
deec9ae3 HS |
282 | if (data) |
283 | seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", | |
284 | data->bytes_xfered, data->blocks, | |
285 | data->blksz, data->flags, data->error); | |
286 | if (stop) | |
287 | seq_printf(s, | |
288 | "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", | |
289 | stop->opcode, stop->arg, stop->flags, | |
290 | stop->resp[0], stop->resp[1], stop->resp[2], | |
d586ebbb | 291 | stop->resp[3], stop->error); |
deec9ae3 HS |
292 | } |
293 | ||
965ebf33 | 294 | spin_unlock_bh(&slot->host->lock); |
deec9ae3 HS |
295 | |
296 | return 0; | |
297 | } | |
298 | ||
299 | static int atmci_req_open(struct inode *inode, struct file *file) | |
300 | { | |
301 | return single_open(file, atmci_req_show, inode->i_private); | |
302 | } | |
303 | ||
304 | static const struct file_operations atmci_req_fops = { | |
305 | .owner = THIS_MODULE, | |
306 | .open = atmci_req_open, | |
307 | .read = seq_read, | |
308 | .llseek = seq_lseek, | |
309 | .release = single_release, | |
310 | }; | |
311 | ||
312 | static void atmci_show_status_reg(struct seq_file *s, | |
313 | const char *regname, u32 value) | |
314 | { | |
315 | static const char *sr_bit[] = { | |
316 | [0] = "CMDRDY", | |
317 | [1] = "RXRDY", | |
318 | [2] = "TXRDY", | |
319 | [3] = "BLKE", | |
320 | [4] = "DTIP", | |
321 | [5] = "NOTBUSY", | |
04d699c3 RE |
322 | [6] = "ENDRX", |
323 | [7] = "ENDTX", | |
deec9ae3 HS |
324 | [8] = "SDIOIRQA", |
325 | [9] = "SDIOIRQB", | |
04d699c3 RE |
326 | [12] = "SDIOWAIT", |
327 | [14] = "RXBUFF", | |
328 | [15] = "TXBUFE", | |
deec9ae3 HS |
329 | [16] = "RINDE", |
330 | [17] = "RDIRE", | |
331 | [18] = "RCRCE", | |
332 | [19] = "RENDE", | |
333 | [20] = "RTOE", | |
334 | [21] = "DCRCE", | |
335 | [22] = "DTOE", | |
04d699c3 RE |
336 | [23] = "CSTOE", |
337 | [24] = "BLKOVRE", | |
338 | [25] = "DMADONE", | |
339 | [26] = "FIFOEMPTY", | |
340 | [27] = "XFRDONE", | |
deec9ae3 HS |
341 | [30] = "OVRE", |
342 | [31] = "UNRE", | |
343 | }; | |
344 | unsigned int i; | |
345 | ||
346 | seq_printf(s, "%s:\t0x%08x", regname, value); | |
347 | for (i = 0; i < ARRAY_SIZE(sr_bit); i++) { | |
348 | if (value & (1 << i)) { | |
349 | if (sr_bit[i]) | |
350 | seq_printf(s, " %s", sr_bit[i]); | |
351 | else | |
352 | seq_puts(s, " UNKNOWN"); | |
353 | } | |
354 | } | |
355 | seq_putc(s, '\n'); | |
356 | } | |
357 | ||
358 | static int atmci_regs_show(struct seq_file *s, void *v) | |
359 | { | |
360 | struct atmel_mci *host = s->private; | |
361 | u32 *buf; | |
362 | ||
2c96a293 | 363 | buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL); |
deec9ae3 HS |
364 | if (!buf) |
365 | return -ENOMEM; | |
366 | ||
965ebf33 HS |
367 | /* |
368 | * Grab a more or less consistent snapshot. Note that we're | |
369 | * not disabling interrupts, so IMR and SR may not be | |
370 | * consistent. | |
371 | */ | |
372 | spin_lock_bh(&host->lock); | |
87e60f2b | 373 | clk_enable(host->mck); |
2c96a293 | 374 | memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE); |
87e60f2b | 375 | clk_disable(host->mck); |
965ebf33 | 376 | spin_unlock_bh(&host->lock); |
deec9ae3 HS |
377 | |
378 | seq_printf(s, "MR:\t0x%08x%s%s CLKDIV=%u\n", | |
2c96a293 LD |
379 | buf[ATMCI_MR / 4], |
380 | buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "", | |
381 | buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "", | |
382 | buf[ATMCI_MR / 4] & 0xff); | |
383 | seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]); | |
384 | seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]); | |
385 | seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]); | |
deec9ae3 | 386 | seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n", |
2c96a293 LD |
387 | buf[ATMCI_BLKR / 4], |
388 | buf[ATMCI_BLKR / 4] & 0xffff, | |
389 | (buf[ATMCI_BLKR / 4] >> 16) & 0xffff); | |
796211b7 | 390 | if (host->caps.has_cstor_reg) |
2c96a293 | 391 | seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]); |
deec9ae3 HS |
392 | |
393 | /* Don't read RSPR and RDR; it will consume the data there */ | |
394 | ||
2c96a293 LD |
395 | atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]); |
396 | atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]); | |
deec9ae3 | 397 | |
796211b7 | 398 | if (host->caps.has_dma) { |
74791a2d NF |
399 | u32 val; |
400 | ||
2c96a293 | 401 | val = buf[ATMCI_DMA / 4]; |
74791a2d NF |
402 | seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n", |
403 | val, val & 3, | |
404 | ((val >> 4) & 3) ? | |
405 | 1 << (((val >> 4) & 3) + 1) : 1, | |
2c96a293 | 406 | val & ATMCI_DMAEN ? " DMAEN" : ""); |
796211b7 LD |
407 | } |
408 | if (host->caps.has_cfg_reg) { | |
409 | u32 val; | |
74791a2d | 410 | |
2c96a293 | 411 | val = buf[ATMCI_CFG / 4]; |
74791a2d NF |
412 | seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n", |
413 | val, | |
2c96a293 LD |
414 | val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "", |
415 | val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "", | |
416 | val & ATMCI_CFG_HSMODE ? " HSMODE" : "", | |
417 | val & ATMCI_CFG_LSYNC ? " LSYNC" : ""); | |
74791a2d NF |
418 | } |
419 | ||
b17339a1 HS |
420 | kfree(buf); |
421 | ||
deec9ae3 HS |
422 | return 0; |
423 | } | |
424 | ||
425 | static int atmci_regs_open(struct inode *inode, struct file *file) | |
426 | { | |
427 | return single_open(file, atmci_regs_show, inode->i_private); | |
428 | } | |
429 | ||
430 | static const struct file_operations atmci_regs_fops = { | |
431 | .owner = THIS_MODULE, | |
432 | .open = atmci_regs_open, | |
433 | .read = seq_read, | |
434 | .llseek = seq_lseek, | |
435 | .release = single_release, | |
436 | }; | |
437 | ||
965ebf33 | 438 | static void atmci_init_debugfs(struct atmel_mci_slot *slot) |
deec9ae3 | 439 | { |
965ebf33 HS |
440 | struct mmc_host *mmc = slot->mmc; |
441 | struct atmel_mci *host = slot->host; | |
442 | struct dentry *root; | |
443 | struct dentry *node; | |
deec9ae3 | 444 | |
deec9ae3 HS |
445 | root = mmc->debugfs_root; |
446 | if (!root) | |
447 | return; | |
448 | ||
449 | node = debugfs_create_file("regs", S_IRUSR, root, host, | |
450 | &atmci_regs_fops); | |
451 | if (IS_ERR(node)) | |
452 | return; | |
453 | if (!node) | |
454 | goto err; | |
455 | ||
965ebf33 | 456 | node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops); |
deec9ae3 HS |
457 | if (!node) |
458 | goto err; | |
459 | ||
c06ad258 HS |
460 | node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); |
461 | if (!node) | |
462 | goto err; | |
463 | ||
deec9ae3 HS |
464 | node = debugfs_create_x32("pending_events", S_IRUSR, root, |
465 | (u32 *)&host->pending_events); | |
466 | if (!node) | |
467 | goto err; | |
468 | ||
469 | node = debugfs_create_x32("completed_events", S_IRUSR, root, | |
470 | (u32 *)&host->completed_events); | |
471 | if (!node) | |
472 | goto err; | |
473 | ||
474 | return; | |
475 | ||
476 | err: | |
965ebf33 | 477 | dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); |
deec9ae3 | 478 | } |
7d2be074 | 479 | |
2c96a293 | 480 | static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host, |
7d2be074 HS |
481 | unsigned int ns) |
482 | { | |
483 | return (ns * (host->bus_hz / 1000000) + 999) / 1000; | |
484 | } | |
485 | ||
486 | static void atmci_set_timeout(struct atmel_mci *host, | |
965ebf33 | 487 | struct atmel_mci_slot *slot, struct mmc_data *data) |
7d2be074 HS |
488 | { |
489 | static unsigned dtomul_to_shift[] = { | |
490 | 0, 4, 7, 8, 10, 12, 16, 20 | |
491 | }; | |
492 | unsigned timeout; | |
493 | unsigned dtocyc; | |
494 | unsigned dtomul; | |
495 | ||
2c96a293 LD |
496 | timeout = atmci_ns_to_clocks(host, data->timeout_ns) |
497 | + data->timeout_clks; | |
7d2be074 HS |
498 | |
499 | for (dtomul = 0; dtomul < 8; dtomul++) { | |
500 | unsigned shift = dtomul_to_shift[dtomul]; | |
501 | dtocyc = (timeout + (1 << shift) - 1) >> shift; | |
502 | if (dtocyc < 15) | |
503 | break; | |
504 | } | |
505 | ||
506 | if (dtomul >= 8) { | |
507 | dtomul = 7; | |
508 | dtocyc = 15; | |
509 | } | |
510 | ||
965ebf33 | 511 | dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n", |
7d2be074 | 512 | dtocyc << dtomul_to_shift[dtomul]); |
03fc9a7f | 513 | atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc))); |
7d2be074 HS |
514 | } |
515 | ||
516 | /* | |
517 | * Return mask with command flags to be enabled for this command. | |
518 | */ | |
519 | static u32 atmci_prepare_command(struct mmc_host *mmc, | |
520 | struct mmc_command *cmd) | |
521 | { | |
522 | struct mmc_data *data; | |
523 | u32 cmdr; | |
524 | ||
525 | cmd->error = -EINPROGRESS; | |
526 | ||
2c96a293 | 527 | cmdr = ATMCI_CMDR_CMDNB(cmd->opcode); |
7d2be074 HS |
528 | |
529 | if (cmd->flags & MMC_RSP_PRESENT) { | |
530 | if (cmd->flags & MMC_RSP_136) | |
2c96a293 | 531 | cmdr |= ATMCI_CMDR_RSPTYP_136BIT; |
7d2be074 | 532 | else |
2c96a293 | 533 | cmdr |= ATMCI_CMDR_RSPTYP_48BIT; |
7d2be074 HS |
534 | } |
535 | ||
536 | /* | |
537 | * This should really be MAXLAT_5 for CMD2 and ACMD41, but | |
538 | * it's too difficult to determine whether this is an ACMD or | |
539 | * not. Better make it 64. | |
540 | */ | |
2c96a293 | 541 | cmdr |= ATMCI_CMDR_MAXLAT_64CYC; |
7d2be074 HS |
542 | |
543 | if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN) | |
2c96a293 | 544 | cmdr |= ATMCI_CMDR_OPDCMD; |
7d2be074 HS |
545 | |
546 | data = cmd->data; | |
547 | if (data) { | |
2c96a293 | 548 | cmdr |= ATMCI_CMDR_START_XFER; |
2f1d7918 NF |
549 | |
550 | if (cmd->opcode == SD_IO_RW_EXTENDED) { | |
2c96a293 | 551 | cmdr |= ATMCI_CMDR_SDIO_BLOCK; |
2f1d7918 NF |
552 | } else { |
553 | if (data->flags & MMC_DATA_STREAM) | |
2c96a293 | 554 | cmdr |= ATMCI_CMDR_STREAM; |
2f1d7918 | 555 | else if (data->blocks > 1) |
2c96a293 | 556 | cmdr |= ATMCI_CMDR_MULTI_BLOCK; |
2f1d7918 | 557 | else |
2c96a293 | 558 | cmdr |= ATMCI_CMDR_BLOCK; |
2f1d7918 | 559 | } |
7d2be074 HS |
560 | |
561 | if (data->flags & MMC_DATA_READ) | |
2c96a293 | 562 | cmdr |= ATMCI_CMDR_TRDIR_READ; |
7d2be074 HS |
563 | } |
564 | ||
565 | return cmdr; | |
566 | } | |
567 | ||
11d1488b | 568 | static void atmci_send_command(struct atmel_mci *host, |
965ebf33 | 569 | struct mmc_command *cmd, u32 cmd_flags) |
7d2be074 | 570 | { |
7d2be074 HS |
571 | WARN_ON(host->cmd); |
572 | host->cmd = cmd; | |
573 | ||
965ebf33 | 574 | dev_vdbg(&host->pdev->dev, |
7d2be074 HS |
575 | "start command: ARGR=0x%08x CMDR=0x%08x\n", |
576 | cmd->arg, cmd_flags); | |
577 | ||
03fc9a7f LD |
578 | atmci_writel(host, ATMCI_ARGR, cmd->arg); |
579 | atmci_writel(host, ATMCI_CMDR, cmd_flags); | |
7d2be074 HS |
580 | } |
581 | ||
2c96a293 | 582 | static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data) |
7d2be074 | 583 | { |
11d1488b | 584 | atmci_send_command(host, data->stop, host->stop_cmdr); |
03fc9a7f | 585 | atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY); |
7d2be074 HS |
586 | } |
587 | ||
796211b7 LD |
588 | /* |
589 | * Configure given PDC buffer taking care of alignement issues. | |
590 | * Update host->data_size and host->sg. | |
591 | */ | |
592 | static void atmci_pdc_set_single_buf(struct atmel_mci *host, | |
593 | enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb) | |
594 | { | |
595 | u32 pointer_reg, counter_reg; | |
596 | ||
597 | if (dir == XFER_RECEIVE) { | |
598 | pointer_reg = ATMEL_PDC_RPR; | |
599 | counter_reg = ATMEL_PDC_RCR; | |
600 | } else { | |
601 | pointer_reg = ATMEL_PDC_TPR; | |
602 | counter_reg = ATMEL_PDC_TCR; | |
603 | } | |
604 | ||
605 | if (buf_nb == PDC_SECOND_BUF) { | |
1ebbe3d3 LD |
606 | pointer_reg += ATMEL_PDC_SCND_BUF_OFF; |
607 | counter_reg += ATMEL_PDC_SCND_BUF_OFF; | |
796211b7 LD |
608 | } |
609 | ||
610 | atmci_writel(host, pointer_reg, sg_dma_address(host->sg)); | |
341fa4c3 | 611 | if (host->data_size <= sg_dma_len(host->sg)) { |
796211b7 LD |
612 | if (host->data_size & 0x3) { |
613 | /* If size is different from modulo 4, transfer bytes */ | |
614 | atmci_writel(host, counter_reg, host->data_size); | |
615 | atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE); | |
616 | } else { | |
617 | /* Else transfer 32-bits words */ | |
618 | atmci_writel(host, counter_reg, host->data_size / 4); | |
619 | } | |
620 | host->data_size = 0; | |
621 | } else { | |
622 | /* We assume the size of a page is 32-bits aligned */ | |
341fa4c3 LD |
623 | atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4); |
624 | host->data_size -= sg_dma_len(host->sg); | |
796211b7 LD |
625 | if (host->data_size) |
626 | host->sg = sg_next(host->sg); | |
627 | } | |
628 | } | |
629 | ||
630 | /* | |
631 | * Configure PDC buffer according to the data size ie configuring one or two | |
632 | * buffers. Don't use this function if you want to configure only the second | |
633 | * buffer. In this case, use atmci_pdc_set_single_buf. | |
634 | */ | |
635 | static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir) | |
65e8b083 | 636 | { |
796211b7 LD |
637 | atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF); |
638 | if (host->data_size) | |
639 | atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF); | |
640 | } | |
641 | ||
642 | /* | |
643 | * Unmap sg lists, called when transfer is finished. | |
644 | */ | |
645 | static void atmci_pdc_cleanup(struct atmel_mci *host) | |
646 | { | |
647 | struct mmc_data *data = host->data; | |
65e8b083 | 648 | |
009a891b | 649 | if (data) |
796211b7 LD |
650 | dma_unmap_sg(&host->pdev->dev, |
651 | data->sg, data->sg_len, | |
652 | ((data->flags & MMC_DATA_WRITE) | |
653 | ? DMA_TO_DEVICE : DMA_FROM_DEVICE)); | |
65e8b083 HS |
654 | } |
655 | ||
796211b7 LD |
656 | /* |
657 | * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after | |
658 | * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY | |
659 | * interrupt needed for both transfer directions. | |
660 | */ | |
661 | static void atmci_pdc_complete(struct atmel_mci *host) | |
65e8b083 | 662 | { |
796211b7 LD |
663 | atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); |
664 | atmci_pdc_cleanup(host); | |
65e8b083 | 665 | |
796211b7 LD |
666 | /* |
667 | * If the card was removed, data will be NULL. No point trying | |
668 | * to send the stop command or waiting for NBUSY in this case. | |
669 | */ | |
670 | if (host->data) { | |
65e8b083 | 671 | atmci_set_pending(host, EVENT_XFER_COMPLETE); |
796211b7 | 672 | tasklet_schedule(&host->tasklet); |
03fc9a7f | 673 | atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); |
65e8b083 HS |
674 | } |
675 | } | |
676 | ||
796211b7 LD |
677 | static void atmci_dma_cleanup(struct atmel_mci *host) |
678 | { | |
679 | struct mmc_data *data = host->data; | |
680 | ||
681 | if (data) | |
682 | dma_unmap_sg(host->dma.chan->device->dev, | |
683 | data->sg, data->sg_len, | |
684 | ((data->flags & MMC_DATA_WRITE) | |
685 | ? DMA_TO_DEVICE : DMA_FROM_DEVICE)); | |
686 | } | |
687 | ||
688 | /* | |
689 | * This function is called by the DMA driver from tasklet context. | |
690 | */ | |
65e8b083 HS |
691 | static void atmci_dma_complete(void *arg) |
692 | { | |
693 | struct atmel_mci *host = arg; | |
694 | struct mmc_data *data = host->data; | |
695 | ||
696 | dev_vdbg(&host->pdev->dev, "DMA complete\n"); | |
697 | ||
796211b7 | 698 | if (host->caps.has_dma) |
74791a2d | 699 | /* Disable DMA hardware handshaking on MCI */ |
03fc9a7f | 700 | atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN); |
74791a2d | 701 | |
65e8b083 HS |
702 | atmci_dma_cleanup(host); |
703 | ||
704 | /* | |
705 | * If the card was removed, data will be NULL. No point trying | |
706 | * to send the stop command or waiting for NBUSY in this case. | |
707 | */ | |
708 | if (data) { | |
709 | atmci_set_pending(host, EVENT_XFER_COMPLETE); | |
710 | tasklet_schedule(&host->tasklet); | |
711 | ||
712 | /* | |
713 | * Regardless of what the documentation says, we have | |
714 | * to wait for NOTBUSY even after block read | |
715 | * operations. | |
716 | * | |
717 | * When the DMA transfer is complete, the controller | |
718 | * may still be reading the CRC from the card, i.e. | |
719 | * the data transfer is still in progress and we | |
720 | * haven't seen all the potential error bits yet. | |
721 | * | |
722 | * The interrupt handler will schedule a different | |
723 | * tasklet to finish things up when the data transfer | |
724 | * is completely done. | |
725 | * | |
726 | * We may not complete the mmc request here anyway | |
727 | * because the mmc layer may call back and cause us to | |
728 | * violate the "don't submit new operations from the | |
729 | * completion callback" rule of the dma engine | |
730 | * framework. | |
731 | */ | |
03fc9a7f | 732 | atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); |
65e8b083 HS |
733 | } |
734 | } | |
735 | ||
796211b7 LD |
736 | /* |
737 | * Returns a mask of interrupt flags to be enabled after the whole | |
738 | * request has been prepared. | |
739 | */ | |
740 | static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data) | |
741 | { | |
742 | u32 iflags; | |
743 | ||
744 | data->error = -EINPROGRESS; | |
745 | ||
746 | host->sg = data->sg; | |
747 | host->data = data; | |
748 | host->data_chan = NULL; | |
749 | ||
750 | iflags = ATMCI_DATA_ERROR_FLAGS; | |
751 | ||
752 | /* | |
753 | * Errata: MMC data write operation with less than 12 | |
754 | * bytes is impossible. | |
755 | * | |
756 | * Errata: MCI Transmit Data Register (TDR) FIFO | |
757 | * corruption when length is not multiple of 4. | |
758 | */ | |
759 | if (data->blocks * data->blksz < 12 | |
760 | || (data->blocks * data->blksz) & 3) | |
761 | host->need_reset = true; | |
762 | ||
763 | host->pio_offset = 0; | |
764 | if (data->flags & MMC_DATA_READ) | |
765 | iflags |= ATMCI_RXRDY; | |
766 | else | |
767 | iflags |= ATMCI_TXRDY; | |
768 | ||
769 | return iflags; | |
770 | } | |
771 | ||
772 | /* | |
773 | * Set interrupt flags and set block length into the MCI mode register even | |
774 | * if this value is also accessible in the MCI block register. It seems to be | |
775 | * necessary before the High Speed MCI version. It also map sg and configure | |
776 | * PDC registers. | |
777 | */ | |
778 | static u32 | |
779 | atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data) | |
780 | { | |
781 | u32 iflags, tmp; | |
782 | unsigned int sg_len; | |
783 | enum dma_data_direction dir; | |
784 | ||
785 | data->error = -EINPROGRESS; | |
786 | ||
787 | host->data = data; | |
788 | host->sg = data->sg; | |
789 | iflags = ATMCI_DATA_ERROR_FLAGS; | |
790 | ||
791 | /* Enable pdc mode */ | |
792 | atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE); | |
793 | ||
794 | if (data->flags & MMC_DATA_READ) { | |
795 | dir = DMA_FROM_DEVICE; | |
796 | iflags |= ATMCI_ENDRX | ATMCI_RXBUFF; | |
797 | } else { | |
798 | dir = DMA_TO_DEVICE; | |
799 | iflags |= ATMCI_ENDTX | ATMCI_TXBUFE; | |
800 | } | |
801 | ||
802 | /* Set BLKLEN */ | |
803 | tmp = atmci_readl(host, ATMCI_MR); | |
804 | tmp &= 0x0000ffff; | |
805 | tmp |= ATMCI_BLKLEN(data->blksz); | |
806 | atmci_writel(host, ATMCI_MR, tmp); | |
807 | ||
808 | /* Configure PDC */ | |
809 | host->data_size = data->blocks * data->blksz; | |
810 | sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, dir); | |
796211b7 LD |
811 | if (host->data_size) |
812 | atmci_pdc_set_both_buf(host, | |
813 | ((dir == DMA_FROM_DEVICE) ? XFER_RECEIVE : XFER_TRANSMIT)); | |
814 | ||
815 | return iflags; | |
816 | } | |
817 | ||
818 | static u32 | |
74791a2d | 819 | atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data) |
65e8b083 HS |
820 | { |
821 | struct dma_chan *chan; | |
822 | struct dma_async_tx_descriptor *desc; | |
823 | struct scatterlist *sg; | |
824 | unsigned int i; | |
825 | enum dma_data_direction direction; | |
05f5799c | 826 | enum dma_transfer_direction slave_dirn; |
657a77fa | 827 | unsigned int sglen; |
796211b7 LD |
828 | u32 iflags; |
829 | ||
830 | data->error = -EINPROGRESS; | |
831 | ||
832 | WARN_ON(host->data); | |
833 | host->sg = NULL; | |
834 | host->data = data; | |
835 | ||
836 | iflags = ATMCI_DATA_ERROR_FLAGS; | |
65e8b083 HS |
837 | |
838 | /* | |
839 | * We don't do DMA on "complex" transfers, i.e. with | |
840 | * non-word-aligned buffers or lengths. Also, we don't bother | |
841 | * with all the DMA setup overhead for short transfers. | |
842 | */ | |
796211b7 LD |
843 | if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD) |
844 | return atmci_prepare_data(host, data); | |
65e8b083 | 845 | if (data->blksz & 3) |
796211b7 | 846 | return atmci_prepare_data(host, data); |
65e8b083 HS |
847 | |
848 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
849 | if (sg->offset & 3 || sg->length & 3) | |
796211b7 | 850 | return atmci_prepare_data(host, data); |
65e8b083 HS |
851 | } |
852 | ||
853 | /* If we don't have a channel, we can't do DMA */ | |
854 | chan = host->dma.chan; | |
6f49a57a | 855 | if (chan) |
65e8b083 | 856 | host->data_chan = chan; |
65e8b083 HS |
857 | |
858 | if (!chan) | |
859 | return -ENODEV; | |
860 | ||
796211b7 | 861 | if (host->caps.has_dma) |
03fc9a7f | 862 | atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(3) | ATMCI_DMAEN); |
74791a2d | 863 | |
05f5799c | 864 | if (data->flags & MMC_DATA_READ) { |
65e8b083 | 865 | direction = DMA_FROM_DEVICE; |
05f5799c VK |
866 | slave_dirn = DMA_DEV_TO_MEM; |
867 | } else { | |
65e8b083 | 868 | direction = DMA_TO_DEVICE; |
05f5799c VK |
869 | slave_dirn = DMA_MEM_TO_DEV; |
870 | } | |
65e8b083 | 871 | |
266ac3f2 | 872 | sglen = dma_map_sg(chan->device->dev, data->sg, |
796211b7 | 873 | data->sg_len, direction); |
88ce4db3 | 874 | |
65e8b083 | 875 | desc = chan->device->device_prep_slave_sg(chan, |
05f5799c | 876 | data->sg, sglen, slave_dirn, |
65e8b083 HS |
877 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
878 | if (!desc) | |
657a77fa | 879 | goto unmap_exit; |
65e8b083 HS |
880 | |
881 | host->dma.data_desc = desc; | |
882 | desc->callback = atmci_dma_complete; | |
883 | desc->callback_param = host; | |
65e8b083 | 884 | |
796211b7 | 885 | return iflags; |
657a77fa | 886 | unmap_exit: |
88ce4db3 | 887 | dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, direction); |
657a77fa | 888 | return -ENOMEM; |
65e8b083 HS |
889 | } |
890 | ||
796211b7 LD |
891 | static void |
892 | atmci_submit_data(struct atmel_mci *host, struct mmc_data *data) | |
893 | { | |
894 | return; | |
895 | } | |
896 | ||
897 | /* | |
898 | * Start PDC according to transfer direction. | |
899 | */ | |
900 | static void | |
901 | atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data) | |
902 | { | |
903 | if (data->flags & MMC_DATA_READ) | |
904 | atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); | |
905 | else | |
906 | atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); | |
907 | } | |
908 | ||
909 | static void | |
910 | atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data) | |
74791a2d NF |
911 | { |
912 | struct dma_chan *chan = host->data_chan; | |
913 | struct dma_async_tx_descriptor *desc = host->dma.data_desc; | |
914 | ||
915 | if (chan) { | |
5328906a LW |
916 | dmaengine_submit(desc); |
917 | dma_async_issue_pending(chan); | |
74791a2d NF |
918 | } |
919 | } | |
920 | ||
796211b7 | 921 | static void atmci_stop_transfer(struct atmel_mci *host) |
65e8b083 | 922 | { |
65e8b083 | 923 | atmci_set_pending(host, EVENT_XFER_COMPLETE); |
03fc9a7f | 924 | atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); |
65e8b083 HS |
925 | } |
926 | ||
7d2be074 | 927 | /* |
796211b7 | 928 | * Stop data transfer because error(s) occured. |
7d2be074 | 929 | */ |
796211b7 | 930 | static void atmci_stop_transfer_pdc(struct atmel_mci *host) |
7d2be074 | 931 | { |
796211b7 LD |
932 | atmci_set_pending(host, EVENT_XFER_COMPLETE); |
933 | atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); | |
934 | } | |
965ebf33 | 935 | |
796211b7 LD |
936 | static void atmci_stop_transfer_dma(struct atmel_mci *host) |
937 | { | |
938 | struct dma_chan *chan = host->data_chan; | |
965ebf33 | 939 | |
796211b7 LD |
940 | if (chan) { |
941 | dmaengine_terminate_all(chan); | |
942 | atmci_dma_cleanup(host); | |
943 | } else { | |
944 | /* Data transfer was stopped by the interrupt handler */ | |
945 | atmci_set_pending(host, EVENT_XFER_COMPLETE); | |
946 | atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); | |
65e8b083 | 947 | } |
7d2be074 HS |
948 | } |
949 | ||
796211b7 LD |
950 | /* |
951 | * Start a request: prepare data if needed, prepare the command and activate | |
952 | * interrupts. | |
953 | */ | |
965ebf33 HS |
954 | static void atmci_start_request(struct atmel_mci *host, |
955 | struct atmel_mci_slot *slot) | |
7d2be074 | 956 | { |
965ebf33 | 957 | struct mmc_request *mrq; |
7d2be074 | 958 | struct mmc_command *cmd; |
965ebf33 | 959 | struct mmc_data *data; |
7d2be074 | 960 | u32 iflags; |
965ebf33 | 961 | u32 cmdflags; |
7d2be074 | 962 | |
965ebf33 HS |
963 | mrq = slot->mrq; |
964 | host->cur_slot = slot; | |
7d2be074 | 965 | host->mrq = mrq; |
965ebf33 | 966 | |
7d2be074 HS |
967 | host->pending_events = 0; |
968 | host->completed_events = 0; | |
ca55f46e | 969 | host->data_status = 0; |
7d2be074 | 970 | |
965ebf33 | 971 | if (host->need_reset) { |
03fc9a7f LD |
972 | atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); |
973 | atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN); | |
974 | atmci_writel(host, ATMCI_MR, host->mode_reg); | |
796211b7 | 975 | if (host->caps.has_cfg_reg) |
03fc9a7f | 976 | atmci_writel(host, ATMCI_CFG, host->cfg_reg); |
965ebf33 HS |
977 | host->need_reset = false; |
978 | } | |
03fc9a7f | 979 | atmci_writel(host, ATMCI_SDCR, slot->sdc_reg); |
965ebf33 | 980 | |
03fc9a7f | 981 | iflags = atmci_readl(host, ATMCI_IMR); |
2c96a293 | 982 | if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB)) |
965ebf33 HS |
983 | dev_warn(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n", |
984 | iflags); | |
985 | ||
986 | if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) { | |
987 | /* Send init sequence (74 clock cycles) */ | |
03fc9a7f LD |
988 | atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT); |
989 | while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY)) | |
965ebf33 HS |
990 | cpu_relax(); |
991 | } | |
74791a2d | 992 | iflags = 0; |
7d2be074 HS |
993 | data = mrq->data; |
994 | if (data) { | |
965ebf33 | 995 | atmci_set_timeout(host, slot, data); |
a252e3e3 HS |
996 | |
997 | /* Must set block count/size before sending command */ | |
03fc9a7f | 998 | atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks) |
2c96a293 | 999 | | ATMCI_BLKLEN(data->blksz)); |
965ebf33 | 1000 | dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n", |
2c96a293 | 1001 | ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz)); |
74791a2d | 1002 | |
796211b7 | 1003 | iflags |= host->prepare_data(host, data); |
7d2be074 HS |
1004 | } |
1005 | ||
2c96a293 | 1006 | iflags |= ATMCI_CMDRDY; |
7d2be074 | 1007 | cmd = mrq->cmd; |
965ebf33 | 1008 | cmdflags = atmci_prepare_command(slot->mmc, cmd); |
11d1488b | 1009 | atmci_send_command(host, cmd, cmdflags); |
7d2be074 HS |
1010 | |
1011 | if (data) | |
796211b7 | 1012 | host->submit_data(host, data); |
7d2be074 HS |
1013 | |
1014 | if (mrq->stop) { | |
965ebf33 | 1015 | host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop); |
2c96a293 | 1016 | host->stop_cmdr |= ATMCI_CMDR_STOP_XFER; |
7d2be074 | 1017 | if (!(data->flags & MMC_DATA_WRITE)) |
2c96a293 | 1018 | host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ; |
7d2be074 | 1019 | if (data->flags & MMC_DATA_STREAM) |
2c96a293 | 1020 | host->stop_cmdr |= ATMCI_CMDR_STREAM; |
7d2be074 | 1021 | else |
2c96a293 | 1022 | host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK; |
7d2be074 HS |
1023 | } |
1024 | ||
1025 | /* | |
1026 | * We could have enabled interrupts earlier, but I suspect | |
1027 | * that would open up a nice can of interesting race | |
1028 | * conditions (e.g. command and data complete, but stop not | |
1029 | * prepared yet.) | |
1030 | */ | |
03fc9a7f | 1031 | atmci_writel(host, ATMCI_IER, iflags); |
965ebf33 | 1032 | } |
7d2be074 | 1033 | |
965ebf33 HS |
1034 | static void atmci_queue_request(struct atmel_mci *host, |
1035 | struct atmel_mci_slot *slot, struct mmc_request *mrq) | |
1036 | { | |
1037 | dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", | |
1038 | host->state); | |
1039 | ||
1040 | spin_lock_bh(&host->lock); | |
1041 | slot->mrq = mrq; | |
1042 | if (host->state == STATE_IDLE) { | |
1043 | host->state = STATE_SENDING_CMD; | |
1044 | atmci_start_request(host, slot); | |
1045 | } else { | |
1046 | list_add_tail(&slot->queue_node, &host->queue); | |
1047 | } | |
1048 | spin_unlock_bh(&host->lock); | |
1049 | } | |
7d2be074 | 1050 | |
965ebf33 HS |
1051 | static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq) |
1052 | { | |
1053 | struct atmel_mci_slot *slot = mmc_priv(mmc); | |
1054 | struct atmel_mci *host = slot->host; | |
1055 | struct mmc_data *data; | |
1056 | ||
1057 | WARN_ON(slot->mrq); | |
1058 | ||
1059 | /* | |
1060 | * We may "know" the card is gone even though there's still an | |
1061 | * electrical connection. If so, we really need to communicate | |
1062 | * this to the MMC core since there won't be any more | |
1063 | * interrupts as the card is completely removed. Otherwise, | |
1064 | * the MMC core might believe the card is still there even | |
1065 | * though the card was just removed very slowly. | |
1066 | */ | |
1067 | if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) { | |
1068 | mrq->cmd->error = -ENOMEDIUM; | |
1069 | mmc_request_done(mmc, mrq); | |
1070 | return; | |
1071 | } | |
1072 | ||
1073 | /* We don't support multiple blocks of weird lengths. */ | |
1074 | data = mrq->data; | |
1075 | if (data && data->blocks > 1 && data->blksz & 3) { | |
1076 | mrq->cmd->error = -EINVAL; | |
1077 | mmc_request_done(mmc, mrq); | |
1078 | } | |
1079 | ||
1080 | atmci_queue_request(host, slot, mrq); | |
7d2be074 HS |
1081 | } |
1082 | ||
1083 | static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
1084 | { | |
965ebf33 HS |
1085 | struct atmel_mci_slot *slot = mmc_priv(mmc); |
1086 | struct atmel_mci *host = slot->host; | |
1087 | unsigned int i; | |
7d2be074 | 1088 | |
2c96a293 | 1089 | slot->sdc_reg &= ~ATMCI_SDCBUS_MASK; |
945533b5 HS |
1090 | switch (ios->bus_width) { |
1091 | case MMC_BUS_WIDTH_1: | |
2c96a293 | 1092 | slot->sdc_reg |= ATMCI_SDCBUS_1BIT; |
945533b5 HS |
1093 | break; |
1094 | case MMC_BUS_WIDTH_4: | |
2c96a293 | 1095 | slot->sdc_reg |= ATMCI_SDCBUS_4BIT; |
945533b5 HS |
1096 | break; |
1097 | } | |
1098 | ||
7d2be074 | 1099 | if (ios->clock) { |
965ebf33 | 1100 | unsigned int clock_min = ~0U; |
7d2be074 HS |
1101 | u32 clkdiv; |
1102 | ||
965ebf33 HS |
1103 | spin_lock_bh(&host->lock); |
1104 | if (!host->mode_reg) { | |
945533b5 | 1105 | clk_enable(host->mck); |
03fc9a7f LD |
1106 | atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); |
1107 | atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN); | |
796211b7 | 1108 | if (host->caps.has_cfg_reg) |
03fc9a7f | 1109 | atmci_writel(host, ATMCI_CFG, host->cfg_reg); |
965ebf33 | 1110 | } |
945533b5 | 1111 | |
965ebf33 HS |
1112 | /* |
1113 | * Use mirror of ios->clock to prevent race with mmc | |
1114 | * core ios update when finding the minimum. | |
1115 | */ | |
1116 | slot->clock = ios->clock; | |
2c96a293 | 1117 | for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { |
965ebf33 HS |
1118 | if (host->slot[i] && host->slot[i]->clock |
1119 | && host->slot[i]->clock < clock_min) | |
1120 | clock_min = host->slot[i]->clock; | |
1121 | } | |
1122 | ||
1123 | /* Calculate clock divider */ | |
1124 | clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1; | |
7d2be074 HS |
1125 | if (clkdiv > 255) { |
1126 | dev_warn(&mmc->class_dev, | |
1127 | "clock %u too slow; using %lu\n", | |
965ebf33 | 1128 | clock_min, host->bus_hz / (2 * 256)); |
7d2be074 HS |
1129 | clkdiv = 255; |
1130 | } | |
1131 | ||
2c96a293 | 1132 | host->mode_reg = ATMCI_MR_CLKDIV(clkdiv); |
04d699c3 | 1133 | |
965ebf33 HS |
1134 | /* |
1135 | * WRPROOF and RDPROOF prevent overruns/underruns by | |
1136 | * stopping the clock when the FIFO is full/empty. | |
1137 | * This state is not expected to last for long. | |
1138 | */ | |
796211b7 | 1139 | if (host->caps.has_rwproof) |
2c96a293 | 1140 | host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF); |
7d2be074 | 1141 | |
796211b7 | 1142 | if (host->caps.has_cfg_reg) { |
99ddffd8 NF |
1143 | /* setup High Speed mode in relation with card capacity */ |
1144 | if (ios->timing == MMC_TIMING_SD_HS) | |
2c96a293 | 1145 | host->cfg_reg |= ATMCI_CFG_HSMODE; |
99ddffd8 | 1146 | else |
2c96a293 | 1147 | host->cfg_reg &= ~ATMCI_CFG_HSMODE; |
99ddffd8 NF |
1148 | } |
1149 | ||
1150 | if (list_empty(&host->queue)) { | |
03fc9a7f | 1151 | atmci_writel(host, ATMCI_MR, host->mode_reg); |
796211b7 | 1152 | if (host->caps.has_cfg_reg) |
03fc9a7f | 1153 | atmci_writel(host, ATMCI_CFG, host->cfg_reg); |
99ddffd8 | 1154 | } else { |
965ebf33 | 1155 | host->need_clock_update = true; |
99ddffd8 | 1156 | } |
965ebf33 HS |
1157 | |
1158 | spin_unlock_bh(&host->lock); | |
945533b5 | 1159 | } else { |
965ebf33 HS |
1160 | bool any_slot_active = false; |
1161 | ||
1162 | spin_lock_bh(&host->lock); | |
1163 | slot->clock = 0; | |
2c96a293 | 1164 | for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { |
965ebf33 HS |
1165 | if (host->slot[i] && host->slot[i]->clock) { |
1166 | any_slot_active = true; | |
1167 | break; | |
1168 | } | |
945533b5 | 1169 | } |
965ebf33 | 1170 | if (!any_slot_active) { |
03fc9a7f | 1171 | atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS); |
965ebf33 | 1172 | if (host->mode_reg) { |
03fc9a7f | 1173 | atmci_readl(host, ATMCI_MR); |
965ebf33 HS |
1174 | clk_disable(host->mck); |
1175 | } | |
1176 | host->mode_reg = 0; | |
1177 | } | |
1178 | spin_unlock_bh(&host->lock); | |
7d2be074 HS |
1179 | } |
1180 | ||
1181 | switch (ios->power_mode) { | |
965ebf33 HS |
1182 | case MMC_POWER_UP: |
1183 | set_bit(ATMCI_CARD_NEED_INIT, &slot->flags); | |
1184 | break; | |
7d2be074 HS |
1185 | default: |
1186 | /* | |
1187 | * TODO: None of the currently available AVR32-based | |
1188 | * boards allow MMC power to be turned off. Implement | |
1189 | * power control when this can be tested properly. | |
965ebf33 HS |
1190 | * |
1191 | * We also need to hook this into the clock management | |
1192 | * somehow so that newly inserted cards aren't | |
1193 | * subjected to a fast clock before we have a chance | |
1194 | * to figure out what the maximum rate is. Currently, | |
1195 | * there's no way to avoid this, and there never will | |
1196 | * be for boards that don't support power control. | |
7d2be074 HS |
1197 | */ |
1198 | break; | |
1199 | } | |
1200 | } | |
1201 | ||
1202 | static int atmci_get_ro(struct mmc_host *mmc) | |
1203 | { | |
965ebf33 HS |
1204 | int read_only = -ENOSYS; |
1205 | struct atmel_mci_slot *slot = mmc_priv(mmc); | |
7d2be074 | 1206 | |
965ebf33 HS |
1207 | if (gpio_is_valid(slot->wp_pin)) { |
1208 | read_only = gpio_get_value(slot->wp_pin); | |
7d2be074 HS |
1209 | dev_dbg(&mmc->class_dev, "card is %s\n", |
1210 | read_only ? "read-only" : "read-write"); | |
7d2be074 HS |
1211 | } |
1212 | ||
1213 | return read_only; | |
1214 | } | |
1215 | ||
965ebf33 HS |
1216 | static int atmci_get_cd(struct mmc_host *mmc) |
1217 | { | |
1218 | int present = -ENOSYS; | |
1219 | struct atmel_mci_slot *slot = mmc_priv(mmc); | |
1220 | ||
1221 | if (gpio_is_valid(slot->detect_pin)) { | |
1c1452be JL |
1222 | present = !(gpio_get_value(slot->detect_pin) ^ |
1223 | slot->detect_is_active_high); | |
965ebf33 HS |
1224 | dev_dbg(&mmc->class_dev, "card is %spresent\n", |
1225 | present ? "" : "not "); | |
1226 | } | |
1227 | ||
1228 | return present; | |
1229 | } | |
1230 | ||
88ff82ed AG |
1231 | static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable) |
1232 | { | |
1233 | struct atmel_mci_slot *slot = mmc_priv(mmc); | |
1234 | struct atmel_mci *host = slot->host; | |
1235 | ||
1236 | if (enable) | |
03fc9a7f | 1237 | atmci_writel(host, ATMCI_IER, slot->sdio_irq); |
88ff82ed | 1238 | else |
03fc9a7f | 1239 | atmci_writel(host, ATMCI_IDR, slot->sdio_irq); |
88ff82ed AG |
1240 | } |
1241 | ||
965ebf33 | 1242 | static const struct mmc_host_ops atmci_ops = { |
7d2be074 HS |
1243 | .request = atmci_request, |
1244 | .set_ios = atmci_set_ios, | |
1245 | .get_ro = atmci_get_ro, | |
965ebf33 | 1246 | .get_cd = atmci_get_cd, |
88ff82ed | 1247 | .enable_sdio_irq = atmci_enable_sdio_irq, |
7d2be074 HS |
1248 | }; |
1249 | ||
965ebf33 HS |
1250 | /* Called with host->lock held */ |
1251 | static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq) | |
1252 | __releases(&host->lock) | |
1253 | __acquires(&host->lock) | |
1254 | { | |
1255 | struct atmel_mci_slot *slot = NULL; | |
1256 | struct mmc_host *prev_mmc = host->cur_slot->mmc; | |
1257 | ||
1258 | WARN_ON(host->cmd || host->data); | |
1259 | ||
1260 | /* | |
1261 | * Update the MMC clock rate if necessary. This may be | |
1262 | * necessary if set_ios() is called when a different slot is | |
25985edc | 1263 | * busy transferring data. |
965ebf33 | 1264 | */ |
99ddffd8 | 1265 | if (host->need_clock_update) { |
03fc9a7f | 1266 | atmci_writel(host, ATMCI_MR, host->mode_reg); |
796211b7 | 1267 | if (host->caps.has_cfg_reg) |
03fc9a7f | 1268 | atmci_writel(host, ATMCI_CFG, host->cfg_reg); |
99ddffd8 | 1269 | } |
965ebf33 HS |
1270 | |
1271 | host->cur_slot->mrq = NULL; | |
1272 | host->mrq = NULL; | |
1273 | if (!list_empty(&host->queue)) { | |
1274 | slot = list_entry(host->queue.next, | |
1275 | struct atmel_mci_slot, queue_node); | |
1276 | list_del(&slot->queue_node); | |
1277 | dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n", | |
1278 | mmc_hostname(slot->mmc)); | |
1279 | host->state = STATE_SENDING_CMD; | |
1280 | atmci_start_request(host, slot); | |
1281 | } else { | |
1282 | dev_vdbg(&host->pdev->dev, "list empty\n"); | |
1283 | host->state = STATE_IDLE; | |
1284 | } | |
1285 | ||
1286 | spin_unlock(&host->lock); | |
1287 | mmc_request_done(prev_mmc, mrq); | |
1288 | spin_lock(&host->lock); | |
1289 | } | |
1290 | ||
7d2be074 | 1291 | static void atmci_command_complete(struct atmel_mci *host, |
c06ad258 | 1292 | struct mmc_command *cmd) |
7d2be074 | 1293 | { |
c06ad258 HS |
1294 | u32 status = host->cmd_status; |
1295 | ||
7d2be074 | 1296 | /* Read the response from the card (up to 16 bytes) */ |
03fc9a7f LD |
1297 | cmd->resp[0] = atmci_readl(host, ATMCI_RSPR); |
1298 | cmd->resp[1] = atmci_readl(host, ATMCI_RSPR); | |
1299 | cmd->resp[2] = atmci_readl(host, ATMCI_RSPR); | |
1300 | cmd->resp[3] = atmci_readl(host, ATMCI_RSPR); | |
7d2be074 | 1301 | |
2c96a293 | 1302 | if (status & ATMCI_RTOE) |
7d2be074 | 1303 | cmd->error = -ETIMEDOUT; |
2c96a293 | 1304 | else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE)) |
7d2be074 | 1305 | cmd->error = -EILSEQ; |
2c96a293 | 1306 | else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE)) |
7d2be074 HS |
1307 | cmd->error = -EIO; |
1308 | else | |
1309 | cmd->error = 0; | |
1310 | ||
1311 | if (cmd->error) { | |
965ebf33 | 1312 | dev_dbg(&host->pdev->dev, |
7d2be074 HS |
1313 | "command error: status=0x%08x\n", status); |
1314 | ||
1315 | if (cmd->data) { | |
796211b7 | 1316 | host->stop_transfer(host); |
009a891b | 1317 | host->data = NULL; |
03fc9a7f | 1318 | atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY |
2c96a293 | 1319 | | ATMCI_TXRDY | ATMCI_RXRDY |
7d2be074 HS |
1320 | | ATMCI_DATA_ERROR_FLAGS); |
1321 | } | |
1322 | } | |
1323 | } | |
1324 | ||
1325 | static void atmci_detect_change(unsigned long data) | |
1326 | { | |
965ebf33 HS |
1327 | struct atmel_mci_slot *slot = (struct atmel_mci_slot *)data; |
1328 | bool present; | |
1329 | bool present_old; | |
7d2be074 HS |
1330 | |
1331 | /* | |
965ebf33 HS |
1332 | * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before |
1333 | * freeing the interrupt. We must not re-enable the interrupt | |
1334 | * if it has been freed, and if we're shutting down, it | |
1335 | * doesn't really matter whether the card is present or not. | |
7d2be074 HS |
1336 | */ |
1337 | smp_rmb(); | |
965ebf33 | 1338 | if (test_bit(ATMCI_SHUTDOWN, &slot->flags)) |
7d2be074 HS |
1339 | return; |
1340 | ||
965ebf33 | 1341 | enable_irq(gpio_to_irq(slot->detect_pin)); |
1c1452be JL |
1342 | present = !(gpio_get_value(slot->detect_pin) ^ |
1343 | slot->detect_is_active_high); | |
965ebf33 | 1344 | present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags); |
7d2be074 | 1345 | |
965ebf33 HS |
1346 | dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n", |
1347 | present, present_old); | |
7d2be074 | 1348 | |
965ebf33 HS |
1349 | if (present != present_old) { |
1350 | struct atmel_mci *host = slot->host; | |
1351 | struct mmc_request *mrq; | |
1352 | ||
1353 | dev_dbg(&slot->mmc->class_dev, "card %s\n", | |
7d2be074 | 1354 | present ? "inserted" : "removed"); |
7d2be074 | 1355 | |
965ebf33 HS |
1356 | spin_lock(&host->lock); |
1357 | ||
1358 | if (!present) | |
1359 | clear_bit(ATMCI_CARD_PRESENT, &slot->flags); | |
1360 | else | |
1361 | set_bit(ATMCI_CARD_PRESENT, &slot->flags); | |
7d2be074 HS |
1362 | |
1363 | /* Clean up queue if present */ | |
965ebf33 | 1364 | mrq = slot->mrq; |
7d2be074 | 1365 | if (mrq) { |
965ebf33 HS |
1366 | if (mrq == host->mrq) { |
1367 | /* | |
1368 | * Reset controller to terminate any ongoing | |
1369 | * commands or data transfers. | |
1370 | */ | |
03fc9a7f LD |
1371 | atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); |
1372 | atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN); | |
1373 | atmci_writel(host, ATMCI_MR, host->mode_reg); | |
796211b7 | 1374 | if (host->caps.has_cfg_reg) |
03fc9a7f | 1375 | atmci_writel(host, ATMCI_CFG, host->cfg_reg); |
965ebf33 HS |
1376 | |
1377 | host->data = NULL; | |
1378 | host->cmd = NULL; | |
1379 | ||
1380 | switch (host->state) { | |
1381 | case STATE_IDLE: | |
c06ad258 | 1382 | break; |
965ebf33 HS |
1383 | case STATE_SENDING_CMD: |
1384 | mrq->cmd->error = -ENOMEDIUM; | |
1385 | if (!mrq->data) | |
1386 | break; | |
1387 | /* fall through */ | |
1388 | case STATE_SENDING_DATA: | |
c06ad258 | 1389 | mrq->data->error = -ENOMEDIUM; |
796211b7 | 1390 | host->stop_transfer(host); |
c06ad258 | 1391 | break; |
965ebf33 HS |
1392 | case STATE_DATA_BUSY: |
1393 | case STATE_DATA_ERROR: | |
1394 | if (mrq->data->error == -EINPROGRESS) | |
1395 | mrq->data->error = -ENOMEDIUM; | |
1396 | if (!mrq->stop) | |
1397 | break; | |
1398 | /* fall through */ | |
1399 | case STATE_SENDING_STOP: | |
1400 | mrq->stop->error = -ENOMEDIUM; | |
1401 | break; | |
1402 | } | |
7d2be074 | 1403 | |
965ebf33 HS |
1404 | atmci_request_end(host, mrq); |
1405 | } else { | |
1406 | list_del(&slot->queue_node); | |
1407 | mrq->cmd->error = -ENOMEDIUM; | |
1408 | if (mrq->data) | |
1409 | mrq->data->error = -ENOMEDIUM; | |
1410 | if (mrq->stop) | |
1411 | mrq->stop->error = -ENOMEDIUM; | |
1412 | ||
1413 | spin_unlock(&host->lock); | |
1414 | mmc_request_done(slot->mmc, mrq); | |
1415 | spin_lock(&host->lock); | |
1416 | } | |
7d2be074 | 1417 | } |
965ebf33 | 1418 | spin_unlock(&host->lock); |
7d2be074 | 1419 | |
965ebf33 | 1420 | mmc_detect_change(slot->mmc, 0); |
7d2be074 HS |
1421 | } |
1422 | } | |
1423 | ||
1424 | static void atmci_tasklet_func(unsigned long priv) | |
1425 | { | |
965ebf33 | 1426 | struct atmel_mci *host = (struct atmel_mci *)priv; |
7d2be074 HS |
1427 | struct mmc_request *mrq = host->mrq; |
1428 | struct mmc_data *data = host->data; | |
c06ad258 HS |
1429 | struct mmc_command *cmd = host->cmd; |
1430 | enum atmel_mci_state state = host->state; | |
1431 | enum atmel_mci_state prev_state; | |
1432 | u32 status; | |
1433 | ||
965ebf33 HS |
1434 | spin_lock(&host->lock); |
1435 | ||
c06ad258 | 1436 | state = host->state; |
7d2be074 | 1437 | |
965ebf33 | 1438 | dev_vdbg(&host->pdev->dev, |
c06ad258 HS |
1439 | "tasklet: state %u pending/completed/mask %lx/%lx/%x\n", |
1440 | state, host->pending_events, host->completed_events, | |
03fc9a7f | 1441 | atmci_readl(host, ATMCI_IMR)); |
7d2be074 | 1442 | |
c06ad258 HS |
1443 | do { |
1444 | prev_state = state; | |
7d2be074 | 1445 | |
c06ad258 | 1446 | switch (state) { |
965ebf33 HS |
1447 | case STATE_IDLE: |
1448 | break; | |
1449 | ||
c06ad258 HS |
1450 | case STATE_SENDING_CMD: |
1451 | if (!atmci_test_and_clear_pending(host, | |
1452 | EVENT_CMD_COMPLETE)) | |
1453 | break; | |
7d2be074 | 1454 | |
c06ad258 HS |
1455 | host->cmd = NULL; |
1456 | atmci_set_completed(host, EVENT_CMD_COMPLETE); | |
1457 | atmci_command_complete(host, mrq->cmd); | |
1458 | if (!mrq->data || cmd->error) { | |
965ebf33 HS |
1459 | atmci_request_end(host, host->mrq); |
1460 | goto unlock; | |
c06ad258 | 1461 | } |
7d2be074 | 1462 | |
c06ad258 HS |
1463 | prev_state = state = STATE_SENDING_DATA; |
1464 | /* fall through */ | |
7d2be074 | 1465 | |
c06ad258 HS |
1466 | case STATE_SENDING_DATA: |
1467 | if (atmci_test_and_clear_pending(host, | |
1468 | EVENT_DATA_ERROR)) { | |
796211b7 | 1469 | host->stop_transfer(host); |
c06ad258 | 1470 | if (data->stop) |
2c96a293 | 1471 | atmci_send_stop_cmd(host, data); |
c06ad258 HS |
1472 | state = STATE_DATA_ERROR; |
1473 | break; | |
1474 | } | |
7d2be074 | 1475 | |
c06ad258 HS |
1476 | if (!atmci_test_and_clear_pending(host, |
1477 | EVENT_XFER_COMPLETE)) | |
1478 | break; | |
7d2be074 | 1479 | |
c06ad258 HS |
1480 | atmci_set_completed(host, EVENT_XFER_COMPLETE); |
1481 | prev_state = state = STATE_DATA_BUSY; | |
1482 | /* fall through */ | |
7d2be074 | 1483 | |
c06ad258 HS |
1484 | case STATE_DATA_BUSY: |
1485 | if (!atmci_test_and_clear_pending(host, | |
1486 | EVENT_DATA_COMPLETE)) | |
1487 | break; | |
1488 | ||
1489 | host->data = NULL; | |
1490 | atmci_set_completed(host, EVENT_DATA_COMPLETE); | |
1491 | status = host->data_status; | |
1492 | if (unlikely(status & ATMCI_DATA_ERROR_FLAGS)) { | |
2c96a293 | 1493 | if (status & ATMCI_DTOE) { |
965ebf33 | 1494 | dev_dbg(&host->pdev->dev, |
c06ad258 HS |
1495 | "data timeout error\n"); |
1496 | data->error = -ETIMEDOUT; | |
2c96a293 | 1497 | } else if (status & ATMCI_DCRCE) { |
965ebf33 | 1498 | dev_dbg(&host->pdev->dev, |
c06ad258 HS |
1499 | "data CRC error\n"); |
1500 | data->error = -EILSEQ; | |
1501 | } else { | |
965ebf33 | 1502 | dev_dbg(&host->pdev->dev, |
c06ad258 HS |
1503 | "data FIFO error (status=%08x)\n", |
1504 | status); | |
1505 | data->error = -EIO; | |
1506 | } | |
1507 | } else { | |
1508 | data->bytes_xfered = data->blocks * data->blksz; | |
1509 | data->error = 0; | |
03fc9a7f | 1510 | atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS); |
c06ad258 HS |
1511 | } |
1512 | ||
1513 | if (!data->stop) { | |
965ebf33 HS |
1514 | atmci_request_end(host, host->mrq); |
1515 | goto unlock; | |
c06ad258 | 1516 | } |
7d2be074 | 1517 | |
c06ad258 HS |
1518 | prev_state = state = STATE_SENDING_STOP; |
1519 | if (!data->error) | |
2c96a293 | 1520 | atmci_send_stop_cmd(host, data); |
c06ad258 HS |
1521 | /* fall through */ |
1522 | ||
1523 | case STATE_SENDING_STOP: | |
1524 | if (!atmci_test_and_clear_pending(host, | |
1525 | EVENT_CMD_COMPLETE)) | |
1526 | break; | |
1527 | ||
1528 | host->cmd = NULL; | |
1529 | atmci_command_complete(host, mrq->stop); | |
965ebf33 HS |
1530 | atmci_request_end(host, host->mrq); |
1531 | goto unlock; | |
c06ad258 HS |
1532 | |
1533 | case STATE_DATA_ERROR: | |
1534 | if (!atmci_test_and_clear_pending(host, | |
1535 | EVENT_XFER_COMPLETE)) | |
1536 | break; | |
1537 | ||
1538 | state = STATE_DATA_BUSY; | |
1539 | break; | |
1540 | } | |
1541 | } while (state != prev_state); | |
1542 | ||
1543 | host->state = state; | |
965ebf33 HS |
1544 | |
1545 | unlock: | |
1546 | spin_unlock(&host->lock); | |
7d2be074 HS |
1547 | } |
1548 | ||
1549 | static void atmci_read_data_pio(struct atmel_mci *host) | |
1550 | { | |
1551 | struct scatterlist *sg = host->sg; | |
1552 | void *buf = sg_virt(sg); | |
1553 | unsigned int offset = host->pio_offset; | |
1554 | struct mmc_data *data = host->data; | |
1555 | u32 value; | |
1556 | u32 status; | |
1557 | unsigned int nbytes = 0; | |
1558 | ||
1559 | do { | |
03fc9a7f | 1560 | value = atmci_readl(host, ATMCI_RDR); |
7d2be074 HS |
1561 | if (likely(offset + 4 <= sg->length)) { |
1562 | put_unaligned(value, (u32 *)(buf + offset)); | |
1563 | ||
1564 | offset += 4; | |
1565 | nbytes += 4; | |
1566 | ||
1567 | if (offset == sg->length) { | |
5e7184ae | 1568 | flush_dcache_page(sg_page(sg)); |
7d2be074 HS |
1569 | host->sg = sg = sg_next(sg); |
1570 | if (!sg) | |
1571 | goto done; | |
1572 | ||
1573 | offset = 0; | |
1574 | buf = sg_virt(sg); | |
1575 | } | |
1576 | } else { | |
1577 | unsigned int remaining = sg->length - offset; | |
1578 | memcpy(buf + offset, &value, remaining); | |
1579 | nbytes += remaining; | |
1580 | ||
1581 | flush_dcache_page(sg_page(sg)); | |
1582 | host->sg = sg = sg_next(sg); | |
1583 | if (!sg) | |
1584 | goto done; | |
1585 | ||
1586 | offset = 4 - remaining; | |
1587 | buf = sg_virt(sg); | |
1588 | memcpy(buf, (u8 *)&value + remaining, offset); | |
1589 | nbytes += offset; | |
1590 | } | |
1591 | ||
03fc9a7f | 1592 | status = atmci_readl(host, ATMCI_SR); |
7d2be074 | 1593 | if (status & ATMCI_DATA_ERROR_FLAGS) { |
03fc9a7f | 1594 | atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY |
7d2be074 HS |
1595 | | ATMCI_DATA_ERROR_FLAGS)); |
1596 | host->data_status = status; | |
965ebf33 HS |
1597 | data->bytes_xfered += nbytes; |
1598 | smp_wmb(); | |
7d2be074 HS |
1599 | atmci_set_pending(host, EVENT_DATA_ERROR); |
1600 | tasklet_schedule(&host->tasklet); | |
965ebf33 | 1601 | return; |
7d2be074 | 1602 | } |
2c96a293 | 1603 | } while (status & ATMCI_RXRDY); |
7d2be074 HS |
1604 | |
1605 | host->pio_offset = offset; | |
1606 | data->bytes_xfered += nbytes; | |
1607 | ||
1608 | return; | |
1609 | ||
1610 | done: | |
03fc9a7f LD |
1611 | atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY); |
1612 | atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); | |
7d2be074 | 1613 | data->bytes_xfered += nbytes; |
965ebf33 | 1614 | smp_wmb(); |
c06ad258 | 1615 | atmci_set_pending(host, EVENT_XFER_COMPLETE); |
7d2be074 HS |
1616 | } |
1617 | ||
1618 | static void atmci_write_data_pio(struct atmel_mci *host) | |
1619 | { | |
1620 | struct scatterlist *sg = host->sg; | |
1621 | void *buf = sg_virt(sg); | |
1622 | unsigned int offset = host->pio_offset; | |
1623 | struct mmc_data *data = host->data; | |
1624 | u32 value; | |
1625 | u32 status; | |
1626 | unsigned int nbytes = 0; | |
1627 | ||
1628 | do { | |
1629 | if (likely(offset + 4 <= sg->length)) { | |
1630 | value = get_unaligned((u32 *)(buf + offset)); | |
03fc9a7f | 1631 | atmci_writel(host, ATMCI_TDR, value); |
7d2be074 HS |
1632 | |
1633 | offset += 4; | |
1634 | nbytes += 4; | |
1635 | if (offset == sg->length) { | |
1636 | host->sg = sg = sg_next(sg); | |
1637 | if (!sg) | |
1638 | goto done; | |
1639 | ||
1640 | offset = 0; | |
1641 | buf = sg_virt(sg); | |
1642 | } | |
1643 | } else { | |
1644 | unsigned int remaining = sg->length - offset; | |
1645 | ||
1646 | value = 0; | |
1647 | memcpy(&value, buf + offset, remaining); | |
1648 | nbytes += remaining; | |
1649 | ||
1650 | host->sg = sg = sg_next(sg); | |
1651 | if (!sg) { | |
03fc9a7f | 1652 | atmci_writel(host, ATMCI_TDR, value); |
7d2be074 HS |
1653 | goto done; |
1654 | } | |
1655 | ||
1656 | offset = 4 - remaining; | |
1657 | buf = sg_virt(sg); | |
1658 | memcpy((u8 *)&value + remaining, buf, offset); | |
03fc9a7f | 1659 | atmci_writel(host, ATMCI_TDR, value); |
7d2be074 HS |
1660 | nbytes += offset; |
1661 | } | |
1662 | ||
03fc9a7f | 1663 | status = atmci_readl(host, ATMCI_SR); |
7d2be074 | 1664 | if (status & ATMCI_DATA_ERROR_FLAGS) { |
03fc9a7f | 1665 | atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY |
7d2be074 HS |
1666 | | ATMCI_DATA_ERROR_FLAGS)); |
1667 | host->data_status = status; | |
965ebf33 HS |
1668 | data->bytes_xfered += nbytes; |
1669 | smp_wmb(); | |
7d2be074 HS |
1670 | atmci_set_pending(host, EVENT_DATA_ERROR); |
1671 | tasklet_schedule(&host->tasklet); | |
965ebf33 | 1672 | return; |
7d2be074 | 1673 | } |
2c96a293 | 1674 | } while (status & ATMCI_TXRDY); |
7d2be074 HS |
1675 | |
1676 | host->pio_offset = offset; | |
1677 | data->bytes_xfered += nbytes; | |
1678 | ||
1679 | return; | |
1680 | ||
1681 | done: | |
03fc9a7f LD |
1682 | atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY); |
1683 | atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); | |
7d2be074 | 1684 | data->bytes_xfered += nbytes; |
965ebf33 | 1685 | smp_wmb(); |
c06ad258 | 1686 | atmci_set_pending(host, EVENT_XFER_COMPLETE); |
7d2be074 HS |
1687 | } |
1688 | ||
965ebf33 | 1689 | static void atmci_cmd_interrupt(struct atmel_mci *host, u32 status) |
7d2be074 | 1690 | { |
03fc9a7f | 1691 | atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY); |
7d2be074 | 1692 | |
c06ad258 | 1693 | host->cmd_status = status; |
965ebf33 | 1694 | smp_wmb(); |
c06ad258 | 1695 | atmci_set_pending(host, EVENT_CMD_COMPLETE); |
7d2be074 HS |
1696 | tasklet_schedule(&host->tasklet); |
1697 | } | |
1698 | ||
88ff82ed AG |
1699 | static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status) |
1700 | { | |
1701 | int i; | |
1702 | ||
2c96a293 | 1703 | for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { |
88ff82ed AG |
1704 | struct atmel_mci_slot *slot = host->slot[i]; |
1705 | if (slot && (status & slot->sdio_irq)) { | |
1706 | mmc_signal_sdio_irq(slot->mmc); | |
1707 | } | |
1708 | } | |
1709 | } | |
1710 | ||
1711 | ||
7d2be074 HS |
1712 | static irqreturn_t atmci_interrupt(int irq, void *dev_id) |
1713 | { | |
965ebf33 | 1714 | struct atmel_mci *host = dev_id; |
7d2be074 HS |
1715 | u32 status, mask, pending; |
1716 | unsigned int pass_count = 0; | |
1717 | ||
7d2be074 | 1718 | do { |
03fc9a7f LD |
1719 | status = atmci_readl(host, ATMCI_SR); |
1720 | mask = atmci_readl(host, ATMCI_IMR); | |
7d2be074 HS |
1721 | pending = status & mask; |
1722 | if (!pending) | |
1723 | break; | |
1724 | ||
1725 | if (pending & ATMCI_DATA_ERROR_FLAGS) { | |
03fc9a7f | 1726 | atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS |
2c96a293 | 1727 | | ATMCI_RXRDY | ATMCI_TXRDY); |
03fc9a7f | 1728 | pending &= atmci_readl(host, ATMCI_IMR); |
965ebf33 | 1729 | |
7d2be074 | 1730 | host->data_status = status; |
965ebf33 | 1731 | smp_wmb(); |
7d2be074 HS |
1732 | atmci_set_pending(host, EVENT_DATA_ERROR); |
1733 | tasklet_schedule(&host->tasklet); | |
1734 | } | |
796211b7 | 1735 | |
796211b7 LD |
1736 | if (pending & ATMCI_TXBUFE) { |
1737 | atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE); | |
7e8ba228 | 1738 | atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX); |
796211b7 LD |
1739 | /* |
1740 | * We can receive this interruption before having configured | |
1741 | * the second pdc buffer, so we need to reconfigure first and | |
1742 | * second buffers again | |
1743 | */ | |
1744 | if (host->data_size) { | |
1745 | atmci_pdc_set_both_buf(host, XFER_TRANSMIT); | |
7e8ba228 | 1746 | atmci_writel(host, ATMCI_IER, ATMCI_ENDTX); |
796211b7 LD |
1747 | atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE); |
1748 | } else { | |
1749 | atmci_pdc_complete(host); | |
1750 | } | |
7e8ba228 LD |
1751 | } else if (pending & ATMCI_ENDTX) { |
1752 | atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX); | |
796211b7 LD |
1753 | |
1754 | if (host->data_size) { | |
1755 | atmci_pdc_set_single_buf(host, | |
7e8ba228 LD |
1756 | XFER_TRANSMIT, PDC_SECOND_BUF); |
1757 | atmci_writel(host, ATMCI_IER, ATMCI_ENDTX); | |
796211b7 LD |
1758 | } |
1759 | } | |
1760 | ||
1761 | if (pending & ATMCI_RXBUFF) { | |
1762 | atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF); | |
7e8ba228 | 1763 | atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX); |
796211b7 LD |
1764 | /* |
1765 | * We can receive this interruption before having configured | |
1766 | * the second pdc buffer, so we need to reconfigure first and | |
1767 | * second buffers again | |
1768 | */ | |
1769 | if (host->data_size) { | |
1770 | atmci_pdc_set_both_buf(host, XFER_RECEIVE); | |
7e8ba228 | 1771 | atmci_writel(host, ATMCI_IER, ATMCI_ENDRX); |
796211b7 LD |
1772 | atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF); |
1773 | } else { | |
1774 | atmci_pdc_complete(host); | |
1775 | } | |
7e8ba228 LD |
1776 | } else if (pending & ATMCI_ENDRX) { |
1777 | atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX); | |
1778 | ||
1779 | if (host->data_size) { | |
1780 | atmci_pdc_set_single_buf(host, | |
1781 | XFER_RECEIVE, PDC_SECOND_BUF); | |
1782 | atmci_writel(host, ATMCI_IER, ATMCI_ENDRX); | |
1783 | } | |
796211b7 LD |
1784 | } |
1785 | ||
7e8ba228 | 1786 | |
2c96a293 | 1787 | if (pending & ATMCI_NOTBUSY) { |
03fc9a7f | 1788 | atmci_writel(host, ATMCI_IDR, |
2c96a293 | 1789 | ATMCI_DATA_ERROR_FLAGS | ATMCI_NOTBUSY); |
ca55f46e HS |
1790 | if (!host->data_status) |
1791 | host->data_status = status; | |
965ebf33 | 1792 | smp_wmb(); |
7d2be074 HS |
1793 | atmci_set_pending(host, EVENT_DATA_COMPLETE); |
1794 | tasklet_schedule(&host->tasklet); | |
1795 | } | |
2c96a293 | 1796 | if (pending & ATMCI_RXRDY) |
7d2be074 | 1797 | atmci_read_data_pio(host); |
2c96a293 | 1798 | if (pending & ATMCI_TXRDY) |
7d2be074 HS |
1799 | atmci_write_data_pio(host); |
1800 | ||
2c96a293 | 1801 | if (pending & ATMCI_CMDRDY) |
965ebf33 | 1802 | atmci_cmd_interrupt(host, status); |
88ff82ed | 1803 | |
2c96a293 | 1804 | if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB)) |
88ff82ed AG |
1805 | atmci_sdio_interrupt(host, status); |
1806 | ||
7d2be074 HS |
1807 | } while (pass_count++ < 5); |
1808 | ||
7d2be074 HS |
1809 | return pass_count ? IRQ_HANDLED : IRQ_NONE; |
1810 | } | |
1811 | ||
1812 | static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id) | |
1813 | { | |
965ebf33 | 1814 | struct atmel_mci_slot *slot = dev_id; |
7d2be074 HS |
1815 | |
1816 | /* | |
1817 | * Disable interrupts until the pin has stabilized and check | |
1818 | * the state then. Use mod_timer() since we may be in the | |
1819 | * middle of the timer routine when this interrupt triggers. | |
1820 | */ | |
1821 | disable_irq_nosync(irq); | |
965ebf33 | 1822 | mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20)); |
7d2be074 HS |
1823 | |
1824 | return IRQ_HANDLED; | |
1825 | } | |
1826 | ||
965ebf33 HS |
1827 | static int __init atmci_init_slot(struct atmel_mci *host, |
1828 | struct mci_slot_pdata *slot_data, unsigned int id, | |
88ff82ed | 1829 | u32 sdc_reg, u32 sdio_irq) |
965ebf33 HS |
1830 | { |
1831 | struct mmc_host *mmc; | |
1832 | struct atmel_mci_slot *slot; | |
1833 | ||
1834 | mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev); | |
1835 | if (!mmc) | |
1836 | return -ENOMEM; | |
1837 | ||
1838 | slot = mmc_priv(mmc); | |
1839 | slot->mmc = mmc; | |
1840 | slot->host = host; | |
1841 | slot->detect_pin = slot_data->detect_pin; | |
1842 | slot->wp_pin = slot_data->wp_pin; | |
1c1452be | 1843 | slot->detect_is_active_high = slot_data->detect_is_active_high; |
965ebf33 | 1844 | slot->sdc_reg = sdc_reg; |
88ff82ed | 1845 | slot->sdio_irq = sdio_irq; |
965ebf33 HS |
1846 | |
1847 | mmc->ops = &atmci_ops; | |
1848 | mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512); | |
1849 | mmc->f_max = host->bus_hz / 2; | |
1850 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; | |
88ff82ed AG |
1851 | if (sdio_irq) |
1852 | mmc->caps |= MMC_CAP_SDIO_IRQ; | |
796211b7 | 1853 | if (host->caps.has_highspeed) |
99ddffd8 | 1854 | mmc->caps |= MMC_CAP_SD_HIGHSPEED; |
965ebf33 HS |
1855 | if (slot_data->bus_width >= 4) |
1856 | mmc->caps |= MMC_CAP_4_BIT_DATA; | |
1857 | ||
a36274e0 | 1858 | mmc->max_segs = 64; |
965ebf33 HS |
1859 | mmc->max_req_size = 32768 * 512; |
1860 | mmc->max_blk_size = 32768; | |
1861 | mmc->max_blk_count = 512; | |
1862 | ||
1863 | /* Assume card is present initially */ | |
1864 | set_bit(ATMCI_CARD_PRESENT, &slot->flags); | |
1865 | if (gpio_is_valid(slot->detect_pin)) { | |
1866 | if (gpio_request(slot->detect_pin, "mmc_detect")) { | |
1867 | dev_dbg(&mmc->class_dev, "no detect pin available\n"); | |
1868 | slot->detect_pin = -EBUSY; | |
1c1452be JL |
1869 | } else if (gpio_get_value(slot->detect_pin) ^ |
1870 | slot->detect_is_active_high) { | |
965ebf33 HS |
1871 | clear_bit(ATMCI_CARD_PRESENT, &slot->flags); |
1872 | } | |
1873 | } | |
1874 | ||
1875 | if (!gpio_is_valid(slot->detect_pin)) | |
1876 | mmc->caps |= MMC_CAP_NEEDS_POLL; | |
1877 | ||
1878 | if (gpio_is_valid(slot->wp_pin)) { | |
1879 | if (gpio_request(slot->wp_pin, "mmc_wp")) { | |
1880 | dev_dbg(&mmc->class_dev, "no WP pin available\n"); | |
1881 | slot->wp_pin = -EBUSY; | |
1882 | } | |
1883 | } | |
1884 | ||
1885 | host->slot[id] = slot; | |
1886 | mmc_add_host(mmc); | |
1887 | ||
1888 | if (gpio_is_valid(slot->detect_pin)) { | |
1889 | int ret; | |
1890 | ||
1891 | setup_timer(&slot->detect_timer, atmci_detect_change, | |
1892 | (unsigned long)slot); | |
1893 | ||
1894 | ret = request_irq(gpio_to_irq(slot->detect_pin), | |
1895 | atmci_detect_interrupt, | |
1896 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, | |
1897 | "mmc-detect", slot); | |
1898 | if (ret) { | |
1899 | dev_dbg(&mmc->class_dev, | |
1900 | "could not request IRQ %d for detect pin\n", | |
1901 | gpio_to_irq(slot->detect_pin)); | |
1902 | gpio_free(slot->detect_pin); | |
1903 | slot->detect_pin = -EBUSY; | |
1904 | } | |
1905 | } | |
1906 | ||
1907 | atmci_init_debugfs(slot); | |
1908 | ||
1909 | return 0; | |
1910 | } | |
1911 | ||
1912 | static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot, | |
1913 | unsigned int id) | |
1914 | { | |
1915 | /* Debugfs stuff is cleaned up by mmc core */ | |
1916 | ||
1917 | set_bit(ATMCI_SHUTDOWN, &slot->flags); | |
1918 | smp_wmb(); | |
1919 | ||
1920 | mmc_remove_host(slot->mmc); | |
1921 | ||
1922 | if (gpio_is_valid(slot->detect_pin)) { | |
1923 | int pin = slot->detect_pin; | |
1924 | ||
1925 | free_irq(gpio_to_irq(pin), slot); | |
1926 | del_timer_sync(&slot->detect_timer); | |
1927 | gpio_free(pin); | |
1928 | } | |
1929 | if (gpio_is_valid(slot->wp_pin)) | |
1930 | gpio_free(slot->wp_pin); | |
1931 | ||
1932 | slot->host->slot[id] = NULL; | |
1933 | mmc_free_host(slot->mmc); | |
1934 | } | |
1935 | ||
2c96a293 | 1936 | static bool atmci_filter(struct dma_chan *chan, void *slave) |
74465b4f | 1937 | { |
2635d1ba | 1938 | struct mci_dma_data *sl = slave; |
74465b4f | 1939 | |
2635d1ba NF |
1940 | if (sl && find_slave_dev(sl) == chan->device->dev) { |
1941 | chan->private = slave_data_ptr(sl); | |
7dd60251 | 1942 | return true; |
2635d1ba | 1943 | } else { |
7dd60251 | 1944 | return false; |
2635d1ba | 1945 | } |
74465b4f | 1946 | } |
2635d1ba NF |
1947 | |
1948 | static void atmci_configure_dma(struct atmel_mci *host) | |
1949 | { | |
1950 | struct mci_platform_data *pdata; | |
1951 | ||
1952 | if (host == NULL) | |
1953 | return; | |
1954 | ||
1955 | pdata = host->pdev->dev.platform_data; | |
1956 | ||
1957 | if (pdata && find_slave_dev(pdata->dma_slave)) { | |
1958 | dma_cap_mask_t mask; | |
1959 | ||
1960 | setup_dma_addr(pdata->dma_slave, | |
2c96a293 LD |
1961 | host->mapbase + ATMCI_TDR, |
1962 | host->mapbase + ATMCI_RDR); | |
2635d1ba NF |
1963 | |
1964 | /* Try to grab a DMA channel */ | |
1965 | dma_cap_zero(mask); | |
1966 | dma_cap_set(DMA_SLAVE, mask); | |
1967 | host->dma.chan = | |
2c96a293 | 1968 | dma_request_channel(mask, atmci_filter, pdata->dma_slave); |
2635d1ba NF |
1969 | } |
1970 | if (!host->dma.chan) | |
1971 | dev_notice(&host->pdev->dev, "DMA not available, using PIO\n"); | |
74791a2d NF |
1972 | else |
1973 | dev_info(&host->pdev->dev, | |
1974 | "Using %s for DMA transfers\n", | |
1975 | dma_chan_name(host->dma.chan)); | |
2635d1ba | 1976 | } |
796211b7 LD |
1977 | |
1978 | static inline unsigned int atmci_get_version(struct atmel_mci *host) | |
1979 | { | |
1980 | return atmci_readl(host, ATMCI_VERSION) & 0x00000fff; | |
1981 | } | |
1982 | ||
1983 | /* | |
1984 | * HSMCI (High Speed MCI) module is not fully compatible with MCI module. | |
1985 | * HSMCI provides DMA support and a new config register but no more supports | |
1986 | * PDC. | |
1987 | */ | |
1988 | static void __init atmci_get_cap(struct atmel_mci *host) | |
1989 | { | |
1990 | unsigned int version; | |
1991 | ||
1992 | version = atmci_get_version(host); | |
1993 | dev_info(&host->pdev->dev, | |
1994 | "version: 0x%x\n", version); | |
1995 | ||
1996 | host->caps.has_dma = 0; | |
1997 | host->caps.has_pdc = 0; | |
1998 | host->caps.has_cfg_reg = 0; | |
1999 | host->caps.has_cstor_reg = 0; | |
2000 | host->caps.has_highspeed = 0; | |
2001 | host->caps.has_rwproof = 0; | |
2002 | ||
2003 | /* keep only major version number */ | |
2004 | switch (version & 0xf00) { | |
2005 | case 0x100: | |
2006 | case 0x200: | |
2007 | host->caps.has_pdc = 1; | |
2008 | host->caps.has_rwproof = 1; | |
2009 | break; | |
2010 | case 0x300: | |
2011 | case 0x400: | |
2012 | case 0x500: | |
2013 | #ifdef CONFIG_AT_HDMAC | |
2014 | host->caps.has_dma = 1; | |
2635d1ba | 2015 | #else |
796211b7 LD |
2016 | host->caps.has_dma = 0; |
2017 | dev_info(&host->pdev->dev, | |
2018 | "has dma capability but dma engine is not selected, then use pio\n"); | |
74465b4f | 2019 | #endif |
796211b7 LD |
2020 | host->caps.has_cfg_reg = 1; |
2021 | host->caps.has_cstor_reg = 1; | |
2022 | host->caps.has_highspeed = 1; | |
2023 | host->caps.has_rwproof = 1; | |
2024 | break; | |
2025 | default: | |
2026 | dev_warn(&host->pdev->dev, | |
2027 | "Unmanaged mci version, set minimum capabilities\n"); | |
2028 | break; | |
2029 | } | |
2030 | } | |
74465b4f | 2031 | |
7d2be074 HS |
2032 | static int __init atmci_probe(struct platform_device *pdev) |
2033 | { | |
2034 | struct mci_platform_data *pdata; | |
965ebf33 HS |
2035 | struct atmel_mci *host; |
2036 | struct resource *regs; | |
2037 | unsigned int nr_slots; | |
2038 | int irq; | |
2039 | int ret; | |
7d2be074 HS |
2040 | |
2041 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2042 | if (!regs) | |
2043 | return -ENXIO; | |
2044 | pdata = pdev->dev.platform_data; | |
2045 | if (!pdata) | |
2046 | return -ENXIO; | |
2047 | irq = platform_get_irq(pdev, 0); | |
2048 | if (irq < 0) | |
2049 | return irq; | |
2050 | ||
965ebf33 HS |
2051 | host = kzalloc(sizeof(struct atmel_mci), GFP_KERNEL); |
2052 | if (!host) | |
7d2be074 HS |
2053 | return -ENOMEM; |
2054 | ||
7d2be074 | 2055 | host->pdev = pdev; |
965ebf33 HS |
2056 | spin_lock_init(&host->lock); |
2057 | INIT_LIST_HEAD(&host->queue); | |
7d2be074 HS |
2058 | |
2059 | host->mck = clk_get(&pdev->dev, "mci_clk"); | |
2060 | if (IS_ERR(host->mck)) { | |
2061 | ret = PTR_ERR(host->mck); | |
2062 | goto err_clk_get; | |
2063 | } | |
2064 | ||
2065 | ret = -ENOMEM; | |
e8e3f6ca | 2066 | host->regs = ioremap(regs->start, resource_size(regs)); |
7d2be074 HS |
2067 | if (!host->regs) |
2068 | goto err_ioremap; | |
2069 | ||
2070 | clk_enable(host->mck); | |
03fc9a7f | 2071 | atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST); |
7d2be074 HS |
2072 | host->bus_hz = clk_get_rate(host->mck); |
2073 | clk_disable(host->mck); | |
2074 | ||
2075 | host->mapbase = regs->start; | |
2076 | ||
965ebf33 | 2077 | tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host); |
7d2be074 | 2078 | |
89c8aa20 | 2079 | ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host); |
7d2be074 HS |
2080 | if (ret) |
2081 | goto err_request_irq; | |
2082 | ||
796211b7 LD |
2083 | /* Get MCI capabilities and set operations according to it */ |
2084 | atmci_get_cap(host); | |
2085 | if (host->caps.has_dma) { | |
2086 | dev_info(&pdev->dev, "using DMA\n"); | |
2087 | host->prepare_data = &atmci_prepare_data_dma; | |
2088 | host->submit_data = &atmci_submit_data_dma; | |
2089 | host->stop_transfer = &atmci_stop_transfer_dma; | |
2090 | } else if (host->caps.has_pdc) { | |
2091 | dev_info(&pdev->dev, "using PDC\n"); | |
2092 | host->prepare_data = &atmci_prepare_data_pdc; | |
2093 | host->submit_data = &atmci_submit_data_pdc; | |
2094 | host->stop_transfer = &atmci_stop_transfer_pdc; | |
2095 | } else { | |
2096 | dev_info(&pdev->dev, "no DMA, no PDC\n"); | |
2097 | host->prepare_data = &atmci_prepare_data; | |
2098 | host->submit_data = &atmci_submit_data; | |
2099 | host->stop_transfer = &atmci_stop_transfer; | |
2100 | } | |
2101 | ||
2102 | if (host->caps.has_dma) | |
2103 | atmci_configure_dma(host); | |
65e8b083 | 2104 | |
7d2be074 HS |
2105 | platform_set_drvdata(pdev, host); |
2106 | ||
965ebf33 HS |
2107 | /* We need at least one slot to succeed */ |
2108 | nr_slots = 0; | |
2109 | ret = -ENODEV; | |
2110 | if (pdata->slot[0].bus_width) { | |
2111 | ret = atmci_init_slot(host, &pdata->slot[0], | |
2c96a293 | 2112 | 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA); |
965ebf33 HS |
2113 | if (!ret) |
2114 | nr_slots++; | |
2115 | } | |
2116 | if (pdata->slot[1].bus_width) { | |
2117 | ret = atmci_init_slot(host, &pdata->slot[1], | |
2c96a293 | 2118 | 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB); |
965ebf33 HS |
2119 | if (!ret) |
2120 | nr_slots++; | |
7d2be074 HS |
2121 | } |
2122 | ||
04d699c3 RE |
2123 | if (!nr_slots) { |
2124 | dev_err(&pdev->dev, "init failed: no slot defined\n"); | |
965ebf33 | 2125 | goto err_init_slot; |
04d699c3 | 2126 | } |
7d2be074 | 2127 | |
965ebf33 HS |
2128 | dev_info(&pdev->dev, |
2129 | "Atmel MCI controller at 0x%08lx irq %d, %u slots\n", | |
2130 | host->mapbase, irq, nr_slots); | |
deec9ae3 | 2131 | |
7d2be074 HS |
2132 | return 0; |
2133 | ||
965ebf33 | 2134 | err_init_slot: |
74465b4f DW |
2135 | if (host->dma.chan) |
2136 | dma_release_channel(host->dma.chan); | |
965ebf33 | 2137 | free_irq(irq, host); |
7d2be074 HS |
2138 | err_request_irq: |
2139 | iounmap(host->regs); | |
2140 | err_ioremap: | |
2141 | clk_put(host->mck); | |
2142 | err_clk_get: | |
965ebf33 | 2143 | kfree(host); |
7d2be074 HS |
2144 | return ret; |
2145 | } | |
2146 | ||
2147 | static int __exit atmci_remove(struct platform_device *pdev) | |
2148 | { | |
965ebf33 HS |
2149 | struct atmel_mci *host = platform_get_drvdata(pdev); |
2150 | unsigned int i; | |
7d2be074 HS |
2151 | |
2152 | platform_set_drvdata(pdev, NULL); | |
2153 | ||
2c96a293 | 2154 | for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { |
965ebf33 HS |
2155 | if (host->slot[i]) |
2156 | atmci_cleanup_slot(host->slot[i], i); | |
2157 | } | |
7d2be074 | 2158 | |
965ebf33 | 2159 | clk_enable(host->mck); |
03fc9a7f LD |
2160 | atmci_writel(host, ATMCI_IDR, ~0UL); |
2161 | atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS); | |
2162 | atmci_readl(host, ATMCI_SR); | |
965ebf33 | 2163 | clk_disable(host->mck); |
7d2be074 | 2164 | |
65e8b083 | 2165 | #ifdef CONFIG_MMC_ATMELMCI_DMA |
74465b4f DW |
2166 | if (host->dma.chan) |
2167 | dma_release_channel(host->dma.chan); | |
65e8b083 HS |
2168 | #endif |
2169 | ||
965ebf33 HS |
2170 | free_irq(platform_get_irq(pdev, 0), host); |
2171 | iounmap(host->regs); | |
7d2be074 | 2172 | |
965ebf33 HS |
2173 | clk_put(host->mck); |
2174 | kfree(host); | |
7d2be074 | 2175 | |
7d2be074 HS |
2176 | return 0; |
2177 | } | |
2178 | ||
5c2f2b9b NF |
2179 | #ifdef CONFIG_PM |
2180 | static int atmci_suspend(struct device *dev) | |
2181 | { | |
2182 | struct atmel_mci *host = dev_get_drvdata(dev); | |
2183 | int i; | |
2184 | ||
2c96a293 | 2185 | for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { |
5c2f2b9b NF |
2186 | struct atmel_mci_slot *slot = host->slot[i]; |
2187 | int ret; | |
2188 | ||
2189 | if (!slot) | |
2190 | continue; | |
2191 | ret = mmc_suspend_host(slot->mmc); | |
2192 | if (ret < 0) { | |
2193 | while (--i >= 0) { | |
2194 | slot = host->slot[i]; | |
2195 | if (slot | |
2196 | && test_bit(ATMCI_SUSPENDED, &slot->flags)) { | |
2197 | mmc_resume_host(host->slot[i]->mmc); | |
2198 | clear_bit(ATMCI_SUSPENDED, &slot->flags); | |
2199 | } | |
2200 | } | |
2201 | return ret; | |
2202 | } else { | |
2203 | set_bit(ATMCI_SUSPENDED, &slot->flags); | |
2204 | } | |
2205 | } | |
2206 | ||
2207 | return 0; | |
2208 | } | |
2209 | ||
2210 | static int atmci_resume(struct device *dev) | |
2211 | { | |
2212 | struct atmel_mci *host = dev_get_drvdata(dev); | |
2213 | int i; | |
2214 | int ret = 0; | |
2215 | ||
2c96a293 | 2216 | for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) { |
5c2f2b9b NF |
2217 | struct atmel_mci_slot *slot = host->slot[i]; |
2218 | int err; | |
2219 | ||
2220 | slot = host->slot[i]; | |
2221 | if (!slot) | |
2222 | continue; | |
2223 | if (!test_bit(ATMCI_SUSPENDED, &slot->flags)) | |
2224 | continue; | |
2225 | err = mmc_resume_host(slot->mmc); | |
2226 | if (err < 0) | |
2227 | ret = err; | |
2228 | else | |
2229 | clear_bit(ATMCI_SUSPENDED, &slot->flags); | |
2230 | } | |
2231 | ||
2232 | return ret; | |
2233 | } | |
2234 | static SIMPLE_DEV_PM_OPS(atmci_pm, atmci_suspend, atmci_resume); | |
2235 | #define ATMCI_PM_OPS (&atmci_pm) | |
2236 | #else | |
2237 | #define ATMCI_PM_OPS NULL | |
2238 | #endif | |
2239 | ||
7d2be074 HS |
2240 | static struct platform_driver atmci_driver = { |
2241 | .remove = __exit_p(atmci_remove), | |
2242 | .driver = { | |
2243 | .name = "atmel_mci", | |
5c2f2b9b | 2244 | .pm = ATMCI_PM_OPS, |
7d2be074 HS |
2245 | }, |
2246 | }; | |
2247 | ||
2248 | static int __init atmci_init(void) | |
2249 | { | |
2250 | return platform_driver_probe(&atmci_driver, atmci_probe); | |
2251 | } | |
2252 | ||
2253 | static void __exit atmci_exit(void) | |
2254 | { | |
2255 | platform_driver_unregister(&atmci_driver); | |
2256 | } | |
2257 | ||
74465b4f | 2258 | late_initcall(atmci_init); /* try to load after dma driver when built-in */ |
7d2be074 HS |
2259 | module_exit(atmci_exit); |
2260 | ||
2261 | MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver"); | |
e05503ef | 2262 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
7d2be074 | 2263 | MODULE_LICENSE("GPL v2"); |