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mmc: sdhci-s3c: Enable runtime power management
[deliverable/linux.git] / drivers / mmc / host / atmel-mci.c
CommitLineData
7d2be074
HS		 1/*
2 * Atmel MultiMedia Card Interface driver
3 *
4 * Copyright (C) 2004-2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/blkdev.h>
11#include <linux/clk.h>
deec9ae3 12#include <linux/debugfs.h>
7d2be074 13#include <linux/device.h>
65e8b083
HS		 14#include <linux/dmaengine.h>
15#include <linux/dma-mapping.h>
fbfca4b8 16#include <linux/err.h>
3c26e170 17#include <linux/gpio.h>
7d2be074
HS		 18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/ioport.h>
21#include <linux/module.h>
22#include <linux/platform_device.h>
23#include <linux/scatterlist.h>
deec9ae3 24#include <linux/seq_file.h>
5a0e3ad6 25#include <linux/slab.h>
deec9ae3 26#include <linux/stat.h>
e2b35f3d 27#include <linux/types.h>
7d2be074
HS		 28
29#include <linux/mmc/host.h>
2f1d7918 30#include <linux/mmc/sdio.h>
2635d1ba
NF		 31
32#include <mach/atmel-mci.h>
c42aa775 33#include <linux/atmel-mci.h>
796211b7 34#include <linux/atmel_pdc.h>
7d2be074 35
7d2be074
HS		 36#include <asm/io.h>
37#include <asm/unaligned.h>
38
04d699c3 39#include <mach/cpu.h>
3663b736 40#include <mach/board.h>
7d2be074
HS		 41
42#include "atmel-mci-regs.h"
43
2c96a293 44#define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
65e8b083 45#define ATMCI_DMA_THRESHOLD 16
7d2be074
HS		 46
47enum {
48 EVENT_CMD_COMPLETE = 0,
7d2be074 49 EVENT_XFER_COMPLETE,
c06ad258
HS		 50 EVENT_DATA_COMPLETE,
51 EVENT_DATA_ERROR,
52};
53
54enum atmel_mci_state {
965ebf33
HS		 55 STATE_IDLE = 0,
56 STATE_SENDING_CMD,
c06ad258
HS		 57 STATE_SENDING_DATA,
58 STATE_DATA_BUSY,
59 STATE_SENDING_STOP,
60 STATE_DATA_ERROR,
7d2be074
HS		 61};
62
796211b7
LD		 63enum atmci_xfer_dir {
64 XFER_RECEIVE = 0,
65 XFER_TRANSMIT,
66};
67
68enum atmci_pdc_buf {
69 PDC_FIRST_BUF = 0,
70 PDC_SECOND_BUF,
71};
72
73struct atmel_mci_caps {
74 bool has_dma;
75 bool has_pdc;
76 bool has_cfg_reg;
77 bool has_cstor_reg;
78 bool has_highspeed;
79 bool has_rwproof;
80};
81
65e8b083 82struct atmel_mci_dma {
65e8b083
HS		 83 struct dma_chan *chan;
84 struct dma_async_tx_descriptor *data_desc;
65e8b083
HS		 85};
86
965ebf33
HS		 87/**
88 * struct atmel_mci - MMC controller state shared between all slots
89 * @lock: Spinlock protecting the queue and associated data.
90 * @regs: Pointer to MMIO registers.
796211b7 91 * @sg: Scatterlist entry currently being processed by PIO or PDC code.
965ebf33
HS		 92 * @pio_offset: Offset into the current scatterlist entry.
93 * @cur_slot: The slot which is currently using the controller.
94 * @mrq: The request currently being processed on @cur_slot,
95 * or NULL if the controller is idle.
96 * @cmd: The command currently being sent to the card, or NULL.
97 * @data: The data currently being transferred, or NULL if no data
98 * transfer is in progress.
796211b7 99 * @data_size: just data->blocks * data->blksz.
65e8b083
HS		 100 * @dma: DMA client state.
101 * @data_chan: DMA channel being used for the current data transfer.
965ebf33
HS		 102 * @cmd_status: Snapshot of SR taken upon completion of the current
103 * command. Only valid when EVENT_CMD_COMPLETE is pending.
104 * @data_status: Snapshot of SR taken upon completion of the current
105 * data transfer. Only valid when EVENT_DATA_COMPLETE or
106 * EVENT_DATA_ERROR is pending.
107 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
108 * to be sent.
109 * @tasklet: Tasklet running the request state machine.
110 * @pending_events: Bitmask of events flagged by the interrupt handler
111 * to be processed by the tasklet.
112 * @completed_events: Bitmask of events which the state machine has
113 * processed.
114 * @state: Tasklet state.
115 * @queue: List of slots waiting for access to the controller.
116 * @need_clock_update: Update the clock rate before the next request.
117 * @need_reset: Reset controller before next request.
118 * @mode_reg: Value of the MR register.
74791a2d 119 * @cfg_reg: Value of the CFG register.
965ebf33
HS		 120 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
121 * rate and timeout calculations.
122 * @mapbase: Physical address of the MMIO registers.
123 * @mck: The peripheral bus clock hooked up to the MMC controller.
124 * @pdev: Platform device associated with the MMC controller.
125 * @slot: Slots sharing this MMC controller.
796211b7
LD		 126 * @caps: MCI capabilities depending on MCI version.
127 * @prepare_data: function to setup MCI before data transfer which
128 * depends on MCI capabilities.
129 * @submit_data: function to start data transfer which depends on MCI
130 * capabilities.
131 * @stop_transfer: function to stop data transfer which depends on MCI
132 * capabilities.
965ebf33
HS		 133 *
134 * Locking
135 * =======
136 *
137 * @lock is a softirq-safe spinlock protecting @queue as well as
138 * @cur_slot, @mrq and @state. These must always be updated
139 * at the same time while holding @lock.
140 *
141 * @lock also protects mode_reg and need_clock_update since these are
142 * used to synchronize mode register updates with the queue
143 * processing.
144 *
145 * The @mrq field of struct atmel_mci_slot is also protected by @lock,
146 * and must always be written at the same time as the slot is added to
147 * @queue.
148 *
149 * @pending_events and @completed_events are accessed using atomic bit
150 * operations, so they don't need any locking.
151 *
152 * None of the fields touched by the interrupt handler need any
153 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
154 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
155 * interrupts must be disabled and @data_status updated with a
156 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
25985edc 157 * CMDRDY interrupt must be disabled and @cmd_status updated with a
965ebf33
HS		 158 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
159 * bytes_xfered field of @data must be written. This is ensured by
160 * using barriers.
161 */
7d2be074 162struct atmel_mci {
965ebf33 163 spinlock_t lock;
7d2be074
HS		 164 void __iomem *regs;
165
166 struct scatterlist *sg;
167 unsigned int pio_offset;
168
965ebf33 169 struct atmel_mci_slot *cur_slot;
7d2be074
HS		 170 struct mmc_request *mrq;
171 struct mmc_command *cmd;
172 struct mmc_data *data;
796211b7 173 unsigned int data_size;
7d2be074 174
65e8b083
HS		 175 struct atmel_mci_dma dma;
176 struct dma_chan *data_chan;
e2b35f3d 177 struct dma_slave_config dma_conf;
65e8b083 178
7d2be074
HS		 179 u32 cmd_status;
180 u32 data_status;
7d2be074
HS		 181 u32 stop_cmdr;
182
7d2be074
HS		 183 struct tasklet_struct tasklet;
184 unsigned long pending_events;
185 unsigned long completed_events;
c06ad258 186 enum atmel_mci_state state;
965ebf33 187 struct list_head queue;
7d2be074 188
965ebf33
HS		 189 bool need_clock_update;
190 bool need_reset;
191 u32 mode_reg;
74791a2d 192 u32 cfg_reg;
7d2be074
HS		 193 unsigned long bus_hz;
194 unsigned long mapbase;
195 struct clk *mck;
196 struct platform_device *pdev;
965ebf33 197
2c96a293 198 struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS];
796211b7
LD		 199
200 struct atmel_mci_caps caps;
201
202 u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
203 void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
204 void (*stop_transfer)(struct atmel_mci *host);
965ebf33
HS		 205};
206
207/**
208 * struct atmel_mci_slot - MMC slot state
209 * @mmc: The mmc_host representing this slot.
210 * @host: The MMC controller this slot is using.
211 * @sdc_reg: Value of SDCR to be written before using this slot.
88ff82ed 212 * @sdio_irq: SDIO irq mask for this slot.
965ebf33
HS		 213 * @mrq: mmc_request currently being processed or waiting to be
214 * processed, or NULL when the slot is idle.
215 * @queue_node: List node for placing this node in the @queue list of
216 * &struct atmel_mci.
217 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
218 * @flags: Random state bits associated with the slot.
219 * @detect_pin: GPIO pin used for card detection, or negative if not
220 * available.
221 * @wp_pin: GPIO pin used for card write protect sending, or negative
222 * if not available.
1c1452be 223 * @detect_is_active_high: The state of the detect pin when it is active.
965ebf33
HS		 224 * @detect_timer: Timer used for debouncing @detect_pin interrupts.
225 */
226struct atmel_mci_slot {
227 struct mmc_host *mmc;
228 struct atmel_mci *host;
229
230 u32 sdc_reg;
88ff82ed 231 u32 sdio_irq;
965ebf33
HS		 232
233 struct mmc_request *mrq;
234 struct list_head queue_node;
235
236 unsigned int clock;
237 unsigned long flags;
238#define ATMCI_CARD_PRESENT 0
239#define ATMCI_CARD_NEED_INIT 1
240#define ATMCI_SHUTDOWN 2
5c2f2b9b 241#define ATMCI_SUSPENDED 3
965ebf33
HS		 242
243 int detect_pin;
244 int wp_pin;
1c1452be 245 bool detect_is_active_high;
965ebf33
HS		 246
247 struct timer_list detect_timer;
7d2be074
HS		 248};
249
7d2be074
HS		 250#define atmci_test_and_clear_pending(host, event) \
251 test_and_clear_bit(event, &host->pending_events)
7d2be074
HS		 252#define atmci_set_completed(host, event) \
253 set_bit(event, &host->completed_events)
254#define atmci_set_pending(host, event) \
255 set_bit(event, &host->pending_events)
7d2be074 256
deec9ae3
HS		 257/*
258 * The debugfs stuff below is mostly optimized away when
259 * CONFIG_DEBUG_FS is not set.
260 */
261static int atmci_req_show(struct seq_file *s, void *v)
262{
965ebf33
HS		 263 struct atmel_mci_slot *slot = s->private;
264 struct mmc_request *mrq;
deec9ae3
HS		 265 struct mmc_command *cmd;
266 struct mmc_command *stop;
267 struct mmc_data *data;
268
269 /* Make sure we get a consistent snapshot */
965ebf33
HS		 270 spin_lock_bh(&slot->host->lock);
271 mrq = slot->mrq;
deec9ae3
HS		 272
273 if (mrq) {
274 cmd = mrq->cmd;
275 data = mrq->data;
276 stop = mrq->stop;
277
278 if (cmd)
279 seq_printf(s,
280 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
281 cmd->opcode, cmd->arg, cmd->flags,
282 cmd->resp[0], cmd->resp[1], cmd->resp[2],
d586ebbb 283 cmd->resp[3], cmd->error);
deec9ae3
HS		 284 if (data)
285 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
286 data->bytes_xfered, data->blocks,
287 data->blksz, data->flags, data->error);
288 if (stop)
289 seq_printf(s,
290 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
291 stop->opcode, stop->arg, stop->flags,
292 stop->resp[0], stop->resp[1], stop->resp[2],
d586ebbb 293 stop->resp[3], stop->error);
deec9ae3
HS		 294 }
295
965ebf33 296 spin_unlock_bh(&slot->host->lock);
deec9ae3
HS		 297
298 return 0;
299}
300
301static int atmci_req_open(struct inode *inode, struct file *file)
302{
303 return single_open(file, atmci_req_show, inode->i_private);
304}
305
306static const struct file_operations atmci_req_fops = {
307 .owner = THIS_MODULE,
308 .open = atmci_req_open,
309 .read = seq_read,
310 .llseek = seq_lseek,
311 .release = single_release,
312};
313
314static void atmci_show_status_reg(struct seq_file *s,
315 const char *regname, u32 value)
316{
317 static const char *sr_bit[] = {
318 [0] = "CMDRDY",
319 [1] = "RXRDY",
320 [2] = "TXRDY",
321 [3] = "BLKE",
322 [4] = "DTIP",
323 [5] = "NOTBUSY",
04d699c3
RE		 324 [6] = "ENDRX",
325 [7] = "ENDTX",
deec9ae3
HS		 326 [8] = "SDIOIRQA",
327 [9] = "SDIOIRQB",
04d699c3
RE		 328 [12] = "SDIOWAIT",
329 [14] = "RXBUFF",
330 [15] = "TXBUFE",
deec9ae3
HS		 331 [16] = "RINDE",
332 [17] = "RDIRE",
333 [18] = "RCRCE",
334 [19] = "RENDE",
335 [20] = "RTOE",
336 [21] = "DCRCE",
337 [22] = "DTOE",
04d699c3
RE		 338 [23] = "CSTOE",
339 [24] = "BLKOVRE",
340 [25] = "DMADONE",
341 [26] = "FIFOEMPTY",
342 [27] = "XFRDONE",
deec9ae3
HS		 343 [30] = "OVRE",
344 [31] = "UNRE",
345 };
346 unsigned int i;
347
348 seq_printf(s, "%s:\t0x%08x", regname, value);
349 for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
350 if (value & (1 << i)) {
351 if (sr_bit[i])
352 seq_printf(s, " %s", sr_bit[i]);
353 else
354 seq_puts(s, " UNKNOWN");
355 }
356 }
357 seq_putc(s, '\n');
358}
359
360static int atmci_regs_show(struct seq_file *s, void *v)
361{
362 struct atmel_mci *host = s->private;
363 u32 *buf;
364
2c96a293 365 buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
deec9ae3
HS		 366 if (!buf)
367 return -ENOMEM;
368
965ebf33
HS		 369 /*
370 * Grab a more or less consistent snapshot. Note that we're
371 * not disabling interrupts, so IMR and SR may not be
372 * consistent.
373 */
374 spin_lock_bh(&host->lock);
87e60f2b 375 clk_enable(host->mck);
2c96a293 376 memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
87e60f2b 377 clk_disable(host->mck);
965ebf33 378 spin_unlock_bh(&host->lock);
deec9ae3
HS		 379
380 seq_printf(s, "MR:\t0x%08x%s%s CLKDIV=%u\n",
2c96a293
LD		 381 buf[ATMCI_MR / 4],
382 buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
383 buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "",
384 buf[ATMCI_MR / 4] & 0xff);
385 seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
386 seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
387 seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
deec9ae3 388 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
2c96a293
LD		 389 buf[ATMCI_BLKR / 4],
390 buf[ATMCI_BLKR / 4] & 0xffff,
391 (buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
796211b7 392 if (host->caps.has_cstor_reg)
2c96a293 393 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
deec9ae3
HS		 394
395 /* Don't read RSPR and RDR; it will consume the data there */
396
2c96a293
LD		 397 atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
398 atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
deec9ae3 399
796211b7 400 if (host->caps.has_dma) {
74791a2d
NF		 401 u32 val;
402
2c96a293 403 val = buf[ATMCI_DMA / 4];
74791a2d
NF		 404 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
405 val, val & 3,
406 ((val >> 4) & 3) ?
407 1 << (((val >> 4) & 3) + 1) : 1,
2c96a293 408 val & ATMCI_DMAEN ? " DMAEN" : "");
796211b7
LD		 409 }
410 if (host->caps.has_cfg_reg) {
411 u32 val;
74791a2d 412
2c96a293 413 val = buf[ATMCI_CFG / 4];
74791a2d
NF		 414 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
415 val,
2c96a293
LD		 416 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
417 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
418 val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
419 val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
74791a2d
NF		 420 }
421
b17339a1
HS		 422 kfree(buf);
423
deec9ae3
HS		 424 return 0;
425}
426
427static int atmci_regs_open(struct inode *inode, struct file *file)
428{
429 return single_open(file, atmci_regs_show, inode->i_private);
430}
431
432static const struct file_operations atmci_regs_fops = {
433 .owner = THIS_MODULE,
434 .open = atmci_regs_open,
435 .read = seq_read,
436 .llseek = seq_lseek,
437 .release = single_release,
438};
439
965ebf33 440static void atmci_init_debugfs(struct atmel_mci_slot *slot)
deec9ae3 441{
965ebf33
HS		 442 struct mmc_host *mmc = slot->mmc;
443 struct atmel_mci *host = slot->host;
444 struct dentry *root;
445 struct dentry *node;
deec9ae3 446
deec9ae3
HS		 447 root = mmc->debugfs_root;
448 if (!root)
449 return;
450
451 node = debugfs_create_file("regs", S_IRUSR, root, host,
452 &atmci_regs_fops);
453 if (IS_ERR(node))
454 return;
455 if (!node)
456 goto err;
457
965ebf33 458 node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
deec9ae3
HS		 459 if (!node)
460 goto err;
461
c06ad258
HS		 462 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
463 if (!node)
464 goto err;
465
deec9ae3
HS		 466 node = debugfs_create_x32("pending_events", S_IRUSR, root,
467 (u32 *)&host->pending_events);
468 if (!node)
469 goto err;
470
471 node = debugfs_create_x32("completed_events", S_IRUSR, root,
472 (u32 *)&host->completed_events);
473 if (!node)
474 goto err;
475
476 return;
477
478err:
965ebf33 479 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
deec9ae3 480}
7d2be074 481
2c96a293 482static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
7d2be074
HS		 483 unsigned int ns)
484{
485 return (ns * (host->bus_hz / 1000000) + 999) / 1000;
486}
487
488static void atmci_set_timeout(struct atmel_mci *host,
965ebf33 489 struct atmel_mci_slot *slot, struct mmc_data *data)
7d2be074
HS		 490{
491 static unsigned dtomul_to_shift[] = {
492 0, 4, 7, 8, 10, 12, 16, 20
493 };
494 unsigned timeout;
495 unsigned dtocyc;
496 unsigned dtomul;
497
2c96a293
LD		 498 timeout = atmci_ns_to_clocks(host, data->timeout_ns)
499 + data->timeout_clks;
7d2be074
HS		 500
501 for (dtomul = 0; dtomul < 8; dtomul++) {
502 unsigned shift = dtomul_to_shift[dtomul];
503 dtocyc = (timeout + (1 << shift) - 1) >> shift;
504 if (dtocyc < 15)
505 break;
506 }
507
508 if (dtomul >= 8) {
509 dtomul = 7;
510 dtocyc = 15;
511 }
512
965ebf33 513 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
7d2be074 514 dtocyc << dtomul_to_shift[dtomul]);
03fc9a7f 515 atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
7d2be074
HS		 516}
517
518/*
519 * Return mask with command flags to be enabled for this command.
520 */
521static u32 atmci_prepare_command(struct mmc_host *mmc,
522 struct mmc_command *cmd)
523{
524 struct mmc_data *data;
525 u32 cmdr;
526
527 cmd->error = -EINPROGRESS;
528
2c96a293 529 cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
7d2be074
HS		 530
531 if (cmd->flags & MMC_RSP_PRESENT) {
532 if (cmd->flags & MMC_RSP_136)
2c96a293 533 cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
7d2be074 534 else
2c96a293 535 cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
7d2be074
HS		 536 }
537
538 /*
539 * This should really be MAXLAT_5 for CMD2 and ACMD41, but
540 * it's too difficult to determine whether this is an ACMD or
541 * not. Better make it 64.
542 */
2c96a293 543 cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
7d2be074
HS		 544
545 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
2c96a293 546 cmdr |= ATMCI_CMDR_OPDCMD;
7d2be074
HS		 547
548 data = cmd->data;
549 if (data) {
2c96a293 550 cmdr |= ATMCI_CMDR_START_XFER;
2f1d7918
NF		 551
552 if (cmd->opcode == SD_IO_RW_EXTENDED) {
2c96a293 553 cmdr |= ATMCI_CMDR_SDIO_BLOCK;
2f1d7918
NF		 554 } else {
555 if (data->flags & MMC_DATA_STREAM)
2c96a293 556 cmdr |= ATMCI_CMDR_STREAM;
2f1d7918 557 else if (data->blocks > 1)
2c96a293 558 cmdr |= ATMCI_CMDR_MULTI_BLOCK;
2f1d7918 559 else
2c96a293 560 cmdr |= ATMCI_CMDR_BLOCK;
2f1d7918 561 }
7d2be074
HS		 562
563 if (data->flags & MMC_DATA_READ)
2c96a293 564 cmdr |= ATMCI_CMDR_TRDIR_READ;
7d2be074
HS		 565 }
566
567 return cmdr;
568}
569
11d1488b 570static void atmci_send_command(struct atmel_mci *host,
965ebf33 571 struct mmc_command *cmd, u32 cmd_flags)
7d2be074 572{
7d2be074
HS		 573 WARN_ON(host->cmd);
574 host->cmd = cmd;
575
965ebf33 576 dev_vdbg(&host->pdev->dev,
7d2be074
HS		 577 "start command: ARGR=0x%08x CMDR=0x%08x\n",
578 cmd->arg, cmd_flags);
579
03fc9a7f
LD		 580 atmci_writel(host, ATMCI_ARGR, cmd->arg);
581 atmci_writel(host, ATMCI_CMDR, cmd_flags);
7d2be074
HS		 582}
583
2c96a293 584static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
7d2be074 585{
11d1488b 586 atmci_send_command(host, data->stop, host->stop_cmdr);
03fc9a7f 587 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
7d2be074
HS		 588}
589
796211b7
LD		 590/*
591 * Configure given PDC buffer taking care of alignement issues.
592 * Update host->data_size and host->sg.
593 */
594static void atmci_pdc_set_single_buf(struct atmel_mci *host,
595 enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
596{
597 u32 pointer_reg, counter_reg;
598
599 if (dir == XFER_RECEIVE) {
600 pointer_reg = ATMEL_PDC_RPR;
601 counter_reg = ATMEL_PDC_RCR;
602 } else {
603 pointer_reg = ATMEL_PDC_TPR;
604 counter_reg = ATMEL_PDC_TCR;
605 }
606
607 if (buf_nb == PDC_SECOND_BUF) {
1ebbe3d3
LD		 608 pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
609 counter_reg += ATMEL_PDC_SCND_BUF_OFF;
796211b7
LD		 610 }
611
612 atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
341fa4c3 613 if (host->data_size <= sg_dma_len(host->sg)) {
796211b7
LD		 614 if (host->data_size & 0x3) {
615 /* If size is different from modulo 4, transfer bytes */
616 atmci_writel(host, counter_reg, host->data_size);
617 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
618 } else {
619 /* Else transfer 32-bits words */
620 atmci_writel(host, counter_reg, host->data_size / 4);
621 }
622 host->data_size = 0;
623 } else {
624 /* We assume the size of a page is 32-bits aligned */
341fa4c3
LD		 625 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
626 host->data_size -= sg_dma_len(host->sg);
796211b7
LD		 627 if (host->data_size)
628 host->sg = sg_next(host->sg);
629 }
630}
631
632/*
633 * Configure PDC buffer according to the data size ie configuring one or two
634 * buffers. Don't use this function if you want to configure only the second
635 * buffer. In this case, use atmci_pdc_set_single_buf.
636 */
637static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
65e8b083 638{
796211b7
LD		 639 atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
640 if (host->data_size)
641 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
642}
643
644/*
645 * Unmap sg lists, called when transfer is finished.
646 */
647static void atmci_pdc_cleanup(struct atmel_mci *host)
648{
649 struct mmc_data *data = host->data;
65e8b083 650
009a891b 651 if (data)
796211b7
LD		 652 dma_unmap_sg(&host->pdev->dev,
653 data->sg, data->sg_len,
654 ((data->flags & MMC_DATA_WRITE)
655 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
65e8b083
HS		 656}
657
796211b7
LD		 658/*
659 * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
660 * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
661 * interrupt needed for both transfer directions.
662 */
663static void atmci_pdc_complete(struct atmel_mci *host)
65e8b083 664{
796211b7
LD		 665 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
666 atmci_pdc_cleanup(host);
65e8b083 667
796211b7
LD		 668 /*
669 * If the card was removed, data will be NULL. No point trying
670 * to send the stop command or waiting for NBUSY in this case.
671 */
672 if (host->data) {
65e8b083 673 atmci_set_pending(host, EVENT_XFER_COMPLETE);
796211b7 674 tasklet_schedule(&host->tasklet);
03fc9a7f 675 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
65e8b083
HS		 676 }
677}
678
796211b7
LD		 679static void atmci_dma_cleanup(struct atmel_mci *host)
680{
681 struct mmc_data *data = host->data;
682
683 if (data)
684 dma_unmap_sg(host->dma.chan->device->dev,
685 data->sg, data->sg_len,
686 ((data->flags & MMC_DATA_WRITE)
687 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
688}
689
690/*
691 * This function is called by the DMA driver from tasklet context.
692 */
65e8b083
HS		 693static void atmci_dma_complete(void *arg)
694{
695 struct atmel_mci *host = arg;
696 struct mmc_data *data = host->data;
697
698 dev_vdbg(&host->pdev->dev, "DMA complete\n");
699
796211b7 700 if (host->caps.has_dma)
74791a2d 701 /* Disable DMA hardware handshaking on MCI */
03fc9a7f 702 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
74791a2d 703
65e8b083
HS		 704 atmci_dma_cleanup(host);
705
706 /*
707 * If the card was removed, data will be NULL. No point trying
708 * to send the stop command or waiting for NBUSY in this case.
709 */
710 if (data) {
711 atmci_set_pending(host, EVENT_XFER_COMPLETE);
712 tasklet_schedule(&host->tasklet);
713
714 /*
715 * Regardless of what the documentation says, we have
716 * to wait for NOTBUSY even after block read
717 * operations.
718 *
719 * When the DMA transfer is complete, the controller
720 * may still be reading the CRC from the card, i.e.
721 * the data transfer is still in progress and we
722 * haven't seen all the potential error bits yet.
723 *
724 * The interrupt handler will schedule a different
725 * tasklet to finish things up when the data transfer
726 * is completely done.
727 *
728 * We may not complete the mmc request here anyway
729 * because the mmc layer may call back and cause us to
730 * violate the "don't submit new operations from the
731 * completion callback" rule of the dma engine
732 * framework.
733 */
03fc9a7f 734 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
65e8b083
HS		 735 }
736}
737
796211b7
LD		 738/*
739 * Returns a mask of interrupt flags to be enabled after the whole
740 * request has been prepared.
741 */
742static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
743{
744 u32 iflags;
745
746 data->error = -EINPROGRESS;
747
748 host->sg = data->sg;
749 host->data = data;
750 host->data_chan = NULL;
751
752 iflags = ATMCI_DATA_ERROR_FLAGS;
753
754 /*
755 * Errata: MMC data write operation with less than 12
756 * bytes is impossible.
757 *
758 * Errata: MCI Transmit Data Register (TDR) FIFO
759 * corruption when length is not multiple of 4.
760 */
761 if (data->blocks * data->blksz < 12
762 || (data->blocks * data->blksz) & 3)
763 host->need_reset = true;
764
765 host->pio_offset = 0;
766 if (data->flags & MMC_DATA_READ)
767 iflags |= ATMCI_RXRDY;
768 else
769 iflags |= ATMCI_TXRDY;
770
771 return iflags;
772}
773
774/*
775 * Set interrupt flags and set block length into the MCI mode register even
776 * if this value is also accessible in the MCI block register. It seems to be
777 * necessary before the High Speed MCI version. It also map sg and configure
778 * PDC registers.
779 */
780static u32
781atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
782{
783 u32 iflags, tmp;
784 unsigned int sg_len;
785 enum dma_data_direction dir;
786
787 data->error = -EINPROGRESS;
788
789 host->data = data;
790 host->sg = data->sg;
791 iflags = ATMCI_DATA_ERROR_FLAGS;
792
793 /* Enable pdc mode */
794 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
795
796 if (data->flags & MMC_DATA_READ) {
797 dir = DMA_FROM_DEVICE;
798 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
799 } else {
800 dir = DMA_TO_DEVICE;
801 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE;
802 }
803
804 /* Set BLKLEN */
805 tmp = atmci_readl(host, ATMCI_MR);
806 tmp &= 0x0000ffff;
807 tmp |= ATMCI_BLKLEN(data->blksz);
808 atmci_writel(host, ATMCI_MR, tmp);
809
810 /* Configure PDC */
811 host->data_size = data->blocks * data->blksz;
812 sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, dir);
796211b7
LD		 813 if (host->data_size)
814 atmci_pdc_set_both_buf(host,
815 ((dir == DMA_FROM_DEVICE) ? XFER_RECEIVE : XFER_TRANSMIT));
816
817 return iflags;
818}
819
820static u32
74791a2d 821atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
65e8b083
HS		 822{
823 struct dma_chan *chan;
824 struct dma_async_tx_descriptor *desc;
825 struct scatterlist *sg;
826 unsigned int i;
827 enum dma_data_direction direction;
05f5799c 828 enum dma_transfer_direction slave_dirn;
657a77fa 829 unsigned int sglen;
796211b7
LD		 830 u32 iflags;
831
832 data->error = -EINPROGRESS;
833
834 WARN_ON(host->data);
835 host->sg = NULL;
836 host->data = data;
837
838 iflags = ATMCI_DATA_ERROR_FLAGS;
65e8b083
HS		 839
840 /*
841 * We don't do DMA on "complex" transfers, i.e. with
842 * non-word-aligned buffers or lengths. Also, we don't bother
843 * with all the DMA setup overhead for short transfers.
844 */
796211b7
LD		 845 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
846 return atmci_prepare_data(host, data);
65e8b083 847 if (data->blksz & 3)
796211b7 848 return atmci_prepare_data(host, data);
65e8b083
HS		 849
850 for_each_sg(data->sg, sg, data->sg_len, i) {
851 if (sg->offset & 3 || sg->length & 3)
796211b7 852 return atmci_prepare_data(host, data);
65e8b083
HS		 853 }
854
855 /* If we don't have a channel, we can't do DMA */
856 chan = host->dma.chan;
6f49a57a 857 if (chan)
65e8b083 858 host->data_chan = chan;
65e8b083
HS		 859
860 if (!chan)
861 return -ENODEV;
862
796211b7 863 if (host->caps.has_dma)
03fc9a7f 864 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(3) | ATMCI_DMAEN);
74791a2d 865
05f5799c 866 if (data->flags & MMC_DATA_READ) {
65e8b083 867 direction = DMA_FROM_DEVICE;
e2b35f3d 868 host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
05f5799c 869 } else {
65e8b083 870 direction = DMA_TO_DEVICE;
e2b35f3d 871 host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
05f5799c 872 }
65e8b083 873
266ac3f2 874 sglen = dma_map_sg(chan->device->dev, data->sg,
796211b7 875 data->sg_len, direction);
88ce4db3 876
e2b35f3d 877 dmaengine_slave_config(chan, &host->dma_conf);
16052827 878 desc = dmaengine_prep_slave_sg(chan,
05f5799c 879 data->sg, sglen, slave_dirn,
65e8b083
HS		 880 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
881 if (!desc)
657a77fa 882 goto unmap_exit;
65e8b083
HS		 883
884 host->dma.data_desc = desc;
885 desc->callback = atmci_dma_complete;
886 desc->callback_param = host;
65e8b083 887
796211b7 888 return iflags;
657a77fa 889unmap_exit:
88ce4db3 890 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, direction);
657a77fa 891 return -ENOMEM;
65e8b083
HS		 892}
893
796211b7
LD		 894static void
895atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
896{
897 return;
898}
899
900/*
901 * Start PDC according to transfer direction.
902 */
903static void
904atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
905{
906 if (data->flags & MMC_DATA_READ)
907 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
908 else
909 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
910}
911
912static void
913atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
74791a2d
NF		 914{
915 struct dma_chan *chan = host->data_chan;
916 struct dma_async_tx_descriptor *desc = host->dma.data_desc;
917
918 if (chan) {
5328906a
LW		 919 dmaengine_submit(desc);
920 dma_async_issue_pending(chan);
74791a2d
NF		 921 }
922}
923
796211b7 924static void atmci_stop_transfer(struct atmel_mci *host)
65e8b083 925{
65e8b083 926 atmci_set_pending(host, EVENT_XFER_COMPLETE);
03fc9a7f 927 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
65e8b083
HS		 928}
929
7d2be074 930/*
796211b7 931 * Stop data transfer because error(s) occured.
7d2be074 932 */
796211b7 933static void atmci_stop_transfer_pdc(struct atmel_mci *host)
7d2be074 934{
796211b7
LD		 935 atmci_set_pending(host, EVENT_XFER_COMPLETE);
936 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
937}
965ebf33 938
796211b7
LD		 939static void atmci_stop_transfer_dma(struct atmel_mci *host)
940{
941 struct dma_chan *chan = host->data_chan;
965ebf33 942
796211b7
LD		 943 if (chan) {
944 dmaengine_terminate_all(chan);
945 atmci_dma_cleanup(host);
946 } else {
947 /* Data transfer was stopped by the interrupt handler */
948 atmci_set_pending(host, EVENT_XFER_COMPLETE);
949 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
65e8b083 950 }
7d2be074
HS		 951}
952
796211b7
LD		 953/*
954 * Start a request: prepare data if needed, prepare the command and activate
955 * interrupts.
956 */
965ebf33
HS		 957static void atmci_start_request(struct atmel_mci *host,
958 struct atmel_mci_slot *slot)
7d2be074 959{
965ebf33 960 struct mmc_request *mrq;
7d2be074 961 struct mmc_command *cmd;
965ebf33 962 struct mmc_data *data;
7d2be074 963 u32 iflags;
965ebf33 964 u32 cmdflags;
7d2be074 965
965ebf33
HS		 966 mrq = slot->mrq;
967 host->cur_slot = slot;
7d2be074 968 host->mrq = mrq;
965ebf33 969
7d2be074
HS		 970 host->pending_events = 0;
971 host->completed_events = 0;
ca55f46e 972 host->data_status = 0;
7d2be074 973
965ebf33 974 if (host->need_reset) {
18ee684b
LD		 975 iflags = atmci_readl(host, ATMCI_IMR);
976 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
03fc9a7f
LD		 977 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
978 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
979 atmci_writel(host, ATMCI_MR, host->mode_reg);
796211b7 980 if (host->caps.has_cfg_reg)
03fc9a7f 981 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
18ee684b 982 atmci_writel(host, ATMCI_IER, iflags);
965ebf33
HS		 983 host->need_reset = false;
984 }
03fc9a7f 985 atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
965ebf33 986
03fc9a7f 987 iflags = atmci_readl(host, ATMCI_IMR);
2c96a293 988 if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
965ebf33
HS		 989 dev_warn(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
990 iflags);
991
992 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
993 /* Send init sequence (74 clock cycles) */
03fc9a7f
LD		 994 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
995 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
965ebf33
HS		 996 cpu_relax();
997 }
74791a2d 998 iflags = 0;
7d2be074
HS		 999 data = mrq->data;
1000 if (data) {
965ebf33 1001 atmci_set_timeout(host, slot, data);
a252e3e3
HS		 1002
1003 /* Must set block count/size before sending command */
03fc9a7f 1004 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
2c96a293 1005 | ATMCI_BLKLEN(data->blksz));
965ebf33 1006 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
2c96a293 1007 ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
74791a2d 1008
796211b7 1009 iflags |= host->prepare_data(host, data);
7d2be074
HS		 1010 }
1011
2c96a293 1012 iflags |= ATMCI_CMDRDY;
7d2be074 1013 cmd = mrq->cmd;
965ebf33 1014 cmdflags = atmci_prepare_command(slot->mmc, cmd);
11d1488b 1015 atmci_send_command(host, cmd, cmdflags);
7d2be074
HS		 1016
1017 if (data)
796211b7 1018 host->submit_data(host, data);
7d2be074
HS		 1019
1020 if (mrq->stop) {
965ebf33 1021 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
2c96a293 1022 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
7d2be074 1023 if (!(data->flags & MMC_DATA_WRITE))
2c96a293 1024 host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
7d2be074 1025 if (data->flags & MMC_DATA_STREAM)
2c96a293 1026 host->stop_cmdr |= ATMCI_CMDR_STREAM;
7d2be074 1027 else
2c96a293 1028 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
7d2be074
HS		 1029 }
1030
1031 /*
1032 * We could have enabled interrupts earlier, but I suspect
1033 * that would open up a nice can of interesting race
1034 * conditions (e.g. command and data complete, but stop not
1035 * prepared yet.)
1036 */
03fc9a7f 1037 atmci_writel(host, ATMCI_IER, iflags);
965ebf33 1038}
7d2be074 1039
965ebf33
HS		 1040static void atmci_queue_request(struct atmel_mci *host,
1041 struct atmel_mci_slot *slot, struct mmc_request *mrq)
1042{
1043 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1044 host->state);
1045
1046 spin_lock_bh(&host->lock);
1047 slot->mrq = mrq;
1048 if (host->state == STATE_IDLE) {
1049 host->state = STATE_SENDING_CMD;
1050 atmci_start_request(host, slot);
1051 } else {
1052 list_add_tail(&slot->queue_node, &host->queue);
1053 }
1054 spin_unlock_bh(&host->lock);
1055}
7d2be074 1056
965ebf33
HS		 1057static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1058{
1059 struct atmel_mci_slot *slot = mmc_priv(mmc);
1060 struct atmel_mci *host = slot->host;
1061 struct mmc_data *data;
1062
1063 WARN_ON(slot->mrq);
1064
1065 /*
1066 * We may "know" the card is gone even though there's still an
1067 * electrical connection. If so, we really need to communicate
1068 * this to the MMC core since there won't be any more
1069 * interrupts as the card is completely removed. Otherwise,
1070 * the MMC core might believe the card is still there even
1071 * though the card was just removed very slowly.
1072 */
1073 if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
1074 mrq->cmd->error = -ENOMEDIUM;
1075 mmc_request_done(mmc, mrq);
1076 return;
1077 }
1078
1079 /* We don't support multiple blocks of weird lengths. */
1080 data = mrq->data;
1081 if (data && data->blocks > 1 && data->blksz & 3) {
1082 mrq->cmd->error = -EINVAL;
1083 mmc_request_done(mmc, mrq);
1084 }
1085
1086 atmci_queue_request(host, slot, mrq);
7d2be074
HS		 1087}
1088
1089static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1090{
965ebf33
HS		 1091 struct atmel_mci_slot *slot = mmc_priv(mmc);
1092 struct atmel_mci *host = slot->host;
1093 unsigned int i;
7d2be074 1094
2c96a293 1095 slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
945533b5
HS		 1096 switch (ios->bus_width) {
1097 case MMC_BUS_WIDTH_1:
2c96a293 1098 slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
945533b5
HS		 1099 break;
1100 case MMC_BUS_WIDTH_4:
2c96a293 1101 slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
945533b5
HS		 1102 break;
1103 }
1104
7d2be074 1105 if (ios->clock) {
965ebf33 1106 unsigned int clock_min = ~0U;
7d2be074
HS		 1107 u32 clkdiv;
1108
965ebf33
HS		 1109 spin_lock_bh(&host->lock);
1110 if (!host->mode_reg) {
945533b5 1111 clk_enable(host->mck);
03fc9a7f
LD		 1112 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1113 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
796211b7 1114 if (host->caps.has_cfg_reg)
03fc9a7f 1115 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
965ebf33 1116 }
945533b5 1117
965ebf33
HS		 1118 /*
1119 * Use mirror of ios->clock to prevent race with mmc
1120 * core ios update when finding the minimum.
1121 */
1122 slot->clock = ios->clock;
2c96a293 1123 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
965ebf33
HS		 1124 if (host->slot[i] && host->slot[i]->clock
1125 && host->slot[i]->clock < clock_min)
1126 clock_min = host->slot[i]->clock;
1127 }
1128
1129 /* Calculate clock divider */
1130 clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
7d2be074
HS		 1131 if (clkdiv > 255) {
1132 dev_warn(&mmc->class_dev,
1133 "clock %u too slow; using %lu\n",
965ebf33 1134 clock_min, host->bus_hz / (2 * 256));
7d2be074
HS		 1135 clkdiv = 255;
1136 }
1137
2c96a293 1138 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
04d699c3 1139
965ebf33
HS		 1140 /*
1141 * WRPROOF and RDPROOF prevent overruns/underruns by
1142 * stopping the clock when the FIFO is full/empty.
1143 * This state is not expected to last for long.
1144 */
796211b7 1145 if (host->caps.has_rwproof)
2c96a293 1146 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
7d2be074 1147
796211b7 1148 if (host->caps.has_cfg_reg) {
99ddffd8
NF		 1149 /* setup High Speed mode in relation with card capacity */
1150 if (ios->timing == MMC_TIMING_SD_HS)
2c96a293 1151 host->cfg_reg |= ATMCI_CFG_HSMODE;
99ddffd8 1152 else
2c96a293 1153 host->cfg_reg &= ~ATMCI_CFG_HSMODE;
99ddffd8
NF		 1154 }
1155
1156 if (list_empty(&host->queue)) {
03fc9a7f 1157 atmci_writel(host, ATMCI_MR, host->mode_reg);
796211b7 1158 if (host->caps.has_cfg_reg)
03fc9a7f 1159 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
99ddffd8 1160 } else {
965ebf33 1161 host->need_clock_update = true;
99ddffd8 1162 }
965ebf33
HS		 1163
1164 spin_unlock_bh(&host->lock);
945533b5 1165 } else {
965ebf33
HS		 1166 bool any_slot_active = false;
1167
1168 spin_lock_bh(&host->lock);
1169 slot->clock = 0;
2c96a293 1170 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
965ebf33
HS		 1171 if (host->slot[i] && host->slot[i]->clock) {
1172 any_slot_active = true;
1173 break;
1174 }
945533b5 1175 }
965ebf33 1176 if (!any_slot_active) {
03fc9a7f 1177 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
965ebf33 1178 if (host->mode_reg) {
03fc9a7f 1179 atmci_readl(host, ATMCI_MR);
965ebf33
HS		 1180 clk_disable(host->mck);
1181 }
1182 host->mode_reg = 0;
1183 }
1184 spin_unlock_bh(&host->lock);
7d2be074
HS		 1185 }
1186
1187 switch (ios->power_mode) {
965ebf33
HS		 1188 case MMC_POWER_UP:
1189 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
1190 break;
7d2be074
HS		 1191 default:
1192 /*
1193 * TODO: None of the currently available AVR32-based
1194 * boards allow MMC power to be turned off. Implement
1195 * power control when this can be tested properly.
965ebf33
HS		 1196 *
1197 * We also need to hook this into the clock management
1198 * somehow so that newly inserted cards aren't
1199 * subjected to a fast clock before we have a chance
1200 * to figure out what the maximum rate is. Currently,
1201 * there's no way to avoid this, and there never will
1202 * be for boards that don't support power control.
7d2be074
HS		 1203 */
1204 break;
1205 }
1206}
1207
1208static int atmci_get_ro(struct mmc_host *mmc)
1209{
965ebf33
HS		 1210 int read_only = -ENOSYS;
1211 struct atmel_mci_slot *slot = mmc_priv(mmc);
7d2be074 1212
965ebf33
HS		 1213 if (gpio_is_valid(slot->wp_pin)) {
1214 read_only = gpio_get_value(slot->wp_pin);
7d2be074
HS		 1215 dev_dbg(&mmc->class_dev, "card is %s\n",
1216 read_only ? "read-only" : "read-write");
7d2be074
HS		 1217 }
1218
1219 return read_only;
1220}
1221
965ebf33
HS		 1222static int atmci_get_cd(struct mmc_host *mmc)
1223{
1224 int present = -ENOSYS;
1225 struct atmel_mci_slot *slot = mmc_priv(mmc);
1226
1227 if (gpio_is_valid(slot->detect_pin)) {
1c1452be
JL		 1228 present = !(gpio_get_value(slot->detect_pin) ^
1229 slot->detect_is_active_high);
965ebf33
HS		 1230 dev_dbg(&mmc->class_dev, "card is %spresent\n",
1231 present ? "" : "not ");
1232 }
1233
1234 return present;
1235}
1236
88ff82ed
AG		 1237static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1238{
1239 struct atmel_mci_slot *slot = mmc_priv(mmc);
1240 struct atmel_mci *host = slot->host;
1241
1242 if (enable)
03fc9a7f 1243 atmci_writel(host, ATMCI_IER, slot->sdio_irq);
88ff82ed 1244 else
03fc9a7f 1245 atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
88ff82ed
AG		 1246}
1247
965ebf33 1248static const struct mmc_host_ops atmci_ops = {
7d2be074
HS		 1249 .request = atmci_request,
1250 .set_ios = atmci_set_ios,
1251 .get_ro = atmci_get_ro,
965ebf33 1252 .get_cd = atmci_get_cd,
88ff82ed 1253 .enable_sdio_irq = atmci_enable_sdio_irq,
7d2be074
HS		 1254};
1255
965ebf33
HS		 1256/* Called with host->lock held */
1257static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1258 __releases(&host->lock)
1259 __acquires(&host->lock)
1260{
1261 struct atmel_mci_slot *slot = NULL;
1262 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1263
1264 WARN_ON(host->cmd || host->data);
1265
1266 /*
1267 * Update the MMC clock rate if necessary. This may be
1268 * necessary if set_ios() is called when a different slot is
25985edc 1269 * busy transferring data.
965ebf33 1270 */
99ddffd8 1271 if (host->need_clock_update) {
03fc9a7f 1272 atmci_writel(host, ATMCI_MR, host->mode_reg);
796211b7 1273 if (host->caps.has_cfg_reg)
03fc9a7f 1274 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
99ddffd8 1275 }
965ebf33
HS		 1276
1277 host->cur_slot->mrq = NULL;
1278 host->mrq = NULL;
1279 if (!list_empty(&host->queue)) {
1280 slot = list_entry(host->queue.next,
1281 struct atmel_mci_slot, queue_node);
1282 list_del(&slot->queue_node);
1283 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1284 mmc_hostname(slot->mmc));
1285 host->state = STATE_SENDING_CMD;
1286 atmci_start_request(host, slot);
1287 } else {
1288 dev_vdbg(&host->pdev->dev, "list empty\n");
1289 host->state = STATE_IDLE;
1290 }
1291
1292 spin_unlock(&host->lock);
1293 mmc_request_done(prev_mmc, mrq);
1294 spin_lock(&host->lock);
1295}
1296
7d2be074 1297static void atmci_command_complete(struct atmel_mci *host,
c06ad258 1298 struct mmc_command *cmd)
7d2be074 1299{
c06ad258
HS		 1300 u32 status = host->cmd_status;
1301
7d2be074 1302 /* Read the response from the card (up to 16 bytes) */
03fc9a7f
LD		 1303 cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
1304 cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
1305 cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
1306 cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
7d2be074 1307
2c96a293 1308 if (status & ATMCI_RTOE)
7d2be074 1309 cmd->error = -ETIMEDOUT;
2c96a293 1310 else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
7d2be074 1311 cmd->error = -EILSEQ;
2c96a293 1312 else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
7d2be074
HS		 1313 cmd->error = -EIO;
1314 else
1315 cmd->error = 0;
1316
1317 if (cmd->error) {
965ebf33 1318 dev_dbg(&host->pdev->dev,
7d2be074
HS		 1319 "command error: status=0x%08x\n", status);
1320
1321 if (cmd->data) {
796211b7 1322 host->stop_transfer(host);
009a891b 1323 host->data = NULL;
03fc9a7f 1324 atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY
2c96a293 1325 | ATMCI_TXRDY | ATMCI_RXRDY
7d2be074
HS		 1326 | ATMCI_DATA_ERROR_FLAGS);
1327 }
1328 }
1329}
1330
1331static void atmci_detect_change(unsigned long data)
1332{
965ebf33
HS		 1333 struct atmel_mci_slot *slot = (struct atmel_mci_slot *)data;
1334 bool present;
1335 bool present_old;
7d2be074
HS		 1336
1337 /*
965ebf33
HS		 1338 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1339 * freeing the interrupt. We must not re-enable the interrupt
1340 * if it has been freed, and if we're shutting down, it
1341 * doesn't really matter whether the card is present or not.
7d2be074
HS		 1342 */
1343 smp_rmb();
965ebf33 1344 if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
7d2be074
HS		 1345 return;
1346
965ebf33 1347 enable_irq(gpio_to_irq(slot->detect_pin));
1c1452be
JL		 1348 present = !(gpio_get_value(slot->detect_pin) ^
1349 slot->detect_is_active_high);
965ebf33 1350 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
7d2be074 1351
965ebf33
HS		 1352 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1353 present, present_old);
7d2be074 1354
965ebf33
HS		 1355 if (present != present_old) {
1356 struct atmel_mci *host = slot->host;
1357 struct mmc_request *mrq;
1358
1359 dev_dbg(&slot->mmc->class_dev, "card %s\n",
7d2be074 1360 present ? "inserted" : "removed");
7d2be074 1361
965ebf33
HS		 1362 spin_lock(&host->lock);
1363
1364 if (!present)
1365 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1366 else
1367 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
7d2be074
HS		 1368
1369 /* Clean up queue if present */
965ebf33 1370 mrq = slot->mrq;
7d2be074 1371 if (mrq) {
965ebf33
HS		 1372 if (mrq == host->mrq) {
1373 /*
1374 * Reset controller to terminate any ongoing
1375 * commands or data transfers.
1376 */
03fc9a7f
LD		 1377 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1378 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1379 atmci_writel(host, ATMCI_MR, host->mode_reg);
796211b7 1380 if (host->caps.has_cfg_reg)
03fc9a7f 1381 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
965ebf33
HS		 1382
1383 host->data = NULL;
1384 host->cmd = NULL;
1385
1386 switch (host->state) {
1387 case STATE_IDLE:
c06ad258 1388 break;
965ebf33
HS		 1389 case STATE_SENDING_CMD:
1390 mrq->cmd->error = -ENOMEDIUM;
1391 if (!mrq->data)
1392 break;
1393 /* fall through */
1394 case STATE_SENDING_DATA:
c06ad258 1395 mrq->data->error = -ENOMEDIUM;
796211b7 1396 host->stop_transfer(host);
c06ad258 1397 break;
965ebf33
HS		 1398 case STATE_DATA_BUSY:
1399 case STATE_DATA_ERROR:
1400 if (mrq->data->error == -EINPROGRESS)
1401 mrq->data->error = -ENOMEDIUM;
1402 if (!mrq->stop)
1403 break;
1404 /* fall through */
1405 case STATE_SENDING_STOP:
1406 mrq->stop->error = -ENOMEDIUM;
1407 break;
1408 }
7d2be074 1409
965ebf33
HS		 1410 atmci_request_end(host, mrq);
1411 } else {
1412 list_del(&slot->queue_node);
1413 mrq->cmd->error = -ENOMEDIUM;
1414 if (mrq->data)
1415 mrq->data->error = -ENOMEDIUM;
1416 if (mrq->stop)
1417 mrq->stop->error = -ENOMEDIUM;
1418
1419 spin_unlock(&host->lock);
1420 mmc_request_done(slot->mmc, mrq);
1421 spin_lock(&host->lock);
1422 }
7d2be074 1423 }
965ebf33 1424 spin_unlock(&host->lock);
7d2be074 1425
965ebf33 1426 mmc_detect_change(slot->mmc, 0);
7d2be074
HS		 1427 }
1428}
1429
1430static void atmci_tasklet_func(unsigned long priv)
1431{
965ebf33 1432 struct atmel_mci *host = (struct atmel_mci *)priv;
7d2be074
HS		 1433 struct mmc_request *mrq = host->mrq;
1434 struct mmc_data *data = host->data;
c06ad258
HS		 1435 struct mmc_command *cmd = host->cmd;
1436 enum atmel_mci_state state = host->state;
1437 enum atmel_mci_state prev_state;
1438 u32 status;
1439
965ebf33
HS		 1440 spin_lock(&host->lock);
1441
c06ad258 1442 state = host->state;
7d2be074 1443
965ebf33 1444 dev_vdbg(&host->pdev->dev,
c06ad258
HS		 1445 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1446 state, host->pending_events, host->completed_events,
03fc9a7f 1447 atmci_readl(host, ATMCI_IMR));
7d2be074 1448
c06ad258
HS		 1449 do {
1450 prev_state = state;
7d2be074 1451
c06ad258 1452 switch (state) {
965ebf33
HS		 1453 case STATE_IDLE:
1454 break;
1455
c06ad258
HS		 1456 case STATE_SENDING_CMD:
1457 if (!atmci_test_and_clear_pending(host,
1458 EVENT_CMD_COMPLETE))
1459 break;
7d2be074 1460
c06ad258
HS		 1461 host->cmd = NULL;
1462 atmci_set_completed(host, EVENT_CMD_COMPLETE);
1463 atmci_command_complete(host, mrq->cmd);
1464 if (!mrq->data || cmd->error) {
965ebf33
HS		 1465 atmci_request_end(host, host->mrq);
1466 goto unlock;
c06ad258 1467 }
7d2be074 1468
c06ad258
HS		 1469 prev_state = state = STATE_SENDING_DATA;
1470 /* fall through */
7d2be074 1471
c06ad258
HS		 1472 case STATE_SENDING_DATA:
1473 if (atmci_test_and_clear_pending(host,
1474 EVENT_DATA_ERROR)) {
796211b7 1475 host->stop_transfer(host);
c06ad258 1476 if (data->stop)
2c96a293 1477 atmci_send_stop_cmd(host, data);
c06ad258
HS		 1478 state = STATE_DATA_ERROR;
1479 break;
1480 }
7d2be074 1481
c06ad258
HS		 1482 if (!atmci_test_and_clear_pending(host,
1483 EVENT_XFER_COMPLETE))
1484 break;
7d2be074 1485
c06ad258
HS		 1486 atmci_set_completed(host, EVENT_XFER_COMPLETE);
1487 prev_state = state = STATE_DATA_BUSY;
1488 /* fall through */
7d2be074 1489
c06ad258
HS		 1490 case STATE_DATA_BUSY:
1491 if (!atmci_test_and_clear_pending(host,
1492 EVENT_DATA_COMPLETE))
1493 break;
1494
1495 host->data = NULL;
1496 atmci_set_completed(host, EVENT_DATA_COMPLETE);
1497 status = host->data_status;
1498 if (unlikely(status & ATMCI_DATA_ERROR_FLAGS)) {
2c96a293 1499 if (status & ATMCI_DTOE) {
965ebf33 1500 dev_dbg(&host->pdev->dev,
c06ad258
HS		 1501 "data timeout error\n");
1502 data->error = -ETIMEDOUT;
2c96a293 1503 } else if (status & ATMCI_DCRCE) {
965ebf33 1504 dev_dbg(&host->pdev->dev,
c06ad258
HS		 1505 "data CRC error\n");
1506 data->error = -EILSEQ;
1507 } else {
965ebf33 1508 dev_dbg(&host->pdev->dev,
c06ad258
HS		 1509 "data FIFO error (status=%08x)\n",
1510 status);
1511 data->error = -EIO;
1512 }
1513 } else {
1514 data->bytes_xfered = data->blocks * data->blksz;
1515 data->error = 0;
03fc9a7f 1516 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS);
c06ad258
HS		 1517 }
1518
1519 if (!data->stop) {
965ebf33
HS		 1520 atmci_request_end(host, host->mrq);
1521 goto unlock;
c06ad258 1522 }
7d2be074 1523
c06ad258
HS		 1524 prev_state = state = STATE_SENDING_STOP;
1525 if (!data->error)
2c96a293 1526 atmci_send_stop_cmd(host, data);
c06ad258
HS		 1527 /* fall through */
1528
1529 case STATE_SENDING_STOP:
1530 if (!atmci_test_and_clear_pending(host,
1531 EVENT_CMD_COMPLETE))
1532 break;
1533
1534 host->cmd = NULL;
1535 atmci_command_complete(host, mrq->stop);
965ebf33
HS		 1536 atmci_request_end(host, host->mrq);
1537 goto unlock;
c06ad258
HS		 1538
1539 case STATE_DATA_ERROR:
1540 if (!atmci_test_and_clear_pending(host,
1541 EVENT_XFER_COMPLETE))
1542 break;
1543
1544 state = STATE_DATA_BUSY;
1545 break;
1546 }
1547 } while (state != prev_state);
1548
1549 host->state = state;
965ebf33
HS		 1550
1551unlock:
1552 spin_unlock(&host->lock);
7d2be074
HS		 1553}
1554
1555static void atmci_read_data_pio(struct atmel_mci *host)
1556{
1557 struct scatterlist *sg = host->sg;
1558 void *buf = sg_virt(sg);
1559 unsigned int offset = host->pio_offset;
1560 struct mmc_data *data = host->data;
1561 u32 value;
1562 u32 status;
1563 unsigned int nbytes = 0;
1564
1565 do {
03fc9a7f 1566 value = atmci_readl(host, ATMCI_RDR);
7d2be074
HS		 1567 if (likely(offset + 4 <= sg->length)) {
1568 put_unaligned(value, (u32 *)(buf + offset));
1569
1570 offset += 4;
1571 nbytes += 4;
1572
1573 if (offset == sg->length) {
5e7184ae 1574 flush_dcache_page(sg_page(sg));
7d2be074
HS		 1575 host->sg = sg = sg_next(sg);
1576 if (!sg)
1577 goto done;
1578
1579 offset = 0;
1580 buf = sg_virt(sg);
1581 }
1582 } else {
1583 unsigned int remaining = sg->length - offset;
1584 memcpy(buf + offset, &value, remaining);
1585 nbytes += remaining;
1586
1587 flush_dcache_page(sg_page(sg));
1588 host->sg = sg = sg_next(sg);
1589 if (!sg)
1590 goto done;
1591
1592 offset = 4 - remaining;
1593 buf = sg_virt(sg);
1594 memcpy(buf, (u8 *)&value + remaining, offset);
1595 nbytes += offset;
1596 }
1597
03fc9a7f 1598 status = atmci_readl(host, ATMCI_SR);
7d2be074 1599 if (status & ATMCI_DATA_ERROR_FLAGS) {
03fc9a7f 1600 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
7d2be074
HS		 1601 | ATMCI_DATA_ERROR_FLAGS));
1602 host->data_status = status;
965ebf33
HS		 1603 data->bytes_xfered += nbytes;
1604 smp_wmb();
7d2be074
HS		 1605 atmci_set_pending(host, EVENT_DATA_ERROR);
1606 tasklet_schedule(&host->tasklet);
965ebf33 1607 return;
7d2be074 1608 }
2c96a293 1609 } while (status & ATMCI_RXRDY);
7d2be074
HS		 1610
1611 host->pio_offset = offset;
1612 data->bytes_xfered += nbytes;
1613
1614 return;
1615
1616done:
03fc9a7f
LD		 1617 atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
1618 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
7d2be074 1619 data->bytes_xfered += nbytes;
965ebf33 1620 smp_wmb();
c06ad258 1621 atmci_set_pending(host, EVENT_XFER_COMPLETE);
7d2be074
HS		 1622}
1623
1624static void atmci_write_data_pio(struct atmel_mci *host)
1625{
1626 struct scatterlist *sg = host->sg;
1627 void *buf = sg_virt(sg);
1628 unsigned int offset = host->pio_offset;
1629 struct mmc_data *data = host->data;
1630 u32 value;
1631 u32 status;
1632 unsigned int nbytes = 0;
1633
1634 do {
1635 if (likely(offset + 4 <= sg->length)) {
1636 value = get_unaligned((u32 *)(buf + offset));
03fc9a7f 1637 atmci_writel(host, ATMCI_TDR, value);
7d2be074
HS		 1638
1639 offset += 4;
1640 nbytes += 4;
1641 if (offset == sg->length) {
1642 host->sg = sg = sg_next(sg);
1643 if (!sg)
1644 goto done;
1645
1646 offset = 0;
1647 buf = sg_virt(sg);
1648 }
1649 } else {
1650 unsigned int remaining = sg->length - offset;
1651
1652 value = 0;
1653 memcpy(&value, buf + offset, remaining);
1654 nbytes += remaining;
1655
1656 host->sg = sg = sg_next(sg);
1657 if (!sg) {
03fc9a7f 1658 atmci_writel(host, ATMCI_TDR, value);
7d2be074
HS		 1659 goto done;
1660 }
1661
1662 offset = 4 - remaining;
1663 buf = sg_virt(sg);
1664 memcpy((u8 *)&value + remaining, buf, offset);
03fc9a7f 1665 atmci_writel(host, ATMCI_TDR, value);
7d2be074
HS		 1666 nbytes += offset;
1667 }
1668
03fc9a7f 1669 status = atmci_readl(host, ATMCI_SR);
7d2be074 1670 if (status & ATMCI_DATA_ERROR_FLAGS) {
03fc9a7f 1671 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
7d2be074
HS		 1672 | ATMCI_DATA_ERROR_FLAGS));
1673 host->data_status = status;
965ebf33
HS		 1674 data->bytes_xfered += nbytes;
1675 smp_wmb();
7d2be074
HS		 1676 atmci_set_pending(host, EVENT_DATA_ERROR);
1677 tasklet_schedule(&host->tasklet);
965ebf33 1678 return;
7d2be074 1679 }
2c96a293 1680 } while (status & ATMCI_TXRDY);
7d2be074
HS		 1681
1682 host->pio_offset = offset;
1683 data->bytes_xfered += nbytes;
1684
1685 return;
1686
1687done:
03fc9a7f
LD		 1688 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
1689 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
7d2be074 1690 data->bytes_xfered += nbytes;
965ebf33 1691 smp_wmb();
c06ad258 1692 atmci_set_pending(host, EVENT_XFER_COMPLETE);
7d2be074
HS		 1693}
1694
965ebf33 1695static void atmci_cmd_interrupt(struct atmel_mci *host, u32 status)
7d2be074 1696{
03fc9a7f 1697 atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
7d2be074 1698
c06ad258 1699 host->cmd_status = status;
965ebf33 1700 smp_wmb();
c06ad258 1701 atmci_set_pending(host, EVENT_CMD_COMPLETE);
7d2be074
HS		 1702 tasklet_schedule(&host->tasklet);
1703}
1704
88ff82ed
AG		 1705static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
1706{
1707 int i;
1708
2c96a293 1709 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
88ff82ed
AG		 1710 struct atmel_mci_slot *slot = host->slot[i];
1711 if (slot && (status & slot->sdio_irq)) {
1712 mmc_signal_sdio_irq(slot->mmc);
1713 }
1714 }
1715}
1716
1717
7d2be074
HS		 1718static irqreturn_t atmci_interrupt(int irq, void *dev_id)
1719{
965ebf33 1720 struct atmel_mci *host = dev_id;
7d2be074
HS		 1721 u32 status, mask, pending;
1722 unsigned int pass_count = 0;
1723
7d2be074 1724 do {
03fc9a7f
LD		 1725 status = atmci_readl(host, ATMCI_SR);
1726 mask = atmci_readl(host, ATMCI_IMR);
7d2be074
HS		 1727 pending = status & mask;
1728 if (!pending)
1729 break;
1730
1731 if (pending & ATMCI_DATA_ERROR_FLAGS) {
03fc9a7f 1732 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
2c96a293 1733 | ATMCI_RXRDY | ATMCI_TXRDY);
03fc9a7f 1734 pending &= atmci_readl(host, ATMCI_IMR);
965ebf33 1735
7d2be074 1736 host->data_status = status;
965ebf33 1737 smp_wmb();
7d2be074
HS		 1738 atmci_set_pending(host, EVENT_DATA_ERROR);
1739 tasklet_schedule(&host->tasklet);
1740 }
796211b7 1741
796211b7
LD		 1742 if (pending & ATMCI_TXBUFE) {
1743 atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
7e8ba228 1744 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
796211b7
LD		 1745 /*
1746 * We can receive this interruption before having configured
1747 * the second pdc buffer, so we need to reconfigure first and
1748 * second buffers again
1749 */
1750 if (host->data_size) {
1751 atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
7e8ba228 1752 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
796211b7
LD		 1753 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
1754 } else {
1755 atmci_pdc_complete(host);
1756 }
7e8ba228
LD		 1757 } else if (pending & ATMCI_ENDTX) {
1758 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
796211b7
LD		 1759
1760 if (host->data_size) {
1761 atmci_pdc_set_single_buf(host,
7e8ba228
LD		 1762 XFER_TRANSMIT, PDC_SECOND_BUF);
1763 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
796211b7
LD		 1764 }
1765 }
1766
1767 if (pending & ATMCI_RXBUFF) {
1768 atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
7e8ba228 1769 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
796211b7
LD		 1770 /*
1771 * We can receive this interruption before having configured
1772 * the second pdc buffer, so we need to reconfigure first and
1773 * second buffers again
1774 */
1775 if (host->data_size) {
1776 atmci_pdc_set_both_buf(host, XFER_RECEIVE);
7e8ba228 1777 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
796211b7
LD		 1778 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
1779 } else {
1780 atmci_pdc_complete(host);
1781 }
7e8ba228
LD		 1782 } else if (pending & ATMCI_ENDRX) {
1783 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
1784
1785 if (host->data_size) {
1786 atmci_pdc_set_single_buf(host,
1787 XFER_RECEIVE, PDC_SECOND_BUF);
1788 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
1789 }
796211b7
LD		 1790 }
1791
7e8ba228 1792
2c96a293 1793 if (pending & ATMCI_NOTBUSY) {
03fc9a7f 1794 atmci_writel(host, ATMCI_IDR,
2c96a293 1795 ATMCI_DATA_ERROR_FLAGS | ATMCI_NOTBUSY);
ca55f46e
HS		 1796 if (!host->data_status)
1797 host->data_status = status;
965ebf33 1798 smp_wmb();
7d2be074
HS		 1799 atmci_set_pending(host, EVENT_DATA_COMPLETE);
1800 tasklet_schedule(&host->tasklet);
1801 }
2c96a293 1802 if (pending & ATMCI_RXRDY)
7d2be074 1803 atmci_read_data_pio(host);
2c96a293 1804 if (pending & ATMCI_TXRDY)
7d2be074
HS		 1805 atmci_write_data_pio(host);
1806
2c96a293 1807 if (pending & ATMCI_CMDRDY)
965ebf33 1808 atmci_cmd_interrupt(host, status);
88ff82ed 1809
2c96a293 1810 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
88ff82ed
AG		 1811 atmci_sdio_interrupt(host, status);
1812
7d2be074
HS		 1813 } while (pass_count++ < 5);
1814
7d2be074
HS		 1815 return pass_count ? IRQ_HANDLED : IRQ_NONE;
1816}
1817
1818static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
1819{
965ebf33 1820 struct atmel_mci_slot *slot = dev_id;
7d2be074
HS		 1821
1822 /*
1823 * Disable interrupts until the pin has stabilized and check
1824 * the state then. Use mod_timer() since we may be in the
1825 * middle of the timer routine when this interrupt triggers.
1826 */
1827 disable_irq_nosync(irq);
965ebf33 1828 mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
7d2be074
HS		 1829
1830 return IRQ_HANDLED;
1831}
1832
965ebf33
HS		 1833static int __init atmci_init_slot(struct atmel_mci *host,
1834 struct mci_slot_pdata *slot_data, unsigned int id,
88ff82ed 1835 u32 sdc_reg, u32 sdio_irq)
965ebf33
HS		 1836{
1837 struct mmc_host *mmc;
1838 struct atmel_mci_slot *slot;
1839
1840 mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
1841 if (!mmc)
1842 return -ENOMEM;
1843
1844 slot = mmc_priv(mmc);
1845 slot->mmc = mmc;
1846 slot->host = host;
1847 slot->detect_pin = slot_data->detect_pin;
1848 slot->wp_pin = slot_data->wp_pin;
1c1452be 1849 slot->detect_is_active_high = slot_data->detect_is_active_high;
965ebf33 1850 slot->sdc_reg = sdc_reg;
88ff82ed 1851 slot->sdio_irq = sdio_irq;
965ebf33
HS		 1852
1853 mmc->ops = &atmci_ops;
1854 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
1855 mmc->f_max = host->bus_hz / 2;
1856 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
88ff82ed
AG		 1857 if (sdio_irq)
1858 mmc->caps |= MMC_CAP_SDIO_IRQ;
796211b7 1859 if (host->caps.has_highspeed)
99ddffd8 1860 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
965ebf33
HS		 1861 if (slot_data->bus_width >= 4)
1862 mmc->caps |= MMC_CAP_4_BIT_DATA;
1863
a36274e0 1864 mmc->max_segs = 64;
965ebf33
HS		 1865 mmc->max_req_size = 32768 * 512;
1866 mmc->max_blk_size = 32768;
1867 mmc->max_blk_count = 512;
1868
1869 /* Assume card is present initially */
1870 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1871 if (gpio_is_valid(slot->detect_pin)) {
1872 if (gpio_request(slot->detect_pin, "mmc_detect")) {
1873 dev_dbg(&mmc->class_dev, "no detect pin available\n");
1874 slot->detect_pin = -EBUSY;
1c1452be
JL		 1875 } else if (gpio_get_value(slot->detect_pin) ^
1876 slot->detect_is_active_high) {
965ebf33
HS		 1877 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1878 }
1879 }
1880
1881 if (!gpio_is_valid(slot->detect_pin))
1882 mmc->caps |= MMC_CAP_NEEDS_POLL;
1883
1884 if (gpio_is_valid(slot->wp_pin)) {
1885 if (gpio_request(slot->wp_pin, "mmc_wp")) {
1886 dev_dbg(&mmc->class_dev, "no WP pin available\n");
1887 slot->wp_pin = -EBUSY;
1888 }
1889 }
1890
1891 host->slot[id] = slot;
1892 mmc_add_host(mmc);
1893
1894 if (gpio_is_valid(slot->detect_pin)) {
1895 int ret;
1896
1897 setup_timer(&slot->detect_timer, atmci_detect_change,
1898 (unsigned long)slot);
1899
1900 ret = request_irq(gpio_to_irq(slot->detect_pin),
1901 atmci_detect_interrupt,
1902 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
1903 "mmc-detect", slot);
1904 if (ret) {
1905 dev_dbg(&mmc->class_dev,
1906 "could not request IRQ %d for detect pin\n",
1907 gpio_to_irq(slot->detect_pin));
1908 gpio_free(slot->detect_pin);
1909 slot->detect_pin = -EBUSY;
1910 }
1911 }
1912
1913 atmci_init_debugfs(slot);
1914
1915 return 0;
1916}
1917
1918static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot,
1919 unsigned int id)
1920{
1921 /* Debugfs stuff is cleaned up by mmc core */
1922
1923 set_bit(ATMCI_SHUTDOWN, &slot->flags);
1924 smp_wmb();
1925
1926 mmc_remove_host(slot->mmc);
1927
1928 if (gpio_is_valid(slot->detect_pin)) {
1929 int pin = slot->detect_pin;
1930
1931 free_irq(gpio_to_irq(pin), slot);
1932 del_timer_sync(&slot->detect_timer);
1933 gpio_free(pin);
1934 }
1935 if (gpio_is_valid(slot->wp_pin))
1936 gpio_free(slot->wp_pin);
1937
1938 slot->host->slot[id] = NULL;
1939 mmc_free_host(slot->mmc);
1940}
1941
2c96a293 1942static bool atmci_filter(struct dma_chan *chan, void *slave)
74465b4f 1943{
2635d1ba 1944 struct mci_dma_data *sl = slave;
74465b4f 1945
2635d1ba
NF		 1946 if (sl && find_slave_dev(sl) == chan->device->dev) {
1947 chan->private = slave_data_ptr(sl);
7dd60251 1948 return true;
2635d1ba 1949 } else {
7dd60251 1950 return false;
2635d1ba 1951 }
74465b4f 1952}
2635d1ba 1953
ef878198 1954static bool atmci_configure_dma(struct atmel_mci *host)
2635d1ba
NF		 1955{
1956 struct mci_platform_data *pdata;
1957
1958 if (host == NULL)
ef878198 1959 return false;
2635d1ba
NF		 1960
1961 pdata = host->pdev->dev.platform_data;
1962
1963 if (pdata && find_slave_dev(pdata->dma_slave)) {
1964 dma_cap_mask_t mask;
1965
2635d1ba
NF		 1966 /* Try to grab a DMA channel */
1967 dma_cap_zero(mask);
1968 dma_cap_set(DMA_SLAVE, mask);
1969 host->dma.chan =
2c96a293 1970 dma_request_channel(mask, atmci_filter, pdata->dma_slave);
2635d1ba 1971 }
ef878198
LD		 1972 if (!host->dma.chan) {
1973 dev_warn(&host->pdev->dev, "no DMA channel available\n");
1974 return false;
1975 } else {
74791a2d 1976 dev_info(&host->pdev->dev,
b81cfc41 1977 "using %s for DMA transfers\n",
74791a2d 1978 dma_chan_name(host->dma.chan));
e2b35f3d
VK		 1979
1980 host->dma_conf.src_addr = host->mapbase + ATMCI_RDR;
1981 host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1982 host->dma_conf.src_maxburst = 1;
1983 host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR;
1984 host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1985 host->dma_conf.dst_maxburst = 1;
1986 host->dma_conf.device_fc = false;
ef878198
LD		 1987 return true;
1988 }
2635d1ba 1989}
796211b7
LD		 1990
1991static inline unsigned int atmci_get_version(struct atmel_mci *host)
1992{
1993 return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
1994}
1995
1996/*
1997 * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
1998 * HSMCI provides DMA support and a new config register but no more supports
1999 * PDC.
2000 */
2001static void __init atmci_get_cap(struct atmel_mci *host)
2002{
2003 unsigned int version;
2004
2005 version = atmci_get_version(host);
2006 dev_info(&host->pdev->dev,
2007 "version: 0x%x\n", version);
2008
2009 host->caps.has_dma = 0;
2010 host->caps.has_pdc = 0;
2011 host->caps.has_cfg_reg = 0;
2012 host->caps.has_cstor_reg = 0;
2013 host->caps.has_highspeed = 0;
2014 host->caps.has_rwproof = 0;
2015
2016 /* keep only major version number */
2017 switch (version & 0xf00) {
2018 case 0x100:
2019 case 0x200:
2020 host->caps.has_pdc = 1;
2021 host->caps.has_rwproof = 1;
2022 break;
2023 case 0x300:
2024 case 0x400:
2025 case 0x500:
2026#ifdef CONFIG_AT_HDMAC
2027 host->caps.has_dma = 1;
2635d1ba 2028#else
796211b7
LD		 2029 host->caps.has_dma = 0;
2030 dev_info(&host->pdev->dev,
2031 "has dma capability but dma engine is not selected, then use pio\n");
74465b4f 2032#endif
796211b7
LD		 2033 host->caps.has_cfg_reg = 1;
2034 host->caps.has_cstor_reg = 1;
2035 host->caps.has_highspeed = 1;
2036 host->caps.has_rwproof = 1;
2037 break;
2038 default:
2039 dev_warn(&host->pdev->dev,
2040 "Unmanaged mci version, set minimum capabilities\n");
2041 break;
2042 }
2043}
74465b4f 2044
7d2be074
HS		 2045static int __init atmci_probe(struct platform_device *pdev)
2046{
2047 struct mci_platform_data *pdata;
965ebf33
HS		 2048 struct atmel_mci *host;
2049 struct resource *regs;
2050 unsigned int nr_slots;
2051 int irq;
2052 int ret;
7d2be074
HS		 2053
2054 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2055 if (!regs)
2056 return -ENXIO;
2057 pdata = pdev->dev.platform_data;
2058 if (!pdata)
2059 return -ENXIO;
2060 irq = platform_get_irq(pdev, 0);
2061 if (irq < 0)
2062 return irq;
2063
965ebf33
HS		 2064 host = kzalloc(sizeof(struct atmel_mci), GFP_KERNEL);
2065 if (!host)
7d2be074
HS		 2066 return -ENOMEM;
2067
7d2be074 2068 host->pdev = pdev;
965ebf33
HS		 2069 spin_lock_init(&host->lock);
2070 INIT_LIST_HEAD(&host->queue);
7d2be074
HS		 2071
2072 host->mck = clk_get(&pdev->dev, "mci_clk");
2073 if (IS_ERR(host->mck)) {
2074 ret = PTR_ERR(host->mck);
2075 goto err_clk_get;
2076 }
2077
2078 ret = -ENOMEM;
e8e3f6ca 2079 host->regs = ioremap(regs->start, resource_size(regs));
7d2be074
HS		 2080 if (!host->regs)
2081 goto err_ioremap;
2082
2083 clk_enable(host->mck);
03fc9a7f 2084 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
7d2be074
HS		 2085 host->bus_hz = clk_get_rate(host->mck);
2086 clk_disable(host->mck);
2087
2088 host->mapbase = regs->start;
2089
965ebf33 2090 tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
7d2be074 2091
89c8aa20 2092 ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
7d2be074
HS		 2093 if (ret)
2094 goto err_request_irq;
2095
796211b7
LD		 2096 /* Get MCI capabilities and set operations according to it */
2097 atmci_get_cap(host);
ef878198 2098 if (host->caps.has_dma && atmci_configure_dma(host)) {
796211b7
LD		 2099 host->prepare_data = &atmci_prepare_data_dma;
2100 host->submit_data = &atmci_submit_data_dma;
2101 host->stop_transfer = &atmci_stop_transfer_dma;
2102 } else if (host->caps.has_pdc) {
2103 dev_info(&pdev->dev, "using PDC\n");
2104 host->prepare_data = &atmci_prepare_data_pdc;
2105 host->submit_data = &atmci_submit_data_pdc;
2106 host->stop_transfer = &atmci_stop_transfer_pdc;
2107 } else {
ef878198 2108 dev_info(&pdev->dev, "using PIO\n");
796211b7
LD		 2109 host->prepare_data = &atmci_prepare_data;
2110 host->submit_data = &atmci_submit_data;
2111 host->stop_transfer = &atmci_stop_transfer;
2112 }
2113
7d2be074
HS		 2114 platform_set_drvdata(pdev, host);
2115
965ebf33
HS		 2116 /* We need at least one slot to succeed */
2117 nr_slots = 0;
2118 ret = -ENODEV;
2119 if (pdata->slot[0].bus_width) {
2120 ret = atmci_init_slot(host, &pdata->slot[0],
2c96a293 2121 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
965ebf33
HS		 2122 if (!ret)
2123 nr_slots++;
2124 }
2125 if (pdata->slot[1].bus_width) {
2126 ret = atmci_init_slot(host, &pdata->slot[1],
2c96a293 2127 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
965ebf33
HS		 2128 if (!ret)
2129 nr_slots++;
7d2be074
HS		 2130 }
2131
04d699c3
RE		 2132 if (!nr_slots) {
2133 dev_err(&pdev->dev, "init failed: no slot defined\n");
965ebf33 2134 goto err_init_slot;
04d699c3 2135 }
7d2be074 2136
965ebf33
HS		 2137 dev_info(&pdev->dev,
2138 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2139 host->mapbase, irq, nr_slots);
deec9ae3 2140
7d2be074
HS		 2141 return 0;
2142
965ebf33 2143err_init_slot:
74465b4f
DW		 2144 if (host->dma.chan)
2145 dma_release_channel(host->dma.chan);
965ebf33 2146 free_irq(irq, host);
7d2be074
HS		 2147err_request_irq:
2148 iounmap(host->regs);
2149err_ioremap:
2150 clk_put(host->mck);
2151err_clk_get:
965ebf33 2152 kfree(host);
7d2be074
HS		 2153 return ret;
2154}
2155
2156static int __exit atmci_remove(struct platform_device *pdev)
2157{
965ebf33
HS		 2158 struct atmel_mci *host = platform_get_drvdata(pdev);
2159 unsigned int i;
7d2be074
HS		 2160
2161 platform_set_drvdata(pdev, NULL);
2162
2c96a293 2163 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
965ebf33
HS		 2164 if (host->slot[i])
2165 atmci_cleanup_slot(host->slot[i], i);
2166 }
7d2be074 2167
965ebf33 2168 clk_enable(host->mck);
03fc9a7f
LD		 2169 atmci_writel(host, ATMCI_IDR, ~0UL);
2170 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
2171 atmci_readl(host, ATMCI_SR);
965ebf33 2172 clk_disable(host->mck);
7d2be074 2173
65e8b083 2174#ifdef CONFIG_MMC_ATMELMCI_DMA
74465b4f
DW		 2175 if (host->dma.chan)
2176 dma_release_channel(host->dma.chan);
65e8b083
HS		 2177#endif
2178
965ebf33
HS		 2179 free_irq(platform_get_irq(pdev, 0), host);
2180 iounmap(host->regs);
7d2be074 2181
965ebf33
HS		 2182 clk_put(host->mck);
2183 kfree(host);
7d2be074 2184
7d2be074
HS		 2185 return 0;
2186}
2187
5c2f2b9b
NF		 2188#ifdef CONFIG_PM
2189static int atmci_suspend(struct device *dev)
2190{
2191 struct atmel_mci *host = dev_get_drvdata(dev);
2192 int i;
2193
2c96a293 2194 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
5c2f2b9b
NF		 2195 struct atmel_mci_slot *slot = host->slot[i];
2196 int ret;
2197
2198 if (!slot)
2199 continue;
2200 ret = mmc_suspend_host(slot->mmc);
2201 if (ret < 0) {
2202 while (--i >= 0) {
2203 slot = host->slot[i];
2204 if (slot
2205 && test_bit(ATMCI_SUSPENDED, &slot->flags)) {
2206 mmc_resume_host(host->slot[i]->mmc);
2207 clear_bit(ATMCI_SUSPENDED, &slot->flags);
2208 }
2209 }
2210 return ret;
2211 } else {
2212 set_bit(ATMCI_SUSPENDED, &slot->flags);
2213 }
2214 }
2215
2216 return 0;
2217}
2218
2219static int atmci_resume(struct device *dev)
2220{
2221 struct atmel_mci *host = dev_get_drvdata(dev);
2222 int i;
2223 int ret = 0;
2224
2c96a293 2225 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
5c2f2b9b
NF		 2226 struct atmel_mci_slot *slot = host->slot[i];
2227 int err;
2228
2229 slot = host->slot[i];
2230 if (!slot)
2231 continue;
2232 if (!test_bit(ATMCI_SUSPENDED, &slot->flags))
2233 continue;
2234 err = mmc_resume_host(slot->mmc);
2235 if (err < 0)
2236 ret = err;
2237 else
2238 clear_bit(ATMCI_SUSPENDED, &slot->flags);
2239 }
2240
2241 return ret;
2242}
2243static SIMPLE_DEV_PM_OPS(atmci_pm, atmci_suspend, atmci_resume);
2244#define ATMCI_PM_OPS (&atmci_pm)
2245#else
2246#define ATMCI_PM_OPS NULL
2247#endif
2248
7d2be074
HS		 2249static struct platform_driver atmci_driver = {
2250 .remove = __exit_p(atmci_remove),
2251 .driver = {
2252 .name = "atmel_mci",
5c2f2b9b 2253 .pm = ATMCI_PM_OPS,
7d2be074
HS		 2254 },
2255};
2256
2257static int __init atmci_init(void)
2258{
2259 return platform_driver_probe(&atmci_driver, atmci_probe);
2260}
2261
2262static void __exit atmci_exit(void)
2263{
2264 platform_driver_unregister(&atmci_driver);
2265}
2266
74465b4f 2267late_initcall(atmci_init); /* try to load after dma driver when built-in */
7d2be074
HS		 2268module_exit(atmci_exit);
2269
2270MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
e05503ef 2271MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
7d2be074 2272MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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