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ba264b34 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/au1xmmc.c - AU1XX0 MMC driver |
ba264b34 PP |
3 | * |
4 | * Copyright (c) 2005, Advanced Micro Devices, Inc. | |
5 | * | |
6 | * Developed with help from the 2.4.30 MMC AU1XXX controller including | |
7 | * the following copyright notices: | |
8 | * Copyright (c) 2003-2004 Embedded Edge, LLC. | |
9 | * Portions Copyright (C) 2002 Embedix, Inc | |
10 | * Copyright 2002 Hewlett-Packard Company | |
11 | ||
12 | * 2.6 version of this driver inspired by: | |
13 | * (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman, | |
14 | * All Rights Reserved. | |
15 | * (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King, | |
16 | * All Rights Reserved. | |
17 | * | |
18 | ||
19 | * This program is free software; you can redistribute it and/or modify | |
20 | * it under the terms of the GNU General Public License version 2 as | |
21 | * published by the Free Software Foundation. | |
22 | */ | |
23 | ||
e2d26477 | 24 | /* Why don't we use the SD controllers' carddetect feature? |
ba264b34 PP |
25 | * |
26 | * From the AU1100 MMC application guide: | |
27 | * If the Au1100-based design is intended to support both MultiMediaCards | |
28 | * and 1- or 4-data bit SecureDigital cards, then the solution is to | |
29 | * connect a weak (560KOhm) pull-up resistor to connector pin 1. | |
30 | * In doing so, a MMC card never enters SPI-mode communications, | |
31 | * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective | |
32 | * (the low to high transition will not occur). | |
ba264b34 PP |
33 | */ |
34 | ||
b6507596 | 35 | #include <linux/clk.h> |
ba264b34 PP |
36 | #include <linux/module.h> |
37 | #include <linux/init.h> | |
b256f9df | 38 | #include <linux/platform_device.h> |
ba264b34 PP |
39 | #include <linux/mm.h> |
40 | #include <linux/interrupt.h> | |
41 | #include <linux/dma-mapping.h> | |
0ada7a02 | 42 | #include <linux/scatterlist.h> |
c4223c2c | 43 | #include <linux/leds.h> |
ba264b34 | 44 | #include <linux/mmc/host.h> |
5a0e3ad6 | 45 | #include <linux/slab.h> |
c4223c2c | 46 | |
ba264b34 PP |
47 | #include <asm/io.h> |
48 | #include <asm/mach-au1x00/au1000.h> | |
49 | #include <asm/mach-au1x00/au1xxx_dbdma.h> | |
50 | #include <asm/mach-au1x00/au1100_mmc.h> | |
ba264b34 | 51 | |
ba264b34 PP |
52 | #define DRIVER_NAME "au1xxx-mmc" |
53 | ||
54 | /* Set this to enable special debugging macros */ | |
c4223c2c | 55 | /* #define DEBUG */ |
ba264b34 | 56 | |
c6563178 | 57 | #ifdef DEBUG |
5c0a889d | 58 | #define DBG(fmt, idx, args...) \ |
a3c76eb9 | 59 | pr_debug("au1xmmc(%d): DEBUG: " fmt, idx, ##args) |
ba264b34 | 60 | #else |
5c0a889d | 61 | #define DBG(fmt, idx, args...) do {} while (0) |
ba264b34 PP |
62 | #endif |
63 | ||
5c0a889d ML |
64 | /* Hardware definitions */ |
65 | #define AU1XMMC_DESCRIPTOR_COUNT 1 | |
e491d230 ML |
66 | |
67 | /* max DMA seg size: 64KB on Au1100, 4MB on Au1200 */ | |
1177d99d ML |
68 | #define AU1100_MMC_DESCRIPTOR_SIZE 0x0000ffff |
69 | #define AU1200_MMC_DESCRIPTOR_SIZE 0x003fffff | |
5c0a889d ML |
70 | |
71 | #define AU1XMMC_OCR (MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \ | |
72 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \ | |
73 | MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36) | |
74 | ||
75 | /* This gives us a hard value for the stop command that we can write directly | |
76 | * to the command register. | |
77 | */ | |
78 | #define STOP_CMD \ | |
79 | (SD_CMD_RT_1B | SD_CMD_CT_7 | (0xC << SD_CMD_CI_SHIFT) | SD_CMD_GO) | |
80 | ||
81 | /* This is the set of interrupts that we configure by default. */ | |
82 | #define AU1XMMC_INTERRUPTS \ | |
83 | (SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_RAT | \ | |
84 | SD_CONFIG_CR | SD_CONFIG_I) | |
85 | ||
86 | /* The poll event (looking for insert/remove events runs twice a second. */ | |
87 | #define AU1XMMC_DETECT_TIMEOUT (HZ/2) | |
88 | ||
89 | struct au1xmmc_host { | |
90 | struct mmc_host *mmc; | |
91 | struct mmc_request *mrq; | |
92 | ||
93 | u32 flags; | |
2f73bfbe | 94 | void __iomem *iobase; |
5c0a889d ML |
95 | u32 clock; |
96 | u32 bus_width; | |
97 | u32 power_mode; | |
98 | ||
99 | int status; | |
100 | ||
101 | struct { | |
102 | int len; | |
103 | int dir; | |
104 | } dma; | |
105 | ||
106 | struct { | |
107 | int index; | |
108 | int offset; | |
109 | int len; | |
110 | } pio; | |
111 | ||
112 | u32 tx_chan; | |
113 | u32 rx_chan; | |
114 | ||
115 | int irq; | |
116 | ||
5c0a889d ML |
117 | struct tasklet_struct finish_task; |
118 | struct tasklet_struct data_task; | |
119 | struct au1xmmc_platform_data *platdata; | |
120 | struct platform_device *pdev; | |
121 | struct resource *ioarea; | |
b6507596 | 122 | struct clk *clk; |
5c0a889d ML |
123 | }; |
124 | ||
125 | /* Status flags used by the host structure */ | |
126 | #define HOST_F_XMIT 0x0001 | |
127 | #define HOST_F_RECV 0x0002 | |
128 | #define HOST_F_DMA 0x0010 | |
1177d99d | 129 | #define HOST_F_DBDMA 0x0020 |
5c0a889d ML |
130 | #define HOST_F_ACTIVE 0x0100 |
131 | #define HOST_F_STOP 0x1000 | |
132 | ||
133 | #define HOST_S_IDLE 0x0001 | |
134 | #define HOST_S_CMD 0x0002 | |
135 | #define HOST_S_DATA 0x0003 | |
136 | #define HOST_S_STOP 0x0004 | |
137 | ||
138 | /* Easy access macros */ | |
139 | #define HOST_STATUS(h) ((h)->iobase + SD_STATUS) | |
140 | #define HOST_CONFIG(h) ((h)->iobase + SD_CONFIG) | |
141 | #define HOST_ENABLE(h) ((h)->iobase + SD_ENABLE) | |
142 | #define HOST_TXPORT(h) ((h)->iobase + SD_TXPORT) | |
143 | #define HOST_RXPORT(h) ((h)->iobase + SD_RXPORT) | |
144 | #define HOST_CMDARG(h) ((h)->iobase + SD_CMDARG) | |
145 | #define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE) | |
146 | #define HOST_CMD(h) ((h)->iobase + SD_CMD) | |
147 | #define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2) | |
148 | #define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT) | |
149 | #define HOST_DEBUG(h) ((h)->iobase + SD_DEBUG) | |
150 | ||
151 | #define DMA_CHANNEL(h) \ | |
152 | (((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan) | |
153 | ||
1177d99d ML |
154 | static inline int has_dbdma(void) |
155 | { | |
156 | switch (alchemy_get_cputype()) { | |
157 | case ALCHEMY_CPU_AU1200: | |
809f36c6 | 158 | case ALCHEMY_CPU_AU1300: |
1177d99d ML |
159 | return 1; |
160 | default: | |
161 | return 0; | |
162 | } | |
163 | } | |
164 | ||
ba264b34 PP |
165 | static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask) |
166 | { | |
2f73bfbe | 167 | u32 val = __raw_readl(HOST_CONFIG(host)); |
ba264b34 | 168 | val |= mask; |
2f73bfbe ML |
169 | __raw_writel(val, HOST_CONFIG(host)); |
170 | wmb(); /* drain writebuffer */ | |
ba264b34 PP |
171 | } |
172 | ||
173 | static inline void FLUSH_FIFO(struct au1xmmc_host *host) | |
174 | { | |
2f73bfbe | 175 | u32 val = __raw_readl(HOST_CONFIG2(host)); |
ba264b34 | 176 | |
2f73bfbe ML |
177 | __raw_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host)); |
178 | wmb(); /* drain writebuffer */ | |
179 | mdelay(1); | |
ba264b34 PP |
180 | |
181 | /* SEND_STOP will turn off clock control - this re-enables it */ | |
182 | val &= ~SD_CONFIG2_DF; | |
183 | ||
2f73bfbe ML |
184 | __raw_writel(val, HOST_CONFIG2(host)); |
185 | wmb(); /* drain writebuffer */ | |
ba264b34 PP |
186 | } |
187 | ||
188 | static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask) | |
189 | { | |
2f73bfbe | 190 | u32 val = __raw_readl(HOST_CONFIG(host)); |
ba264b34 | 191 | val &= ~mask; |
2f73bfbe ML |
192 | __raw_writel(val, HOST_CONFIG(host)); |
193 | wmb(); /* drain writebuffer */ | |
ba264b34 PP |
194 | } |
195 | ||
196 | static inline void SEND_STOP(struct au1xmmc_host *host) | |
197 | { | |
281dd23e | 198 | u32 config2; |
ba264b34 PP |
199 | |
200 | WARN_ON(host->status != HOST_S_DATA); | |
201 | host->status = HOST_S_STOP; | |
202 | ||
2f73bfbe ML |
203 | config2 = __raw_readl(HOST_CONFIG2(host)); |
204 | __raw_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host)); | |
205 | wmb(); /* drain writebuffer */ | |
ba264b34 | 206 | |
b595076a | 207 | /* Send the stop command */ |
2f73bfbe ML |
208 | __raw_writel(STOP_CMD, HOST_CMD(host)); |
209 | wmb(); /* drain writebuffer */ | |
ba264b34 PP |
210 | } |
211 | ||
212 | static void au1xmmc_set_power(struct au1xmmc_host *host, int state) | |
213 | { | |
c4223c2c ML |
214 | if (host->platdata && host->platdata->set_power) |
215 | host->platdata->set_power(host->mmc, state); | |
ba264b34 PP |
216 | } |
217 | ||
e2d26477 | 218 | static int au1xmmc_card_inserted(struct mmc_host *mmc) |
ba264b34 | 219 | { |
e2d26477 | 220 | struct au1xmmc_host *host = mmc_priv(mmc); |
c4223c2c ML |
221 | |
222 | if (host->platdata && host->platdata->card_inserted) | |
e2d26477 | 223 | return !!host->platdata->card_inserted(host->mmc); |
c4223c2c | 224 | |
e2d26477 | 225 | return -ENOSYS; |
ba264b34 PP |
226 | } |
227 | ||
82999770 | 228 | static int au1xmmc_card_readonly(struct mmc_host *mmc) |
ba264b34 | 229 | { |
82999770 | 230 | struct au1xmmc_host *host = mmc_priv(mmc); |
c4223c2c ML |
231 | |
232 | if (host->platdata && host->platdata->card_readonly) | |
e2d26477 | 233 | return !!host->platdata->card_readonly(mmc); |
c4223c2c | 234 | |
e2d26477 | 235 | return -ENOSYS; |
ba264b34 PP |
236 | } |
237 | ||
238 | static void au1xmmc_finish_request(struct au1xmmc_host *host) | |
239 | { | |
ba264b34 PP |
240 | struct mmc_request *mrq = host->mrq; |
241 | ||
242 | host->mrq = NULL; | |
c4223c2c | 243 | host->flags &= HOST_F_ACTIVE | HOST_F_DMA; |
ba264b34 PP |
244 | |
245 | host->dma.len = 0; | |
246 | host->dma.dir = 0; | |
247 | ||
248 | host->pio.index = 0; | |
249 | host->pio.offset = 0; | |
250 | host->pio.len = 0; | |
251 | ||
252 | host->status = HOST_S_IDLE; | |
253 | ||
ba264b34 PP |
254 | mmc_request_done(host->mmc, mrq); |
255 | } | |
256 | ||
257 | static void au1xmmc_tasklet_finish(unsigned long param) | |
258 | { | |
259 | struct au1xmmc_host *host = (struct au1xmmc_host *) param; | |
260 | au1xmmc_finish_request(host); | |
261 | } | |
262 | ||
263 | static int au1xmmc_send_command(struct au1xmmc_host *host, int wait, | |
be0192aa | 264 | struct mmc_command *cmd, struct mmc_data *data) |
ba264b34 | 265 | { |
ba264b34 PP |
266 | u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT); |
267 | ||
e142c24c | 268 | switch (mmc_resp_type(cmd)) { |
279bc445 ML |
269 | case MMC_RSP_NONE: |
270 | break; | |
ba264b34 PP |
271 | case MMC_RSP_R1: |
272 | mmccmd |= SD_CMD_RT_1; | |
273 | break; | |
274 | case MMC_RSP_R1B: | |
275 | mmccmd |= SD_CMD_RT_1B; | |
276 | break; | |
277 | case MMC_RSP_R2: | |
278 | mmccmd |= SD_CMD_RT_2; | |
279 | break; | |
280 | case MMC_RSP_R3: | |
281 | mmccmd |= SD_CMD_RT_3; | |
282 | break; | |
279bc445 | 283 | default: |
a3c76eb9 | 284 | pr_info("au1xmmc: unhandled response type %02x\n", |
279bc445 | 285 | mmc_resp_type(cmd)); |
17b0429d | 286 | return -EINVAL; |
ba264b34 PP |
287 | } |
288 | ||
be0192aa | 289 | if (data) { |
6356a9d9 | 290 | if (data->flags & MMC_DATA_READ) { |
be0192aa PO |
291 | if (data->blocks > 1) |
292 | mmccmd |= SD_CMD_CT_4; | |
293 | else | |
294 | mmccmd |= SD_CMD_CT_2; | |
6356a9d9 | 295 | } else if (data->flags & MMC_DATA_WRITE) { |
be0192aa PO |
296 | if (data->blocks > 1) |
297 | mmccmd |= SD_CMD_CT_3; | |
298 | else | |
299 | mmccmd |= SD_CMD_CT_1; | |
300 | } | |
ba264b34 PP |
301 | } |
302 | ||
2f73bfbe ML |
303 | __raw_writel(cmd->arg, HOST_CMDARG(host)); |
304 | wmb(); /* drain writebuffer */ | |
ba264b34 PP |
305 | |
306 | if (wait) | |
307 | IRQ_OFF(host, SD_CONFIG_CR); | |
308 | ||
2f73bfbe ML |
309 | __raw_writel((mmccmd | SD_CMD_GO), HOST_CMD(host)); |
310 | wmb(); /* drain writebuffer */ | |
ba264b34 PP |
311 | |
312 | /* Wait for the command to go on the line */ | |
2f73bfbe | 313 | while (__raw_readl(HOST_CMD(host)) & SD_CMD_GO) |
5c0a889d | 314 | /* nop */; |
ba264b34 PP |
315 | |
316 | /* Wait for the command to come back */ | |
ba264b34 | 317 | if (wait) { |
2f73bfbe | 318 | u32 status = __raw_readl(HOST_STATUS(host)); |
ba264b34 | 319 | |
5c0a889d | 320 | while (!(status & SD_STATUS_CR)) |
2f73bfbe | 321 | status = __raw_readl(HOST_STATUS(host)); |
ba264b34 PP |
322 | |
323 | /* Clear the CR status */ | |
2f73bfbe | 324 | __raw_writel(SD_STATUS_CR, HOST_STATUS(host)); |
ba264b34 PP |
325 | |
326 | IRQ_ON(host, SD_CONFIG_CR); | |
327 | } | |
328 | ||
17b0429d | 329 | return 0; |
ba264b34 PP |
330 | } |
331 | ||
332 | static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status) | |
333 | { | |
ba264b34 PP |
334 | struct mmc_request *mrq = host->mrq; |
335 | struct mmc_data *data; | |
336 | u32 crc; | |
337 | ||
5c0a889d | 338 | WARN_ON((host->status != HOST_S_DATA) && (host->status != HOST_S_STOP)); |
ba264b34 PP |
339 | |
340 | if (host->mrq == NULL) | |
341 | return; | |
342 | ||
343 | data = mrq->cmd->data; | |
344 | ||
345 | if (status == 0) | |
2f73bfbe | 346 | status = __raw_readl(HOST_STATUS(host)); |
ba264b34 PP |
347 | |
348 | /* The transaction is really over when the SD_STATUS_DB bit is clear */ | |
5c0a889d | 349 | while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB)) |
2f73bfbe | 350 | status = __raw_readl(HOST_STATUS(host)); |
ba264b34 | 351 | |
17b0429d | 352 | data->error = 0; |
ba264b34 PP |
353 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir); |
354 | ||
355 | /* Process any errors */ | |
ba264b34 PP |
356 | crc = (status & (SD_STATUS_WC | SD_STATUS_RC)); |
357 | if (host->flags & HOST_F_XMIT) | |
358 | crc |= ((status & 0x07) == 0x02) ? 0 : 1; | |
359 | ||
360 | if (crc) | |
17b0429d | 361 | data->error = -EILSEQ; |
ba264b34 PP |
362 | |
363 | /* Clear the CRC bits */ | |
2f73bfbe | 364 | __raw_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host)); |
ba264b34 PP |
365 | |
366 | data->bytes_xfered = 0; | |
367 | ||
17b0429d | 368 | if (!data->error) { |
1177d99d | 369 | if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) { |
ba264b34 PP |
370 | u32 chan = DMA_CHANNEL(host); |
371 | ||
5c0a889d | 372 | chan_tab_t *c = *((chan_tab_t **)chan); |
ba264b34 PP |
373 | au1x_dma_chan_t *cp = c->chan_ptr; |
374 | data->bytes_xfered = cp->ddma_bytecnt; | |
5c0a889d | 375 | } else |
ba264b34 | 376 | data->bytes_xfered = |
5c0a889d | 377 | (data->blocks * data->blksz) - host->pio.len; |
ba264b34 PP |
378 | } |
379 | ||
380 | au1xmmc_finish_request(host); | |
381 | } | |
382 | ||
383 | static void au1xmmc_tasklet_data(unsigned long param) | |
384 | { | |
5c0a889d | 385 | struct au1xmmc_host *host = (struct au1xmmc_host *)param; |
ba264b34 | 386 | |
2f73bfbe | 387 | u32 status = __raw_readl(HOST_STATUS(host)); |
ba264b34 PP |
388 | au1xmmc_data_complete(host, status); |
389 | } | |
390 | ||
391 | #define AU1XMMC_MAX_TRANSFER 8 | |
392 | ||
393 | static void au1xmmc_send_pio(struct au1xmmc_host *host) | |
394 | { | |
5c0a889d ML |
395 | struct mmc_data *data; |
396 | int sg_len, max, count; | |
397 | unsigned char *sg_ptr, val; | |
398 | u32 status; | |
ba264b34 PP |
399 | struct scatterlist *sg; |
400 | ||
401 | data = host->mrq->data; | |
402 | ||
403 | if (!(host->flags & HOST_F_XMIT)) | |
404 | return; | |
405 | ||
406 | /* This is the pointer to the data buffer */ | |
407 | sg = &data->sg[host->pio.index]; | |
45711f1a | 408 | sg_ptr = sg_virt(sg) + host->pio.offset; |
ba264b34 PP |
409 | |
410 | /* This is the space left inside the buffer */ | |
411 | sg_len = data->sg[host->pio.index].length - host->pio.offset; | |
412 | ||
5c0a889d | 413 | /* Check if we need less than the size of the sg_buffer */ |
ba264b34 | 414 | max = (sg_len > host->pio.len) ? host->pio.len : sg_len; |
5c0a889d ML |
415 | if (max > AU1XMMC_MAX_TRANSFER) |
416 | max = AU1XMMC_MAX_TRANSFER; | |
ba264b34 | 417 | |
5c0a889d | 418 | for (count = 0; count < max; count++) { |
2f73bfbe | 419 | status = __raw_readl(HOST_STATUS(host)); |
ba264b34 PP |
420 | |
421 | if (!(status & SD_STATUS_TH)) | |
422 | break; | |
423 | ||
424 | val = *sg_ptr++; | |
425 | ||
2f73bfbe ML |
426 | __raw_writel((unsigned long)val, HOST_TXPORT(host)); |
427 | wmb(); /* drain writebuffer */ | |
ba264b34 PP |
428 | } |
429 | ||
430 | host->pio.len -= count; | |
431 | host->pio.offset += count; | |
432 | ||
433 | if (count == sg_len) { | |
434 | host->pio.index++; | |
435 | host->pio.offset = 0; | |
436 | } | |
437 | ||
438 | if (host->pio.len == 0) { | |
439 | IRQ_OFF(host, SD_CONFIG_TH); | |
440 | ||
441 | if (host->flags & HOST_F_STOP) | |
442 | SEND_STOP(host); | |
443 | ||
444 | tasklet_schedule(&host->data_task); | |
445 | } | |
446 | } | |
447 | ||
448 | static void au1xmmc_receive_pio(struct au1xmmc_host *host) | |
449 | { | |
5c0a889d ML |
450 | struct mmc_data *data; |
451 | int max, count, sg_len = 0; | |
452 | unsigned char *sg_ptr = NULL; | |
453 | u32 status, val; | |
ba264b34 PP |
454 | struct scatterlist *sg; |
455 | ||
456 | data = host->mrq->data; | |
457 | ||
458 | if (!(host->flags & HOST_F_RECV)) | |
459 | return; | |
460 | ||
461 | max = host->pio.len; | |
462 | ||
463 | if (host->pio.index < host->dma.len) { | |
464 | sg = &data->sg[host->pio.index]; | |
45711f1a | 465 | sg_ptr = sg_virt(sg) + host->pio.offset; |
ba264b34 PP |
466 | |
467 | /* This is the space left inside the buffer */ | |
468 | sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset; | |
469 | ||
5c0a889d ML |
470 | /* Check if we need less than the size of the sg_buffer */ |
471 | if (sg_len < max) | |
472 | max = sg_len; | |
ba264b34 PP |
473 | } |
474 | ||
475 | if (max > AU1XMMC_MAX_TRANSFER) | |
476 | max = AU1XMMC_MAX_TRANSFER; | |
477 | ||
5c0a889d | 478 | for (count = 0; count < max; count++) { |
2f73bfbe | 479 | status = __raw_readl(HOST_STATUS(host)); |
ba264b34 PP |
480 | |
481 | if (!(status & SD_STATUS_NE)) | |
482 | break; | |
483 | ||
484 | if (status & SD_STATUS_RC) { | |
c4223c2c | 485 | DBG("RX CRC Error [%d + %d].\n", host->pdev->id, |
ba264b34 PP |
486 | host->pio.len, count); |
487 | break; | |
488 | } | |
489 | ||
490 | if (status & SD_STATUS_RO) { | |
c4223c2c | 491 | DBG("RX Overrun [%d + %d]\n", host->pdev->id, |
ba264b34 PP |
492 | host->pio.len, count); |
493 | break; | |
494 | } | |
495 | else if (status & SD_STATUS_RU) { | |
c4223c2c | 496 | DBG("RX Underrun [%d + %d]\n", host->pdev->id, |
ba264b34 PP |
497 | host->pio.len, count); |
498 | break; | |
499 | } | |
500 | ||
2f73bfbe | 501 | val = __raw_readl(HOST_RXPORT(host)); |
ba264b34 PP |
502 | |
503 | if (sg_ptr) | |
5c0a889d | 504 | *sg_ptr++ = (unsigned char)(val & 0xFF); |
ba264b34 PP |
505 | } |
506 | ||
507 | host->pio.len -= count; | |
508 | host->pio.offset += count; | |
509 | ||
510 | if (sg_len && count == sg_len) { | |
511 | host->pio.index++; | |
512 | host->pio.offset = 0; | |
513 | } | |
514 | ||
515 | if (host->pio.len == 0) { | |
5c0a889d | 516 | /* IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF); */ |
ba264b34 PP |
517 | IRQ_OFF(host, SD_CONFIG_NE); |
518 | ||
519 | if (host->flags & HOST_F_STOP) | |
520 | SEND_STOP(host); | |
521 | ||
522 | tasklet_schedule(&host->data_task); | |
523 | } | |
524 | } | |
525 | ||
5c0a889d ML |
526 | /* This is called when a command has been completed - grab the response |
527 | * and check for errors. Then start the data transfer if it is indicated. | |
528 | */ | |
ba264b34 PP |
529 | static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) |
530 | { | |
ba264b34 PP |
531 | struct mmc_request *mrq = host->mrq; |
532 | struct mmc_command *cmd; | |
5c0a889d ML |
533 | u32 r[4]; |
534 | int i, trans; | |
ba264b34 PP |
535 | |
536 | if (!host->mrq) | |
537 | return; | |
538 | ||
539 | cmd = mrq->cmd; | |
17b0429d | 540 | cmd->error = 0; |
ba264b34 | 541 | |
e9225176 RK |
542 | if (cmd->flags & MMC_RSP_PRESENT) { |
543 | if (cmd->flags & MMC_RSP_136) { | |
2f73bfbe ML |
544 | r[0] = __raw_readl(host->iobase + SD_RESP3); |
545 | r[1] = __raw_readl(host->iobase + SD_RESP2); | |
546 | r[2] = __raw_readl(host->iobase + SD_RESP1); | |
547 | r[3] = __raw_readl(host->iobase + SD_RESP0); | |
e9225176 RK |
548 | |
549 | /* The CRC is omitted from the response, so really | |
550 | * we only got 120 bytes, but the engine expects | |
5c0a889d | 551 | * 128 bits, so we have to shift things up. |
e9225176 | 552 | */ |
5c0a889d | 553 | for (i = 0; i < 4; i++) { |
e9225176 RK |
554 | cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8; |
555 | if (i != 3) | |
556 | cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24; | |
557 | } | |
558 | } else { | |
559 | /* Techincally, we should be getting all 48 bits of | |
560 | * the response (SD_RESP1 + SD_RESP2), but because | |
561 | * our response omits the CRC, our data ends up | |
562 | * being shifted 8 bits to the right. In this case, | |
563 | * that means that the OSR data starts at bit 31, | |
5c0a889d | 564 | * so we can just read RESP0 and return that. |
e9225176 | 565 | */ |
2f73bfbe | 566 | cmd->resp[0] = __raw_readl(host->iobase + SD_RESP0); |
ba264b34 PP |
567 | } |
568 | } | |
569 | ||
570 | /* Figure out errors */ | |
ba264b34 | 571 | if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC)) |
17b0429d | 572 | cmd->error = -EILSEQ; |
ba264b34 PP |
573 | |
574 | trans = host->flags & (HOST_F_XMIT | HOST_F_RECV); | |
575 | ||
17b0429d | 576 | if (!trans || cmd->error) { |
5c0a889d | 577 | IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); |
ba264b34 PP |
578 | tasklet_schedule(&host->finish_task); |
579 | return; | |
580 | } | |
581 | ||
582 | host->status = HOST_S_DATA; | |
583 | ||
1177d99d | 584 | if ((host->flags & (HOST_F_DMA | HOST_F_DBDMA))) { |
ba264b34 PP |
585 | u32 channel = DMA_CHANNEL(host); |
586 | ||
1177d99d | 587 | /* Start the DBDMA as soon as the buffer gets something in it */ |
ba264b34 PP |
588 | |
589 | if (host->flags & HOST_F_RECV) { | |
590 | u32 mask = SD_STATUS_DB | SD_STATUS_NE; | |
591 | ||
592 | while((status & mask) != mask) | |
2f73bfbe | 593 | status = __raw_readl(HOST_STATUS(host)); |
ba264b34 PP |
594 | } |
595 | ||
596 | au1xxx_dbdma_start(channel); | |
597 | } | |
598 | } | |
599 | ||
600 | static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate) | |
601 | { | |
b6507596 ML |
602 | unsigned int pbus = clk_get_rate(host->clk); |
603 | unsigned int divisor = ((pbus / rate) / 2) - 1; | |
ba264b34 PP |
604 | u32 config; |
605 | ||
2f73bfbe | 606 | config = __raw_readl(HOST_CONFIG(host)); |
ba264b34 PP |
607 | |
608 | config &= ~(SD_CONFIG_DIV); | |
609 | config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE; | |
610 | ||
2f73bfbe ML |
611 | __raw_writel(config, HOST_CONFIG(host)); |
612 | wmb(); /* drain writebuffer */ | |
ba264b34 PP |
613 | } |
614 | ||
5c0a889d ML |
615 | static int au1xmmc_prepare_data(struct au1xmmc_host *host, |
616 | struct mmc_data *data) | |
ba264b34 | 617 | { |
2c171bf1 | 618 | int datalen = data->blocks * data->blksz; |
ba264b34 | 619 | |
ba264b34 PP |
620 | if (data->flags & MMC_DATA_READ) |
621 | host->flags |= HOST_F_RECV; | |
622 | else | |
623 | host->flags |= HOST_F_XMIT; | |
624 | ||
625 | if (host->mrq->stop) | |
626 | host->flags |= HOST_F_STOP; | |
627 | ||
628 | host->dma.dir = DMA_BIDIRECTIONAL; | |
629 | ||
630 | host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg, | |
631 | data->sg_len, host->dma.dir); | |
632 | ||
633 | if (host->dma.len == 0) | |
17b0429d | 634 | return -ETIMEDOUT; |
ba264b34 | 635 | |
2f73bfbe | 636 | __raw_writel(data->blksz - 1, HOST_BLKSIZE(host)); |
ba264b34 | 637 | |
1177d99d | 638 | if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) { |
ba264b34 PP |
639 | int i; |
640 | u32 channel = DMA_CHANNEL(host); | |
641 | ||
642 | au1xxx_dbdma_stop(channel); | |
643 | ||
5c0a889d | 644 | for (i = 0; i < host->dma.len; i++) { |
ba264b34 PP |
645 | u32 ret = 0, flags = DDMA_FLAGS_NOIE; |
646 | struct scatterlist *sg = &data->sg[i]; | |
647 | int sg_len = sg->length; | |
648 | ||
649 | int len = (datalen > sg_len) ? sg_len : datalen; | |
650 | ||
651 | if (i == host->dma.len - 1) | |
652 | flags = DDMA_FLAGS_IE; | |
653 | ||
5c0a889d | 654 | if (host->flags & HOST_F_XMIT) { |
ea071cc7 | 655 | ret = au1xxx_dbdma_put_source(channel, |
963accbc | 656 | sg_phys(sg), len, flags); |
5c0a889d | 657 | } else { |
ea071cc7 | 658 | ret = au1xxx_dbdma_put_dest(channel, |
963accbc | 659 | sg_phys(sg), len, flags); |
ba264b34 PP |
660 | } |
661 | ||
c4223c2c | 662 | if (!ret) |
ba264b34 PP |
663 | goto dataerr; |
664 | ||
665 | datalen -= len; | |
666 | } | |
5c0a889d | 667 | } else { |
ba264b34 PP |
668 | host->pio.index = 0; |
669 | host->pio.offset = 0; | |
670 | host->pio.len = datalen; | |
671 | ||
672 | if (host->flags & HOST_F_XMIT) | |
673 | IRQ_ON(host, SD_CONFIG_TH); | |
674 | else | |
675 | IRQ_ON(host, SD_CONFIG_NE); | |
5c0a889d | 676 | /* IRQ_ON(host, SD_CONFIG_RA | SD_CONFIG_RF); */ |
ba264b34 PP |
677 | } |
678 | ||
17b0429d | 679 | return 0; |
ba264b34 | 680 | |
c4223c2c ML |
681 | dataerr: |
682 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, | |
683 | host->dma.dir); | |
17b0429d | 684 | return -ETIMEDOUT; |
ba264b34 PP |
685 | } |
686 | ||
5c0a889d | 687 | /* This actually starts a command or data transaction */ |
ba264b34 PP |
688 | static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq) |
689 | { | |
ba264b34 | 690 | struct au1xmmc_host *host = mmc_priv(mmc); |
17b0429d | 691 | int ret = 0; |
ba264b34 PP |
692 | |
693 | WARN_ON(irqs_disabled()); | |
694 | WARN_ON(host->status != HOST_S_IDLE); | |
695 | ||
696 | host->mrq = mrq; | |
697 | host->status = HOST_S_CMD; | |
698 | ||
88b8d9a8 | 699 | /* fail request immediately if no card is present */ |
e2d26477 | 700 | if (0 == au1xmmc_card_inserted(mmc)) { |
88b8d9a8 ML |
701 | mrq->cmd->error = -ENOMEDIUM; |
702 | au1xmmc_finish_request(host); | |
703 | return; | |
704 | } | |
705 | ||
ba264b34 PP |
706 | if (mrq->data) { |
707 | FLUSH_FIFO(host); | |
708 | ret = au1xmmc_prepare_data(host, mrq->data); | |
709 | } | |
710 | ||
17b0429d | 711 | if (!ret) |
be0192aa | 712 | ret = au1xmmc_send_command(host, 0, mrq->cmd, mrq->data); |
ba264b34 | 713 | |
17b0429d | 714 | if (ret) { |
ba264b34 PP |
715 | mrq->cmd->error = ret; |
716 | au1xmmc_finish_request(host); | |
717 | } | |
718 | } | |
719 | ||
720 | static void au1xmmc_reset_controller(struct au1xmmc_host *host) | |
721 | { | |
ba264b34 | 722 | /* Apply the clock */ |
2f73bfbe ML |
723 | __raw_writel(SD_ENABLE_CE, HOST_ENABLE(host)); |
724 | wmb(); /* drain writebuffer */ | |
725 | mdelay(1); | |
ba264b34 | 726 | |
2f73bfbe ML |
727 | __raw_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host)); |
728 | wmb(); /* drain writebuffer */ | |
729 | mdelay(5); | |
ba264b34 | 730 | |
2f73bfbe ML |
731 | __raw_writel(~0, HOST_STATUS(host)); |
732 | wmb(); /* drain writebuffer */ | |
ba264b34 | 733 | |
2f73bfbe ML |
734 | __raw_writel(0, HOST_BLKSIZE(host)); |
735 | __raw_writel(0x001fffff, HOST_TIMEOUT(host)); | |
736 | wmb(); /* drain writebuffer */ | |
ba264b34 | 737 | |
2f73bfbe ML |
738 | __raw_writel(SD_CONFIG2_EN, HOST_CONFIG2(host)); |
739 | wmb(); /* drain writebuffer */ | |
ba264b34 | 740 | |
2f73bfbe ML |
741 | __raw_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host)); |
742 | wmb(); /* drain writebuffer */ | |
743 | mdelay(1); | |
ba264b34 | 744 | |
2f73bfbe ML |
745 | __raw_writel(SD_CONFIG2_EN, HOST_CONFIG2(host)); |
746 | wmb(); /* drain writebuffer */ | |
ba264b34 PP |
747 | |
748 | /* Configure interrupts */ | |
2f73bfbe ML |
749 | __raw_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host)); |
750 | wmb(); /* drain writebuffer */ | |
ba264b34 PP |
751 | } |
752 | ||
753 | ||
5c0a889d | 754 | static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
ba264b34 PP |
755 | { |
756 | struct au1xmmc_host *host = mmc_priv(mmc); | |
281dd23e | 757 | u32 config2; |
ba264b34 | 758 | |
ba264b34 PP |
759 | if (ios->power_mode == MMC_POWER_OFF) |
760 | au1xmmc_set_power(host, 0); | |
761 | else if (ios->power_mode == MMC_POWER_ON) { | |
762 | au1xmmc_set_power(host, 1); | |
763 | } | |
764 | ||
765 | if (ios->clock && ios->clock != host->clock) { | |
766 | au1xmmc_set_clock(host, ios->clock); | |
767 | host->clock = ios->clock; | |
768 | } | |
281dd23e | 769 | |
2f73bfbe | 770 | config2 = __raw_readl(HOST_CONFIG2(host)); |
281dd23e | 771 | switch (ios->bus_width) { |
809f36c6 ML |
772 | case MMC_BUS_WIDTH_8: |
773 | config2 |= SD_CONFIG2_BB; | |
774 | break; | |
281dd23e | 775 | case MMC_BUS_WIDTH_4: |
809f36c6 | 776 | config2 &= ~SD_CONFIG2_BB; |
281dd23e ML |
777 | config2 |= SD_CONFIG2_WB; |
778 | break; | |
779 | case MMC_BUS_WIDTH_1: | |
809f36c6 | 780 | config2 &= ~(SD_CONFIG2_WB | SD_CONFIG2_BB); |
281dd23e ML |
781 | break; |
782 | } | |
2f73bfbe ML |
783 | __raw_writel(config2, HOST_CONFIG2(host)); |
784 | wmb(); /* drain writebuffer */ | |
ba264b34 PP |
785 | } |
786 | ||
ba264b34 PP |
787 | #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT) |
788 | #define STATUS_DATA_IN (SD_STATUS_NE) | |
789 | #define STATUS_DATA_OUT (SD_STATUS_TH) | |
790 | ||
7d12e780 | 791 | static irqreturn_t au1xmmc_irq(int irq, void *dev_id) |
ba264b34 | 792 | { |
c4223c2c | 793 | struct au1xmmc_host *host = dev_id; |
ba264b34 | 794 | u32 status; |
ba264b34 | 795 | |
2f73bfbe | 796 | status = __raw_readl(HOST_STATUS(host)); |
ba264b34 | 797 | |
c4223c2c ML |
798 | if (!(status & SD_STATUS_I)) |
799 | return IRQ_NONE; /* not ours */ | |
ba264b34 | 800 | |
20f522ff ML |
801 | if (status & SD_STATUS_SI) /* SDIO */ |
802 | mmc_signal_sdio_irq(host->mmc); | |
803 | ||
c4223c2c ML |
804 | if (host->mrq && (status & STATUS_TIMEOUT)) { |
805 | if (status & SD_STATUS_RAT) | |
806 | host->mrq->cmd->error = -ETIMEDOUT; | |
807 | else if (status & SD_STATUS_DT) | |
808 | host->mrq->data->error = -ETIMEDOUT; | |
ba264b34 | 809 | |
c4223c2c ML |
810 | /* In PIO mode, interrupts might still be enabled */ |
811 | IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH); | |
ba264b34 | 812 | |
c4223c2c ML |
813 | /* IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); */ |
814 | tasklet_schedule(&host->finish_task); | |
815 | } | |
ba264b34 | 816 | #if 0 |
c4223c2c ML |
817 | else if (status & SD_STATUS_DD) { |
818 | /* Sometimes we get a DD before a NE in PIO mode */ | |
819 | if (!(host->flags & HOST_F_DMA) && (status & SD_STATUS_NE)) | |
820 | au1xmmc_receive_pio(host); | |
821 | else { | |
822 | au1xmmc_data_complete(host, status); | |
823 | /* tasklet_schedule(&host->data_task); */ | |
ba264b34 | 824 | } |
ba264b34 | 825 | } |
c4223c2c ML |
826 | #endif |
827 | else if (status & SD_STATUS_CR) { | |
828 | if (host->status == HOST_S_CMD) | |
829 | au1xmmc_cmd_complete(host, status); | |
830 | ||
831 | } else if (!(host->flags & HOST_F_DMA)) { | |
832 | if ((host->flags & HOST_F_XMIT) && (status & STATUS_DATA_OUT)) | |
833 | au1xmmc_send_pio(host); | |
834 | else if ((host->flags & HOST_F_RECV) && (status & STATUS_DATA_IN)) | |
835 | au1xmmc_receive_pio(host); | |
836 | ||
837 | } else if (status & 0x203F3C70) { | |
838 | DBG("Unhandled status %8.8x\n", host->pdev->id, | |
839 | status); | |
ba264b34 PP |
840 | } |
841 | ||
2f73bfbe ML |
842 | __raw_writel(status, HOST_STATUS(host)); |
843 | wmb(); /* drain writebuffer */ | |
ba264b34 | 844 | |
c4223c2c | 845 | return IRQ_HANDLED; |
ba264b34 PP |
846 | } |
847 | ||
c4223c2c ML |
848 | /* 8bit memory DMA device */ |
849 | static dbdev_tab_t au1xmmc_mem_dbdev = { | |
850 | .dev_id = DSCR_CMD0_ALWAYS, | |
851 | .dev_flags = DEV_FLAGS_ANYUSE, | |
852 | .dev_tsize = 0, | |
853 | .dev_devwidth = 8, | |
854 | .dev_physaddr = 0x00000000, | |
855 | .dev_intlevel = 0, | |
856 | .dev_intpolarity = 0, | |
ba264b34 | 857 | }; |
c4223c2c | 858 | static int memid; |
ba264b34 | 859 | |
c4223c2c | 860 | static void au1xmmc_dbdma_callback(int irq, void *dev_id) |
ba264b34 | 861 | { |
c4223c2c | 862 | struct au1xmmc_host *host = (struct au1xmmc_host *)dev_id; |
ba264b34 | 863 | |
c4223c2c ML |
864 | /* Avoid spurious interrupts */ |
865 | if (!host->mrq) | |
866 | return; | |
ba264b34 | 867 | |
c4223c2c ML |
868 | if (host->flags & HOST_F_STOP) |
869 | SEND_STOP(host); | |
ba264b34 | 870 | |
c4223c2c ML |
871 | tasklet_schedule(&host->data_task); |
872 | } | |
ba264b34 | 873 | |
c4223c2c ML |
874 | static int au1xmmc_dbdma_init(struct au1xmmc_host *host) |
875 | { | |
876 | struct resource *res; | |
877 | int txid, rxid; | |
878 | ||
879 | res = platform_get_resource(host->pdev, IORESOURCE_DMA, 0); | |
880 | if (!res) | |
881 | return -ENODEV; | |
882 | txid = res->start; | |
883 | ||
884 | res = platform_get_resource(host->pdev, IORESOURCE_DMA, 1); | |
885 | if (!res) | |
886 | return -ENODEV; | |
887 | rxid = res->start; | |
888 | ||
889 | if (!memid) | |
890 | return -ENODEV; | |
891 | ||
892 | host->tx_chan = au1xxx_dbdma_chan_alloc(memid, txid, | |
893 | au1xmmc_dbdma_callback, (void *)host); | |
894 | if (!host->tx_chan) { | |
895 | dev_err(&host->pdev->dev, "cannot allocate TX DMA\n"); | |
896 | return -ENODEV; | |
897 | } | |
898 | ||
899 | host->rx_chan = au1xxx_dbdma_chan_alloc(rxid, memid, | |
900 | au1xmmc_dbdma_callback, (void *)host); | |
901 | if (!host->rx_chan) { | |
902 | dev_err(&host->pdev->dev, "cannot allocate RX DMA\n"); | |
903 | au1xxx_dbdma_chan_free(host->tx_chan); | |
904 | return -ENODEV; | |
905 | } | |
ba264b34 | 906 | |
c4223c2c ML |
907 | au1xxx_dbdma_set_devwidth(host->tx_chan, 8); |
908 | au1xxx_dbdma_set_devwidth(host->rx_chan, 8); | |
ba264b34 | 909 | |
c4223c2c ML |
910 | au1xxx_dbdma_ring_alloc(host->tx_chan, AU1XMMC_DESCRIPTOR_COUNT); |
911 | au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT); | |
ba264b34 | 912 | |
c4223c2c | 913 | /* DBDMA is good to go */ |
1177d99d | 914 | host->flags |= HOST_F_DMA | HOST_F_DBDMA; |
ba264b34 | 915 | |
c4223c2c ML |
916 | return 0; |
917 | } | |
ba264b34 | 918 | |
c4223c2c ML |
919 | static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host) |
920 | { | |
921 | if (host->flags & HOST_F_DMA) { | |
922 | host->flags &= ~HOST_F_DMA; | |
923 | au1xxx_dbdma_chan_free(host->tx_chan); | |
924 | au1xxx_dbdma_chan_free(host->rx_chan); | |
925 | } | |
ba264b34 PP |
926 | } |
927 | ||
20f522ff ML |
928 | static void au1xmmc_enable_sdio_irq(struct mmc_host *mmc, int en) |
929 | { | |
930 | struct au1xmmc_host *host = mmc_priv(mmc); | |
931 | ||
932 | if (en) | |
933 | IRQ_ON(host, SD_CONFIG_SI); | |
934 | else | |
935 | IRQ_OFF(host, SD_CONFIG_SI); | |
936 | } | |
937 | ||
bf8c80a6 | 938 | static const struct mmc_host_ops au1xmmc_ops = { |
ba264b34 PP |
939 | .request = au1xmmc_request, |
940 | .set_ios = au1xmmc_set_ios, | |
82999770 | 941 | .get_ro = au1xmmc_card_readonly, |
e2d26477 | 942 | .get_cd = au1xmmc_card_inserted, |
20f522ff | 943 | .enable_sdio_irq = au1xmmc_enable_sdio_irq, |
ba264b34 PP |
944 | }; |
945 | ||
c3be1efd | 946 | static int au1xmmc_probe(struct platform_device *pdev) |
c4223c2c ML |
947 | { |
948 | struct mmc_host *mmc; | |
949 | struct au1xmmc_host *host; | |
950 | struct resource *r; | |
809f36c6 | 951 | int ret, iflag; |
c4223c2c ML |
952 | |
953 | mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev); | |
954 | if (!mmc) { | |
955 | dev_err(&pdev->dev, "no memory for mmc_host\n"); | |
956 | ret = -ENOMEM; | |
957 | goto out0; | |
ba264b34 PP |
958 | } |
959 | ||
c4223c2c ML |
960 | host = mmc_priv(mmc); |
961 | host->mmc = mmc; | |
962 | host->platdata = pdev->dev.platform_data; | |
963 | host->pdev = pdev; | |
ba264b34 | 964 | |
c4223c2c ML |
965 | ret = -ENODEV; |
966 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
967 | if (!r) { | |
968 | dev_err(&pdev->dev, "no mmio defined\n"); | |
969 | goto out1; | |
970 | } | |
ba264b34 | 971 | |
7a5ea56a | 972 | host->ioarea = request_mem_region(r->start, resource_size(r), |
c4223c2c ML |
973 | pdev->name); |
974 | if (!host->ioarea) { | |
975 | dev_err(&pdev->dev, "mmio already in use\n"); | |
976 | goto out1; | |
977 | } | |
ba264b34 | 978 | |
2f73bfbe | 979 | host->iobase = ioremap(r->start, 0x3c); |
c4223c2c ML |
980 | if (!host->iobase) { |
981 | dev_err(&pdev->dev, "cannot remap mmio\n"); | |
982 | goto out2; | |
983 | } | |
984 | ||
985 | r = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
986 | if (!r) { | |
987 | dev_err(&pdev->dev, "no IRQ defined\n"); | |
988 | goto out3; | |
989 | } | |
c4223c2c | 990 | host->irq = r->start; |
ba264b34 | 991 | |
c4223c2c | 992 | mmc->ops = &au1xmmc_ops; |
ba264b34 | 993 | |
c4223c2c ML |
994 | mmc->f_min = 450000; |
995 | mmc->f_max = 24000000; | |
fe4a3c7a | 996 | |
809f36c6 ML |
997 | mmc->max_blk_size = 2048; |
998 | mmc->max_blk_count = 512; | |
999 | ||
1000 | mmc->ocr_avail = AU1XMMC_OCR; | |
1001 | mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; | |
1002 | mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT; | |
1003 | ||
1004 | iflag = IRQF_SHARED; /* Au1100/Au1200: one int for both ctrls */ | |
1005 | ||
1177d99d ML |
1006 | switch (alchemy_get_cputype()) { |
1007 | case ALCHEMY_CPU_AU1100: | |
1008 | mmc->max_seg_size = AU1100_MMC_DESCRIPTOR_SIZE; | |
1177d99d ML |
1009 | break; |
1010 | case ALCHEMY_CPU_AU1200: | |
1011 | mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE; | |
809f36c6 ML |
1012 | break; |
1013 | case ALCHEMY_CPU_AU1300: | |
1014 | iflag = 0; /* nothing is shared */ | |
1015 | mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE; | |
1016 | mmc->f_max = 52000000; | |
1017 | if (host->ioarea->start == AU1100_SD0_PHYS_ADDR) | |
1018 | mmc->caps |= MMC_CAP_8_BIT_DATA; | |
1177d99d ML |
1019 | break; |
1020 | } | |
ba264b34 | 1021 | |
809f36c6 ML |
1022 | ret = request_irq(host->irq, au1xmmc_irq, iflag, DRIVER_NAME, host); |
1023 | if (ret) { | |
1024 | dev_err(&pdev->dev, "cannot grab IRQ\n"); | |
1025 | goto out3; | |
1026 | } | |
ba264b34 | 1027 | |
b6507596 ML |
1028 | host->clk = clk_get(&pdev->dev, ALCHEMY_PERIPH_CLK); |
1029 | if (IS_ERR(host->clk)) { | |
1030 | dev_err(&pdev->dev, "cannot find clock\n"); | |
ee9d19d4 | 1031 | ret = PTR_ERR(host->clk); |
b6507596 ML |
1032 | goto out_irq; |
1033 | } | |
ee9d19d4 WY |
1034 | |
1035 | ret = clk_prepare_enable(host->clk); | |
1036 | if (ret) { | |
b6507596 ML |
1037 | dev_err(&pdev->dev, "cannot enable clock\n"); |
1038 | goto out_clk; | |
1039 | } | |
1040 | ||
c4223c2c | 1041 | host->status = HOST_S_IDLE; |
ba264b34 | 1042 | |
c4223c2c ML |
1043 | /* board-specific carddetect setup, if any */ |
1044 | if (host->platdata && host->platdata->cd_setup) { | |
1045 | ret = host->platdata->cd_setup(mmc, 1); | |
1046 | if (ret) { | |
e2d26477 ML |
1047 | dev_warn(&pdev->dev, "board CD setup failed\n"); |
1048 | mmc->caps |= MMC_CAP_NEEDS_POLL; | |
c4223c2c | 1049 | } |
e2d26477 ML |
1050 | } else |
1051 | mmc->caps |= MMC_CAP_NEEDS_POLL; | |
ba264b34 | 1052 | |
3b839070 ML |
1053 | /* platform may not be able to use all advertised caps */ |
1054 | if (host->platdata) | |
1055 | mmc->caps &= ~(host->platdata->mask_host_caps); | |
1056 | ||
c4223c2c ML |
1057 | tasklet_init(&host->data_task, au1xmmc_tasklet_data, |
1058 | (unsigned long)host); | |
ba264b34 | 1059 | |
c4223c2c ML |
1060 | tasklet_init(&host->finish_task, au1xmmc_tasklet_finish, |
1061 | (unsigned long)host); | |
ba264b34 | 1062 | |
1177d99d ML |
1063 | if (has_dbdma()) { |
1064 | ret = au1xmmc_dbdma_init(host); | |
1065 | if (ret) | |
d6748066 | 1066 | pr_info(DRIVER_NAME ": DBDMA init failed; using PIO\n"); |
1177d99d | 1067 | } |
ba264b34 | 1068 | |
c4223c2c ML |
1069 | #ifdef CONFIG_LEDS_CLASS |
1070 | if (host->platdata && host->platdata->led) { | |
1071 | struct led_classdev *led = host->platdata->led; | |
1072 | led->name = mmc_hostname(mmc); | |
1073 | led->brightness = LED_OFF; | |
1074 | led->default_trigger = mmc_hostname(mmc); | |
1075 | ret = led_classdev_register(mmc_dev(mmc), led); | |
1076 | if (ret) | |
1077 | goto out5; | |
1078 | } | |
1079 | #endif | |
ba264b34 | 1080 | |
c4223c2c | 1081 | au1xmmc_reset_controller(host); |
ba264b34 | 1082 | |
c4223c2c ML |
1083 | ret = mmc_add_host(mmc); |
1084 | if (ret) { | |
1085 | dev_err(&pdev->dev, "cannot add mmc host\n"); | |
1086 | goto out6; | |
1087 | } | |
ba264b34 | 1088 | |
dd8572af | 1089 | platform_set_drvdata(pdev, host); |
ba264b34 | 1090 | |
2f73bfbe | 1091 | pr_info(DRIVER_NAME ": MMC Controller %d set up at %p" |
c4223c2c ML |
1092 | " (mode=%s)\n", pdev->id, host->iobase, |
1093 | host->flags & HOST_F_DMA ? "dma" : "pio"); | |
ba264b34 | 1094 | |
c4223c2c | 1095 | return 0; /* all ok */ |
ba264b34 | 1096 | |
c4223c2c ML |
1097 | out6: |
1098 | #ifdef CONFIG_LEDS_CLASS | |
1099 | if (host->platdata && host->platdata->led) | |
1100 | led_classdev_unregister(host->platdata->led); | |
1101 | out5: | |
1102 | #endif | |
2f73bfbe ML |
1103 | __raw_writel(0, HOST_ENABLE(host)); |
1104 | __raw_writel(0, HOST_CONFIG(host)); | |
1105 | __raw_writel(0, HOST_CONFIG2(host)); | |
1106 | wmb(); /* drain writebuffer */ | |
c4223c2c | 1107 | |
1177d99d ML |
1108 | if (host->flags & HOST_F_DBDMA) |
1109 | au1xmmc_dbdma_shutdown(host); | |
c4223c2c ML |
1110 | |
1111 | tasklet_kill(&host->data_task); | |
1112 | tasklet_kill(&host->finish_task); | |
1113 | ||
e2d26477 ML |
1114 | if (host->platdata && host->platdata->cd_setup && |
1115 | !(mmc->caps & MMC_CAP_NEEDS_POLL)) | |
c4223c2c | 1116 | host->platdata->cd_setup(mmc, 0); |
b6507596 ML |
1117 | out_clk: |
1118 | clk_disable_unprepare(host->clk); | |
1119 | clk_put(host->clk); | |
1120 | out_irq: | |
c4223c2c ML |
1121 | free_irq(host->irq, host); |
1122 | out3: | |
1123 | iounmap((void *)host->iobase); | |
1124 | out2: | |
1125 | release_resource(host->ioarea); | |
1126 | kfree(host->ioarea); | |
1127 | out1: | |
1128 | mmc_free_host(mmc); | |
1129 | out0: | |
1130 | return ret; | |
ba264b34 PP |
1131 | } |
1132 | ||
6e0ee714 | 1133 | static int au1xmmc_remove(struct platform_device *pdev) |
ba264b34 | 1134 | { |
dd8572af | 1135 | struct au1xmmc_host *host = platform_get_drvdata(pdev); |
c4223c2c | 1136 | |
dd8572af ML |
1137 | if (host) { |
1138 | mmc_remove_host(host->mmc); | |
ba264b34 | 1139 | |
c4223c2c ML |
1140 | #ifdef CONFIG_LEDS_CLASS |
1141 | if (host->platdata && host->platdata->led) | |
1142 | led_classdev_unregister(host->platdata->led); | |
1143 | #endif | |
ba264b34 | 1144 | |
e2d26477 | 1145 | if (host->platdata && host->platdata->cd_setup && |
dd8572af ML |
1146 | !(host->mmc->caps & MMC_CAP_NEEDS_POLL)) |
1147 | host->platdata->cd_setup(host->mmc, 0); | |
ba264b34 | 1148 | |
2f73bfbe ML |
1149 | __raw_writel(0, HOST_ENABLE(host)); |
1150 | __raw_writel(0, HOST_CONFIG(host)); | |
1151 | __raw_writel(0, HOST_CONFIG2(host)); | |
1152 | wmb(); /* drain writebuffer */ | |
ba264b34 PP |
1153 | |
1154 | tasklet_kill(&host->data_task); | |
1155 | tasklet_kill(&host->finish_task); | |
1156 | ||
1177d99d ML |
1157 | if (host->flags & HOST_F_DBDMA) |
1158 | au1xmmc_dbdma_shutdown(host); | |
1159 | ||
ba264b34 PP |
1160 | au1xmmc_set_power(host, 0); |
1161 | ||
b6507596 ML |
1162 | clk_disable_unprepare(host->clk); |
1163 | clk_put(host->clk); | |
1164 | ||
c4223c2c ML |
1165 | free_irq(host->irq, host); |
1166 | iounmap((void *)host->iobase); | |
1167 | release_resource(host->ioarea); | |
1168 | kfree(host->ioarea); | |
ba264b34 | 1169 | |
dd8572af | 1170 | mmc_free_host(host->mmc); |
ba264b34 | 1171 | } |
ba264b34 PP |
1172 | return 0; |
1173 | } | |
1174 | ||
dd8572af ML |
1175 | #ifdef CONFIG_PM |
1176 | static int au1xmmc_suspend(struct platform_device *pdev, pm_message_t state) | |
1177 | { | |
1178 | struct au1xmmc_host *host = platform_get_drvdata(pdev); | |
dd8572af | 1179 | |
2f73bfbe ML |
1180 | __raw_writel(0, HOST_CONFIG2(host)); |
1181 | __raw_writel(0, HOST_CONFIG(host)); | |
1182 | __raw_writel(0xffffffff, HOST_STATUS(host)); | |
1183 | __raw_writel(0, HOST_ENABLE(host)); | |
1184 | wmb(); /* drain writebuffer */ | |
dd8572af ML |
1185 | |
1186 | return 0; | |
1187 | } | |
1188 | ||
1189 | static int au1xmmc_resume(struct platform_device *pdev) | |
1190 | { | |
1191 | struct au1xmmc_host *host = platform_get_drvdata(pdev); | |
1192 | ||
1193 | au1xmmc_reset_controller(host); | |
1194 | ||
1e63d485 | 1195 | return 0; |
dd8572af ML |
1196 | } |
1197 | #else | |
1198 | #define au1xmmc_suspend NULL | |
1199 | #define au1xmmc_resume NULL | |
1200 | #endif | |
1201 | ||
b256f9df | 1202 | static struct platform_driver au1xmmc_driver = { |
ba264b34 PP |
1203 | .probe = au1xmmc_probe, |
1204 | .remove = au1xmmc_remove, | |
dd8572af ML |
1205 | .suspend = au1xmmc_suspend, |
1206 | .resume = au1xmmc_resume, | |
b256f9df MM |
1207 | .driver = { |
1208 | .name = DRIVER_NAME, | |
1209 | }, | |
ba264b34 PP |
1210 | }; |
1211 | ||
1212 | static int __init au1xmmc_init(void) | |
1213 | { | |
1177d99d ML |
1214 | if (has_dbdma()) { |
1215 | /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride | |
1216 | * of 8 bits. And since devices are shared, we need to create | |
1217 | * our own to avoid freaking out other devices. | |
1218 | */ | |
1219 | memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev); | |
1220 | if (!memid) | |
d6748066 | 1221 | pr_err("au1xmmc: cannot add memory dbdma\n"); |
1177d99d | 1222 | } |
b256f9df | 1223 | return platform_driver_register(&au1xmmc_driver); |
ba264b34 PP |
1224 | } |
1225 | ||
1226 | static void __exit au1xmmc_exit(void) | |
1227 | { | |
1177d99d | 1228 | if (has_dbdma() && memid) |
c4223c2c | 1229 | au1xxx_ddma_del_device(memid); |
1177d99d | 1230 | |
b256f9df | 1231 | platform_driver_unregister(&au1xmmc_driver); |
ba264b34 PP |
1232 | } |
1233 | ||
1234 | module_init(au1xmmc_init); | |
1235 | module_exit(au1xmmc_exit); | |
1236 | ||
ba264b34 PP |
1237 | MODULE_AUTHOR("Advanced Micro Devices, Inc"); |
1238 | MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX"); | |
1239 | MODULE_LICENSE("GPL"); | |
bc65c724 | 1240 | MODULE_ALIAS("platform:au1xxx-mmc"); |