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4cdc2ec1 | 1 | /* |
2 | * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | */ | |
9 | ||
10 | #include <linux/module.h> | |
11 | #include <linux/platform_device.h> | |
12 | #include <linux/clk.h> | |
13 | #include <linux/mmc/host.h> | |
14 | #include <linux/mmc/dw_mmc.h> | |
15 | #include <linux/of_address.h> | |
cbb79e43 | 16 | #include <linux/slab.h> |
4cdc2ec1 | 17 | |
18 | #include "dw_mmc.h" | |
19 | #include "dw_mmc-pltfm.h" | |
20 | ||
21 | #define RK3288_CLKGEN_DIV 2 | |
22 | ||
cbb79e43 AS |
23 | struct dw_mci_rockchip_priv_data { |
24 | struct clk *drv_clk; | |
25 | struct clk *sample_clk; | |
26 | int default_sample_phase; | |
27 | }; | |
28 | ||
4cdc2ec1 | 29 | static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios) |
30 | { | |
cbb79e43 | 31 | struct dw_mci_rockchip_priv_data *priv = host->priv; |
4cdc2ec1 | 32 | int ret; |
33 | unsigned int cclkin; | |
34 | u32 bus_hz; | |
35 | ||
e7791079 DA |
36 | if (ios->clock == 0) |
37 | return; | |
38 | ||
4cdc2ec1 | 39 | /* |
40 | * cclkin: source clock of mmc controller | |
41 | * bus_hz: card interface clock generated by CLKGEN | |
42 | * bus_hz = cclkin / RK3288_CLKGEN_DIV | |
43 | * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div)) | |
44 | * | |
45 | * Note: div can only be 0 or 1 | |
46 | * if DDR50 8bit mode(only emmc work in 8bit mode), | |
47 | * div must be set 1 | |
48 | */ | |
49 | if (ios->bus_width == MMC_BUS_WIDTH_8 && | |
50 | ios->timing == MMC_TIMING_MMC_DDR52) | |
51 | cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV; | |
52 | else | |
53 | cclkin = ios->clock * RK3288_CLKGEN_DIV; | |
54 | ||
55 | ret = clk_set_rate(host->ciu_clk, cclkin); | |
56 | if (ret) | |
57 | dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock); | |
58 | ||
59 | bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV; | |
60 | if (bus_hz != host->bus_hz) { | |
61 | host->bus_hz = bus_hz; | |
62 | /* force dw_mci_setup_bus() */ | |
63 | host->current_speed = 0; | |
64 | } | |
cbb79e43 AS |
65 | |
66 | /* Make sure we use phases which we can enumerate with */ | |
67 | if (!IS_ERR(priv->sample_clk)) | |
68 | clk_set_phase(priv->sample_clk, priv->default_sample_phase); | |
d4aa908c DA |
69 | |
70 | /* | |
71 | * Set the drive phase offset based on speed mode to achieve hold times. | |
72 | * | |
73 | * NOTE: this is _not_ a value that is dynamically tuned and is also | |
74 | * _not_ a value that will vary from board to board. It is a value | |
75 | * that could vary between different SoC models if they had massively | |
76 | * different output clock delays inside their dw_mmc IP block (delay_o), | |
77 | * but since it's OK to overshoot a little we don't need to do complex | |
78 | * calculations and can pick values that will just work for everyone. | |
79 | * | |
80 | * When picking values we'll stick with picking 0/90/180/270 since | |
81 | * those can be made very accurately on all known Rockchip SoCs. | |
82 | * | |
83 | * Note that these values match values from the DesignWare Databook | |
84 | * tables for the most part except for SDR12 and "ID mode". For those | |
85 | * two modes the databook calculations assume a clock in of 50MHz. As | |
86 | * seen above, we always use a clock in rate that is exactly the | |
87 | * card's input clock (times RK3288_CLKGEN_DIV, but that gets divided | |
88 | * back out before the controller sees it). | |
89 | * | |
90 | * From measurement of a single device, it appears that delay_o is | |
91 | * about .5 ns. Since we try to leave a bit of margin, it's expected | |
92 | * that numbers here will be fine even with much larger delay_o | |
93 | * (the 1.4 ns assumed by the DesignWare Databook would result in the | |
94 | * same results, for instance). | |
95 | */ | |
96 | if (!IS_ERR(priv->drv_clk)) { | |
97 | int phase; | |
98 | ||
99 | /* | |
100 | * In almost all cases a 90 degree phase offset will provide | |
101 | * sufficient hold times across all valid input clock rates | |
102 | * assuming delay_o is not absurd for a given SoC. We'll use | |
103 | * that as a default. | |
104 | */ | |
105 | phase = 90; | |
106 | ||
107 | switch (ios->timing) { | |
108 | case MMC_TIMING_MMC_DDR52: | |
109 | /* | |
110 | * Since clock in rate with MMC_DDR52 is doubled when | |
111 | * bus width is 8 we need to double the phase offset | |
112 | * to get the same timings. | |
113 | */ | |
114 | if (ios->bus_width == MMC_BUS_WIDTH_8) | |
115 | phase = 180; | |
116 | break; | |
117 | case MMC_TIMING_UHS_SDR104: | |
118 | case MMC_TIMING_MMC_HS200: | |
119 | /* | |
120 | * In the case of 150 MHz clock (typical max for | |
121 | * Rockchip SoCs), 90 degree offset will add a delay | |
122 | * of 1.67 ns. That will meet min hold time of .8 ns | |
123 | * as long as clock output delay is < .87 ns. On | |
124 | * SoCs measured this seems to be OK, but it doesn't | |
125 | * hurt to give margin here, so we use 180. | |
126 | */ | |
127 | phase = 180; | |
128 | break; | |
129 | } | |
130 | ||
131 | clk_set_phase(priv->drv_clk, phase); | |
132 | } | |
cbb79e43 AS |
133 | } |
134 | ||
135 | #define NUM_PHASES 360 | |
136 | #define TUNING_ITERATION_TO_PHASE(i) (DIV_ROUND_UP((i) * 360, NUM_PHASES)) | |
137 | ||
9979dbe5 | 138 | static int dw_mci_rk3288_execute_tuning(struct dw_mci_slot *slot, u32 opcode) |
cbb79e43 AS |
139 | { |
140 | struct dw_mci *host = slot->host; | |
141 | struct dw_mci_rockchip_priv_data *priv = host->priv; | |
142 | struct mmc_host *mmc = slot->mmc; | |
143 | int ret = 0; | |
144 | int i; | |
145 | bool v, prev_v = 0, first_v; | |
146 | struct range_t { | |
147 | int start; | |
148 | int end; /* inclusive */ | |
149 | }; | |
150 | struct range_t *ranges; | |
151 | unsigned int range_count = 0; | |
152 | int longest_range_len = -1; | |
153 | int longest_range = -1; | |
154 | int middle_phase; | |
155 | ||
156 | if (IS_ERR(priv->sample_clk)) { | |
157 | dev_err(host->dev, "Tuning clock (sample_clk) not defined.\n"); | |
158 | return -EIO; | |
159 | } | |
160 | ||
161 | ranges = kmalloc_array(NUM_PHASES / 2 + 1, sizeof(*ranges), GFP_KERNEL); | |
162 | if (!ranges) | |
163 | return -ENOMEM; | |
164 | ||
165 | /* Try each phase and extract good ranges */ | |
166 | for (i = 0; i < NUM_PHASES; ) { | |
167 | clk_set_phase(priv->sample_clk, TUNING_ITERATION_TO_PHASE(i)); | |
168 | ||
9979dbe5 | 169 | v = !mmc_send_tuning(mmc, opcode, NULL); |
cbb79e43 AS |
170 | |
171 | if (i == 0) | |
172 | first_v = v; | |
173 | ||
174 | if ((!prev_v) && v) { | |
175 | range_count++; | |
176 | ranges[range_count-1].start = i; | |
177 | } | |
178 | if (v) { | |
179 | ranges[range_count-1].end = i; | |
180 | i++; | |
181 | } else if (i == NUM_PHASES - 1) { | |
182 | /* No extra skipping rules if we're at the end */ | |
183 | i++; | |
184 | } else { | |
185 | /* | |
186 | * No need to check too close to an invalid | |
187 | * one since testing bad phases is slow. Skip | |
188 | * 20 degrees. | |
189 | */ | |
190 | i += DIV_ROUND_UP(20 * NUM_PHASES, 360); | |
191 | ||
192 | /* Always test the last one */ | |
193 | if (i >= NUM_PHASES) | |
194 | i = NUM_PHASES - 1; | |
195 | } | |
196 | ||
197 | prev_v = v; | |
198 | } | |
199 | ||
200 | if (range_count == 0) { | |
201 | dev_warn(host->dev, "All phases bad!"); | |
202 | ret = -EIO; | |
203 | goto free; | |
204 | } | |
205 | ||
206 | /* wrap around case, merge the end points */ | |
207 | if ((range_count > 1) && first_v && v) { | |
208 | ranges[0].start = ranges[range_count-1].start; | |
209 | range_count--; | |
210 | } | |
211 | ||
212 | if (ranges[0].start == 0 && ranges[0].end == NUM_PHASES - 1) { | |
213 | clk_set_phase(priv->sample_clk, priv->default_sample_phase); | |
214 | dev_info(host->dev, "All phases work, using default phase %d.", | |
215 | priv->default_sample_phase); | |
216 | goto free; | |
217 | } | |
218 | ||
219 | /* Find the longest range */ | |
220 | for (i = 0; i < range_count; i++) { | |
221 | int len = (ranges[i].end - ranges[i].start + 1); | |
222 | ||
223 | if (len < 0) | |
224 | len += NUM_PHASES; | |
225 | ||
226 | if (longest_range_len < len) { | |
227 | longest_range_len = len; | |
228 | longest_range = i; | |
229 | } | |
230 | ||
231 | dev_dbg(host->dev, "Good phase range %d-%d (%d len)\n", | |
232 | TUNING_ITERATION_TO_PHASE(ranges[i].start), | |
233 | TUNING_ITERATION_TO_PHASE(ranges[i].end), | |
234 | len | |
235 | ); | |
236 | } | |
237 | ||
238 | dev_dbg(host->dev, "Best phase range %d-%d (%d len)\n", | |
239 | TUNING_ITERATION_TO_PHASE(ranges[longest_range].start), | |
240 | TUNING_ITERATION_TO_PHASE(ranges[longest_range].end), | |
241 | longest_range_len | |
242 | ); | |
243 | ||
244 | middle_phase = ranges[longest_range].start + longest_range_len / 2; | |
245 | middle_phase %= NUM_PHASES; | |
246 | dev_info(host->dev, "Successfully tuned phase to %d\n", | |
247 | TUNING_ITERATION_TO_PHASE(middle_phase)); | |
248 | ||
249 | clk_set_phase(priv->sample_clk, | |
250 | TUNING_ITERATION_TO_PHASE(middle_phase)); | |
251 | ||
252 | free: | |
253 | kfree(ranges); | |
254 | return ret; | |
255 | } | |
256 | ||
257 | static int dw_mci_rk3288_parse_dt(struct dw_mci *host) | |
258 | { | |
259 | struct device_node *np = host->dev->of_node; | |
260 | struct dw_mci_rockchip_priv_data *priv; | |
261 | ||
262 | priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); | |
263 | if (!priv) | |
264 | return -ENOMEM; | |
265 | ||
266 | if (of_property_read_u32(np, "rockchip,default-sample-phase", | |
267 | &priv->default_sample_phase)) | |
268 | priv->default_sample_phase = 0; | |
269 | ||
270 | priv->drv_clk = devm_clk_get(host->dev, "ciu-drive"); | |
271 | if (IS_ERR(priv->drv_clk)) | |
272 | dev_dbg(host->dev, "ciu_drv not available\n"); | |
273 | ||
274 | priv->sample_clk = devm_clk_get(host->dev, "ciu-sample"); | |
275 | if (IS_ERR(priv->sample_clk)) | |
276 | dev_dbg(host->dev, "ciu_sample not available\n"); | |
277 | ||
278 | host->priv = priv; | |
279 | ||
280 | return 0; | |
4cdc2ec1 | 281 | } |
282 | ||
76756234 AK |
283 | static int dw_mci_rockchip_init(struct dw_mci *host) |
284 | { | |
285 | /* It is slot 8 on Rockchip SoCs */ | |
286 | host->sdio_id0 = 8; | |
287 | ||
57e10486 AK |
288 | /* It needs this quirk on all Rockchip SoCs */ |
289 | host->pdata->quirks |= DW_MCI_QUIRK_BROKEN_DTO; | |
290 | ||
19756760 SL |
291 | if (of_device_is_compatible(host->dev->of_node, |
292 | "rockchip,rk3288-dw-mshc")) | |
293 | host->bus_hz /= RK3288_CLKGEN_DIV; | |
294 | ||
76756234 AK |
295 | return 0; |
296 | } | |
297 | ||
c6a9bf99 SL |
298 | /* Common capabilities of RK3288 SoC */ |
299 | static unsigned long dw_mci_rk3288_dwmmc_caps[4] = { | |
d57fe83e SL |
300 | MMC_CAP_ERASE | MMC_CAP_CMD23, |
301 | MMC_CAP_ERASE | MMC_CAP_CMD23, | |
302 | MMC_CAP_ERASE | MMC_CAP_CMD23, | |
303 | MMC_CAP_ERASE | MMC_CAP_CMD23, | |
c6a9bf99 SL |
304 | }; |
305 | ||
4cdc2ec1 | 306 | static const struct dw_mci_drv_data rk2928_drv_data = { |
76756234 | 307 | .init = dw_mci_rockchip_init, |
4cdc2ec1 | 308 | }; |
309 | ||
310 | static const struct dw_mci_drv_data rk3288_drv_data = { | |
c6a9bf99 | 311 | .caps = dw_mci_rk3288_dwmmc_caps, |
4cdc2ec1 | 312 | .set_ios = dw_mci_rk3288_set_ios, |
cbb79e43 AS |
313 | .execute_tuning = dw_mci_rk3288_execute_tuning, |
314 | .parse_dt = dw_mci_rk3288_parse_dt, | |
76756234 | 315 | .init = dw_mci_rockchip_init, |
4cdc2ec1 | 316 | }; |
317 | ||
318 | static const struct of_device_id dw_mci_rockchip_match[] = { | |
319 | { .compatible = "rockchip,rk2928-dw-mshc", | |
320 | .data = &rk2928_drv_data }, | |
321 | { .compatible = "rockchip,rk3288-dw-mshc", | |
322 | .data = &rk3288_drv_data }, | |
323 | {}, | |
324 | }; | |
325 | MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match); | |
326 | ||
327 | static int dw_mci_rockchip_probe(struct platform_device *pdev) | |
328 | { | |
329 | const struct dw_mci_drv_data *drv_data; | |
330 | const struct of_device_id *match; | |
331 | ||
332 | if (!pdev->dev.of_node) | |
333 | return -ENODEV; | |
334 | ||
335 | match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node); | |
336 | drv_data = match->data; | |
337 | ||
338 | return dw_mci_pltfm_register(pdev, drv_data); | |
339 | } | |
340 | ||
4cdc2ec1 | 341 | static struct platform_driver dw_mci_rockchip_pltfm_driver = { |
342 | .probe = dw_mci_rockchip_probe, | |
96083379 | 343 | .remove = dw_mci_pltfm_remove, |
4cdc2ec1 | 344 | .driver = { |
345 | .name = "dwmmc_rockchip", | |
346 | .of_match_table = dw_mci_rockchip_match, | |
31fa8353 | 347 | .pm = &dw_mci_pltfm_pmops, |
4cdc2ec1 | 348 | }, |
349 | }; | |
350 | ||
351 | module_platform_driver(dw_mci_rockchip_pltfm_driver); | |
352 | ||
353 | MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>"); | |
354 | MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension"); | |
a7ca2b16 | 355 | MODULE_ALIAS("platform:dwmmc_rockchip"); |
4cdc2ec1 | 356 | MODULE_LICENSE("GPL v2"); |