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Merge tag 'timer' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[deliverable/linux.git] / drivers / mmc / host / dw_mmc.c
CommitLineData
f95f3850
WN		 1/*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/blkdev.h>
15#include <linux/clk.h>
16#include <linux/debugfs.h>
17#include <linux/device.h>
18#include <linux/dma-mapping.h>
19#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/ioport.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
f95f3850
WN		 25#include <linux/seq_file.h>
26#include <linux/slab.h>
27#include <linux/stat.h>
28#include <linux/delay.h>
29#include <linux/irq.h>
30#include <linux/mmc/host.h>
31#include <linux/mmc/mmc.h>
32#include <linux/mmc/dw_mmc.h>
33#include <linux/bitops.h>
c07946a3 34#include <linux/regulator/consumer.h>
1791b13e 35#include <linux/workqueue.h>
f95f3850
WN		 36
37#include "dw_mmc.h"
38
39/* Common flag combinations */
40#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \
41 SDMMC_INT_HTO | SDMMC_INT_SBE | \
42 SDMMC_INT_EBE)
43#define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
44 SDMMC_INT_RESP_ERR)
45#define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
46 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
47#define DW_MCI_SEND_STATUS 1
48#define DW_MCI_RECV_STATUS 2
49#define DW_MCI_DMA_THRESHOLD 16
50
51#ifdef CONFIG_MMC_DW_IDMAC
52struct idmac_desc {
53 u32 des0; /* Control Descriptor */
54#define IDMAC_DES0_DIC BIT(1)
55#define IDMAC_DES0_LD BIT(2)
56#define IDMAC_DES0_FD BIT(3)
57#define IDMAC_DES0_CH BIT(4)
58#define IDMAC_DES0_ER BIT(5)
59#define IDMAC_DES0_CES BIT(30)
60#define IDMAC_DES0_OWN BIT(31)
61
62 u32 des1; /* Buffer sizes */
63#define IDMAC_SET_BUFFER1_SIZE(d, s) \
9b7bbe10 64 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
f95f3850
WN		 65
66 u32 des2; /* buffer 1 physical address */
67
68 u32 des3; /* buffer 2 physical address */
69};
70#endif /* CONFIG_MMC_DW_IDMAC */
71
72/**
73 * struct dw_mci_slot - MMC slot state
74 * @mmc: The mmc_host representing this slot.
75 * @host: The MMC controller this slot is using.
76 * @ctype: Card type for this slot.
77 * @mrq: mmc_request currently being processed or waiting to be
78 * processed, or NULL when the slot is idle.
79 * @queue_node: List node for placing this node in the @queue list of
80 * &struct dw_mci.
81 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
82 * @flags: Random state bits associated with the slot.
83 * @id: Number of this slot.
84 * @last_detect_state: Most recently observed card detect state.
85 */
86struct dw_mci_slot {
87 struct mmc_host *mmc;
88 struct dw_mci *host;
89
90 u32 ctype;
91
92 struct mmc_request *mrq;
93 struct list_head queue_node;
94
95 unsigned int clock;
96 unsigned long flags;
97#define DW_MMC_CARD_PRESENT 0
98#define DW_MMC_CARD_NEED_INIT 1
99 int id;
100 int last_detect_state;
101};
102
103#if defined(CONFIG_DEBUG_FS)
104static int dw_mci_req_show(struct seq_file *s, void *v)
105{
106 struct dw_mci_slot *slot = s->private;
107 struct mmc_request *mrq;
108 struct mmc_command *cmd;
109 struct mmc_command *stop;
110 struct mmc_data *data;
111
112 /* Make sure we get a consistent snapshot */
113 spin_lock_bh(&slot->host->lock);
114 mrq = slot->mrq;
115
116 if (mrq) {
117 cmd = mrq->cmd;
118 data = mrq->data;
119 stop = mrq->stop;
120
121 if (cmd)
122 seq_printf(s,
123 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
124 cmd->opcode, cmd->arg, cmd->flags,
125 cmd->resp[0], cmd->resp[1], cmd->resp[2],
126 cmd->resp[2], cmd->error);
127 if (data)
128 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
129 data->bytes_xfered, data->blocks,
130 data->blksz, data->flags, data->error);
131 if (stop)
132 seq_printf(s,
133 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
134 stop->opcode, stop->arg, stop->flags,
135 stop->resp[0], stop->resp[1], stop->resp[2],
136 stop->resp[2], stop->error);
137 }
138
139 spin_unlock_bh(&slot->host->lock);
140
141 return 0;
142}
143
144static int dw_mci_req_open(struct inode *inode, struct file *file)
145{
146 return single_open(file, dw_mci_req_show, inode->i_private);
147}
148
149static const struct file_operations dw_mci_req_fops = {
150 .owner = THIS_MODULE,
151 .open = dw_mci_req_open,
152 .read = seq_read,
153 .llseek = seq_lseek,
154 .release = single_release,
155};
156
157static int dw_mci_regs_show(struct seq_file *s, void *v)
158{
159 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
160 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
161 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
162 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
163 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
164 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
165
166 return 0;
167}
168
169static int dw_mci_regs_open(struct inode *inode, struct file *file)
170{
171 return single_open(file, dw_mci_regs_show, inode->i_private);
172}
173
174static const struct file_operations dw_mci_regs_fops = {
175 .owner = THIS_MODULE,
176 .open = dw_mci_regs_open,
177 .read = seq_read,
178 .llseek = seq_lseek,
179 .release = single_release,
180};
181
182static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
183{
184 struct mmc_host *mmc = slot->mmc;
185 struct dw_mci *host = slot->host;
186 struct dentry *root;
187 struct dentry *node;
188
189 root = mmc->debugfs_root;
190 if (!root)
191 return;
192
193 node = debugfs_create_file("regs", S_IRUSR, root, host,
194 &dw_mci_regs_fops);
195 if (!node)
196 goto err;
197
198 node = debugfs_create_file("req", S_IRUSR, root, slot,
199 &dw_mci_req_fops);
200 if (!node)
201 goto err;
202
203 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
204 if (!node)
205 goto err;
206
207 node = debugfs_create_x32("pending_events", S_IRUSR, root,
208 (u32 *)&host->pending_events);
209 if (!node)
210 goto err;
211
212 node = debugfs_create_x32("completed_events", S_IRUSR, root,
213 (u32 *)&host->completed_events);
214 if (!node)
215 goto err;
216
217 return;
218
219err:
220 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
221}
222#endif /* defined(CONFIG_DEBUG_FS) */
223
224static void dw_mci_set_timeout(struct dw_mci *host)
225{
226 /* timeout (maximum) */
227 mci_writel(host, TMOUT, 0xffffffff);
228}
229
230static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
231{
232 struct mmc_data *data;
233 u32 cmdr;
234 cmd->error = -EINPROGRESS;
235
236 cmdr = cmd->opcode;
237
238 if (cmdr == MMC_STOP_TRANSMISSION)
239 cmdr |= SDMMC_CMD_STOP;
240 else
241 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
242
243 if (cmd->flags & MMC_RSP_PRESENT) {
244 /* We expect a response, so set this bit */
245 cmdr |= SDMMC_CMD_RESP_EXP;
246 if (cmd->flags & MMC_RSP_136)
247 cmdr |= SDMMC_CMD_RESP_LONG;
248 }
249
250 if (cmd->flags & MMC_RSP_CRC)
251 cmdr |= SDMMC_CMD_RESP_CRC;
252
253 data = cmd->data;
254 if (data) {
255 cmdr |= SDMMC_CMD_DAT_EXP;
256 if (data->flags & MMC_DATA_STREAM)
257 cmdr |= SDMMC_CMD_STRM_MODE;
258 if (data->flags & MMC_DATA_WRITE)
259 cmdr |= SDMMC_CMD_DAT_WR;
260 }
261
262 return cmdr;
263}
264
265static void dw_mci_start_command(struct dw_mci *host,
266 struct mmc_command *cmd, u32 cmd_flags)
267{
268 host->cmd = cmd;
62ca8034 269 dev_vdbg(&host->dev,
f95f3850
WN		 270 "start command: ARGR=0x%08x CMDR=0x%08x\n",
271 cmd->arg, cmd_flags);
272
273 mci_writel(host, CMDARG, cmd->arg);
274 wmb();
275
276 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
277}
278
279static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
280{
281 dw_mci_start_command(host, data->stop, host->stop_cmdr);
282}
283
284/* DMA interface functions */
285static void dw_mci_stop_dma(struct dw_mci *host)
286{
03e8cb53 287 if (host->using_dma) {
f95f3850
WN		 288 host->dma_ops->stop(host);
289 host->dma_ops->cleanup(host);
290 } else {
291 /* Data transfer was stopped by the interrupt handler */
292 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
293 }
294}
295
9aa51408
SJ		 296static int dw_mci_get_dma_dir(struct mmc_data *data)
297{
298 if (data->flags & MMC_DATA_WRITE)
299 return DMA_TO_DEVICE;
300 else
301 return DMA_FROM_DEVICE;
302}
303
9beee912 304#ifdef CONFIG_MMC_DW_IDMAC
f95f3850
WN		 305static void dw_mci_dma_cleanup(struct dw_mci *host)
306{
307 struct mmc_data *data = host->data;
308
309 if (data)
9aa51408
SJ		 310 if (!data->host_cookie)
311 dma_unmap_sg(&host->dev,
312 data->sg,
313 data->sg_len,
314 dw_mci_get_dma_dir(data));
f95f3850
WN		 315}
316
317static void dw_mci_idmac_stop_dma(struct dw_mci *host)
318{
319 u32 temp;
320
321 /* Disable and reset the IDMAC interface */
322 temp = mci_readl(host, CTRL);
323 temp &= ~SDMMC_CTRL_USE_IDMAC;
324 temp |= SDMMC_CTRL_DMA_RESET;
325 mci_writel(host, CTRL, temp);
326
327 /* Stop the IDMAC running */
328 temp = mci_readl(host, BMOD);
a5289a43 329 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
f95f3850
WN		 330 mci_writel(host, BMOD, temp);
331}
332
333static void dw_mci_idmac_complete_dma(struct dw_mci *host)
334{
335 struct mmc_data *data = host->data;
336
62ca8034 337 dev_vdbg(&host->dev, "DMA complete\n");
f95f3850
WN		 338
339 host->dma_ops->cleanup(host);
340
341 /*
342 * If the card was removed, data will be NULL. No point in trying to
343 * send the stop command or waiting for NBUSY in this case.
344 */
345 if (data) {
346 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
347 tasklet_schedule(&host->tasklet);
348 }
349}
350
351static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
352 unsigned int sg_len)
353{
354 int i;
355 struct idmac_desc *desc = host->sg_cpu;
356
357 for (i = 0; i < sg_len; i++, desc++) {
358 unsigned int length = sg_dma_len(&data->sg[i]);
359 u32 mem_addr = sg_dma_address(&data->sg[i]);
360
361 /* Set the OWN bit and disable interrupts for this descriptor */
362 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
363
364 /* Buffer length */
365 IDMAC_SET_BUFFER1_SIZE(desc, length);
366
367 /* Physical address to DMA to/from */
368 desc->des2 = mem_addr;
369 }
370
371 /* Set first descriptor */
372 desc = host->sg_cpu;
373 desc->des0 |= IDMAC_DES0_FD;
374
375 /* Set last descriptor */
376 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
377 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
378 desc->des0 |= IDMAC_DES0_LD;
379
380 wmb();
381}
382
383static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
384{
385 u32 temp;
386
387 dw_mci_translate_sglist(host, host->data, sg_len);
388
389 /* Select IDMAC interface */
390 temp = mci_readl(host, CTRL);
391 temp |= SDMMC_CTRL_USE_IDMAC;
392 mci_writel(host, CTRL, temp);
393
394 wmb();
395
396 /* Enable the IDMAC */
397 temp = mci_readl(host, BMOD);
a5289a43 398 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
f95f3850
WN		 399 mci_writel(host, BMOD, temp);
400
401 /* Start it running */
402 mci_writel(host, PLDMND, 1);
403}
404
405static int dw_mci_idmac_init(struct dw_mci *host)
406{
407 struct idmac_desc *p;
94c6cee9 408 int i, dma_support;
f95f3850
WN		 409
410 /* Number of descriptors in the ring buffer */
411 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
412
94c6cee9
G		 413 /* Check if Hardware Configuration Register has support for DMA */
414 dma_support = (mci_readl(host, HCON) >> 16) & 0x3;
415
416 if (!dma_support || dma_support > 2) {
417 dev_err(&host->dev,
418 "Host Controller does not support IDMA Tx.\n");
419 host->dma_ops = NULL;
420 return -ENODEV;
421 }
422
423 dev_info(&host->dev, "Using internal DMA controller.\n");
424
f95f3850
WN		 425 /* Forward link the descriptor list */
426 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
427 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
428
429 /* Set the last descriptor as the end-of-ring descriptor */
430 p->des3 = host->sg_dma;
431 p->des0 = IDMAC_DES0_ER;
432
141a712a
SJ		 433 mci_writel(host, BMOD, SDMMC_IDMAC_SWRESET);
434
f95f3850
WN		 435 /* Mask out interrupts - get Tx & Rx complete only */
436 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
437 SDMMC_IDMAC_INT_TI);
438
439 /* Set the descriptor base address */
440 mci_writel(host, DBADDR, host->sg_dma);
441 return 0;
442}
443
885c3e80
SJ		 444static struct dw_mci_dma_ops dw_mci_idmac_ops = {
445 .init = dw_mci_idmac_init,
446 .start = dw_mci_idmac_start_dma,
447 .stop = dw_mci_idmac_stop_dma,
448 .complete = dw_mci_idmac_complete_dma,
449 .cleanup = dw_mci_dma_cleanup,
450};
451#endif /* CONFIG_MMC_DW_IDMAC */
452
9aa51408
SJ		 453static int dw_mci_pre_dma_transfer(struct dw_mci *host,
454 struct mmc_data *data,
455 bool next)
f95f3850
WN		 456{
457 struct scatterlist *sg;
9aa51408 458 unsigned int i, sg_len;
03e8cb53 459
9aa51408
SJ		 460 if (!next && data->host_cookie)
461 return data->host_cookie;
f95f3850
WN		 462
463 /*
464 * We don't do DMA on "complex" transfers, i.e. with
465 * non-word-aligned buffers or lengths. Also, we don't bother
466 * with all the DMA setup overhead for short transfers.
467 */
468 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
469 return -EINVAL;
9aa51408 470
f95f3850
WN		 471 if (data->blksz & 3)
472 return -EINVAL;
473
474 for_each_sg(data->sg, sg, data->sg_len, i) {
475 if (sg->offset & 3 || sg->length & 3)
476 return -EINVAL;
477 }
478
9aa51408
SJ		 479 sg_len = dma_map_sg(&host->dev,
480 data->sg,
481 data->sg_len,
482 dw_mci_get_dma_dir(data));
483 if (sg_len == 0)
484 return -EINVAL;
03e8cb53 485
9aa51408
SJ		 486 if (next)
487 data->host_cookie = sg_len;
f95f3850 488
9aa51408
SJ		 489 return sg_len;
490}
491
9aa51408
SJ		 492static void dw_mci_pre_req(struct mmc_host *mmc,
493 struct mmc_request *mrq,
494 bool is_first_req)
495{
496 struct dw_mci_slot *slot = mmc_priv(mmc);
497 struct mmc_data *data = mrq->data;
498
499 if (!slot->host->use_dma || !data)
500 return;
501
502 if (data->host_cookie) {
503 data->host_cookie = 0;
504 return;
505 }
506
507 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
508 data->host_cookie = 0;
509}
510
511static void dw_mci_post_req(struct mmc_host *mmc,
512 struct mmc_request *mrq,
513 int err)
514{
515 struct dw_mci_slot *slot = mmc_priv(mmc);
516 struct mmc_data *data = mrq->data;
517
518 if (!slot->host->use_dma || !data)
519 return;
520
521 if (data->host_cookie)
522 dma_unmap_sg(&slot->host->dev,
523 data->sg,
524 data->sg_len,
525 dw_mci_get_dma_dir(data));
526 data->host_cookie = 0;
527}
528
529static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
530{
531 int sg_len;
532 u32 temp;
533
534 host->using_dma = 0;
535
536 /* If we don't have a channel, we can't do DMA */
537 if (!host->use_dma)
538 return -ENODEV;
539
540 sg_len = dw_mci_pre_dma_transfer(host, data, 0);
a99aa9b9
SJ		 541 if (sg_len < 0) {
542 host->dma_ops->stop(host);
9aa51408 543 return sg_len;
a99aa9b9 544 }
9aa51408
SJ		 545
546 host->using_dma = 1;
f95f3850 547
62ca8034 548 dev_vdbg(&host->dev,
f95f3850
WN		 549 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
550 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
551 sg_len);
552
553 /* Enable the DMA interface */
554 temp = mci_readl(host, CTRL);
555 temp |= SDMMC_CTRL_DMA_ENABLE;
556 mci_writel(host, CTRL, temp);
557
558 /* Disable RX/TX IRQs, let DMA handle it */
559 temp = mci_readl(host, INTMASK);
560 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
561 mci_writel(host, INTMASK, temp);
562
563 host->dma_ops->start(host, sg_len);
564
565 return 0;
566}
567
568static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
569{
570 u32 temp;
571
572 data->error = -EINPROGRESS;
573
574 WARN_ON(host->data);
575 host->sg = NULL;
576 host->data = data;
577
55c5efbc
JH		 578 if (data->flags & MMC_DATA_READ)
579 host->dir_status = DW_MCI_RECV_STATUS;
580 else
581 host->dir_status = DW_MCI_SEND_STATUS;
582
f95f3850 583 if (dw_mci_submit_data_dma(host, data)) {
f9c2a0dc
SJ		 584 int flags = SG_MITER_ATOMIC;
585 if (host->data->flags & MMC_DATA_READ)
586 flags |= SG_MITER_TO_SG;
587 else
588 flags |= SG_MITER_FROM_SG;
589
590 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
f95f3850 591 host->sg = data->sg;
34b664a2
JH		 592 host->part_buf_start = 0;
593 host->part_buf_count = 0;
f95f3850 594
b40af3aa 595 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
f95f3850
WN		 596 temp = mci_readl(host, INTMASK);
597 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
598 mci_writel(host, INTMASK, temp);
599
600 temp = mci_readl(host, CTRL);
601 temp &= ~SDMMC_CTRL_DMA_ENABLE;
602 mci_writel(host, CTRL, temp);
603 }
604}
605
606static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
607{
608 struct dw_mci *host = slot->host;
609 unsigned long timeout = jiffies + msecs_to_jiffies(500);
610 unsigned int cmd_status = 0;
611
612 mci_writel(host, CMDARG, arg);
613 wmb();
614 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
615
616 while (time_before(jiffies, timeout)) {
617 cmd_status = mci_readl(host, CMD);
618 if (!(cmd_status & SDMMC_CMD_START))
619 return;
620 }
621 dev_err(&slot->mmc->class_dev,
622 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
623 cmd, arg, cmd_status);
624}
625
626static void dw_mci_setup_bus(struct dw_mci_slot *slot)
627{
628 struct dw_mci *host = slot->host;
629 u32 div;
630
631 if (slot->clock != host->current_speed) {
e419990b
SJ		 632 div = host->bus_hz / slot->clock;
633 if (host->bus_hz % slot->clock && host->bus_hz > slot->clock)
f95f3850
WN		 634 /*
635 * move the + 1 after the divide to prevent
636 * over-clocking the card.
637 */
e419990b
SJ		 638 div += 1;
639
640 div = (host->bus_hz != slot->clock) ? DIV_ROUND_UP(div, 2) : 0;
f95f3850
WN		 641
642 dev_info(&slot->mmc->class_dev,
643 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"
644 " div = %d)\n", slot->id, host->bus_hz, slot->clock,
645 div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div);
646
647 /* disable clock */
648 mci_writel(host, CLKENA, 0);
649 mci_writel(host, CLKSRC, 0);
650
651 /* inform CIU */
652 mci_send_cmd(slot,
653 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
654
655 /* set clock to desired speed */
656 mci_writel(host, CLKDIV, div);
657
658 /* inform CIU */
659 mci_send_cmd(slot,
660 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
661
662 /* enable clock */
e3891dc5
JC		 663 mci_writel(host, CLKENA, ((SDMMC_CLKEN_ENABLE |
664 SDMMC_CLKEN_LOW_PWR) << slot->id));
f95f3850
WN		 665
666 /* inform CIU */
667 mci_send_cmd(slot,
668 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
669
670 host->current_speed = slot->clock;
671 }
672
673 /* Set the current slot bus width */
1d56c453 674 mci_writel(host, CTYPE, (slot->ctype << slot->id));
f95f3850
WN		 675}
676
053b3ce6
SJ		 677static void __dw_mci_start_request(struct dw_mci *host,
678 struct dw_mci_slot *slot,
679 struct mmc_command *cmd)
f95f3850
WN		 680{
681 struct mmc_request *mrq;
f95f3850
WN		 682 struct mmc_data *data;
683 u32 cmdflags;
684
685 mrq = slot->mrq;
686 if (host->pdata->select_slot)
687 host->pdata->select_slot(slot->id);
688
689 /* Slot specific timing and width adjustment */
690 dw_mci_setup_bus(slot);
691
692 host->cur_slot = slot;
693 host->mrq = mrq;
694
695 host->pending_events = 0;
696 host->completed_events = 0;
697 host->data_status = 0;
698
053b3ce6 699 data = cmd->data;
f95f3850
WN		 700 if (data) {
701 dw_mci_set_timeout(host);
702 mci_writel(host, BYTCNT, data->blksz*data->blocks);
703 mci_writel(host, BLKSIZ, data->blksz);
704 }
705
f95f3850
WN		 706 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
707
708 /* this is the first command, send the initialization clock */
709 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
710 cmdflags |= SDMMC_CMD_INIT;
711
712 if (data) {
713 dw_mci_submit_data(host, data);
714 wmb();
715 }
716
717 dw_mci_start_command(host, cmd, cmdflags);
718
719 if (mrq->stop)
720 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
721}
722
053b3ce6
SJ		 723static void dw_mci_start_request(struct dw_mci *host,
724 struct dw_mci_slot *slot)
725{
726 struct mmc_request *mrq = slot->mrq;
727 struct mmc_command *cmd;
728
729 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
730 __dw_mci_start_request(host, slot, cmd);
731}
732
7456caae 733/* must be called with host->lock held */
f95f3850
WN		 734static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
735 struct mmc_request *mrq)
736{
737 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
738 host->state);
739
f95f3850
WN		 740 slot->mrq = mrq;
741
742 if (host->state == STATE_IDLE) {
743 host->state = STATE_SENDING_CMD;
744 dw_mci_start_request(host, slot);
745 } else {
746 list_add_tail(&slot->queue_node, &host->queue);
747 }
f95f3850
WN		 748}
749
750static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
751{
752 struct dw_mci_slot *slot = mmc_priv(mmc);
753 struct dw_mci *host = slot->host;
754
755 WARN_ON(slot->mrq);
756
7456caae
JH		 757 /*
758 * The check for card presence and queueing of the request must be
759 * atomic, otherwise the card could be removed in between and the
760 * request wouldn't fail until another card was inserted.
761 */
762 spin_lock_bh(&host->lock);
763
f95f3850 764 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
7456caae 765 spin_unlock_bh(&host->lock);
f95f3850
WN		 766 mrq->cmd->error = -ENOMEDIUM;
767 mmc_request_done(mmc, mrq);
768 return;
769 }
770
f95f3850 771 dw_mci_queue_request(host, slot, mrq);
7456caae
JH		 772
773 spin_unlock_bh(&host->lock);
f95f3850
WN		 774}
775
776static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
777{
778 struct dw_mci_slot *slot = mmc_priv(mmc);
41babf75 779 u32 regs;
f95f3850
WN		 780
781 /* set default 1 bit mode */
782 slot->ctype = SDMMC_CTYPE_1BIT;
783
784 switch (ios->bus_width) {
785 case MMC_BUS_WIDTH_1:
786 slot->ctype = SDMMC_CTYPE_1BIT;
787 break;
788 case MMC_BUS_WIDTH_4:
789 slot->ctype = SDMMC_CTYPE_4BIT;
790 break;
c9b2a06f
JC		 791 case MMC_BUS_WIDTH_8:
792 slot->ctype = SDMMC_CTYPE_8BIT;
793 break;
f95f3850
WN		 794 }
795
3f514291
SJ		 796 regs = mci_readl(slot->host, UHS_REG);
797
41babf75 798 /* DDR mode set */
3f514291 799 if (ios->timing == MMC_TIMING_UHS_DDR50)
41babf75 800 regs |= (0x1 << slot->id) << 16;
3f514291
SJ		 801 else
802 regs &= ~(0x1 << slot->id) << 16;
803
804 mci_writel(slot->host, UHS_REG, regs);
41babf75 805
f95f3850
WN		 806 if (ios->clock) {
807 /*
808 * Use mirror of ios->clock to prevent race with mmc
809 * core ios update when finding the minimum.
810 */
811 slot->clock = ios->clock;
812 }
813
814 switch (ios->power_mode) {
815 case MMC_POWER_UP:
816 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
817 break;
818 default:
819 break;
820 }
821}
822
823static int dw_mci_get_ro(struct mmc_host *mmc)
824{
825 int read_only;
826 struct dw_mci_slot *slot = mmc_priv(mmc);
827 struct dw_mci_board *brd = slot->host->pdata;
828
829 /* Use platform get_ro function, else try on board write protect */
830 if (brd->get_ro)
831 read_only = brd->get_ro(slot->id);
832 else
833 read_only =
834 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
835
836 dev_dbg(&mmc->class_dev, "card is %s\n",
837 read_only ? "read-only" : "read-write");
838
839 return read_only;
840}
841
842static int dw_mci_get_cd(struct mmc_host *mmc)
843{
844 int present;
845 struct dw_mci_slot *slot = mmc_priv(mmc);
846 struct dw_mci_board *brd = slot->host->pdata;
847
848 /* Use platform get_cd function, else try onboard card detect */
fc3d7720
JC		 849 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
850 present = 1;
851 else if (brd->get_cd)
f95f3850
WN		 852 present = !brd->get_cd(slot->id);
853 else
854 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
855 == 0 ? 1 : 0;
856
857 if (present)
858 dev_dbg(&mmc->class_dev, "card is present\n");
859 else
860 dev_dbg(&mmc->class_dev, "card is not present\n");
861
862 return present;
863}
864
1a5c8e1f
SH		 865static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
866{
867 struct dw_mci_slot *slot = mmc_priv(mmc);
868 struct dw_mci *host = slot->host;
869 u32 int_mask;
870
871 /* Enable/disable Slot Specific SDIO interrupt */
872 int_mask = mci_readl(host, INTMASK);
873 if (enb) {
874 mci_writel(host, INTMASK,
705ad047 875 (int_mask | SDMMC_INT_SDIO(slot->id)));
1a5c8e1f
SH		 876 } else {
877 mci_writel(host, INTMASK,
705ad047 878 (int_mask & ~SDMMC_INT_SDIO(slot->id)));
1a5c8e1f
SH		 879 }
880}
881
f95f3850 882static const struct mmc_host_ops dw_mci_ops = {
1a5c8e1f 883 .request = dw_mci_request,
9aa51408
SJ		 884 .pre_req = dw_mci_pre_req,
885 .post_req = dw_mci_post_req,
1a5c8e1f
SH		 886 .set_ios = dw_mci_set_ios,
887 .get_ro = dw_mci_get_ro,
888 .get_cd = dw_mci_get_cd,
889 .enable_sdio_irq = dw_mci_enable_sdio_irq,
f95f3850
WN		 890};
891
892static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
893 __releases(&host->lock)
894 __acquires(&host->lock)
895{
896 struct dw_mci_slot *slot;
897 struct mmc_host *prev_mmc = host->cur_slot->mmc;
898
899 WARN_ON(host->cmd || host->data);
900
901 host->cur_slot->mrq = NULL;
902 host->mrq = NULL;
903 if (!list_empty(&host->queue)) {
904 slot = list_entry(host->queue.next,
905 struct dw_mci_slot, queue_node);
906 list_del(&slot->queue_node);
62ca8034 907 dev_vdbg(&host->dev, "list not empty: %s is next\n",
f95f3850
WN		 908 mmc_hostname(slot->mmc));
909 host->state = STATE_SENDING_CMD;
910 dw_mci_start_request(host, slot);
911 } else {
62ca8034 912 dev_vdbg(&host->dev, "list empty\n");
f95f3850
WN		 913 host->state = STATE_IDLE;
914 }
915
916 spin_unlock(&host->lock);
917 mmc_request_done(prev_mmc, mrq);
918 spin_lock(&host->lock);
919}
920
921static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
922{
923 u32 status = host->cmd_status;
924
925 host->cmd_status = 0;
926
927 /* Read the response from the card (up to 16 bytes) */
928 if (cmd->flags & MMC_RSP_PRESENT) {
929 if (cmd->flags & MMC_RSP_136) {
930 cmd->resp[3] = mci_readl(host, RESP0);
931 cmd->resp[2] = mci_readl(host, RESP1);
932 cmd->resp[1] = mci_readl(host, RESP2);
933 cmd->resp[0] = mci_readl(host, RESP3);
934 } else {
935 cmd->resp[0] = mci_readl(host, RESP0);
936 cmd->resp[1] = 0;
937 cmd->resp[2] = 0;
938 cmd->resp[3] = 0;
939 }
940 }
941
942 if (status & SDMMC_INT_RTO)
943 cmd->error = -ETIMEDOUT;
944 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
945 cmd->error = -EILSEQ;
946 else if (status & SDMMC_INT_RESP_ERR)
947 cmd->error = -EIO;
948 else
949 cmd->error = 0;
950
951 if (cmd->error) {
952 /* newer ip versions need a delay between retries */
953 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
954 mdelay(20);
955
956 if (cmd->data) {
f95f3850 957 dw_mci_stop_dma(host);
fda5f736 958 host->data = NULL;
f95f3850
WN		 959 }
960 }
961}
962
963static void dw_mci_tasklet_func(unsigned long priv)
964{
965 struct dw_mci *host = (struct dw_mci *)priv;
966 struct mmc_data *data;
967 struct mmc_command *cmd;
968 enum dw_mci_state state;
969 enum dw_mci_state prev_state;
94dd5b33 970 u32 status, ctrl;
f95f3850
WN		 971
972 spin_lock(&host->lock);
973
974 state = host->state;
975 data = host->data;
976
977 do {
978 prev_state = state;
979
980 switch (state) {
981 case STATE_IDLE:
982 break;
983
984 case STATE_SENDING_CMD:
985 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
986 &host->pending_events))
987 break;
988
989 cmd = host->cmd;
990 host->cmd = NULL;
991 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
053b3ce6
SJ		 992 dw_mci_command_complete(host, cmd);
993 if (cmd == host->mrq->sbc && !cmd->error) {
994 prev_state = state = STATE_SENDING_CMD;
995 __dw_mci_start_request(host, host->cur_slot,
996 host->mrq->cmd);
997 goto unlock;
998 }
999
f95f3850
WN		 1000 if (!host->mrq->data || cmd->error) {
1001 dw_mci_request_end(host, host->mrq);
1002 goto unlock;
1003 }
1004
1005 prev_state = state = STATE_SENDING_DATA;
1006 /* fall through */
1007
1008 case STATE_SENDING_DATA:
1009 if (test_and_clear_bit(EVENT_DATA_ERROR,
1010 &host->pending_events)) {
1011 dw_mci_stop_dma(host);
1012 if (data->stop)
1013 send_stop_cmd(host, data);
1014 state = STATE_DATA_ERROR;
1015 break;
1016 }
1017
1018 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1019 &host->pending_events))
1020 break;
1021
1022 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1023 prev_state = state = STATE_DATA_BUSY;
1024 /* fall through */
1025
1026 case STATE_DATA_BUSY:
1027 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1028 &host->pending_events))
1029 break;
1030
1031 host->data = NULL;
1032 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1033 status = host->data_status;
1034
1035 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1036 if (status & SDMMC_INT_DTO) {
f95f3850
WN		 1037 data->error = -ETIMEDOUT;
1038 } else if (status & SDMMC_INT_DCRC) {
f95f3850 1039 data->error = -EILSEQ;
55c5efbc
JH		 1040 } else if (status & SDMMC_INT_EBE &&
1041 host->dir_status ==
1042 DW_MCI_SEND_STATUS) {
1043 /*
1044 * No data CRC status was returned.
1045 * The number of bytes transferred will
1046 * be exaggerated in PIO mode.
1047 */
1048 data->bytes_xfered = 0;
1049 data->error = -ETIMEDOUT;
f95f3850 1050 } else {
62ca8034 1051 dev_err(&host->dev,
f95f3850
WN		 1052 "data FIFO error "
1053 "(status=%08x)\n",
1054 status);
1055 data->error = -EIO;
1056 }
94dd5b33
JH		 1057 /*
1058 * After an error, there may be data lingering
1059 * in the FIFO, so reset it - doing so
1060 * generates a block interrupt, hence setting
1061 * the scatter-gather pointer to NULL.
1062 */
f9c2a0dc 1063 sg_miter_stop(&host->sg_miter);
94dd5b33
JH		 1064 host->sg = NULL;
1065 ctrl = mci_readl(host, CTRL);
1066 ctrl |= SDMMC_CTRL_FIFO_RESET;
1067 mci_writel(host, CTRL, ctrl);
f95f3850
WN		 1068 } else {
1069 data->bytes_xfered = data->blocks * data->blksz;
1070 data->error = 0;
1071 }
1072
1073 if (!data->stop) {
1074 dw_mci_request_end(host, host->mrq);
1075 goto unlock;
1076 }
1077
053b3ce6
SJ		 1078 if (host->mrq->sbc && !data->error) {
1079 data->stop->error = 0;
1080 dw_mci_request_end(host, host->mrq);
1081 goto unlock;
1082 }
1083
f95f3850
WN		 1084 prev_state = state = STATE_SENDING_STOP;
1085 if (!data->error)
1086 send_stop_cmd(host, data);
1087 /* fall through */
1088
1089 case STATE_SENDING_STOP:
1090 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1091 &host->pending_events))
1092 break;
1093
1094 host->cmd = NULL;
1095 dw_mci_command_complete(host, host->mrq->stop);
1096 dw_mci_request_end(host, host->mrq);
1097 goto unlock;
1098
1099 case STATE_DATA_ERROR:
1100 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1101 &host->pending_events))
1102 break;
1103
1104 state = STATE_DATA_BUSY;
1105 break;
1106 }
1107 } while (state != prev_state);
1108
1109 host->state = state;
1110unlock:
1111 spin_unlock(&host->lock);
1112
1113}
1114
34b664a2
JH		 1115/* push final bytes to part_buf, only use during push */
1116static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 1117{
34b664a2
JH		 1118 memcpy((void *)&host->part_buf, buf, cnt);
1119 host->part_buf_count = cnt;
1120}
f95f3850 1121
34b664a2
JH		 1122/* append bytes to part_buf, only use during push */
1123static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1124{
1125 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1126 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1127 host->part_buf_count += cnt;
1128 return cnt;
1129}
f95f3850 1130
34b664a2
JH		 1131/* pull first bytes from part_buf, only use during pull */
1132static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1133{
1134 cnt = min(cnt, (int)host->part_buf_count);
1135 if (cnt) {
1136 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1137 cnt);
1138 host->part_buf_count -= cnt;
1139 host->part_buf_start += cnt;
f95f3850 1140 }
34b664a2 1141 return cnt;
f95f3850
WN		 1142}
1143
34b664a2
JH		 1144/* pull final bytes from the part_buf, assuming it's just been filled */
1145static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 1146{
34b664a2
JH		 1147 memcpy(buf, &host->part_buf, cnt);
1148 host->part_buf_start = cnt;
1149 host->part_buf_count = (1 << host->data_shift) - cnt;
1150}
f95f3850 1151
34b664a2
JH		 1152static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1153{
1154 /* try and push anything in the part_buf */
1155 if (unlikely(host->part_buf_count)) {
1156 int len = dw_mci_push_part_bytes(host, buf, cnt);
1157 buf += len;
1158 cnt -= len;
1159 if (!sg_next(host->sg) || host->part_buf_count == 2) {
4e0a5adf
JC		 1160 mci_writew(host, DATA(host->data_offset),
1161 host->part_buf16);
34b664a2
JH		 1162 host->part_buf_count = 0;
1163 }
1164 }
1165#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1166 if (unlikely((unsigned long)buf & 0x1)) {
1167 while (cnt >= 2) {
1168 u16 aligned_buf[64];
1169 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1170 int items = len >> 1;
1171 int i;
1172 /* memcpy from input buffer into aligned buffer */
1173 memcpy(aligned_buf, buf, len);
1174 buf += len;
1175 cnt -= len;
1176 /* push data from aligned buffer into fifo */
1177 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1178 mci_writew(host, DATA(host->data_offset),
1179 aligned_buf[i]);
34b664a2
JH		 1180 }
1181 } else
1182#endif
1183 {
1184 u16 *pdata = buf;
1185 for (; cnt >= 2; cnt -= 2)
4e0a5adf 1186 mci_writew(host, DATA(host->data_offset), *pdata++);
34b664a2
JH		 1187 buf = pdata;
1188 }
1189 /* put anything remaining in the part_buf */
1190 if (cnt) {
1191 dw_mci_set_part_bytes(host, buf, cnt);
1192 if (!sg_next(host->sg))
4e0a5adf
JC		 1193 mci_writew(host, DATA(host->data_offset),
1194 host->part_buf16);
34b664a2
JH		 1195 }
1196}
f95f3850 1197
34b664a2
JH		 1198static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1199{
1200#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1201 if (unlikely((unsigned long)buf & 0x1)) {
1202 while (cnt >= 2) {
1203 /* pull data from fifo into aligned buffer */
1204 u16 aligned_buf[64];
1205 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1206 int items = len >> 1;
1207 int i;
1208 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1209 aligned_buf[i] = mci_readw(host,
1210 DATA(host->data_offset));
34b664a2
JH		 1211 /* memcpy from aligned buffer into output buffer */
1212 memcpy(buf, aligned_buf, len);
1213 buf += len;
1214 cnt -= len;
1215 }
1216 } else
1217#endif
1218 {
1219 u16 *pdata = buf;
1220 for (; cnt >= 2; cnt -= 2)
4e0a5adf 1221 *pdata++ = mci_readw(host, DATA(host->data_offset));
34b664a2
JH		 1222 buf = pdata;
1223 }
1224 if (cnt) {
4e0a5adf 1225 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
34b664a2 1226 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 1227 }
1228}
1229
1230static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
1231{
34b664a2
JH		 1232 /* try and push anything in the part_buf */
1233 if (unlikely(host->part_buf_count)) {
1234 int len = dw_mci_push_part_bytes(host, buf, cnt);
1235 buf += len;
1236 cnt -= len;
1237 if (!sg_next(host->sg) || host->part_buf_count == 4) {
4e0a5adf
JC		 1238 mci_writel(host, DATA(host->data_offset),
1239 host->part_buf32);
34b664a2
JH		 1240 host->part_buf_count = 0;
1241 }
1242 }
1243#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1244 if (unlikely((unsigned long)buf & 0x3)) {
1245 while (cnt >= 4) {
1246 u32 aligned_buf[32];
1247 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1248 int items = len >> 2;
1249 int i;
1250 /* memcpy from input buffer into aligned buffer */
1251 memcpy(aligned_buf, buf, len);
1252 buf += len;
1253 cnt -= len;
1254 /* push data from aligned buffer into fifo */
1255 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1256 mci_writel(host, DATA(host->data_offset),
1257 aligned_buf[i]);
34b664a2
JH		 1258 }
1259 } else
1260#endif
1261 {
1262 u32 *pdata = buf;
1263 for (; cnt >= 4; cnt -= 4)
4e0a5adf 1264 mci_writel(host, DATA(host->data_offset), *pdata++);
34b664a2
JH		 1265 buf = pdata;
1266 }
1267 /* put anything remaining in the part_buf */
1268 if (cnt) {
1269 dw_mci_set_part_bytes(host, buf, cnt);
1270 if (!sg_next(host->sg))
4e0a5adf
JC		 1271 mci_writel(host, DATA(host->data_offset),
1272 host->part_buf32);
f95f3850
WN		 1273 }
1274}
1275
1276static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1277{
34b664a2
JH		 1278#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1279 if (unlikely((unsigned long)buf & 0x3)) {
1280 while (cnt >= 4) {
1281 /* pull data from fifo into aligned buffer */
1282 u32 aligned_buf[32];
1283 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1284 int items = len >> 2;
1285 int i;
1286 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1287 aligned_buf[i] = mci_readl(host,
1288 DATA(host->data_offset));
34b664a2
JH		 1289 /* memcpy from aligned buffer into output buffer */
1290 memcpy(buf, aligned_buf, len);
1291 buf += len;
1292 cnt -= len;
1293 }
1294 } else
1295#endif
1296 {
1297 u32 *pdata = buf;
1298 for (; cnt >= 4; cnt -= 4)
4e0a5adf 1299 *pdata++ = mci_readl(host, DATA(host->data_offset));
34b664a2
JH		 1300 buf = pdata;
1301 }
1302 if (cnt) {
4e0a5adf 1303 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
34b664a2 1304 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 1305 }
1306}
1307
1308static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1309{
34b664a2
JH		 1310 /* try and push anything in the part_buf */
1311 if (unlikely(host->part_buf_count)) {
1312 int len = dw_mci_push_part_bytes(host, buf, cnt);
1313 buf += len;
1314 cnt -= len;
1315 if (!sg_next(host->sg) || host->part_buf_count == 8) {
4e0a5adf
JC		 1316 mci_writew(host, DATA(host->data_offset),
1317 host->part_buf);
34b664a2
JH		 1318 host->part_buf_count = 0;
1319 }
1320 }
1321#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1322 if (unlikely((unsigned long)buf & 0x7)) {
1323 while (cnt >= 8) {
1324 u64 aligned_buf[16];
1325 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1326 int items = len >> 3;
1327 int i;
1328 /* memcpy from input buffer into aligned buffer */
1329 memcpy(aligned_buf, buf, len);
1330 buf += len;
1331 cnt -= len;
1332 /* push data from aligned buffer into fifo */
1333 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1334 mci_writeq(host, DATA(host->data_offset),
1335 aligned_buf[i]);
34b664a2
JH		 1336 }
1337 } else
1338#endif
1339 {
1340 u64 *pdata = buf;
1341 for (; cnt >= 8; cnt -= 8)
4e0a5adf 1342 mci_writeq(host, DATA(host->data_offset), *pdata++);
34b664a2
JH		 1343 buf = pdata;
1344 }
1345 /* put anything remaining in the part_buf */
1346 if (cnt) {
1347 dw_mci_set_part_bytes(host, buf, cnt);
1348 if (!sg_next(host->sg))
4e0a5adf
JC		 1349 mci_writeq(host, DATA(host->data_offset),
1350 host->part_buf);
f95f3850
WN		 1351 }
1352}
1353
1354static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1355{
34b664a2
JH		 1356#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1357 if (unlikely((unsigned long)buf & 0x7)) {
1358 while (cnt >= 8) {
1359 /* pull data from fifo into aligned buffer */
1360 u64 aligned_buf[16];
1361 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1362 int items = len >> 3;
1363 int i;
1364 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1365 aligned_buf[i] = mci_readq(host,
1366 DATA(host->data_offset));
34b664a2
JH		 1367 /* memcpy from aligned buffer into output buffer */
1368 memcpy(buf, aligned_buf, len);
1369 buf += len;
1370 cnt -= len;
1371 }
1372 } else
1373#endif
1374 {
1375 u64 *pdata = buf;
1376 for (; cnt >= 8; cnt -= 8)
4e0a5adf 1377 *pdata++ = mci_readq(host, DATA(host->data_offset));
34b664a2
JH		 1378 buf = pdata;
1379 }
1380 if (cnt) {
4e0a5adf 1381 host->part_buf = mci_readq(host, DATA(host->data_offset));
34b664a2
JH		 1382 dw_mci_pull_final_bytes(host, buf, cnt);
1383 }
1384}
f95f3850 1385
34b664a2
JH		 1386static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
1387{
1388 int len;
f95f3850 1389
34b664a2
JH		 1390 /* get remaining partial bytes */
1391 len = dw_mci_pull_part_bytes(host, buf, cnt);
1392 if (unlikely(len == cnt))
1393 return;
1394 buf += len;
1395 cnt -= len;
1396
1397 /* get the rest of the data */
1398 host->pull_data(host, buf, cnt);
f95f3850
WN		 1399}
1400
1401static void dw_mci_read_data_pio(struct dw_mci *host)
1402{
f9c2a0dc
SJ		 1403 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1404 void *buf;
1405 unsigned int offset;
f95f3850
WN		 1406 struct mmc_data *data = host->data;
1407 int shift = host->data_shift;
1408 u32 status;
ba6a902d 1409 unsigned int nbytes = 0, len;
f9c2a0dc 1410 unsigned int remain, fcnt;
f95f3850
WN		 1411
1412 do {
f9c2a0dc
SJ		 1413 if (!sg_miter_next(sg_miter))
1414 goto done;
1415
1416 host->sg = sg_miter->__sg;
1417 buf = sg_miter->addr;
1418 remain = sg_miter->length;
1419 offset = 0;
1420
1421 do {
1422 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
1423 << shift) + host->part_buf_count;
1424 len = min(remain, fcnt);
1425 if (!len)
1426 break;
34b664a2 1427 dw_mci_pull_data(host, (void *)(buf + offset), len);
f95f3850
WN		 1428 offset += len;
1429 nbytes += len;
f9c2a0dc
SJ		 1430 remain -= len;
1431 } while (remain);
1432 sg_miter->consumed = offset;
f95f3850
WN		 1433
1434 status = mci_readl(host, MINTSTS);
1435 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1436 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1437 host->data_status = status;
1438 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1439 sg_miter_stop(sg_miter);
1440 host->sg = NULL;
f95f3850
WN		 1441 smp_wmb();
1442
1443 set_bit(EVENT_DATA_ERROR, &host->pending_events);
1444
1445 tasklet_schedule(&host->tasklet);
1446 return;
1447 }
f95f3850 1448 } while (status & SDMMC_INT_RXDR); /*if the RXDR is ready read again*/
f95f3850 1449 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1450
1451 if (!remain) {
1452 if (!sg_miter_next(sg_miter))
1453 goto done;
1454 sg_miter->consumed = 0;
1455 }
1456 sg_miter_stop(sg_miter);
f95f3850
WN		 1457 return;
1458
1459done:
1460 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1461 sg_miter_stop(sg_miter);
1462 host->sg = NULL;
f95f3850
WN		 1463 smp_wmb();
1464 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1465}
1466
1467static void dw_mci_write_data_pio(struct dw_mci *host)
1468{
f9c2a0dc
SJ		 1469 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1470 void *buf;
1471 unsigned int offset;
f95f3850
WN		 1472 struct mmc_data *data = host->data;
1473 int shift = host->data_shift;
1474 u32 status;
1475 unsigned int nbytes = 0, len;
f9c2a0dc
SJ		 1476 unsigned int fifo_depth = host->fifo_depth;
1477 unsigned int remain, fcnt;
f95f3850
WN		 1478
1479 do {
f9c2a0dc
SJ		 1480 if (!sg_miter_next(sg_miter))
1481 goto done;
1482
1483 host->sg = sg_miter->__sg;
1484 buf = sg_miter->addr;
1485 remain = sg_miter->length;
1486 offset = 0;
1487
1488 do {
1489 fcnt = ((fifo_depth -
1490 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
1491 << shift) - host->part_buf_count;
1492 len = min(remain, fcnt);
1493 if (!len)
1494 break;
f95f3850 1495 host->push_data(host, (void *)(buf + offset), len);
f95f3850
WN		 1496 offset += len;
1497 nbytes += len;
f9c2a0dc
SJ		 1498 remain -= len;
1499 } while (remain);
1500 sg_miter->consumed = offset;
f95f3850
WN		 1501
1502 status = mci_readl(host, MINTSTS);
1503 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1504 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1505 host->data_status = status;
1506 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1507 sg_miter_stop(sg_miter);
1508 host->sg = NULL;
f95f3850
WN		 1509
1510 smp_wmb();
1511
1512 set_bit(EVENT_DATA_ERROR, &host->pending_events);
1513
1514 tasklet_schedule(&host->tasklet);
1515 return;
1516 }
1517 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
f95f3850 1518 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1519
1520 if (!remain) {
1521 if (!sg_miter_next(sg_miter))
1522 goto done;
1523 sg_miter->consumed = 0;
1524 }
1525 sg_miter_stop(sg_miter);
f95f3850
WN		 1526 return;
1527
1528done:
1529 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1530 sg_miter_stop(sg_miter);
1531 host->sg = NULL;
f95f3850
WN		 1532 smp_wmb();
1533 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1534}
1535
1536static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
1537{
1538 if (!host->cmd_status)
1539 host->cmd_status = status;
1540
1541 smp_wmb();
1542
1543 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1544 tasklet_schedule(&host->tasklet);
1545}
1546
1547static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
1548{
1549 struct dw_mci *host = dev_id;
1550 u32 status, pending;
1551 unsigned int pass_count = 0;
1a5c8e1f 1552 int i;
f95f3850
WN		 1553
1554 do {
1555 status = mci_readl(host, RINTSTS);
1556 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
1557
1558 /*
1559 * DTO fix - version 2.10a and below, and only if internal DMA
1560 * is configured.
1561 */
1562 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
1563 if (!pending &&
1564 ((mci_readl(host, STATUS) >> 17) & 0x1fff))
1565 pending |= SDMMC_INT_DATA_OVER;
1566 }
1567
1568 if (!pending)
1569 break;
1570
1571 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
1572 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
1573 host->cmd_status = status;
1574 smp_wmb();
1575 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
f95f3850
WN		 1576 }
1577
1578 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
1579 /* if there is an error report DATA_ERROR */
1580 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
1581 host->data_status = status;
1582 smp_wmb();
1583 set_bit(EVENT_DATA_ERROR, &host->pending_events);
6e83e10d
SJ		 1584 if (!(pending & (SDMMC_INT_DTO | SDMMC_INT_DCRC |
1585 SDMMC_INT_SBE | SDMMC_INT_EBE)))
1586 tasklet_schedule(&host->tasklet);
f95f3850
WN		 1587 }
1588
1589 if (pending & SDMMC_INT_DATA_OVER) {
1590 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1591 if (!host->data_status)
1592 host->data_status = status;
1593 smp_wmb();
1594 if (host->dir_status == DW_MCI_RECV_STATUS) {
1595 if (host->sg != NULL)
1596 dw_mci_read_data_pio(host);
1597 }
1598 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1599 tasklet_schedule(&host->tasklet);
1600 }
1601
1602 if (pending & SDMMC_INT_RXDR) {
1603 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
b40af3aa 1604 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
f95f3850
WN		 1605 dw_mci_read_data_pio(host);
1606 }
1607
1608 if (pending & SDMMC_INT_TXDR) {
1609 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
b40af3aa 1610 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
f95f3850
WN		 1611 dw_mci_write_data_pio(host);
1612 }
1613
1614 if (pending & SDMMC_INT_CMD_DONE) {
1615 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
1616 dw_mci_cmd_interrupt(host, status);
1617 }
1618
1619 if (pending & SDMMC_INT_CD) {
1620 mci_writel(host, RINTSTS, SDMMC_INT_CD);
95dcc2cb 1621 queue_work(host->card_workqueue, &host->card_work);
f95f3850
WN		 1622 }
1623
1a5c8e1f
SH		 1624 /* Handle SDIO Interrupts */
1625 for (i = 0; i < host->num_slots; i++) {
1626 struct dw_mci_slot *slot = host->slot[i];
1627 if (pending & SDMMC_INT_SDIO(i)) {
1628 mci_writel(host, RINTSTS, SDMMC_INT_SDIO(i));
1629 mmc_signal_sdio_irq(slot->mmc);
1630 }
1631 }
1632
f95f3850
WN		 1633 } while (pass_count++ < 5);
1634
1635#ifdef CONFIG_MMC_DW_IDMAC
1636 /* Handle DMA interrupts */
1637 pending = mci_readl(host, IDSTS);
1638 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
1639 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
1640 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
f95f3850
WN		 1641 host->dma_ops->complete(host);
1642 }
1643#endif
1644
1645 return IRQ_HANDLED;
1646}
1647
1791b13e 1648static void dw_mci_work_routine_card(struct work_struct *work)
f95f3850 1649{
1791b13e 1650 struct dw_mci *host = container_of(work, struct dw_mci, card_work);
f95f3850
WN		 1651 int i;
1652
1653 for (i = 0; i < host->num_slots; i++) {
1654 struct dw_mci_slot *slot = host->slot[i];
1655 struct mmc_host *mmc = slot->mmc;
1656 struct mmc_request *mrq;
1657 int present;
1658 u32 ctrl;
1659
1660 present = dw_mci_get_cd(mmc);
1661 while (present != slot->last_detect_state) {
f95f3850
WN		 1662 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1663 present ? "inserted" : "removed");
1664
1791b13e
JH		 1665 /* Power up slot (before spin_lock, may sleep) */
1666 if (present != 0 && host->pdata->setpower)
1667 host->pdata->setpower(slot->id, mmc->ocr_avail);
1668
1669 spin_lock_bh(&host->lock);
1670
f95f3850
WN		 1671 /* Card change detected */
1672 slot->last_detect_state = present;
1673
1791b13e
JH		 1674 /* Mark card as present if applicable */
1675 if (present != 0)
f95f3850 1676 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
f95f3850
WN		 1677
1678 /* Clean up queue if present */
1679 mrq = slot->mrq;
1680 if (mrq) {
1681 if (mrq == host->mrq) {
1682 host->data = NULL;
1683 host->cmd = NULL;
1684
1685 switch (host->state) {
1686 case STATE_IDLE:
1687 break;
1688 case STATE_SENDING_CMD:
1689 mrq->cmd->error = -ENOMEDIUM;
1690 if (!mrq->data)
1691 break;
1692 /* fall through */
1693 case STATE_SENDING_DATA:
1694 mrq->data->error = -ENOMEDIUM;
1695 dw_mci_stop_dma(host);
1696 break;
1697 case STATE_DATA_BUSY:
1698 case STATE_DATA_ERROR:
1699 if (mrq->data->error == -EINPROGRESS)
1700 mrq->data->error = -ENOMEDIUM;
1701 if (!mrq->stop)
1702 break;
1703 /* fall through */
1704 case STATE_SENDING_STOP:
1705 mrq->stop->error = -ENOMEDIUM;
1706 break;
1707 }
1708
1709 dw_mci_request_end(host, mrq);
1710 } else {
1711 list_del(&slot->queue_node);
1712 mrq->cmd->error = -ENOMEDIUM;
1713 if (mrq->data)
1714 mrq->data->error = -ENOMEDIUM;
1715 if (mrq->stop)
1716 mrq->stop->error = -ENOMEDIUM;
1717
1718 spin_unlock(&host->lock);
1719 mmc_request_done(slot->mmc, mrq);
1720 spin_lock(&host->lock);
1721 }
1722 }
1723
1724 /* Power down slot */
1725 if (present == 0) {
f95f3850
WN		 1726 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1727
1728 /*
1729 * Clear down the FIFO - doing so generates a
1730 * block interrupt, hence setting the
1731 * scatter-gather pointer to NULL.
1732 */
f9c2a0dc 1733 sg_miter_stop(&host->sg_miter);
f95f3850
WN		 1734 host->sg = NULL;
1735
1736 ctrl = mci_readl(host, CTRL);
1737 ctrl |= SDMMC_CTRL_FIFO_RESET;
1738 mci_writel(host, CTRL, ctrl);
1739
1740#ifdef CONFIG_MMC_DW_IDMAC
1741 ctrl = mci_readl(host, BMOD);
141a712a
SJ		 1742 /* Software reset of DMA */
1743 ctrl |= SDMMC_IDMAC_SWRESET;
f95f3850
WN		 1744 mci_writel(host, BMOD, ctrl);
1745#endif
1746
1747 }
1748
1791b13e
JH		 1749 spin_unlock_bh(&host->lock);
1750
1751 /* Power down slot (after spin_unlock, may sleep) */
1752 if (present == 0 && host->pdata->setpower)
1753 host->pdata->setpower(slot->id, 0);
1754
f95f3850
WN		 1755 present = dw_mci_get_cd(mmc);
1756 }
1757
1758 mmc_detect_change(slot->mmc,
1759 msecs_to_jiffies(host->pdata->detect_delay_ms));
1760 }
1761}
1762
1763static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)
1764{
1765 struct mmc_host *mmc;
1766 struct dw_mci_slot *slot;
1767
62ca8034 1768 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), &host->dev);
f95f3850
WN		 1769 if (!mmc)
1770 return -ENOMEM;
1771
1772 slot = mmc_priv(mmc);
1773 slot->id = id;
1774 slot->mmc = mmc;
1775 slot->host = host;
1776
1777 mmc->ops = &dw_mci_ops;
1778 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510);
1779 mmc->f_max = host->bus_hz;
1780
1781 if (host->pdata->get_ocr)
1782 mmc->ocr_avail = host->pdata->get_ocr(id);
1783 else
1784 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1785
1786 /*
1787 * Start with slot power disabled, it will be enabled when a card
1788 * is detected.
1789 */
1790 if (host->pdata->setpower)
1791 host->pdata->setpower(id, 0);
1792
fc3d7720
JC		 1793 if (host->pdata->caps)
1794 mmc->caps = host->pdata->caps;
fc3d7720 1795
4f408cc6
SJ		 1796 if (host->pdata->caps2)
1797 mmc->caps2 = host->pdata->caps2;
4f408cc6 1798
f95f3850
WN		 1799 if (host->pdata->get_bus_wd)
1800 if (host->pdata->get_bus_wd(slot->id) >= 4)
1801 mmc->caps |= MMC_CAP_4_BIT_DATA;
1802
1803 if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED)
6daa7778 1804 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
f95f3850 1805
356ac2cf
JC		 1806 if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY)
1807 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT;
1808 else
1809 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE;
1810
f95f3850
WN		 1811 if (host->pdata->blk_settings) {
1812 mmc->max_segs = host->pdata->blk_settings->max_segs;
1813 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
1814 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
1815 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
1816 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
1817 } else {
1818 /* Useful defaults if platform data is unset. */
a39e5746
JC		 1819#ifdef CONFIG_MMC_DW_IDMAC
1820 mmc->max_segs = host->ring_size;
1821 mmc->max_blk_size = 65536;
1822 mmc->max_blk_count = host->ring_size;
1823 mmc->max_seg_size = 0x1000;
1824 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
1825#else
f95f3850
WN		 1826 mmc->max_segs = 64;
1827 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
1828 mmc->max_blk_count = 512;
1829 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1830 mmc->max_seg_size = mmc->max_req_size;
f95f3850 1831#endif /* CONFIG_MMC_DW_IDMAC */
a39e5746 1832 }
f95f3850 1833
c07946a3
JC		 1834 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
1835 if (IS_ERR(host->vmmc)) {
a3c76eb9 1836 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
c07946a3
JC		 1837 host->vmmc = NULL;
1838 } else
1839 regulator_enable(host->vmmc);
1840
f95f3850
WN		 1841 if (dw_mci_get_cd(mmc))
1842 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1843 else
1844 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1845
1846 host->slot[id] = slot;
1847 mmc_add_host(mmc);
1848
1849#if defined(CONFIG_DEBUG_FS)
1850 dw_mci_init_debugfs(slot);
1851#endif
1852
1853 /* Card initially undetected */
1854 slot->last_detect_state = 0;
1855
dd6c4b98
WN		 1856 /*
1857 * Card may have been plugged in prior to boot so we
1858 * need to run the detect tasklet
1859 */
95dcc2cb 1860 queue_work(host->card_workqueue, &host->card_work);
dd6c4b98 1861
f95f3850
WN		 1862 return 0;
1863}
1864
1865static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
1866{
1867 /* Shutdown detect IRQ */
1868 if (slot->host->pdata->exit)
1869 slot->host->pdata->exit(id);
1870
1871 /* Debugfs stuff is cleaned up by mmc core */
1872 mmc_remove_host(slot->mmc);
1873 slot->host->slot[id] = NULL;
1874 mmc_free_host(slot->mmc);
1875}
1876
1877static void dw_mci_init_dma(struct dw_mci *host)
1878{
1879 /* Alloc memory for sg translation */
62ca8034 1880 host->sg_cpu = dma_alloc_coherent(&host->dev, PAGE_SIZE,
f95f3850
WN		 1881 &host->sg_dma, GFP_KERNEL);
1882 if (!host->sg_cpu) {
62ca8034 1883 dev_err(&host->dev, "%s: could not alloc DMA memory\n",
f95f3850
WN		 1884 __func__);
1885 goto no_dma;
1886 }
1887
1888 /* Determine which DMA interface to use */
1889#ifdef CONFIG_MMC_DW_IDMAC
1890 host->dma_ops = &dw_mci_idmac_ops;
f95f3850
WN		 1891#endif
1892
1893 if (!host->dma_ops)
1894 goto no_dma;
1895
e1631f98
JC		 1896 if (host->dma_ops->init && host->dma_ops->start &&
1897 host->dma_ops->stop && host->dma_ops->cleanup) {
f95f3850 1898 if (host->dma_ops->init(host)) {
62ca8034 1899 dev_err(&host->dev, "%s: Unable to initialize "
f95f3850
WN		 1900 "DMA Controller.\n", __func__);
1901 goto no_dma;
1902 }
1903 } else {
62ca8034 1904 dev_err(&host->dev, "DMA initialization not found.\n");
f95f3850
WN		 1905 goto no_dma;
1906 }
1907
1908 host->use_dma = 1;
1909 return;
1910
1911no_dma:
62ca8034 1912 dev_info(&host->dev, "Using PIO mode.\n");
f95f3850
WN		 1913 host->use_dma = 0;
1914 return;
1915}
1916
1917static bool mci_wait_reset(struct device *dev, struct dw_mci *host)
1918{
1919 unsigned long timeout = jiffies + msecs_to_jiffies(500);
1920 unsigned int ctrl;
1921
1922 mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1923 SDMMC_CTRL_DMA_RESET));
1924
1925 /* wait till resets clear */
1926 do {
1927 ctrl = mci_readl(host, CTRL);
1928 if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1929 SDMMC_CTRL_DMA_RESET)))
1930 return true;
1931 } while (time_before(jiffies, timeout));
1932
1933 dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl);
1934
1935 return false;
1936}
1937
62ca8034 1938int dw_mci_probe(struct dw_mci *host)
f95f3850 1939{
62ca8034 1940 int width, i, ret = 0;
f95f3850
WN		 1941 u32 fifo_size;
1942
62ca8034
SH		 1943 if (!host->pdata || !host->pdata->init) {
1944 dev_err(&host->dev,
f95f3850 1945 "Platform data must supply init function\n");
62ca8034 1946 return -ENODEV;
f95f3850
WN		 1947 }
1948
62ca8034
SH		 1949 if (!host->pdata->select_slot && host->pdata->num_slots > 1) {
1950 dev_err(&host->dev,
f95f3850 1951 "Platform data must supply select_slot function\n");
62ca8034 1952 return -ENODEV;
f95f3850
WN		 1953 }
1954
62ca8034
SH		 1955 if (!host->pdata->bus_hz) {
1956 dev_err(&host->dev,
f95f3850 1957 "Platform data must supply bus speed\n");
62ca8034 1958 return -ENODEV;
f95f3850
WN		 1959 }
1960
62ca8034
SH		 1961 host->bus_hz = host->pdata->bus_hz;
1962 host->quirks = host->pdata->quirks;
f95f3850
WN		 1963
1964 spin_lock_init(&host->lock);
1965 INIT_LIST_HEAD(&host->queue);
1966
f95f3850
WN		 1967 /*
1968 * Get the host data width - this assumes that HCON has been set with
1969 * the correct values.
1970 */
1971 i = (mci_readl(host, HCON) >> 7) & 0x7;
1972 if (!i) {
1973 host->push_data = dw_mci_push_data16;
1974 host->pull_data = dw_mci_pull_data16;
1975 width = 16;
1976 host->data_shift = 1;
1977 } else if (i == 2) {
1978 host->push_data = dw_mci_push_data64;
1979 host->pull_data = dw_mci_pull_data64;
1980 width = 64;
1981 host->data_shift = 3;
1982 } else {
1983 /* Check for a reserved value, and warn if it is */
1984 WARN((i != 1),
1985 "HCON reports a reserved host data width!\n"
1986 "Defaulting to 32-bit access.\n");
1987 host->push_data = dw_mci_push_data32;
1988 host->pull_data = dw_mci_pull_data32;
1989 width = 32;
1990 host->data_shift = 2;
1991 }
1992
1993 /* Reset all blocks */
141a712a
SJ		 1994 if (!mci_wait_reset(&host->dev, host))
1995 return -ENODEV;
1996
1997 host->dma_ops = host->pdata->dma_ops;
1998 dw_mci_init_dma(host);
f95f3850
WN		 1999
2000 /* Clear the interrupts for the host controller */
2001 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2002 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2003
2004 /* Put in max timeout */
2005 mci_writel(host, TMOUT, 0xFFFFFFFF);
2006
2007 /*
2008 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
2009 * Tx Mark = fifo_size / 2 DMA Size = 8
2010 */
b86d8253
JH		 2011 if (!host->pdata->fifo_depth) {
2012 /*
2013 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
2014 * have been overwritten by the bootloader, just like we're
2015 * about to do, so if you know the value for your hardware, you
2016 * should put it in the platform data.
2017 */
2018 fifo_size = mci_readl(host, FIFOTH);
8234e869 2019 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
b86d8253
JH		 2020 } else {
2021 fifo_size = host->pdata->fifo_depth;
2022 }
2023 host->fifo_depth = fifo_size;
e61cf118
JC		 2024 host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) |
2025 ((fifo_size/2) << 0));
2026 mci_writel(host, FIFOTH, host->fifoth_val);
f95f3850
WN		 2027
2028 /* disable clock to CIU */
2029 mci_writel(host, CLKENA, 0);
2030 mci_writel(host, CLKSRC, 0);
2031
2032 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
95dcc2cb 2033 host->card_workqueue = alloc_workqueue("dw-mci-card",
1791b13e 2034 WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
95dcc2cb 2035 if (!host->card_workqueue)
1791b13e
JH		 2036 goto err_dmaunmap;
2037 INIT_WORK(&host->card_work, dw_mci_work_routine_card);
62ca8034 2038 ret = request_irq(host->irq, dw_mci_interrupt, host->irq_flags, "dw-mci", host);
f95f3850 2039 if (ret)
1791b13e 2040 goto err_workqueue;
f95f3850 2041
f95f3850
WN		 2042 if (host->pdata->num_slots)
2043 host->num_slots = host->pdata->num_slots;
2044 else
2045 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
2046
2047 /* We need at least one slot to succeed */
2048 for (i = 0; i < host->num_slots; i++) {
2049 ret = dw_mci_init_slot(host, i);
2050 if (ret) {
2051 ret = -ENODEV;
2052 goto err_init_slot;
2053 }
2054 }
2055
4e0a5adf
JC		 2056 /*
2057 * In 2.40a spec, Data offset is changed.
2058 * Need to check the version-id and set data-offset for DATA register.
2059 */
2060 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
62ca8034 2061 dev_info(&host->dev, "Version ID is %04x\n", host->verid);
4e0a5adf
JC		 2062
2063 if (host->verid < DW_MMC_240A)
2064 host->data_offset = DATA_OFFSET;
2065 else
2066 host->data_offset = DATA_240A_OFFSET;
2067
f95f3850
WN		 2068 /*
2069 * Enable interrupts for command done, data over, data empty, card det,
2070 * receive ready and error such as transmit, receive timeout, crc error
2071 */
2072 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2073 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2074 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2075 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2076 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
2077
62ca8034 2078 dev_info(&host->dev, "DW MMC controller at irq %d, "
b86d8253
JH		 2079 "%d bit host data width, "
2080 "%u deep fifo\n",
62ca8034 2081 host->irq, width, fifo_size);
f95f3850 2082 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
62ca8034 2083 dev_info(&host->dev, "Internal DMAC interrupt fix enabled.\n");
f95f3850
WN		 2084
2085 return 0;
2086
2087err_init_slot:
2088 /* De-init any initialized slots */
2089 while (i > 0) {
2090 if (host->slot[i])
2091 dw_mci_cleanup_slot(host->slot[i], i);
2092 i--;
2093 }
62ca8034 2094 free_irq(host->irq, host);
f95f3850 2095
1791b13e 2096err_workqueue:
95dcc2cb 2097 destroy_workqueue(host->card_workqueue);
1791b13e 2098
f95f3850
WN		 2099err_dmaunmap:
2100 if (host->use_dma && host->dma_ops->exit)
2101 host->dma_ops->exit(host);
62ca8034 2102 dma_free_coherent(&host->dev, PAGE_SIZE,
f95f3850 2103 host->sg_cpu, host->sg_dma);
f95f3850 2104
c07946a3
JC		 2105 if (host->vmmc) {
2106 regulator_disable(host->vmmc);
2107 regulator_put(host->vmmc);
2108 }
f95f3850
WN		 2109 return ret;
2110}
62ca8034 2111EXPORT_SYMBOL(dw_mci_probe);
f95f3850 2112
62ca8034 2113void dw_mci_remove(struct dw_mci *host)
f95f3850 2114{
f95f3850
WN		 2115 int i;
2116
2117 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2118 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2119
f95f3850 2120 for (i = 0; i < host->num_slots; i++) {
62ca8034 2121 dev_dbg(&host->dev, "remove slot %d\n", i);
f95f3850
WN		 2122 if (host->slot[i])
2123 dw_mci_cleanup_slot(host->slot[i], i);
2124 }
2125
2126 /* disable clock to CIU */
2127 mci_writel(host, CLKENA, 0);
2128 mci_writel(host, CLKSRC, 0);
2129
62ca8034 2130 free_irq(host->irq, host);
95dcc2cb 2131 destroy_workqueue(host->card_workqueue);
62ca8034 2132 dma_free_coherent(&host->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
f95f3850
WN		 2133
2134 if (host->use_dma && host->dma_ops->exit)
2135 host->dma_ops->exit(host);
2136
c07946a3
JC		 2137 if (host->vmmc) {
2138 regulator_disable(host->vmmc);
2139 regulator_put(host->vmmc);
2140 }
2141
f95f3850 2142}
62ca8034
SH		 2143EXPORT_SYMBOL(dw_mci_remove);
2144
2145
f95f3850 2146
6fe8890d 2147#ifdef CONFIG_PM_SLEEP
f95f3850
WN		 2148/*
2149 * TODO: we should probably disable the clock to the card in the suspend path.
2150 */
62ca8034 2151int dw_mci_suspend(struct dw_mci *host)
f95f3850 2152{
62ca8034 2153 int i, ret = 0;
f95f3850
WN		 2154
2155 for (i = 0; i < host->num_slots; i++) {
2156 struct dw_mci_slot *slot = host->slot[i];
2157 if (!slot)
2158 continue;
2159 ret = mmc_suspend_host(slot->mmc);
2160 if (ret < 0) {
2161 while (--i >= 0) {
2162 slot = host->slot[i];
2163 if (slot)
2164 mmc_resume_host(host->slot[i]->mmc);
2165 }
2166 return ret;
2167 }
2168 }
2169
c07946a3
JC		 2170 if (host->vmmc)
2171 regulator_disable(host->vmmc);
2172
f95f3850
WN		 2173 return 0;
2174}
62ca8034 2175EXPORT_SYMBOL(dw_mci_suspend);
f95f3850 2176
62ca8034 2177int dw_mci_resume(struct dw_mci *host)
f95f3850
WN		 2178{
2179 int i, ret;
f95f3850 2180
1d6c4e0a
JC		 2181 if (host->vmmc)
2182 regulator_enable(host->vmmc);
2183
62ca8034 2184 if (!mci_wait_reset(&host->dev, host)) {
e61cf118
JC		 2185 ret = -ENODEV;
2186 return ret;
2187 }
2188
3bfe619d 2189 if (host->use_dma && host->dma_ops->init)
141a712a
SJ		 2190 host->dma_ops->init(host);
2191
e61cf118
JC		 2192 /* Restore the old value at FIFOTH register */
2193 mci_writel(host, FIFOTH, host->fifoth_val);
2194
2195 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2196 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2197 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2198 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2199 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2200
f95f3850
WN		 2201 for (i = 0; i < host->num_slots; i++) {
2202 struct dw_mci_slot *slot = host->slot[i];
2203 if (!slot)
2204 continue;
2205 ret = mmc_resume_host(host->slot[i]->mmc);
2206 if (ret < 0)
2207 return ret;
2208 }
f95f3850
WN		 2209 return 0;
2210}
62ca8034 2211EXPORT_SYMBOL(dw_mci_resume);
6fe8890d
JC		 2212#endif /* CONFIG_PM_SLEEP */
2213
f95f3850
WN		 2214static int __init dw_mci_init(void)
2215{
62ca8034
SH		 2216 printk(KERN_INFO "Synopsys Designware Multimedia Card Interface Driver");
2217 return 0;
f95f3850
WN		 2218}
2219
2220static void __exit dw_mci_exit(void)
2221{
f95f3850
WN		 2222}
2223
2224module_init(dw_mci_init);
2225module_exit(dw_mci_exit);
2226
2227MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
2228MODULE_AUTHOR("NXP Semiconductor VietNam");
2229MODULE_AUTHOR("Imagination Technologies Ltd");
2230MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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