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mmc: dw_mmc: Add "disable-wp" device tree property
[deliverable/linux.git] / drivers / mmc / host / dw_mmc.c
CommitLineData
f95f3850
WN		 1/*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/blkdev.h>
15#include <linux/clk.h>
16#include <linux/debugfs.h>
17#include <linux/device.h>
18#include <linux/dma-mapping.h>
19#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/ioport.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
f95f3850
WN		 25#include <linux/seq_file.h>
26#include <linux/slab.h>
27#include <linux/stat.h>
28#include <linux/delay.h>
29#include <linux/irq.h>
30#include <linux/mmc/host.h>
31#include <linux/mmc/mmc.h>
32#include <linux/mmc/dw_mmc.h>
33#include <linux/bitops.h>
c07946a3 34#include <linux/regulator/consumer.h>
1791b13e 35#include <linux/workqueue.h>
c91eab4b 36#include <linux/of.h>
f95f3850
WN		 37
38#include "dw_mmc.h"
39
40/* Common flag combinations */
41#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \
42 SDMMC_INT_HTO | SDMMC_INT_SBE | \
43 SDMMC_INT_EBE)
44#define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
45 SDMMC_INT_RESP_ERR)
46#define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
47 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
48#define DW_MCI_SEND_STATUS 1
49#define DW_MCI_RECV_STATUS 2
50#define DW_MCI_DMA_THRESHOLD 16
51
52#ifdef CONFIG_MMC_DW_IDMAC
53struct idmac_desc {
54 u32 des0; /* Control Descriptor */
55#define IDMAC_DES0_DIC BIT(1)
56#define IDMAC_DES0_LD BIT(2)
57#define IDMAC_DES0_FD BIT(3)
58#define IDMAC_DES0_CH BIT(4)
59#define IDMAC_DES0_ER BIT(5)
60#define IDMAC_DES0_CES BIT(30)
61#define IDMAC_DES0_OWN BIT(31)
62
63 u32 des1; /* Buffer sizes */
64#define IDMAC_SET_BUFFER1_SIZE(d, s) \
9b7bbe10 65 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
f95f3850
WN		 66
67 u32 des2; /* buffer 1 physical address */
68
69 u32 des3; /* buffer 2 physical address */
70};
71#endif /* CONFIG_MMC_DW_IDMAC */
72
73/**
74 * struct dw_mci_slot - MMC slot state
75 * @mmc: The mmc_host representing this slot.
76 * @host: The MMC controller this slot is using.
a70aaa64 77 * @quirks: Slot-level quirks (DW_MCI_SLOT_QUIRK_XXX)
f95f3850
WN		 78 * @ctype: Card type for this slot.
79 * @mrq: mmc_request currently being processed or waiting to be
80 * processed, or NULL when the slot is idle.
81 * @queue_node: List node for placing this node in the @queue list of
82 * &struct dw_mci.
83 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
84 * @flags: Random state bits associated with the slot.
85 * @id: Number of this slot.
86 * @last_detect_state: Most recently observed card detect state.
87 */
88struct dw_mci_slot {
89 struct mmc_host *mmc;
90 struct dw_mci *host;
91
a70aaa64
DA		 92 int quirks;
93
f95f3850
WN		 94 u32 ctype;
95
96 struct mmc_request *mrq;
97 struct list_head queue_node;
98
99 unsigned int clock;
100 unsigned long flags;
101#define DW_MMC_CARD_PRESENT 0
102#define DW_MMC_CARD_NEED_INIT 1
103 int id;
104 int last_detect_state;
105};
106
107#if defined(CONFIG_DEBUG_FS)
108static int dw_mci_req_show(struct seq_file *s, void *v)
109{
110 struct dw_mci_slot *slot = s->private;
111 struct mmc_request *mrq;
112 struct mmc_command *cmd;
113 struct mmc_command *stop;
114 struct mmc_data *data;
115
116 /* Make sure we get a consistent snapshot */
117 spin_lock_bh(&slot->host->lock);
118 mrq = slot->mrq;
119
120 if (mrq) {
121 cmd = mrq->cmd;
122 data = mrq->data;
123 stop = mrq->stop;
124
125 if (cmd)
126 seq_printf(s,
127 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
128 cmd->opcode, cmd->arg, cmd->flags,
129 cmd->resp[0], cmd->resp[1], cmd->resp[2],
130 cmd->resp[2], cmd->error);
131 if (data)
132 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
133 data->bytes_xfered, data->blocks,
134 data->blksz, data->flags, data->error);
135 if (stop)
136 seq_printf(s,
137 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
138 stop->opcode, stop->arg, stop->flags,
139 stop->resp[0], stop->resp[1], stop->resp[2],
140 stop->resp[2], stop->error);
141 }
142
143 spin_unlock_bh(&slot->host->lock);
144
145 return 0;
146}
147
148static int dw_mci_req_open(struct inode *inode, struct file *file)
149{
150 return single_open(file, dw_mci_req_show, inode->i_private);
151}
152
153static const struct file_operations dw_mci_req_fops = {
154 .owner = THIS_MODULE,
155 .open = dw_mci_req_open,
156 .read = seq_read,
157 .llseek = seq_lseek,
158 .release = single_release,
159};
160
161static int dw_mci_regs_show(struct seq_file *s, void *v)
162{
163 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
164 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
165 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
166 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
167 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
168 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
169
170 return 0;
171}
172
173static int dw_mci_regs_open(struct inode *inode, struct file *file)
174{
175 return single_open(file, dw_mci_regs_show, inode->i_private);
176}
177
178static const struct file_operations dw_mci_regs_fops = {
179 .owner = THIS_MODULE,
180 .open = dw_mci_regs_open,
181 .read = seq_read,
182 .llseek = seq_lseek,
183 .release = single_release,
184};
185
186static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
187{
188 struct mmc_host *mmc = slot->mmc;
189 struct dw_mci *host = slot->host;
190 struct dentry *root;
191 struct dentry *node;
192
193 root = mmc->debugfs_root;
194 if (!root)
195 return;
196
197 node = debugfs_create_file("regs", S_IRUSR, root, host,
198 &dw_mci_regs_fops);
199 if (!node)
200 goto err;
201
202 node = debugfs_create_file("req", S_IRUSR, root, slot,
203 &dw_mci_req_fops);
204 if (!node)
205 goto err;
206
207 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
208 if (!node)
209 goto err;
210
211 node = debugfs_create_x32("pending_events", S_IRUSR, root,
212 (u32 *)&host->pending_events);
213 if (!node)
214 goto err;
215
216 node = debugfs_create_x32("completed_events", S_IRUSR, root,
217 (u32 *)&host->completed_events);
218 if (!node)
219 goto err;
220
221 return;
222
223err:
224 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
225}
226#endif /* defined(CONFIG_DEBUG_FS) */
227
228static void dw_mci_set_timeout(struct dw_mci *host)
229{
230 /* timeout (maximum) */
231 mci_writel(host, TMOUT, 0xffffffff);
232}
233
234static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
235{
236 struct mmc_data *data;
800d78bf 237 struct dw_mci_slot *slot = mmc_priv(mmc);
e95baf13 238 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
f95f3850
WN		 239 u32 cmdr;
240 cmd->error = -EINPROGRESS;
241
242 cmdr = cmd->opcode;
243
244 if (cmdr == MMC_STOP_TRANSMISSION)
245 cmdr |= SDMMC_CMD_STOP;
246 else
247 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
248
249 if (cmd->flags & MMC_RSP_PRESENT) {
250 /* We expect a response, so set this bit */
251 cmdr |= SDMMC_CMD_RESP_EXP;
252 if (cmd->flags & MMC_RSP_136)
253 cmdr |= SDMMC_CMD_RESP_LONG;
254 }
255
256 if (cmd->flags & MMC_RSP_CRC)
257 cmdr |= SDMMC_CMD_RESP_CRC;
258
259 data = cmd->data;
260 if (data) {
261 cmdr |= SDMMC_CMD_DAT_EXP;
262 if (data->flags & MMC_DATA_STREAM)
263 cmdr |= SDMMC_CMD_STRM_MODE;
264 if (data->flags & MMC_DATA_WRITE)
265 cmdr |= SDMMC_CMD_DAT_WR;
266 }
267
cb27a843
JH		 268 if (drv_data && drv_data->prepare_command)
269 drv_data->prepare_command(slot->host, &cmdr);
800d78bf 270
f95f3850
WN		 271 return cmdr;
272}
273
274static void dw_mci_start_command(struct dw_mci *host,
275 struct mmc_command *cmd, u32 cmd_flags)
276{
277 host->cmd = cmd;
4a90920c 278 dev_vdbg(host->dev,
f95f3850
WN		 279 "start command: ARGR=0x%08x CMDR=0x%08x\n",
280 cmd->arg, cmd_flags);
281
282 mci_writel(host, CMDARG, cmd->arg);
283 wmb();
284
285 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
286}
287
288static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
289{
290 dw_mci_start_command(host, data->stop, host->stop_cmdr);
291}
292
293/* DMA interface functions */
294static void dw_mci_stop_dma(struct dw_mci *host)
295{
03e8cb53 296 if (host->using_dma) {
f95f3850
WN		 297 host->dma_ops->stop(host);
298 host->dma_ops->cleanup(host);
299 } else {
300 /* Data transfer was stopped by the interrupt handler */
301 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
302 }
303}
304
9aa51408
SJ		 305static int dw_mci_get_dma_dir(struct mmc_data *data)
306{
307 if (data->flags & MMC_DATA_WRITE)
308 return DMA_TO_DEVICE;
309 else
310 return DMA_FROM_DEVICE;
311}
312
9beee912 313#ifdef CONFIG_MMC_DW_IDMAC
f95f3850
WN		 314static void dw_mci_dma_cleanup(struct dw_mci *host)
315{
316 struct mmc_data *data = host->data;
317
318 if (data)
9aa51408 319 if (!data->host_cookie)
4a90920c 320 dma_unmap_sg(host->dev,
9aa51408
SJ		 321 data->sg,
322 data->sg_len,
323 dw_mci_get_dma_dir(data));
f95f3850
WN		 324}
325
326static void dw_mci_idmac_stop_dma(struct dw_mci *host)
327{
328 u32 temp;
329
330 /* Disable and reset the IDMAC interface */
331 temp = mci_readl(host, CTRL);
332 temp &= ~SDMMC_CTRL_USE_IDMAC;
333 temp |= SDMMC_CTRL_DMA_RESET;
334 mci_writel(host, CTRL, temp);
335
336 /* Stop the IDMAC running */
337 temp = mci_readl(host, BMOD);
a5289a43 338 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
f95f3850
WN		 339 mci_writel(host, BMOD, temp);
340}
341
342static void dw_mci_idmac_complete_dma(struct dw_mci *host)
343{
344 struct mmc_data *data = host->data;
345
4a90920c 346 dev_vdbg(host->dev, "DMA complete\n");
f95f3850
WN		 347
348 host->dma_ops->cleanup(host);
349
350 /*
351 * If the card was removed, data will be NULL. No point in trying to
352 * send the stop command or waiting for NBUSY in this case.
353 */
354 if (data) {
355 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
356 tasklet_schedule(&host->tasklet);
357 }
358}
359
360static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
361 unsigned int sg_len)
362{
363 int i;
364 struct idmac_desc *desc = host->sg_cpu;
365
366 for (i = 0; i < sg_len; i++, desc++) {
367 unsigned int length = sg_dma_len(&data->sg[i]);
368 u32 mem_addr = sg_dma_address(&data->sg[i]);
369
370 /* Set the OWN bit and disable interrupts for this descriptor */
371 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
372
373 /* Buffer length */
374 IDMAC_SET_BUFFER1_SIZE(desc, length);
375
376 /* Physical address to DMA to/from */
377 desc->des2 = mem_addr;
378 }
379
380 /* Set first descriptor */
381 desc = host->sg_cpu;
382 desc->des0 |= IDMAC_DES0_FD;
383
384 /* Set last descriptor */
385 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
386 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
387 desc->des0 |= IDMAC_DES0_LD;
388
389 wmb();
390}
391
392static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
393{
394 u32 temp;
395
396 dw_mci_translate_sglist(host, host->data, sg_len);
397
398 /* Select IDMAC interface */
399 temp = mci_readl(host, CTRL);
400 temp |= SDMMC_CTRL_USE_IDMAC;
401 mci_writel(host, CTRL, temp);
402
403 wmb();
404
405 /* Enable the IDMAC */
406 temp = mci_readl(host, BMOD);
a5289a43 407 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
f95f3850
WN		 408 mci_writel(host, BMOD, temp);
409
410 /* Start it running */
411 mci_writel(host, PLDMND, 1);
412}
413
414static int dw_mci_idmac_init(struct dw_mci *host)
415{
416 struct idmac_desc *p;
897b69e7 417 int i;
f95f3850
WN		 418
419 /* Number of descriptors in the ring buffer */
420 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
421
422 /* Forward link the descriptor list */
423 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
424 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
425
426 /* Set the last descriptor as the end-of-ring descriptor */
427 p->des3 = host->sg_dma;
428 p->des0 = IDMAC_DES0_ER;
429
141a712a
SJ		 430 mci_writel(host, BMOD, SDMMC_IDMAC_SWRESET);
431
f95f3850
WN		 432 /* Mask out interrupts - get Tx & Rx complete only */
433 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
434 SDMMC_IDMAC_INT_TI);
435
436 /* Set the descriptor base address */
437 mci_writel(host, DBADDR, host->sg_dma);
438 return 0;
439}
440
8e2b36ea 441static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
885c3e80
SJ		 442 .init = dw_mci_idmac_init,
443 .start = dw_mci_idmac_start_dma,
444 .stop = dw_mci_idmac_stop_dma,
445 .complete = dw_mci_idmac_complete_dma,
446 .cleanup = dw_mci_dma_cleanup,
447};
448#endif /* CONFIG_MMC_DW_IDMAC */
449
9aa51408
SJ		 450static int dw_mci_pre_dma_transfer(struct dw_mci *host,
451 struct mmc_data *data,
452 bool next)
f95f3850
WN		 453{
454 struct scatterlist *sg;
9aa51408 455 unsigned int i, sg_len;
03e8cb53 456
9aa51408
SJ		 457 if (!next && data->host_cookie)
458 return data->host_cookie;
f95f3850
WN		 459
460 /*
461 * We don't do DMA on "complex" transfers, i.e. with
462 * non-word-aligned buffers or lengths. Also, we don't bother
463 * with all the DMA setup overhead for short transfers.
464 */
465 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
466 return -EINVAL;
9aa51408 467
f95f3850
WN		 468 if (data->blksz & 3)
469 return -EINVAL;
470
471 for_each_sg(data->sg, sg, data->sg_len, i) {
472 if (sg->offset & 3 || sg->length & 3)
473 return -EINVAL;
474 }
475
4a90920c 476 sg_len = dma_map_sg(host->dev,
9aa51408
SJ		 477 data->sg,
478 data->sg_len,
479 dw_mci_get_dma_dir(data));
480 if (sg_len == 0)
481 return -EINVAL;
03e8cb53 482
9aa51408
SJ		 483 if (next)
484 data->host_cookie = sg_len;
f95f3850 485
9aa51408
SJ		 486 return sg_len;
487}
488
9aa51408
SJ		 489static void dw_mci_pre_req(struct mmc_host *mmc,
490 struct mmc_request *mrq,
491 bool is_first_req)
492{
493 struct dw_mci_slot *slot = mmc_priv(mmc);
494 struct mmc_data *data = mrq->data;
495
496 if (!slot->host->use_dma || !data)
497 return;
498
499 if (data->host_cookie) {
500 data->host_cookie = 0;
501 return;
502 }
503
504 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
505 data->host_cookie = 0;
506}
507
508static void dw_mci_post_req(struct mmc_host *mmc,
509 struct mmc_request *mrq,
510 int err)
511{
512 struct dw_mci_slot *slot = mmc_priv(mmc);
513 struct mmc_data *data = mrq->data;
514
515 if (!slot->host->use_dma || !data)
516 return;
517
518 if (data->host_cookie)
4a90920c 519 dma_unmap_sg(slot->host->dev,
9aa51408
SJ		 520 data->sg,
521 data->sg_len,
522 dw_mci_get_dma_dir(data));
523 data->host_cookie = 0;
524}
525
526static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
527{
528 int sg_len;
529 u32 temp;
530
531 host->using_dma = 0;
532
533 /* If we don't have a channel, we can't do DMA */
534 if (!host->use_dma)
535 return -ENODEV;
536
537 sg_len = dw_mci_pre_dma_transfer(host, data, 0);
a99aa9b9
SJ		 538 if (sg_len < 0) {
539 host->dma_ops->stop(host);
9aa51408 540 return sg_len;
a99aa9b9 541 }
9aa51408
SJ		 542
543 host->using_dma = 1;
f95f3850 544
4a90920c 545 dev_vdbg(host->dev,
f95f3850
WN		 546 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
547 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
548 sg_len);
549
550 /* Enable the DMA interface */
551 temp = mci_readl(host, CTRL);
552 temp |= SDMMC_CTRL_DMA_ENABLE;
553 mci_writel(host, CTRL, temp);
554
555 /* Disable RX/TX IRQs, let DMA handle it */
556 temp = mci_readl(host, INTMASK);
557 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
558 mci_writel(host, INTMASK, temp);
559
560 host->dma_ops->start(host, sg_len);
561
562 return 0;
563}
564
565static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
566{
567 u32 temp;
568
569 data->error = -EINPROGRESS;
570
571 WARN_ON(host->data);
572 host->sg = NULL;
573 host->data = data;
574
55c5efbc
JH		 575 if (data->flags & MMC_DATA_READ)
576 host->dir_status = DW_MCI_RECV_STATUS;
577 else
578 host->dir_status = DW_MCI_SEND_STATUS;
579
f95f3850 580 if (dw_mci_submit_data_dma(host, data)) {
f9c2a0dc
SJ		 581 int flags = SG_MITER_ATOMIC;
582 if (host->data->flags & MMC_DATA_READ)
583 flags |= SG_MITER_TO_SG;
584 else
585 flags |= SG_MITER_FROM_SG;
586
587 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
f95f3850 588 host->sg = data->sg;
34b664a2
JH		 589 host->part_buf_start = 0;
590 host->part_buf_count = 0;
f95f3850 591
b40af3aa 592 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
f95f3850
WN		 593 temp = mci_readl(host, INTMASK);
594 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
595 mci_writel(host, INTMASK, temp);
596
597 temp = mci_readl(host, CTRL);
598 temp &= ~SDMMC_CTRL_DMA_ENABLE;
599 mci_writel(host, CTRL, temp);
600 }
601}
602
603static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
604{
605 struct dw_mci *host = slot->host;
606 unsigned long timeout = jiffies + msecs_to_jiffies(500);
607 unsigned int cmd_status = 0;
608
609 mci_writel(host, CMDARG, arg);
610 wmb();
611 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
612
613 while (time_before(jiffies, timeout)) {
614 cmd_status = mci_readl(host, CMD);
615 if (!(cmd_status & SDMMC_CMD_START))
616 return;
617 }
618 dev_err(&slot->mmc->class_dev,
619 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
620 cmd, arg, cmd_status);
621}
622
ab269128 623static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
f95f3850
WN		 624{
625 struct dw_mci *host = slot->host;
626 u32 div;
9623b5b9 627 u32 clk_en_a;
f95f3850 628
ab269128 629 if (slot->clock != host->current_speed || force_clkinit) {
e419990b
SJ		 630 div = host->bus_hz / slot->clock;
631 if (host->bus_hz % slot->clock && host->bus_hz > slot->clock)
f95f3850
WN		 632 /*
633 * move the + 1 after the divide to prevent
634 * over-clocking the card.
635 */
e419990b
SJ		 636 div += 1;
637
638 div = (host->bus_hz != slot->clock) ? DIV_ROUND_UP(div, 2) : 0;
f95f3850
WN		 639
640 dev_info(&slot->mmc->class_dev,
641 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"
642 " div = %d)\n", slot->id, host->bus_hz, slot->clock,
643 div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div);
644
645 /* disable clock */
646 mci_writel(host, CLKENA, 0);
647 mci_writel(host, CLKSRC, 0);
648
649 /* inform CIU */
650 mci_send_cmd(slot,
651 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
652
653 /* set clock to desired speed */
654 mci_writel(host, CLKDIV, div);
655
656 /* inform CIU */
657 mci_send_cmd(slot,
658 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
659
9623b5b9
DA		 660 /* enable clock; only low power if no SDIO */
661 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
662 if (!(mci_readl(host, INTMASK) & SDMMC_INT_SDIO(slot->id)))
663 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
664 mci_writel(host, CLKENA, clk_en_a);
f95f3850
WN		 665
666 /* inform CIU */
667 mci_send_cmd(slot,
668 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
669
670 host->current_speed = slot->clock;
671 }
672
673 /* Set the current slot bus width */
1d56c453 674 mci_writel(host, CTYPE, (slot->ctype << slot->id));
f95f3850
WN		 675}
676
053b3ce6
SJ		 677static void __dw_mci_start_request(struct dw_mci *host,
678 struct dw_mci_slot *slot,
679 struct mmc_command *cmd)
f95f3850
WN		 680{
681 struct mmc_request *mrq;
f95f3850
WN		 682 struct mmc_data *data;
683 u32 cmdflags;
684
685 mrq = slot->mrq;
686 if (host->pdata->select_slot)
687 host->pdata->select_slot(slot->id);
688
f95f3850
WN		 689 host->cur_slot = slot;
690 host->mrq = mrq;
691
692 host->pending_events = 0;
693 host->completed_events = 0;
694 host->data_status = 0;
695
053b3ce6 696 data = cmd->data;
f95f3850
WN		 697 if (data) {
698 dw_mci_set_timeout(host);
699 mci_writel(host, BYTCNT, data->blksz*data->blocks);
700 mci_writel(host, BLKSIZ, data->blksz);
701 }
702
f95f3850
WN		 703 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
704
705 /* this is the first command, send the initialization clock */
706 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
707 cmdflags |= SDMMC_CMD_INIT;
708
709 if (data) {
710 dw_mci_submit_data(host, data);
711 wmb();
712 }
713
714 dw_mci_start_command(host, cmd, cmdflags);
715
716 if (mrq->stop)
717 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
718}
719
053b3ce6
SJ		 720static void dw_mci_start_request(struct dw_mci *host,
721 struct dw_mci_slot *slot)
722{
723 struct mmc_request *mrq = slot->mrq;
724 struct mmc_command *cmd;
725
726 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
727 __dw_mci_start_request(host, slot, cmd);
728}
729
7456caae 730/* must be called with host->lock held */
f95f3850
WN		 731static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
732 struct mmc_request *mrq)
733{
734 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
735 host->state);
736
f95f3850
WN		 737 slot->mrq = mrq;
738
739 if (host->state == STATE_IDLE) {
740 host->state = STATE_SENDING_CMD;
741 dw_mci_start_request(host, slot);
742 } else {
743 list_add_tail(&slot->queue_node, &host->queue);
744 }
f95f3850
WN		 745}
746
747static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
748{
749 struct dw_mci_slot *slot = mmc_priv(mmc);
750 struct dw_mci *host = slot->host;
751
752 WARN_ON(slot->mrq);
753
7456caae
JH		 754 /*
755 * The check for card presence and queueing of the request must be
756 * atomic, otherwise the card could be removed in between and the
757 * request wouldn't fail until another card was inserted.
758 */
759 spin_lock_bh(&host->lock);
760
f95f3850 761 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
7456caae 762 spin_unlock_bh(&host->lock);
f95f3850
WN		 763 mrq->cmd->error = -ENOMEDIUM;
764 mmc_request_done(mmc, mrq);
765 return;
766 }
767
f95f3850 768 dw_mci_queue_request(host, slot, mrq);
7456caae
JH		 769
770 spin_unlock_bh(&host->lock);
f95f3850
WN		 771}
772
773static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
774{
775 struct dw_mci_slot *slot = mmc_priv(mmc);
e95baf13 776 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
41babf75 777 u32 regs;
f95f3850 778
f95f3850 779 switch (ios->bus_width) {
f95f3850
WN		 780 case MMC_BUS_WIDTH_4:
781 slot->ctype = SDMMC_CTYPE_4BIT;
782 break;
c9b2a06f
JC		 783 case MMC_BUS_WIDTH_8:
784 slot->ctype = SDMMC_CTYPE_8BIT;
785 break;
b2f7cb45
JC		 786 default:
787 /* set default 1 bit mode */
788 slot->ctype = SDMMC_CTYPE_1BIT;
f95f3850
WN		 789 }
790
3f514291
SJ		 791 regs = mci_readl(slot->host, UHS_REG);
792
41babf75 793 /* DDR mode set */
3f514291 794 if (ios->timing == MMC_TIMING_UHS_DDR50)
41babf75 795 regs |= (0x1 << slot->id) << 16;
3f514291
SJ		 796 else
797 regs &= ~(0x1 << slot->id) << 16;
798
799 mci_writel(slot->host, UHS_REG, regs);
41babf75 800
f95f3850
WN		 801 if (ios->clock) {
802 /*
803 * Use mirror of ios->clock to prevent race with mmc
804 * core ios update when finding the minimum.
805 */
806 slot->clock = ios->clock;
807 }
808
cb27a843
JH		 809 if (drv_data && drv_data->set_ios)
810 drv_data->set_ios(slot->host, ios);
800d78bf 811
bf7cb224
JC		 812 /* Slot specific timing and width adjustment */
813 dw_mci_setup_bus(slot, false);
814
f95f3850
WN		 815 switch (ios->power_mode) {
816 case MMC_POWER_UP:
817 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
818 break;
819 default:
820 break;
821 }
822}
823
824static int dw_mci_get_ro(struct mmc_host *mmc)
825{
826 int read_only;
827 struct dw_mci_slot *slot = mmc_priv(mmc);
828 struct dw_mci_board *brd = slot->host->pdata;
829
830 /* Use platform get_ro function, else try on board write protect */
a70aaa64
DA		 831
832 /*
833 * NOTE: DW_MCI_QUIRK_NO_WRITE_PROTECT will be removed in a future
834 * patch in the series once reference to it is removed.
835 */
836 if ((brd->quirks & DW_MCI_QUIRK_NO_WRITE_PROTECT) ||
837 (slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT))
b4967aa5
TA		 838 read_only = 0;
839 else if (brd->get_ro)
f95f3850
WN		 840 read_only = brd->get_ro(slot->id);
841 else
842 read_only =
843 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
844
845 dev_dbg(&mmc->class_dev, "card is %s\n",
846 read_only ? "read-only" : "read-write");
847
848 return read_only;
849}
850
851static int dw_mci_get_cd(struct mmc_host *mmc)
852{
853 int present;
854 struct dw_mci_slot *slot = mmc_priv(mmc);
855 struct dw_mci_board *brd = slot->host->pdata;
856
857 /* Use platform get_cd function, else try onboard card detect */
fc3d7720
JC		 858 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
859 present = 1;
860 else if (brd->get_cd)
f95f3850
WN		 861 present = !brd->get_cd(slot->id);
862 else
863 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
864 == 0 ? 1 : 0;
865
866 if (present)
867 dev_dbg(&mmc->class_dev, "card is present\n");
868 else
869 dev_dbg(&mmc->class_dev, "card is not present\n");
870
871 return present;
872}
873
9623b5b9
DA		 874/*
875 * Disable lower power mode.
876 *
877 * Low power mode will stop the card clock when idle. According to the
878 * description of the CLKENA register we should disable low power mode
879 * for SDIO cards if we need SDIO interrupts to work.
880 *
881 * This function is fast if low power mode is already disabled.
882 */
883static void dw_mci_disable_low_power(struct dw_mci_slot *slot)
884{
885 struct dw_mci *host = slot->host;
886 u32 clk_en_a;
887 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
888
889 clk_en_a = mci_readl(host, CLKENA);
890
891 if (clk_en_a & clken_low_pwr) {
892 mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr);
893 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
894 SDMMC_CMD_PRV_DAT_WAIT, 0);
895 }
896}
897
1a5c8e1f
SH		 898static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
899{
900 struct dw_mci_slot *slot = mmc_priv(mmc);
901 struct dw_mci *host = slot->host;
902 u32 int_mask;
903
904 /* Enable/disable Slot Specific SDIO interrupt */
905 int_mask = mci_readl(host, INTMASK);
906 if (enb) {
9623b5b9
DA		 907 /*
908 * Turn off low power mode if it was enabled. This is a bit of
909 * a heavy operation and we disable / enable IRQs a lot, so
910 * we'll leave low power mode disabled and it will get
911 * re-enabled again in dw_mci_setup_bus().
912 */
913 dw_mci_disable_low_power(slot);
914
1a5c8e1f 915 mci_writel(host, INTMASK,
705ad047 916 (int_mask | SDMMC_INT_SDIO(slot->id)));
1a5c8e1f
SH		 917 } else {
918 mci_writel(host, INTMASK,
705ad047 919 (int_mask & ~SDMMC_INT_SDIO(slot->id)));
1a5c8e1f
SH		 920 }
921}
922
f95f3850 923static const struct mmc_host_ops dw_mci_ops = {
1a5c8e1f 924 .request = dw_mci_request,
9aa51408
SJ		 925 .pre_req = dw_mci_pre_req,
926 .post_req = dw_mci_post_req,
1a5c8e1f
SH		 927 .set_ios = dw_mci_set_ios,
928 .get_ro = dw_mci_get_ro,
929 .get_cd = dw_mci_get_cd,
930 .enable_sdio_irq = dw_mci_enable_sdio_irq,
f95f3850
WN		 931};
932
933static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
934 __releases(&host->lock)
935 __acquires(&host->lock)
936{
937 struct dw_mci_slot *slot;
938 struct mmc_host *prev_mmc = host->cur_slot->mmc;
939
940 WARN_ON(host->cmd || host->data);
941
942 host->cur_slot->mrq = NULL;
943 host->mrq = NULL;
944 if (!list_empty(&host->queue)) {
945 slot = list_entry(host->queue.next,
946 struct dw_mci_slot, queue_node);
947 list_del(&slot->queue_node);
4a90920c 948 dev_vdbg(host->dev, "list not empty: %s is next\n",
f95f3850
WN		 949 mmc_hostname(slot->mmc));
950 host->state = STATE_SENDING_CMD;
951 dw_mci_start_request(host, slot);
952 } else {
4a90920c 953 dev_vdbg(host->dev, "list empty\n");
f95f3850
WN		 954 host->state = STATE_IDLE;
955 }
956
957 spin_unlock(&host->lock);
958 mmc_request_done(prev_mmc, mrq);
959 spin_lock(&host->lock);
960}
961
962static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
963{
964 u32 status = host->cmd_status;
965
966 host->cmd_status = 0;
967
968 /* Read the response from the card (up to 16 bytes) */
969 if (cmd->flags & MMC_RSP_PRESENT) {
970 if (cmd->flags & MMC_RSP_136) {
971 cmd->resp[3] = mci_readl(host, RESP0);
972 cmd->resp[2] = mci_readl(host, RESP1);
973 cmd->resp[1] = mci_readl(host, RESP2);
974 cmd->resp[0] = mci_readl(host, RESP3);
975 } else {
976 cmd->resp[0] = mci_readl(host, RESP0);
977 cmd->resp[1] = 0;
978 cmd->resp[2] = 0;
979 cmd->resp[3] = 0;
980 }
981 }
982
983 if (status & SDMMC_INT_RTO)
984 cmd->error = -ETIMEDOUT;
985 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
986 cmd->error = -EILSEQ;
987 else if (status & SDMMC_INT_RESP_ERR)
988 cmd->error = -EIO;
989 else
990 cmd->error = 0;
991
992 if (cmd->error) {
993 /* newer ip versions need a delay between retries */
994 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
995 mdelay(20);
996
997 if (cmd->data) {
f95f3850 998 dw_mci_stop_dma(host);
fda5f736 999 host->data = NULL;
f95f3850
WN		 1000 }
1001 }
1002}
1003
1004static void dw_mci_tasklet_func(unsigned long priv)
1005{
1006 struct dw_mci *host = (struct dw_mci *)priv;
1007 struct mmc_data *data;
1008 struct mmc_command *cmd;
1009 enum dw_mci_state state;
1010 enum dw_mci_state prev_state;
94dd5b33 1011 u32 status, ctrl;
f95f3850
WN		 1012
1013 spin_lock(&host->lock);
1014
1015 state = host->state;
1016 data = host->data;
1017
1018 do {
1019 prev_state = state;
1020
1021 switch (state) {
1022 case STATE_IDLE:
1023 break;
1024
1025 case STATE_SENDING_CMD:
1026 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1027 &host->pending_events))
1028 break;
1029
1030 cmd = host->cmd;
1031 host->cmd = NULL;
1032 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
053b3ce6
SJ		 1033 dw_mci_command_complete(host, cmd);
1034 if (cmd == host->mrq->sbc && !cmd->error) {
1035 prev_state = state = STATE_SENDING_CMD;
1036 __dw_mci_start_request(host, host->cur_slot,
1037 host->mrq->cmd);
1038 goto unlock;
1039 }
1040
f95f3850
WN		 1041 if (!host->mrq->data || cmd->error) {
1042 dw_mci_request_end(host, host->mrq);
1043 goto unlock;
1044 }
1045
1046 prev_state = state = STATE_SENDING_DATA;
1047 /* fall through */
1048
1049 case STATE_SENDING_DATA:
1050 if (test_and_clear_bit(EVENT_DATA_ERROR,
1051 &host->pending_events)) {
1052 dw_mci_stop_dma(host);
1053 if (data->stop)
1054 send_stop_cmd(host, data);
1055 state = STATE_DATA_ERROR;
1056 break;
1057 }
1058
1059 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1060 &host->pending_events))
1061 break;
1062
1063 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1064 prev_state = state = STATE_DATA_BUSY;
1065 /* fall through */
1066
1067 case STATE_DATA_BUSY:
1068 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1069 &host->pending_events))
1070 break;
1071
1072 host->data = NULL;
1073 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1074 status = host->data_status;
1075
1076 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1077 if (status & SDMMC_INT_DTO) {
f95f3850
WN		 1078 data->error = -ETIMEDOUT;
1079 } else if (status & SDMMC_INT_DCRC) {
f95f3850 1080 data->error = -EILSEQ;
55c5efbc
JH		 1081 } else if (status & SDMMC_INT_EBE &&
1082 host->dir_status ==
1083 DW_MCI_SEND_STATUS) {
1084 /*
1085 * No data CRC status was returned.
1086 * The number of bytes transferred will
1087 * be exaggerated in PIO mode.
1088 */
1089 data->bytes_xfered = 0;
1090 data->error = -ETIMEDOUT;
f95f3850 1091 } else {
4a90920c 1092 dev_err(host->dev,
f95f3850
WN		 1093 "data FIFO error "
1094 "(status=%08x)\n",
1095 status);
1096 data->error = -EIO;
1097 }
94dd5b33
JH		 1098 /*
1099 * After an error, there may be data lingering
1100 * in the FIFO, so reset it - doing so
1101 * generates a block interrupt, hence setting
1102 * the scatter-gather pointer to NULL.
1103 */
f9c2a0dc 1104 sg_miter_stop(&host->sg_miter);
94dd5b33
JH		 1105 host->sg = NULL;
1106 ctrl = mci_readl(host, CTRL);
1107 ctrl |= SDMMC_CTRL_FIFO_RESET;
1108 mci_writel(host, CTRL, ctrl);
f95f3850
WN		 1109 } else {
1110 data->bytes_xfered = data->blocks * data->blksz;
1111 data->error = 0;
1112 }
1113
1114 if (!data->stop) {
1115 dw_mci_request_end(host, host->mrq);
1116 goto unlock;
1117 }
1118
053b3ce6
SJ		 1119 if (host->mrq->sbc && !data->error) {
1120 data->stop->error = 0;
1121 dw_mci_request_end(host, host->mrq);
1122 goto unlock;
1123 }
1124
f95f3850
WN		 1125 prev_state = state = STATE_SENDING_STOP;
1126 if (!data->error)
1127 send_stop_cmd(host, data);
1128 /* fall through */
1129
1130 case STATE_SENDING_STOP:
1131 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1132 &host->pending_events))
1133 break;
1134
1135 host->cmd = NULL;
1136 dw_mci_command_complete(host, host->mrq->stop);
1137 dw_mci_request_end(host, host->mrq);
1138 goto unlock;
1139
1140 case STATE_DATA_ERROR:
1141 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1142 &host->pending_events))
1143 break;
1144
1145 state = STATE_DATA_BUSY;
1146 break;
1147 }
1148 } while (state != prev_state);
1149
1150 host->state = state;
1151unlock:
1152 spin_unlock(&host->lock);
1153
1154}
1155
34b664a2
JH		 1156/* push final bytes to part_buf, only use during push */
1157static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 1158{
34b664a2
JH		 1159 memcpy((void *)&host->part_buf, buf, cnt);
1160 host->part_buf_count = cnt;
1161}
f95f3850 1162
34b664a2
JH		 1163/* append bytes to part_buf, only use during push */
1164static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1165{
1166 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1167 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1168 host->part_buf_count += cnt;
1169 return cnt;
1170}
f95f3850 1171
34b664a2
JH		 1172/* pull first bytes from part_buf, only use during pull */
1173static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1174{
1175 cnt = min(cnt, (int)host->part_buf_count);
1176 if (cnt) {
1177 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1178 cnt);
1179 host->part_buf_count -= cnt;
1180 host->part_buf_start += cnt;
f95f3850 1181 }
34b664a2 1182 return cnt;
f95f3850
WN		 1183}
1184
34b664a2
JH		 1185/* pull final bytes from the part_buf, assuming it's just been filled */
1186static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 1187{
34b664a2
JH		 1188 memcpy(buf, &host->part_buf, cnt);
1189 host->part_buf_start = cnt;
1190 host->part_buf_count = (1 << host->data_shift) - cnt;
1191}
f95f3850 1192
34b664a2
JH		 1193static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1194{
1195 /* try and push anything in the part_buf */
1196 if (unlikely(host->part_buf_count)) {
1197 int len = dw_mci_push_part_bytes(host, buf, cnt);
1198 buf += len;
1199 cnt -= len;
1200 if (!sg_next(host->sg) || host->part_buf_count == 2) {
4e0a5adf
JC		 1201 mci_writew(host, DATA(host->data_offset),
1202 host->part_buf16);
34b664a2
JH		 1203 host->part_buf_count = 0;
1204 }
1205 }
1206#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1207 if (unlikely((unsigned long)buf & 0x1)) {
1208 while (cnt >= 2) {
1209 u16 aligned_buf[64];
1210 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1211 int items = len >> 1;
1212 int i;
1213 /* memcpy from input buffer into aligned buffer */
1214 memcpy(aligned_buf, buf, len);
1215 buf += len;
1216 cnt -= len;
1217 /* push data from aligned buffer into fifo */
1218 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1219 mci_writew(host, DATA(host->data_offset),
1220 aligned_buf[i]);
34b664a2
JH		 1221 }
1222 } else
1223#endif
1224 {
1225 u16 *pdata = buf;
1226 for (; cnt >= 2; cnt -= 2)
4e0a5adf 1227 mci_writew(host, DATA(host->data_offset), *pdata++);
34b664a2
JH		 1228 buf = pdata;
1229 }
1230 /* put anything remaining in the part_buf */
1231 if (cnt) {
1232 dw_mci_set_part_bytes(host, buf, cnt);
1233 if (!sg_next(host->sg))
4e0a5adf
JC		 1234 mci_writew(host, DATA(host->data_offset),
1235 host->part_buf16);
34b664a2
JH		 1236 }
1237}
f95f3850 1238
34b664a2
JH		 1239static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1240{
1241#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1242 if (unlikely((unsigned long)buf & 0x1)) {
1243 while (cnt >= 2) {
1244 /* pull data from fifo into aligned buffer */
1245 u16 aligned_buf[64];
1246 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1247 int items = len >> 1;
1248 int i;
1249 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1250 aligned_buf[i] = mci_readw(host,
1251 DATA(host->data_offset));
34b664a2
JH		 1252 /* memcpy from aligned buffer into output buffer */
1253 memcpy(buf, aligned_buf, len);
1254 buf += len;
1255 cnt -= len;
1256 }
1257 } else
1258#endif
1259 {
1260 u16 *pdata = buf;
1261 for (; cnt >= 2; cnt -= 2)
4e0a5adf 1262 *pdata++ = mci_readw(host, DATA(host->data_offset));
34b664a2
JH		 1263 buf = pdata;
1264 }
1265 if (cnt) {
4e0a5adf 1266 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
34b664a2 1267 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 1268 }
1269}
1270
1271static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
1272{
34b664a2
JH		 1273 /* try and push anything in the part_buf */
1274 if (unlikely(host->part_buf_count)) {
1275 int len = dw_mci_push_part_bytes(host, buf, cnt);
1276 buf += len;
1277 cnt -= len;
1278 if (!sg_next(host->sg) || host->part_buf_count == 4) {
4e0a5adf
JC		 1279 mci_writel(host, DATA(host->data_offset),
1280 host->part_buf32);
34b664a2
JH		 1281 host->part_buf_count = 0;
1282 }
1283 }
1284#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1285 if (unlikely((unsigned long)buf & 0x3)) {
1286 while (cnt >= 4) {
1287 u32 aligned_buf[32];
1288 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1289 int items = len >> 2;
1290 int i;
1291 /* memcpy from input buffer into aligned buffer */
1292 memcpy(aligned_buf, buf, len);
1293 buf += len;
1294 cnt -= len;
1295 /* push data from aligned buffer into fifo */
1296 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1297 mci_writel(host, DATA(host->data_offset),
1298 aligned_buf[i]);
34b664a2
JH		 1299 }
1300 } else
1301#endif
1302 {
1303 u32 *pdata = buf;
1304 for (; cnt >= 4; cnt -= 4)
4e0a5adf 1305 mci_writel(host, DATA(host->data_offset), *pdata++);
34b664a2
JH		 1306 buf = pdata;
1307 }
1308 /* put anything remaining in the part_buf */
1309 if (cnt) {
1310 dw_mci_set_part_bytes(host, buf, cnt);
1311 if (!sg_next(host->sg))
4e0a5adf
JC		 1312 mci_writel(host, DATA(host->data_offset),
1313 host->part_buf32);
f95f3850
WN		 1314 }
1315}
1316
1317static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1318{
34b664a2
JH		 1319#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1320 if (unlikely((unsigned long)buf & 0x3)) {
1321 while (cnt >= 4) {
1322 /* pull data from fifo into aligned buffer */
1323 u32 aligned_buf[32];
1324 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1325 int items = len >> 2;
1326 int i;
1327 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1328 aligned_buf[i] = mci_readl(host,
1329 DATA(host->data_offset));
34b664a2
JH		 1330 /* memcpy from aligned buffer into output buffer */
1331 memcpy(buf, aligned_buf, len);
1332 buf += len;
1333 cnt -= len;
1334 }
1335 } else
1336#endif
1337 {
1338 u32 *pdata = buf;
1339 for (; cnt >= 4; cnt -= 4)
4e0a5adf 1340 *pdata++ = mci_readl(host, DATA(host->data_offset));
34b664a2
JH		 1341 buf = pdata;
1342 }
1343 if (cnt) {
4e0a5adf 1344 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
34b664a2 1345 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 1346 }
1347}
1348
1349static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1350{
34b664a2
JH		 1351 /* try and push anything in the part_buf */
1352 if (unlikely(host->part_buf_count)) {
1353 int len = dw_mci_push_part_bytes(host, buf, cnt);
1354 buf += len;
1355 cnt -= len;
1356 if (!sg_next(host->sg) || host->part_buf_count == 8) {
4e0a5adf
JC		 1357 mci_writew(host, DATA(host->data_offset),
1358 host->part_buf);
34b664a2
JH		 1359 host->part_buf_count = 0;
1360 }
1361 }
1362#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1363 if (unlikely((unsigned long)buf & 0x7)) {
1364 while (cnt >= 8) {
1365 u64 aligned_buf[16];
1366 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1367 int items = len >> 3;
1368 int i;
1369 /* memcpy from input buffer into aligned buffer */
1370 memcpy(aligned_buf, buf, len);
1371 buf += len;
1372 cnt -= len;
1373 /* push data from aligned buffer into fifo */
1374 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1375 mci_writeq(host, DATA(host->data_offset),
1376 aligned_buf[i]);
34b664a2
JH		 1377 }
1378 } else
1379#endif
1380 {
1381 u64 *pdata = buf;
1382 for (; cnt >= 8; cnt -= 8)
4e0a5adf 1383 mci_writeq(host, DATA(host->data_offset), *pdata++);
34b664a2
JH		 1384 buf = pdata;
1385 }
1386 /* put anything remaining in the part_buf */
1387 if (cnt) {
1388 dw_mci_set_part_bytes(host, buf, cnt);
1389 if (!sg_next(host->sg))
4e0a5adf
JC		 1390 mci_writeq(host, DATA(host->data_offset),
1391 host->part_buf);
f95f3850
WN		 1392 }
1393}
1394
1395static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1396{
34b664a2
JH		 1397#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1398 if (unlikely((unsigned long)buf & 0x7)) {
1399 while (cnt >= 8) {
1400 /* pull data from fifo into aligned buffer */
1401 u64 aligned_buf[16];
1402 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1403 int items = len >> 3;
1404 int i;
1405 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1406 aligned_buf[i] = mci_readq(host,
1407 DATA(host->data_offset));
34b664a2
JH		 1408 /* memcpy from aligned buffer into output buffer */
1409 memcpy(buf, aligned_buf, len);
1410 buf += len;
1411 cnt -= len;
1412 }
1413 } else
1414#endif
1415 {
1416 u64 *pdata = buf;
1417 for (; cnt >= 8; cnt -= 8)
4e0a5adf 1418 *pdata++ = mci_readq(host, DATA(host->data_offset));
34b664a2
JH		 1419 buf = pdata;
1420 }
1421 if (cnt) {
4e0a5adf 1422 host->part_buf = mci_readq(host, DATA(host->data_offset));
34b664a2
JH		 1423 dw_mci_pull_final_bytes(host, buf, cnt);
1424 }
1425}
f95f3850 1426
34b664a2
JH		 1427static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
1428{
1429 int len;
f95f3850 1430
34b664a2
JH		 1431 /* get remaining partial bytes */
1432 len = dw_mci_pull_part_bytes(host, buf, cnt);
1433 if (unlikely(len == cnt))
1434 return;
1435 buf += len;
1436 cnt -= len;
1437
1438 /* get the rest of the data */
1439 host->pull_data(host, buf, cnt);
f95f3850
WN		 1440}
1441
1442static void dw_mci_read_data_pio(struct dw_mci *host)
1443{
f9c2a0dc
SJ		 1444 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1445 void *buf;
1446 unsigned int offset;
f95f3850
WN		 1447 struct mmc_data *data = host->data;
1448 int shift = host->data_shift;
1449 u32 status;
ba6a902d 1450 unsigned int nbytes = 0, len;
f9c2a0dc 1451 unsigned int remain, fcnt;
f95f3850
WN		 1452
1453 do {
f9c2a0dc
SJ		 1454 if (!sg_miter_next(sg_miter))
1455 goto done;
1456
1457 host->sg = sg_miter->__sg;
1458 buf = sg_miter->addr;
1459 remain = sg_miter->length;
1460 offset = 0;
1461
1462 do {
1463 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
1464 << shift) + host->part_buf_count;
1465 len = min(remain, fcnt);
1466 if (!len)
1467 break;
34b664a2 1468 dw_mci_pull_data(host, (void *)(buf + offset), len);
f95f3850
WN		 1469 offset += len;
1470 nbytes += len;
f9c2a0dc
SJ		 1471 remain -= len;
1472 } while (remain);
f95f3850 1473
e74f3a9c 1474 sg_miter->consumed = offset;
f95f3850
WN		 1475 status = mci_readl(host, MINTSTS);
1476 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
f95f3850 1477 } while (status & SDMMC_INT_RXDR); /*if the RXDR is ready read again*/
f95f3850 1478 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1479
1480 if (!remain) {
1481 if (!sg_miter_next(sg_miter))
1482 goto done;
1483 sg_miter->consumed = 0;
1484 }
1485 sg_miter_stop(sg_miter);
f95f3850
WN		 1486 return;
1487
1488done:
1489 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1490 sg_miter_stop(sg_miter);
1491 host->sg = NULL;
f95f3850
WN		 1492 smp_wmb();
1493 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1494}
1495
1496static void dw_mci_write_data_pio(struct dw_mci *host)
1497{
f9c2a0dc
SJ		 1498 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1499 void *buf;
1500 unsigned int offset;
f95f3850
WN		 1501 struct mmc_data *data = host->data;
1502 int shift = host->data_shift;
1503 u32 status;
1504 unsigned int nbytes = 0, len;
f9c2a0dc
SJ		 1505 unsigned int fifo_depth = host->fifo_depth;
1506 unsigned int remain, fcnt;
f95f3850
WN		 1507
1508 do {
f9c2a0dc
SJ		 1509 if (!sg_miter_next(sg_miter))
1510 goto done;
1511
1512 host->sg = sg_miter->__sg;
1513 buf = sg_miter->addr;
1514 remain = sg_miter->length;
1515 offset = 0;
1516
1517 do {
1518 fcnt = ((fifo_depth -
1519 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
1520 << shift) - host->part_buf_count;
1521 len = min(remain, fcnt);
1522 if (!len)
1523 break;
f95f3850 1524 host->push_data(host, (void *)(buf + offset), len);
f95f3850
WN		 1525 offset += len;
1526 nbytes += len;
f9c2a0dc
SJ		 1527 remain -= len;
1528 } while (remain);
f95f3850 1529
e74f3a9c 1530 sg_miter->consumed = offset;
f95f3850
WN		 1531 status = mci_readl(host, MINTSTS);
1532 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
f95f3850 1533 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
f95f3850 1534 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1535
1536 if (!remain) {
1537 if (!sg_miter_next(sg_miter))
1538 goto done;
1539 sg_miter->consumed = 0;
1540 }
1541 sg_miter_stop(sg_miter);
f95f3850
WN		 1542 return;
1543
1544done:
1545 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1546 sg_miter_stop(sg_miter);
1547 host->sg = NULL;
f95f3850
WN		 1548 smp_wmb();
1549 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1550}
1551
1552static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
1553{
1554 if (!host->cmd_status)
1555 host->cmd_status = status;
1556
1557 smp_wmb();
1558
1559 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1560 tasklet_schedule(&host->tasklet);
1561}
1562
1563static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
1564{
1565 struct dw_mci *host = dev_id;
182c9081 1566 u32 pending;
f95f3850 1567 unsigned int pass_count = 0;
1a5c8e1f 1568 int i;
f95f3850
WN		 1569
1570 do {
f95f3850
WN		 1571 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
1572
1573 /*
1574 * DTO fix - version 2.10a and below, and only if internal DMA
1575 * is configured.
1576 */
1577 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
1578 if (!pending &&
1579 ((mci_readl(host, STATUS) >> 17) & 0x1fff))
1580 pending |= SDMMC_INT_DATA_OVER;
1581 }
1582
1583 if (!pending)
1584 break;
1585
1586 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
1587 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
182c9081 1588 host->cmd_status = pending;
f95f3850
WN		 1589 smp_wmb();
1590 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
f95f3850
WN		 1591 }
1592
1593 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
1594 /* if there is an error report DATA_ERROR */
1595 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
182c9081 1596 host->data_status = pending;
f95f3850
WN		 1597 smp_wmb();
1598 set_bit(EVENT_DATA_ERROR, &host->pending_events);
9b2026a1 1599 tasklet_schedule(&host->tasklet);
f95f3850
WN		 1600 }
1601
1602 if (pending & SDMMC_INT_DATA_OVER) {
1603 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1604 if (!host->data_status)
182c9081 1605 host->data_status = pending;
f95f3850
WN		 1606 smp_wmb();
1607 if (host->dir_status == DW_MCI_RECV_STATUS) {
1608 if (host->sg != NULL)
1609 dw_mci_read_data_pio(host);
1610 }
1611 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1612 tasklet_schedule(&host->tasklet);
1613 }
1614
1615 if (pending & SDMMC_INT_RXDR) {
1616 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
b40af3aa 1617 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
f95f3850
WN		 1618 dw_mci_read_data_pio(host);
1619 }
1620
1621 if (pending & SDMMC_INT_TXDR) {
1622 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
b40af3aa 1623 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
f95f3850
WN		 1624 dw_mci_write_data_pio(host);
1625 }
1626
1627 if (pending & SDMMC_INT_CMD_DONE) {
1628 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
182c9081 1629 dw_mci_cmd_interrupt(host, pending);
f95f3850
WN		 1630 }
1631
1632 if (pending & SDMMC_INT_CD) {
1633 mci_writel(host, RINTSTS, SDMMC_INT_CD);
95dcc2cb 1634 queue_work(host->card_workqueue, &host->card_work);
f95f3850
WN		 1635 }
1636
1a5c8e1f
SH		 1637 /* Handle SDIO Interrupts */
1638 for (i = 0; i < host->num_slots; i++) {
1639 struct dw_mci_slot *slot = host->slot[i];
1640 if (pending & SDMMC_INT_SDIO(i)) {
1641 mci_writel(host, RINTSTS, SDMMC_INT_SDIO(i));
1642 mmc_signal_sdio_irq(slot->mmc);
1643 }
1644 }
1645
f95f3850
WN		 1646 } while (pass_count++ < 5);
1647
1648#ifdef CONFIG_MMC_DW_IDMAC
1649 /* Handle DMA interrupts */
1650 pending = mci_readl(host, IDSTS);
1651 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
1652 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
1653 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
f95f3850
WN		 1654 host->dma_ops->complete(host);
1655 }
1656#endif
1657
1658 return IRQ_HANDLED;
1659}
1660
1791b13e 1661static void dw_mci_work_routine_card(struct work_struct *work)
f95f3850 1662{
1791b13e 1663 struct dw_mci *host = container_of(work, struct dw_mci, card_work);
f95f3850
WN		 1664 int i;
1665
1666 for (i = 0; i < host->num_slots; i++) {
1667 struct dw_mci_slot *slot = host->slot[i];
1668 struct mmc_host *mmc = slot->mmc;
1669 struct mmc_request *mrq;
1670 int present;
1671 u32 ctrl;
1672
1673 present = dw_mci_get_cd(mmc);
1674 while (present != slot->last_detect_state) {
f95f3850
WN		 1675 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1676 present ? "inserted" : "removed");
1677
1791b13e
JH		 1678 /* Power up slot (before spin_lock, may sleep) */
1679 if (present != 0 && host->pdata->setpower)
1680 host->pdata->setpower(slot->id, mmc->ocr_avail);
1681
1682 spin_lock_bh(&host->lock);
1683
f95f3850
WN		 1684 /* Card change detected */
1685 slot->last_detect_state = present;
1686
1791b13e
JH		 1687 /* Mark card as present if applicable */
1688 if (present != 0)
f95f3850 1689 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
f95f3850
WN		 1690
1691 /* Clean up queue if present */
1692 mrq = slot->mrq;
1693 if (mrq) {
1694 if (mrq == host->mrq) {
1695 host->data = NULL;
1696 host->cmd = NULL;
1697
1698 switch (host->state) {
1699 case STATE_IDLE:
1700 break;
1701 case STATE_SENDING_CMD:
1702 mrq->cmd->error = -ENOMEDIUM;
1703 if (!mrq->data)
1704 break;
1705 /* fall through */
1706 case STATE_SENDING_DATA:
1707 mrq->data->error = -ENOMEDIUM;
1708 dw_mci_stop_dma(host);
1709 break;
1710 case STATE_DATA_BUSY:
1711 case STATE_DATA_ERROR:
1712 if (mrq->data->error == -EINPROGRESS)
1713 mrq->data->error = -ENOMEDIUM;
1714 if (!mrq->stop)
1715 break;
1716 /* fall through */
1717 case STATE_SENDING_STOP:
1718 mrq->stop->error = -ENOMEDIUM;
1719 break;
1720 }
1721
1722 dw_mci_request_end(host, mrq);
1723 } else {
1724 list_del(&slot->queue_node);
1725 mrq->cmd->error = -ENOMEDIUM;
1726 if (mrq->data)
1727 mrq->data->error = -ENOMEDIUM;
1728 if (mrq->stop)
1729 mrq->stop->error = -ENOMEDIUM;
1730
1731 spin_unlock(&host->lock);
1732 mmc_request_done(slot->mmc, mrq);
1733 spin_lock(&host->lock);
1734 }
1735 }
1736
1737 /* Power down slot */
1738 if (present == 0) {
f95f3850
WN		 1739 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1740
1741 /*
1742 * Clear down the FIFO - doing so generates a
1743 * block interrupt, hence setting the
1744 * scatter-gather pointer to NULL.
1745 */
f9c2a0dc 1746 sg_miter_stop(&host->sg_miter);
f95f3850
WN		 1747 host->sg = NULL;
1748
1749 ctrl = mci_readl(host, CTRL);
1750 ctrl |= SDMMC_CTRL_FIFO_RESET;
1751 mci_writel(host, CTRL, ctrl);
1752
1753#ifdef CONFIG_MMC_DW_IDMAC
1754 ctrl = mci_readl(host, BMOD);
141a712a
SJ		 1755 /* Software reset of DMA */
1756 ctrl |= SDMMC_IDMAC_SWRESET;
f95f3850
WN		 1757 mci_writel(host, BMOD, ctrl);
1758#endif
1759
1760 }
1761
1791b13e
JH		 1762 spin_unlock_bh(&host->lock);
1763
1764 /* Power down slot (after spin_unlock, may sleep) */
1765 if (present == 0 && host->pdata->setpower)
1766 host->pdata->setpower(slot->id, 0);
1767
f95f3850
WN		 1768 present = dw_mci_get_cd(mmc);
1769 }
1770
1771 mmc_detect_change(slot->mmc,
1772 msecs_to_jiffies(host->pdata->detect_delay_ms));
1773 }
1774}
1775
c91eab4b
TA		 1776#ifdef CONFIG_OF
1777/* given a slot id, find out the device node representing that slot */
1778static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
1779{
1780 struct device_node *np;
1781 const __be32 *addr;
1782 int len;
1783
1784 if (!dev || !dev->of_node)
1785 return NULL;
1786
1787 for_each_child_of_node(dev->of_node, np) {
1788 addr = of_get_property(np, "reg", &len);
1789 if (!addr || (len < sizeof(int)))
1790 continue;
1791 if (be32_to_cpup(addr) == slot)
1792 return np;
1793 }
1794 return NULL;
1795}
1796
a70aaa64
DA		 1797static struct dw_mci_of_slot_quirks {
1798 char *quirk;
1799 int id;
1800} of_slot_quirks[] = {
1801 {
1802 .quirk = "disable-wp",
1803 .id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
1804 },
1805};
1806
1807static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
1808{
1809 struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
1810 int quirks = 0;
1811 int idx;
1812
1813 /* get quirks */
1814 for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++)
1815 if (of_get_property(np, of_slot_quirks[idx].quirk, NULL))
1816 quirks |= of_slot_quirks[idx].id;
1817
1818 return quirks;
1819}
1820
c91eab4b
TA		 1821/* find out bus-width for a given slot */
1822static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
1823{
1824 struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
1825 u32 bus_wd = 1;
1826
1827 if (!np)
1828 return 1;
1829
1830 if (of_property_read_u32(np, "bus-width", &bus_wd))
1831 dev_err(dev, "bus-width property not found, assuming width"
1832 " as 1\n");
1833 return bus_wd;
1834}
1835#else /* CONFIG_OF */
a70aaa64
DA		 1836static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
1837{
1838 return 0;
1839}
c91eab4b
TA		 1840static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
1841{
1842 return 1;
1843}
1844static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
1845{
1846 return NULL;
1847}
1848#endif /* CONFIG_OF */
1849
36c179a9 1850static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
f95f3850
WN		 1851{
1852 struct mmc_host *mmc;
1853 struct dw_mci_slot *slot;
e95baf13 1854 const struct dw_mci_drv_data *drv_data = host->drv_data;
800d78bf 1855 int ctrl_id, ret;
c91eab4b 1856 u8 bus_width;
f95f3850 1857
4a90920c 1858 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
f95f3850
WN		 1859 if (!mmc)
1860 return -ENOMEM;
1861
1862 slot = mmc_priv(mmc);
1863 slot->id = id;
1864 slot->mmc = mmc;
1865 slot->host = host;
c91eab4b 1866 host->slot[id] = slot;
f95f3850 1867
a70aaa64
DA		 1868 slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
1869
f95f3850
WN		 1870 mmc->ops = &dw_mci_ops;
1871 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510);
1872 mmc->f_max = host->bus_hz;
1873
1874 if (host->pdata->get_ocr)
1875 mmc->ocr_avail = host->pdata->get_ocr(id);
1876 else
1877 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1878
1879 /*
1880 * Start with slot power disabled, it will be enabled when a card
1881 * is detected.
1882 */
1883 if (host->pdata->setpower)
1884 host->pdata->setpower(id, 0);
1885
fc3d7720
JC		 1886 if (host->pdata->caps)
1887 mmc->caps = host->pdata->caps;
fc3d7720 1888
ab269128
AK		 1889 if (host->pdata->pm_caps)
1890 mmc->pm_caps = host->pdata->pm_caps;
1891
800d78bf
TA		 1892 if (host->dev->of_node) {
1893 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
1894 if (ctrl_id < 0)
1895 ctrl_id = 0;
1896 } else {
1897 ctrl_id = to_platform_device(host->dev)->id;
1898 }
cb27a843
JH		 1899 if (drv_data && drv_data->caps)
1900 mmc->caps |= drv_data->caps[ctrl_id];
800d78bf 1901
4f408cc6
SJ		 1902 if (host->pdata->caps2)
1903 mmc->caps2 = host->pdata->caps2;
4f408cc6 1904
f95f3850 1905 if (host->pdata->get_bus_wd)
c91eab4b
TA		 1906 bus_width = host->pdata->get_bus_wd(slot->id);
1907 else if (host->dev->of_node)
1908 bus_width = dw_mci_of_get_bus_wd(host->dev, slot->id);
1909 else
1910 bus_width = 1;
1911
cb27a843 1912 if (drv_data && drv_data->setup_bus) {
800d78bf
TA		 1913 struct device_node *slot_np;
1914 slot_np = dw_mci_of_find_slot_node(host->dev, slot->id);
cb27a843 1915 ret = drv_data->setup_bus(host, slot_np, bus_width);
800d78bf
TA		 1916 if (ret)
1917 goto err_setup_bus;
1918 }
1919
c91eab4b
TA		 1920 switch (bus_width) {
1921 case 8:
1922 mmc->caps |= MMC_CAP_8_BIT_DATA;
1923 case 4:
1924 mmc->caps |= MMC_CAP_4_BIT_DATA;
1925 }
f95f3850
WN		 1926
1927 if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED)
6daa7778 1928 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
f95f3850 1929
f95f3850
WN		 1930 if (host->pdata->blk_settings) {
1931 mmc->max_segs = host->pdata->blk_settings->max_segs;
1932 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
1933 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
1934 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
1935 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
1936 } else {
1937 /* Useful defaults if platform data is unset. */
a39e5746
JC		 1938#ifdef CONFIG_MMC_DW_IDMAC
1939 mmc->max_segs = host->ring_size;
1940 mmc->max_blk_size = 65536;
1941 mmc->max_blk_count = host->ring_size;
1942 mmc->max_seg_size = 0x1000;
1943 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
1944#else
f95f3850
WN		 1945 mmc->max_segs = 64;
1946 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
1947 mmc->max_blk_count = 512;
1948 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1949 mmc->max_seg_size = mmc->max_req_size;
f95f3850 1950#endif /* CONFIG_MMC_DW_IDMAC */
a39e5746 1951 }
f95f3850 1952
780f22af 1953 host->vmmc = devm_regulator_get(mmc_dev(mmc), "vmmc");
c07946a3 1954 if (IS_ERR(host->vmmc)) {
a3c76eb9 1955 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
c07946a3
JC		 1956 host->vmmc = NULL;
1957 } else
1958 regulator_enable(host->vmmc);
1959
f95f3850
WN		 1960 if (dw_mci_get_cd(mmc))
1961 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1962 else
1963 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1964
f95f3850
WN		 1965 mmc_add_host(mmc);
1966
1967#if defined(CONFIG_DEBUG_FS)
1968 dw_mci_init_debugfs(slot);
1969#endif
1970
1971 /* Card initially undetected */
1972 slot->last_detect_state = 0;
1973
dd6c4b98
WN		 1974 /*
1975 * Card may have been plugged in prior to boot so we
1976 * need to run the detect tasklet
1977 */
95dcc2cb 1978 queue_work(host->card_workqueue, &host->card_work);
dd6c4b98 1979
f95f3850 1980 return 0;
800d78bf
TA		 1981
1982err_setup_bus:
1983 mmc_free_host(mmc);
1984 return -EINVAL;
f95f3850
WN		 1985}
1986
1987static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
1988{
1989 /* Shutdown detect IRQ */
1990 if (slot->host->pdata->exit)
1991 slot->host->pdata->exit(id);
1992
1993 /* Debugfs stuff is cleaned up by mmc core */
1994 mmc_remove_host(slot->mmc);
1995 slot->host->slot[id] = NULL;
1996 mmc_free_host(slot->mmc);
1997}
1998
1999static void dw_mci_init_dma(struct dw_mci *host)
2000{
2001 /* Alloc memory for sg translation */
780f22af 2002 host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
f95f3850
WN		 2003 &host->sg_dma, GFP_KERNEL);
2004 if (!host->sg_cpu) {
4a90920c 2005 dev_err(host->dev, "%s: could not alloc DMA memory\n",
f95f3850
WN		 2006 __func__);
2007 goto no_dma;
2008 }
2009
2010 /* Determine which DMA interface to use */
2011#ifdef CONFIG_MMC_DW_IDMAC
2012 host->dma_ops = &dw_mci_idmac_ops;
00956ea3 2013 dev_info(host->dev, "Using internal DMA controller.\n");
f95f3850
WN		 2014#endif
2015
2016 if (!host->dma_ops)
2017 goto no_dma;
2018
e1631f98
JC		 2019 if (host->dma_ops->init && host->dma_ops->start &&
2020 host->dma_ops->stop && host->dma_ops->cleanup) {
f95f3850 2021 if (host->dma_ops->init(host)) {
4a90920c 2022 dev_err(host->dev, "%s: Unable to initialize "
f95f3850
WN		 2023 "DMA Controller.\n", __func__);
2024 goto no_dma;
2025 }
2026 } else {
4a90920c 2027 dev_err(host->dev, "DMA initialization not found.\n");
f95f3850
WN		 2028 goto no_dma;
2029 }
2030
2031 host->use_dma = 1;
2032 return;
2033
2034no_dma:
4a90920c 2035 dev_info(host->dev, "Using PIO mode.\n");
f95f3850
WN		 2036 host->use_dma = 0;
2037 return;
2038}
2039
2040static bool mci_wait_reset(struct device *dev, struct dw_mci *host)
2041{
2042 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2043 unsigned int ctrl;
2044
2045 mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
2046 SDMMC_CTRL_DMA_RESET));
2047
2048 /* wait till resets clear */
2049 do {
2050 ctrl = mci_readl(host, CTRL);
2051 if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
2052 SDMMC_CTRL_DMA_RESET)))
2053 return true;
2054 } while (time_before(jiffies, timeout));
2055
2056 dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl);
2057
2058 return false;
2059}
2060
c91eab4b
TA		 2061#ifdef CONFIG_OF
2062static struct dw_mci_of_quirks {
2063 char *quirk;
2064 int id;
2065} of_quirks[] = {
2066 {
2067 .quirk = "supports-highspeed",
2068 .id = DW_MCI_QUIRK_HIGHSPEED,
2069 }, {
2070 .quirk = "broken-cd",
2071 .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
2072 },
2073};
2074
2075static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2076{
2077 struct dw_mci_board *pdata;
2078 struct device *dev = host->dev;
2079 struct device_node *np = dev->of_node;
e95baf13 2080 const struct dw_mci_drv_data *drv_data = host->drv_data;
800d78bf 2081 int idx, ret;
c91eab4b
TA		 2082
2083 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2084 if (!pdata) {
2085 dev_err(dev, "could not allocate memory for pdata\n");
2086 return ERR_PTR(-ENOMEM);
2087 }
2088
2089 /* find out number of slots supported */
2090 if (of_property_read_u32(dev->of_node, "num-slots",
2091 &pdata->num_slots)) {
2092 dev_info(dev, "num-slots property not found, "
2093 "assuming 1 slot is available\n");
2094 pdata->num_slots = 1;
2095 }
2096
2097 /* get quirks */
2098 for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
2099 if (of_get_property(np, of_quirks[idx].quirk, NULL))
2100 pdata->quirks |= of_quirks[idx].id;
2101
2102 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2103 dev_info(dev, "fifo-depth property not found, using "
2104 "value of FIFOTH register as default\n");
2105
2106 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2107
cb27a843
JH		 2108 if (drv_data && drv_data->parse_dt) {
2109 ret = drv_data->parse_dt(host);
800d78bf
TA		 2110 if (ret)
2111 return ERR_PTR(ret);
2112 }
2113
ab269128
AK		 2114 if (of_find_property(np, "keep-power-in-suspend", NULL))
2115 pdata->pm_caps |= MMC_PM_KEEP_POWER;
2116
2117 if (of_find_property(np, "enable-sdio-wakeup", NULL))
2118 pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
2119
c91eab4b
TA		 2120 return pdata;
2121}
2122
2123#else /* CONFIG_OF */
2124static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2125{
2126 return ERR_PTR(-EINVAL);
2127}
2128#endif /* CONFIG_OF */
2129
62ca8034 2130int dw_mci_probe(struct dw_mci *host)
f95f3850 2131{
e95baf13 2132 const struct dw_mci_drv_data *drv_data = host->drv_data;
62ca8034 2133 int width, i, ret = 0;
f95f3850 2134 u32 fifo_size;
1c2215b7 2135 int init_slots = 0;
f95f3850 2136
c91eab4b
TA		 2137 if (!host->pdata) {
2138 host->pdata = dw_mci_parse_dt(host);
2139 if (IS_ERR(host->pdata)) {
2140 dev_err(host->dev, "platform data not available\n");
2141 return -EINVAL;
2142 }
f95f3850
WN		 2143 }
2144
62ca8034 2145 if (!host->pdata->select_slot && host->pdata->num_slots > 1) {
4a90920c 2146 dev_err(host->dev,
f95f3850 2147 "Platform data must supply select_slot function\n");
62ca8034 2148 return -ENODEV;
f95f3850
WN		 2149 }
2150
780f22af 2151 host->biu_clk = devm_clk_get(host->dev, "biu");
f90a0612
TA		 2152 if (IS_ERR(host->biu_clk)) {
2153 dev_dbg(host->dev, "biu clock not available\n");
2154 } else {
2155 ret = clk_prepare_enable(host->biu_clk);
2156 if (ret) {
2157 dev_err(host->dev, "failed to enable biu clock\n");
f90a0612
TA		 2158 return ret;
2159 }
2160 }
2161
780f22af 2162 host->ciu_clk = devm_clk_get(host->dev, "ciu");
f90a0612
TA		 2163 if (IS_ERR(host->ciu_clk)) {
2164 dev_dbg(host->dev, "ciu clock not available\n");
2165 } else {
2166 ret = clk_prepare_enable(host->ciu_clk);
2167 if (ret) {
2168 dev_err(host->dev, "failed to enable ciu clock\n");
f90a0612
TA		 2169 goto err_clk_biu;
2170 }
2171 }
2172
2173 if (IS_ERR(host->ciu_clk))
2174 host->bus_hz = host->pdata->bus_hz;
2175 else
2176 host->bus_hz = clk_get_rate(host->ciu_clk);
2177
cb27a843
JH		 2178 if (drv_data && drv_data->setup_clock) {
2179 ret = drv_data->setup_clock(host);
800d78bf
TA		 2180 if (ret) {
2181 dev_err(host->dev,
2182 "implementation specific clock setup failed\n");
2183 goto err_clk_ciu;
2184 }
2185 }
2186
f90a0612 2187 if (!host->bus_hz) {
4a90920c 2188 dev_err(host->dev,
f95f3850 2189 "Platform data must supply bus speed\n");
f90a0612
TA		 2190 ret = -ENODEV;
2191 goto err_clk_ciu;
f95f3850
WN		 2192 }
2193
62ca8034 2194 host->quirks = host->pdata->quirks;
f95f3850
WN		 2195
2196 spin_lock_init(&host->lock);
2197 INIT_LIST_HEAD(&host->queue);
2198
f95f3850
WN		 2199 /*
2200 * Get the host data width - this assumes that HCON has been set with
2201 * the correct values.
2202 */
2203 i = (mci_readl(host, HCON) >> 7) & 0x7;
2204 if (!i) {
2205 host->push_data = dw_mci_push_data16;
2206 host->pull_data = dw_mci_pull_data16;
2207 width = 16;
2208 host->data_shift = 1;
2209 } else if (i == 2) {
2210 host->push_data = dw_mci_push_data64;
2211 host->pull_data = dw_mci_pull_data64;
2212 width = 64;
2213 host->data_shift = 3;
2214 } else {
2215 /* Check for a reserved value, and warn if it is */
2216 WARN((i != 1),
2217 "HCON reports a reserved host data width!\n"
2218 "Defaulting to 32-bit access.\n");
2219 host->push_data = dw_mci_push_data32;
2220 host->pull_data = dw_mci_pull_data32;
2221 width = 32;
2222 host->data_shift = 2;
2223 }
2224
2225 /* Reset all blocks */
4a90920c 2226 if (!mci_wait_reset(host->dev, host))
141a712a
SJ		 2227 return -ENODEV;
2228
2229 host->dma_ops = host->pdata->dma_ops;
2230 dw_mci_init_dma(host);
f95f3850
WN		 2231
2232 /* Clear the interrupts for the host controller */
2233 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2234 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2235
2236 /* Put in max timeout */
2237 mci_writel(host, TMOUT, 0xFFFFFFFF);
2238
2239 /*
2240 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
2241 * Tx Mark = fifo_size / 2 DMA Size = 8
2242 */
b86d8253
JH		 2243 if (!host->pdata->fifo_depth) {
2244 /*
2245 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
2246 * have been overwritten by the bootloader, just like we're
2247 * about to do, so if you know the value for your hardware, you
2248 * should put it in the platform data.
2249 */
2250 fifo_size = mci_readl(host, FIFOTH);
8234e869 2251 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
b86d8253
JH		 2252 } else {
2253 fifo_size = host->pdata->fifo_depth;
2254 }
2255 host->fifo_depth = fifo_size;
e61cf118
JC		 2256 host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) |
2257 ((fifo_size/2) << 0));
2258 mci_writel(host, FIFOTH, host->fifoth_val);
f95f3850
WN		 2259
2260 /* disable clock to CIU */
2261 mci_writel(host, CLKENA, 0);
2262 mci_writel(host, CLKSRC, 0);
2263
2264 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
95dcc2cb 2265 host->card_workqueue = alloc_workqueue("dw-mci-card",
1791b13e 2266 WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
95dcc2cb 2267 if (!host->card_workqueue)
1791b13e
JH		 2268 goto err_dmaunmap;
2269 INIT_WORK(&host->card_work, dw_mci_work_routine_card);
780f22af
SJ		 2270 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
2271 host->irq_flags, "dw-mci", host);
f95f3850 2272 if (ret)
1791b13e 2273 goto err_workqueue;
f95f3850 2274
f95f3850
WN		 2275 if (host->pdata->num_slots)
2276 host->num_slots = host->pdata->num_slots;
2277 else
2278 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
2279
2da1d7f2
YC		 2280 /*
2281 * Enable interrupts for command done, data over, data empty, card det,
2282 * receive ready and error such as transmit, receive timeout, crc error
2283 */
2284 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2285 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2286 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2287 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2288 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
2289
2290 dev_info(host->dev, "DW MMC controller at irq %d, "
2291 "%d bit host data width, "
2292 "%u deep fifo\n",
2293 host->irq, width, fifo_size);
2294
f95f3850
WN		 2295 /* We need at least one slot to succeed */
2296 for (i = 0; i < host->num_slots; i++) {
2297 ret = dw_mci_init_slot(host, i);
1c2215b7
TA		 2298 if (ret)
2299 dev_dbg(host->dev, "slot %d init failed\n", i);
2300 else
2301 init_slots++;
2302 }
2303
2304 if (init_slots) {
2305 dev_info(host->dev, "%d slots initialized\n", init_slots);
2306 } else {
2307 dev_dbg(host->dev, "attempted to initialize %d slots, "
2308 "but failed on all\n", host->num_slots);
780f22af 2309 goto err_workqueue;
f95f3850
WN		 2310 }
2311
4e0a5adf
JC		 2312 /*
2313 * In 2.40a spec, Data offset is changed.
2314 * Need to check the version-id and set data-offset for DATA register.
2315 */
2316 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
4a90920c 2317 dev_info(host->dev, "Version ID is %04x\n", host->verid);
4e0a5adf
JC		 2318
2319 if (host->verid < DW_MMC_240A)
2320 host->data_offset = DATA_OFFSET;
2321 else
2322 host->data_offset = DATA_240A_OFFSET;
2323
f95f3850 2324 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
4a90920c 2325 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
f95f3850
WN		 2326
2327 return 0;
2328
1791b13e 2329err_workqueue:
95dcc2cb 2330 destroy_workqueue(host->card_workqueue);
1791b13e 2331
f95f3850
WN		 2332err_dmaunmap:
2333 if (host->use_dma && host->dma_ops->exit)
2334 host->dma_ops->exit(host);
f95f3850 2335
780f22af 2336 if (host->vmmc)
c07946a3 2337 regulator_disable(host->vmmc);
f90a0612
TA		 2338
2339err_clk_ciu:
780f22af 2340 if (!IS_ERR(host->ciu_clk))
f90a0612 2341 clk_disable_unprepare(host->ciu_clk);
780f22af 2342
f90a0612 2343err_clk_biu:
780f22af 2344 if (!IS_ERR(host->biu_clk))
f90a0612 2345 clk_disable_unprepare(host->biu_clk);
780f22af 2346
f95f3850
WN		 2347 return ret;
2348}
62ca8034 2349EXPORT_SYMBOL(dw_mci_probe);
f95f3850 2350
62ca8034 2351void dw_mci_remove(struct dw_mci *host)
f95f3850 2352{
f95f3850
WN		 2353 int i;
2354
2355 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2356 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2357
f95f3850 2358 for (i = 0; i < host->num_slots; i++) {
4a90920c 2359 dev_dbg(host->dev, "remove slot %d\n", i);
f95f3850
WN		 2360 if (host->slot[i])
2361 dw_mci_cleanup_slot(host->slot[i], i);
2362 }
2363
2364 /* disable clock to CIU */
2365 mci_writel(host, CLKENA, 0);
2366 mci_writel(host, CLKSRC, 0);
2367
95dcc2cb 2368 destroy_workqueue(host->card_workqueue);
f95f3850
WN		 2369
2370 if (host->use_dma && host->dma_ops->exit)
2371 host->dma_ops->exit(host);
2372
780f22af 2373 if (host->vmmc)
c07946a3 2374 regulator_disable(host->vmmc);
c07946a3 2375
f90a0612
TA		 2376 if (!IS_ERR(host->ciu_clk))
2377 clk_disable_unprepare(host->ciu_clk);
780f22af 2378
f90a0612
TA		 2379 if (!IS_ERR(host->biu_clk))
2380 clk_disable_unprepare(host->biu_clk);
f95f3850 2381}
62ca8034
SH		 2382EXPORT_SYMBOL(dw_mci_remove);
2383
2384
f95f3850 2385
6fe8890d 2386#ifdef CONFIG_PM_SLEEP
f95f3850
WN		 2387/*
2388 * TODO: we should probably disable the clock to the card in the suspend path.
2389 */
62ca8034 2390int dw_mci_suspend(struct dw_mci *host)
f95f3850 2391{
62ca8034 2392 int i, ret = 0;
f95f3850
WN		 2393
2394 for (i = 0; i < host->num_slots; i++) {
2395 struct dw_mci_slot *slot = host->slot[i];
2396 if (!slot)
2397 continue;
2398 ret = mmc_suspend_host(slot->mmc);
2399 if (ret < 0) {
2400 while (--i >= 0) {
2401 slot = host->slot[i];
2402 if (slot)
2403 mmc_resume_host(host->slot[i]->mmc);
2404 }
2405 return ret;
2406 }
2407 }
2408
c07946a3
JC		 2409 if (host->vmmc)
2410 regulator_disable(host->vmmc);
2411
f95f3850
WN		 2412 return 0;
2413}
62ca8034 2414EXPORT_SYMBOL(dw_mci_suspend);
f95f3850 2415
62ca8034 2416int dw_mci_resume(struct dw_mci *host)
f95f3850
WN		 2417{
2418 int i, ret;
f95f3850 2419
1d6c4e0a
JC		 2420 if (host->vmmc)
2421 regulator_enable(host->vmmc);
2422
4a90920c 2423 if (!mci_wait_reset(host->dev, host)) {
e61cf118
JC		 2424 ret = -ENODEV;
2425 return ret;
2426 }
2427
3bfe619d 2428 if (host->use_dma && host->dma_ops->init)
141a712a
SJ		 2429 host->dma_ops->init(host);
2430
e61cf118
JC		 2431 /* Restore the old value at FIFOTH register */
2432 mci_writel(host, FIFOTH, host->fifoth_val);
2433
2434 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2435 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2436 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2437 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2438 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2439
f95f3850
WN		 2440 for (i = 0; i < host->num_slots; i++) {
2441 struct dw_mci_slot *slot = host->slot[i];
2442 if (!slot)
2443 continue;
ab269128
AK		 2444 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
2445 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
2446 dw_mci_setup_bus(slot, true);
2447 }
2448
f95f3850
WN		 2449 ret = mmc_resume_host(host->slot[i]->mmc);
2450 if (ret < 0)
2451 return ret;
2452 }
f95f3850
WN		 2453 return 0;
2454}
62ca8034 2455EXPORT_SYMBOL(dw_mci_resume);
6fe8890d
JC		 2456#endif /* CONFIG_PM_SLEEP */
2457
f95f3850
WN		 2458static int __init dw_mci_init(void)
2459{
62ca8034
SH		 2460 printk(KERN_INFO "Synopsys Designware Multimedia Card Interface Driver");
2461 return 0;
f95f3850
WN		 2462}
2463
2464static void __exit dw_mci_exit(void)
2465{
f95f3850
WN		 2466}
2467
2468module_init(dw_mci_init);
2469module_exit(dw_mci_exit);
2470
2471MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
2472MODULE_AUTHOR("NXP Semiconductor VietNam");
2473MODULE_AUTHOR("Imagination Technologies Ltd");
2474MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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