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f95f3850 WN |
1 | /* |
2 | * Synopsys DesignWare Multimedia Card Interface driver | |
3 | * (Based on NXP driver for lpc 31xx) | |
4 | * | |
5 | * Copyright (C) 2009 NXP Semiconductors | |
6 | * Copyright (C) 2009, 2010 Imagination Technologies Ltd. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #ifndef _DW_MMC_H_ | |
15 | #define _DW_MMC_H_ | |
16 | ||
4e0a5adf JC |
17 | #define DW_MMC_240A 0x240a |
18 | ||
f95f3850 WN |
19 | #define SDMMC_CTRL 0x000 |
20 | #define SDMMC_PWREN 0x004 | |
21 | #define SDMMC_CLKDIV 0x008 | |
22 | #define SDMMC_CLKSRC 0x00c | |
23 | #define SDMMC_CLKENA 0x010 | |
24 | #define SDMMC_TMOUT 0x014 | |
25 | #define SDMMC_CTYPE 0x018 | |
26 | #define SDMMC_BLKSIZ 0x01c | |
27 | #define SDMMC_BYTCNT 0x020 | |
28 | #define SDMMC_INTMASK 0x024 | |
29 | #define SDMMC_CMDARG 0x028 | |
30 | #define SDMMC_CMD 0x02c | |
31 | #define SDMMC_RESP0 0x030 | |
32 | #define SDMMC_RESP1 0x034 | |
33 | #define SDMMC_RESP2 0x038 | |
34 | #define SDMMC_RESP3 0x03c | |
35 | #define SDMMC_MINTSTS 0x040 | |
36 | #define SDMMC_RINTSTS 0x044 | |
37 | #define SDMMC_STATUS 0x048 | |
38 | #define SDMMC_FIFOTH 0x04c | |
39 | #define SDMMC_CDETECT 0x050 | |
40 | #define SDMMC_WRTPRT 0x054 | |
41 | #define SDMMC_GPIO 0x058 | |
42 | #define SDMMC_TCBCNT 0x05c | |
43 | #define SDMMC_TBBCNT 0x060 | |
44 | #define SDMMC_DEBNCE 0x064 | |
45 | #define SDMMC_USRID 0x068 | |
46 | #define SDMMC_VERID 0x06c | |
47 | #define SDMMC_HCON 0x070 | |
41babf75 | 48 | #define SDMMC_UHS_REG 0x074 |
f95f3850 WN |
49 | #define SDMMC_BMOD 0x080 |
50 | #define SDMMC_PLDMND 0x084 | |
51 | #define SDMMC_DBADDR 0x088 | |
52 | #define SDMMC_IDSTS 0x08c | |
53 | #define SDMMC_IDINTEN 0x090 | |
54 | #define SDMMC_DSCADDR 0x094 | |
55 | #define SDMMC_BUFADDR 0x098 | |
f1d2736c | 56 | #define SDMMC_CDTHRCTL 0x100 |
4e0a5adf | 57 | #define SDMMC_DATA(x) (x) |
69d99fdc PT |
58 | /* |
59 | * Registers to support idmac 64-bit address mode | |
60 | */ | |
61 | #define SDMMC_DBADDRL 0x088 | |
62 | #define SDMMC_DBADDRU 0x08c | |
63 | #define SDMMC_IDSTS64 0x090 | |
64 | #define SDMMC_IDINTEN64 0x094 | |
65 | #define SDMMC_DSCADDRL 0x098 | |
66 | #define SDMMC_DSCADDRU 0x09c | |
67 | #define SDMMC_BUFADDRL 0x0A0 | |
68 | #define SDMMC_BUFADDRU 0x0A4 | |
4e0a5adf JC |
69 | |
70 | /* | |
71 | * Data offset is difference according to Version | |
72 | * Lower than 2.40a : data register offest is 0x100 | |
73 | */ | |
74 | #define DATA_OFFSET 0x100 | |
75 | #define DATA_240A_OFFSET 0x200 | |
f95f3850 WN |
76 | |
77 | /* shift bit field */ | |
78 | #define _SBF(f, v) ((v) << (f)) | |
79 | ||
80 | /* Control register defines */ | |
81 | #define SDMMC_CTRL_USE_IDMAC BIT(25) | |
82 | #define SDMMC_CTRL_CEATA_INT_EN BIT(11) | |
83 | #define SDMMC_CTRL_SEND_AS_CCSD BIT(10) | |
84 | #define SDMMC_CTRL_SEND_CCSD BIT(9) | |
85 | #define SDMMC_CTRL_ABRT_READ_DATA BIT(8) | |
86 | #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7) | |
87 | #define SDMMC_CTRL_READ_WAIT BIT(6) | |
88 | #define SDMMC_CTRL_DMA_ENABLE BIT(5) | |
89 | #define SDMMC_CTRL_INT_ENABLE BIT(4) | |
90 | #define SDMMC_CTRL_DMA_RESET BIT(2) | |
91 | #define SDMMC_CTRL_FIFO_RESET BIT(1) | |
92 | #define SDMMC_CTRL_RESET BIT(0) | |
93 | /* Clock Enable register defines */ | |
94 | #define SDMMC_CLKEN_LOW_PWR BIT(16) | |
95 | #define SDMMC_CLKEN_ENABLE BIT(0) | |
96 | /* time-out register defines */ | |
97 | #define SDMMC_TMOUT_DATA(n) _SBF(8, (n)) | |
98 | #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00 | |
99 | #define SDMMC_TMOUT_RESP(n) ((n) & 0xFF) | |
100 | #define SDMMC_TMOUT_RESP_MSK 0xFF | |
101 | /* card-type register defines */ | |
102 | #define SDMMC_CTYPE_8BIT BIT(16) | |
103 | #define SDMMC_CTYPE_4BIT BIT(0) | |
104 | #define SDMMC_CTYPE_1BIT 0 | |
105 | /* Interrupt status & mask register defines */ | |
1a5c8e1f | 106 | #define SDMMC_INT_SDIO(n) BIT(16 + (n)) |
f95f3850 WN |
107 | #define SDMMC_INT_EBE BIT(15) |
108 | #define SDMMC_INT_ACD BIT(14) | |
109 | #define SDMMC_INT_SBE BIT(13) | |
110 | #define SDMMC_INT_HLE BIT(12) | |
111 | #define SDMMC_INT_FRUN BIT(11) | |
112 | #define SDMMC_INT_HTO BIT(10) | |
01730558 | 113 | #define SDMMC_INT_VOLT_SWITCH BIT(10) /* overloads bit 10! */ |
3f7eec62 | 114 | #define SDMMC_INT_DRTO BIT(9) |
f95f3850 WN |
115 | #define SDMMC_INT_RTO BIT(8) |
116 | #define SDMMC_INT_DCRC BIT(7) | |
117 | #define SDMMC_INT_RCRC BIT(6) | |
118 | #define SDMMC_INT_RXDR BIT(5) | |
119 | #define SDMMC_INT_TXDR BIT(4) | |
120 | #define SDMMC_INT_DATA_OVER BIT(3) | |
121 | #define SDMMC_INT_CMD_DONE BIT(2) | |
122 | #define SDMMC_INT_RESP_ERR BIT(1) | |
123 | #define SDMMC_INT_CD BIT(0) | |
124 | #define SDMMC_INT_ERROR 0xbfc2 | |
125 | /* Command register defines */ | |
126 | #define SDMMC_CMD_START BIT(31) | |
eede2111 | 127 | #define SDMMC_CMD_USE_HOLD_REG BIT(29) |
01730558 | 128 | #define SDMMC_CMD_VOLT_SWITCH BIT(28) |
f95f3850 WN |
129 | #define SDMMC_CMD_CCS_EXP BIT(23) |
130 | #define SDMMC_CMD_CEATA_RD BIT(22) | |
131 | #define SDMMC_CMD_UPD_CLK BIT(21) | |
132 | #define SDMMC_CMD_INIT BIT(15) | |
133 | #define SDMMC_CMD_STOP BIT(14) | |
134 | #define SDMMC_CMD_PRV_DAT_WAIT BIT(13) | |
135 | #define SDMMC_CMD_SEND_STOP BIT(12) | |
136 | #define SDMMC_CMD_STRM_MODE BIT(11) | |
137 | #define SDMMC_CMD_DAT_WR BIT(10) | |
138 | #define SDMMC_CMD_DAT_EXP BIT(9) | |
139 | #define SDMMC_CMD_RESP_CRC BIT(8) | |
140 | #define SDMMC_CMD_RESP_LONG BIT(7) | |
141 | #define SDMMC_CMD_RESP_EXP BIT(6) | |
142 | #define SDMMC_CMD_INDX(n) ((n) & 0x1F) | |
143 | /* Status register defines */ | |
ee5d19b2 | 144 | #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF) |
3a33a94c | 145 | #define SDMMC_STATUS_DMA_REQ BIT(31) |
01730558 | 146 | #define SDMMC_STATUS_BUSY BIT(9) |
52426899 SJ |
147 | /* FIFOTH register defines */ |
148 | #define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \ | |
149 | ((r) & 0xFFF) << 16 | \ | |
150 | ((t) & 0xFFF)) | |
3fc7eaef SL |
151 | /* HCON register defines */ |
152 | #define DMA_INTERFACE_IDMA (0x0) | |
153 | #define DMA_INTERFACE_DWDMA (0x1) | |
154 | #define DMA_INTERFACE_GDMA (0x2) | |
155 | #define DMA_INTERFACE_NODMA (0x3) | |
156 | #define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3) | |
70692752 SL |
157 | #define SDMMC_GET_SLOT_NUM(x) ((((x)>>1) & 0x1F) + 1) |
158 | #define SDMMC_GET_HDATA_WIDTH(x) (((x)>>7) & 0x7) | |
159 | #define SDMMC_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1) | |
f95f3850 WN |
160 | /* Internal DMAC interrupt defines */ |
161 | #define SDMMC_IDMAC_INT_AI BIT(9) | |
162 | #define SDMMC_IDMAC_INT_NI BIT(8) | |
163 | #define SDMMC_IDMAC_INT_CES BIT(5) | |
164 | #define SDMMC_IDMAC_INT_DU BIT(4) | |
165 | #define SDMMC_IDMAC_INT_FBE BIT(2) | |
166 | #define SDMMC_IDMAC_INT_RI BIT(1) | |
167 | #define SDMMC_IDMAC_INT_TI BIT(0) | |
168 | /* Internal DMAC bus mode bits */ | |
169 | #define SDMMC_IDMAC_ENABLE BIT(7) | |
170 | #define SDMMC_IDMAC_FB BIT(1) | |
171 | #define SDMMC_IDMAC_SWRESET BIT(0) | |
4e0a5adf JC |
172 | /* Version ID register define */ |
173 | #define SDMMC_GET_VERID(x) ((x) & 0xFFFF) | |
f1d2736c | 174 | /* Card read threshold */ |
98daafd8 | 175 | #define SDMMC_SET_RD_THLD(v, x) (((v) & 0xFFF) << 16 | (x)) |
01730558 | 176 | #define SDMMC_UHS_18V BIT(0) |
3a33a94c SR |
177 | /* All ctrl reset bits */ |
178 | #define SDMMC_CTRL_ALL_RESET_FLAGS \ | |
179 | (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET) | |
180 | ||
76184ac1 BD |
181 | /* FIFO register access macros. These should not change the data endian-ness |
182 | * as they are written to memory to be dealt with by the upper layers */ | |
183 | #define mci_fifo_readw(__reg) __raw_readw(__reg) | |
184 | #define mci_fifo_readl(__reg) __raw_readl(__reg) | |
185 | #define mci_fifo_readq(__reg) __raw_readq(__reg) | |
186 | ||
187 | #define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value) | |
188 | #define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value) | |
189 | #define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value) | |
190 | ||
f95f3850 WN |
191 | /* Register access macros */ |
192 | #define mci_readl(dev, reg) \ | |
a2f17680 | 193 | readl_relaxed((dev)->regs + SDMMC_##reg) |
f95f3850 | 194 | #define mci_writel(dev, reg, value) \ |
a2f17680 | 195 | writel_relaxed((value), (dev)->regs + SDMMC_##reg) |
f95f3850 WN |
196 | |
197 | /* 16-bit FIFO access macros */ | |
198 | #define mci_readw(dev, reg) \ | |
a2f17680 | 199 | readw_relaxed((dev)->regs + SDMMC_##reg) |
f95f3850 | 200 | #define mci_writew(dev, reg, value) \ |
a2f17680 | 201 | writew_relaxed((value), (dev)->regs + SDMMC_##reg) |
f95f3850 WN |
202 | |
203 | /* 64-bit FIFO access macros */ | |
204 | #ifdef readq | |
205 | #define mci_readq(dev, reg) \ | |
a2f17680 | 206 | readq_relaxed((dev)->regs + SDMMC_##reg) |
f95f3850 | 207 | #define mci_writeq(dev, reg, value) \ |
a2f17680 | 208 | writeq_relaxed((value), (dev)->regs + SDMMC_##reg) |
f95f3850 WN |
209 | #else |
210 | /* | |
211 | * Dummy readq implementation for architectures that don't define it. | |
212 | * | |
213 | * We would assume that none of these architectures would configure | |
214 | * the IP block with a 64bit FIFO width, so this code will never be | |
215 | * executed on those machines. Defining these macros here keeps the | |
216 | * rest of the code free from ifdefs. | |
217 | */ | |
218 | #define mci_readq(dev, reg) \ | |
892b1e31 | 219 | (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg)) |
f95f3850 | 220 | #define mci_writeq(dev, reg, value) \ |
892b1e31 | 221 | (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value)) |
76184ac1 BD |
222 | |
223 | #define __raw_writeq(__value, __reg) \ | |
224 | (*(volatile u64 __force *)(__reg) = (__value)) | |
225 | #define __raw_readq(__reg) (*(volatile u64 __force *)(__reg)) | |
f95f3850 WN |
226 | #endif |
227 | ||
62ca8034 SH |
228 | extern int dw_mci_probe(struct dw_mci *host); |
229 | extern void dw_mci_remove(struct dw_mci *host); | |
370aede6 | 230 | #ifdef CONFIG_PM_SLEEP |
62ca8034 SH |
231 | extern int dw_mci_suspend(struct dw_mci *host); |
232 | extern int dw_mci_resume(struct dw_mci *host); | |
233 | #endif | |
234 | ||
0976f16d SJ |
235 | /** |
236 | * struct dw_mci_slot - MMC slot state | |
237 | * @mmc: The mmc_host representing this slot. | |
238 | * @host: The MMC controller this slot is using. | |
0976f16d SJ |
239 | * @ctype: Card type for this slot. |
240 | * @mrq: mmc_request currently being processed or waiting to be | |
241 | * processed, or NULL when the slot is idle. | |
242 | * @queue_node: List node for placing this node in the @queue list of | |
243 | * &struct dw_mci. | |
244 | * @clock: Clock rate configured by set_ios(). Protected by host->lock. | |
245 | * @__clk_old: The last updated clock with reflecting clock divider. | |
246 | * Keeping track of this helps us to avoid spamming the console | |
247 | * with CONFIG_MMC_CLKGATE. | |
248 | * @flags: Random state bits associated with the slot. | |
249 | * @id: Number of this slot. | |
76756234 | 250 | * @sdio_id: Number of this slot in the SDIO interrupt registers. |
0976f16d SJ |
251 | */ |
252 | struct dw_mci_slot { | |
253 | struct mmc_host *mmc; | |
254 | struct dw_mci *host; | |
255 | ||
0976f16d SJ |
256 | u32 ctype; |
257 | ||
258 | struct mmc_request *mrq; | |
259 | struct list_head queue_node; | |
260 | ||
261 | unsigned int clock; | |
262 | unsigned int __clk_old; | |
263 | ||
264 | unsigned long flags; | |
265 | #define DW_MMC_CARD_PRESENT 0 | |
266 | #define DW_MMC_CARD_NEED_INIT 1 | |
b24c8b26 | 267 | #define DW_MMC_CARD_NO_LOW_PWR 2 |
aaaaeb7a | 268 | #define DW_MMC_CARD_NO_USE_HOLD 3 |
0976f16d | 269 | int id; |
76756234 | 270 | int sdio_id; |
0976f16d SJ |
271 | }; |
272 | ||
800d78bf TA |
273 | /** |
274 | * dw_mci driver data - dw-mshc implementation specific driver data. | |
275 | * @caps: mmc subsystem specified capabilities of the controller(s). | |
276 | * @init: early implementation specific initialization. | |
277 | * @setup_clock: implementation specific clock configuration. | |
800d78bf TA |
278 | * @set_ios: handle bus specific extensions. |
279 | * @parse_dt: parse implementation specific device tree properties. | |
5532ec51 | 280 | * @execute_tuning: implementation specific tuning procedure. |
800d78bf TA |
281 | * |
282 | * Provide controller implementation specific extensions. The usage of this | |
283 | * data structure is fully optional and usage of each member in this structure | |
284 | * is optional as well. | |
285 | */ | |
286 | struct dw_mci_drv_data { | |
287 | unsigned long *caps; | |
288 | int (*init)(struct dw_mci *host); | |
289 | int (*setup_clock)(struct dw_mci *host); | |
800d78bf TA |
290 | void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios); |
291 | int (*parse_dt)(struct dw_mci *host); | |
9979dbe5 | 292 | int (*execute_tuning)(struct dw_mci_slot *slot, u32 opcode); |
80113132 SJ |
293 | int (*prepare_hs400_tuning)(struct dw_mci *host, |
294 | struct mmc_ios *ios); | |
8f7849c4 ZG |
295 | int (*switch_voltage)(struct mmc_host *mmc, |
296 | struct mmc_ios *ios); | |
800d78bf | 297 | }; |
f95f3850 | 298 | #endif /* _DW_MMC_H_ */ |