projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| f95f3850 WN |
1 | /* |
| 2 | * Synopsys DesignWare Multimedia Card Interface driver | |
| 3 | * (Based on NXP driver for lpc 31xx) | |
| 4 | * | |
| 5 | * Copyright (C) 2009 NXP Semiconductors | |
| 6 | * Copyright (C) 2009, 2010 Imagination Technologies Ltd. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or modify | |
| 9 | * it under the terms of the GNU General Public License as published by | |
| 10 | * the Free Software Foundation; either version 2 of the License, or | |
| 11 | * (at your option) any later version. | |
| 12 | */ | |
| 13 | ||
| 14 | #ifndef _DW_MMC_H_ | |
| 15 | #define _DW_MMC_H_ | |
| 16 | ||
| 17 | #define SDMMC_CTRL 0x000 | |
| 18 | #define SDMMC_PWREN 0x004 | |
| 19 | #define SDMMC_CLKDIV 0x008 | |
| 20 | #define SDMMC_CLKSRC 0x00c | |
| 21 | #define SDMMC_CLKENA 0x010 | |
| 22 | #define SDMMC_TMOUT 0x014 | |
| 23 | #define SDMMC_CTYPE 0x018 | |
| 24 | #define SDMMC_BLKSIZ 0x01c | |
| 25 | #define SDMMC_BYTCNT 0x020 | |
| 26 | #define SDMMC_INTMASK 0x024 | |
| 27 | #define SDMMC_CMDARG 0x028 | |
| 28 | #define SDMMC_CMD 0x02c | |
| 29 | #define SDMMC_RESP0 0x030 | |
| 30 | #define SDMMC_RESP1 0x034 | |
| 31 | #define SDMMC_RESP2 0x038 | |
| 32 | #define SDMMC_RESP3 0x03c | |
| 33 | #define SDMMC_MINTSTS 0x040 | |
| 34 | #define SDMMC_RINTSTS 0x044 | |
| 35 | #define SDMMC_STATUS 0x048 | |
| 36 | #define SDMMC_FIFOTH 0x04c | |
| 37 | #define SDMMC_CDETECT 0x050 | |
| 38 | #define SDMMC_WRTPRT 0x054 | |
| 39 | #define SDMMC_GPIO 0x058 | |
| 40 | #define SDMMC_TCBCNT 0x05c | |
| 41 | #define SDMMC_TBBCNT 0x060 | |
| 42 | #define SDMMC_DEBNCE 0x064 | |
| 43 | #define SDMMC_USRID 0x068 | |
| 44 | #define SDMMC_VERID 0x06c | |
| 45 | #define SDMMC_HCON 0x070 | |
| 46 | #define SDMMC_BMOD 0x080 | |
| 47 | #define SDMMC_PLDMND 0x084 | |
| 48 | #define SDMMC_DBADDR 0x088 | |
| 49 | #define SDMMC_IDSTS 0x08c | |
| 50 | #define SDMMC_IDINTEN 0x090 | |
| 51 | #define SDMMC_DSCADDR 0x094 | |
| 52 | #define SDMMC_BUFADDR 0x098 | |
| 53 | #define SDMMC_DATA 0x100 | |
| 54 | #define SDMMC_DATA_ADR 0x100 | |
| 55 | ||
| 56 | /* shift bit field */ | |
| 57 | #define _SBF(f, v) ((v) << (f)) | |
| 58 | ||
| 59 | /* Control register defines */ | |
| 60 | #define SDMMC_CTRL_USE_IDMAC BIT(25) | |
| 61 | #define SDMMC_CTRL_CEATA_INT_EN BIT(11) | |
| 62 | #define SDMMC_CTRL_SEND_AS_CCSD BIT(10) | |
| 63 | #define SDMMC_CTRL_SEND_CCSD BIT(9) | |
| 64 | #define SDMMC_CTRL_ABRT_READ_DATA BIT(8) | |
| 65 | #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7) | |
| 66 | #define SDMMC_CTRL_READ_WAIT BIT(6) | |
| 67 | #define SDMMC_CTRL_DMA_ENABLE BIT(5) | |
| 68 | #define SDMMC_CTRL_INT_ENABLE BIT(4) | |
| 69 | #define SDMMC_CTRL_DMA_RESET BIT(2) | |
| 70 | #define SDMMC_CTRL_FIFO_RESET BIT(1) | |
| 71 | #define SDMMC_CTRL_RESET BIT(0) | |
| 72 | /* Clock Enable register defines */ | |
| 73 | #define SDMMC_CLKEN_LOW_PWR BIT(16) | |
| 74 | #define SDMMC_CLKEN_ENABLE BIT(0) | |
| 75 | /* time-out register defines */ | |
| 76 | #define SDMMC_TMOUT_DATA(n) _SBF(8, (n)) | |
| 77 | #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00 | |
| 78 | #define SDMMC_TMOUT_RESP(n) ((n) & 0xFF) | |
| 79 | #define SDMMC_TMOUT_RESP_MSK 0xFF | |
| 80 | /* card-type register defines */ | |
| 81 | #define SDMMC_CTYPE_8BIT BIT(16) | |
| 82 | #define SDMMC_CTYPE_4BIT BIT(0) | |
| 83 | #define SDMMC_CTYPE_1BIT 0 | |
| 84 | /* Interrupt status & mask register defines */ | |
| 85 | #define SDMMC_INT_SDIO BIT(16) | |
| 86 | #define SDMMC_INT_EBE BIT(15) | |
| 87 | #define SDMMC_INT_ACD BIT(14) | |
| 88 | #define SDMMC_INT_SBE BIT(13) | |
| 89 | #define SDMMC_INT_HLE BIT(12) | |
| 90 | #define SDMMC_INT_FRUN BIT(11) | |
| 91 | #define SDMMC_INT_HTO BIT(10) | |
| 92 | #define SDMMC_INT_DTO BIT(9) | |
| 93 | #define SDMMC_INT_RTO BIT(8) | |
| 94 | #define SDMMC_INT_DCRC BIT(7) | |
| 95 | #define SDMMC_INT_RCRC BIT(6) | |
| 96 | #define SDMMC_INT_RXDR BIT(5) | |
| 97 | #define SDMMC_INT_TXDR BIT(4) | |
| 98 | #define SDMMC_INT_DATA_OVER BIT(3) | |
| 99 | #define SDMMC_INT_CMD_DONE BIT(2) | |
| 100 | #define SDMMC_INT_RESP_ERR BIT(1) | |
| 101 | #define SDMMC_INT_CD BIT(0) | |
| 102 | #define SDMMC_INT_ERROR 0xbfc2 | |
| 103 | /* Command register defines */ | |
| 104 | #define SDMMC_CMD_START BIT(31) | |
| 105 | #define SDMMC_CMD_CCS_EXP BIT(23) | |
| 106 | #define SDMMC_CMD_CEATA_RD BIT(22) | |
| 107 | #define SDMMC_CMD_UPD_CLK BIT(21) | |
| 108 | #define SDMMC_CMD_INIT BIT(15) | |
| 109 | #define SDMMC_CMD_STOP BIT(14) | |
| 110 | #define SDMMC_CMD_PRV_DAT_WAIT BIT(13) | |
| 111 | #define SDMMC_CMD_SEND_STOP BIT(12) | |
| 112 | #define SDMMC_CMD_STRM_MODE BIT(11) | |
| 113 | #define SDMMC_CMD_DAT_WR BIT(10) | |
| 114 | #define SDMMC_CMD_DAT_EXP BIT(9) | |
| 115 | #define SDMMC_CMD_RESP_CRC BIT(8) | |
| 116 | #define SDMMC_CMD_RESP_LONG BIT(7) | |
| 117 | #define SDMMC_CMD_RESP_EXP BIT(6) | |
| 118 | #define SDMMC_CMD_INDX(n) ((n) & 0x1F) | |
| 119 | /* Status register defines */ | |
| 120 | #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FF) | |
| 121 | #define SDMMC_FIFO_SZ 32 | |
| 122 | /* Internal DMAC interrupt defines */ | |
| 123 | #define SDMMC_IDMAC_INT_AI BIT(9) | |
| 124 | #define SDMMC_IDMAC_INT_NI BIT(8) | |
| 125 | #define SDMMC_IDMAC_INT_CES BIT(5) | |
| 126 | #define SDMMC_IDMAC_INT_DU BIT(4) | |
| 127 | #define SDMMC_IDMAC_INT_FBE BIT(2) | |
| 128 | #define SDMMC_IDMAC_INT_RI BIT(1) | |
| 129 | #define SDMMC_IDMAC_INT_TI BIT(0) | |
| 130 | /* Internal DMAC bus mode bits */ | |
| 131 | #define SDMMC_IDMAC_ENABLE BIT(7) | |
| 132 | #define SDMMC_IDMAC_FB BIT(1) | |
| 133 | #define SDMMC_IDMAC_SWRESET BIT(0) | |
| 134 | ||
| 135 | /* Register access macros */ | |
| 136 | #define mci_readl(dev, reg) \ | |
| 137 | __raw_readl(dev->regs + SDMMC_##reg) | |
| 138 | #define mci_writel(dev, reg, value) \ | |
| 139 | __raw_writel((value), dev->regs + SDMMC_##reg) | |
| 140 | ||
| 141 | /* 16-bit FIFO access macros */ | |
| 142 | #define mci_readw(dev, reg) \ | |
| 143 | __raw_readw(dev->regs + SDMMC_##reg) | |
| 144 | #define mci_writew(dev, reg, value) \ | |
| 145 | __raw_writew((value), dev->regs + SDMMC_##reg) | |
| 146 | ||
| 147 | /* 64-bit FIFO access macros */ | |
| 148 | #ifdef readq | |
| 149 | #define mci_readq(dev, reg) \ | |
| 150 | __raw_readq(dev->regs + SDMMC_##reg) | |
| 151 | #define mci_writeq(dev, reg, value) \ | |
| 152 | __raw_writeq((value), dev->regs + SDMMC_##reg) | |
| 153 | #else | |
| 154 | /* | |
| 155 | * Dummy readq implementation for architectures that don't define it. | |
| 156 | * | |
| 157 | * We would assume that none of these architectures would configure | |
| 158 | * the IP block with a 64bit FIFO width, so this code will never be | |
| 159 | * executed on those machines. Defining these macros here keeps the | |
| 160 | * rest of the code free from ifdefs. | |
| 161 | */ | |
| 162 | #define mci_readq(dev, reg) \ | |
| 163 | (*(volatile u64 __force *)(dev->regs + SDMMC_##reg)) | |
| 164 | #define mci_writeq(dev, reg, value) \ | |
| 165 | (*(volatile u64 __force *)(dev->regs + SDMMC_##reg) = value) | |
| 166 | #endif | |
| 167 | ||
| 168 | #endif /* _DW_MMC_H_ */ |