Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. | |
c8ebae37 | 5 | * Copyright (C) 2010 ST-Ericsson SA |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/interrupt.h> | |
613b152c | 17 | #include <linux/kernel.h> |
000bc9d5 | 18 | #include <linux/slab.h> |
1da177e4 LT |
19 | #include <linux/delay.h> |
20 | #include <linux/err.h> | |
21 | #include <linux/highmem.h> | |
019a5f56 | 22 | #include <linux/log2.h> |
70be208f | 23 | #include <linux/mmc/pm.h> |
1da177e4 | 24 | #include <linux/mmc/host.h> |
34177802 | 25 | #include <linux/mmc/card.h> |
a62c80e5 | 26 | #include <linux/amba/bus.h> |
f8ce2547 | 27 | #include <linux/clk.h> |
bd6dee6f | 28 | #include <linux/scatterlist.h> |
89001446 | 29 | #include <linux/gpio.h> |
9a597016 | 30 | #include <linux/of_gpio.h> |
34e84f39 | 31 | #include <linux/regulator/consumer.h> |
c8ebae37 RK |
32 | #include <linux/dmaengine.h> |
33 | #include <linux/dma-mapping.h> | |
34 | #include <linux/amba/mmci.h> | |
1c3be369 | 35 | #include <linux/pm_runtime.h> |
258aea76 | 36 | #include <linux/types.h> |
a9a83785 | 37 | #include <linux/pinctrl/consumer.h> |
1da177e4 | 38 | |
7b09cdac | 39 | #include <asm/div64.h> |
1da177e4 | 40 | #include <asm/io.h> |
c6b8fdad | 41 | #include <asm/sizes.h> |
1da177e4 LT |
42 | |
43 | #include "mmci.h" | |
44 | ||
45 | #define DRIVER_NAME "mmci-pl18x" | |
46 | ||
1da177e4 LT |
47 | static unsigned int fmax = 515633; |
48 | ||
4956e109 RV |
49 | /** |
50 | * struct variant_data - MMCI variant-specific quirks | |
51 | * @clkreg: default value for MCICLOCK register | |
4380c14f | 52 | * @clkreg_enable: enable value for MMCICLOCK register |
08458ef6 | 53 | * @datalength_bits: number of bits in the MMCIDATALENGTH register |
8301bb68 RV |
54 | * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY |
55 | * is asserted (likewise for RX) | |
56 | * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY | |
57 | * is asserted (likewise for RX) | |
34177802 | 58 | * @sdio: variant supports SDIO |
b70a67f9 | 59 | * @st_clkdiv: true if using a ST-specific clock divider algorithm |
1784b157 | 60 | * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register |
7d72a1d4 | 61 | * @pwrreg_powerup: power up value for MMCIPOWER register |
4d1a3a0d | 62 | * @signal_direction: input/out direction of bus signals can be indicated |
f4670dae | 63 | * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock |
4956e109 RV |
64 | */ |
65 | struct variant_data { | |
66 | unsigned int clkreg; | |
4380c14f | 67 | unsigned int clkreg_enable; |
08458ef6 | 68 | unsigned int datalength_bits; |
8301bb68 RV |
69 | unsigned int fifosize; |
70 | unsigned int fifohalfsize; | |
34177802 | 71 | bool sdio; |
b70a67f9 | 72 | bool st_clkdiv; |
1784b157 | 73 | bool blksz_datactrl16; |
7d72a1d4 | 74 | u32 pwrreg_powerup; |
4d1a3a0d | 75 | bool signal_direction; |
f4670dae | 76 | bool pwrreg_clkgate; |
4956e109 RV |
77 | }; |
78 | ||
79 | static struct variant_data variant_arm = { | |
8301bb68 RV |
80 | .fifosize = 16 * 4, |
81 | .fifohalfsize = 8 * 4, | |
08458ef6 | 82 | .datalength_bits = 16, |
7d72a1d4 | 83 | .pwrreg_powerup = MCI_PWR_UP, |
4956e109 RV |
84 | }; |
85 | ||
768fbc18 PM |
86 | static struct variant_data variant_arm_extended_fifo = { |
87 | .fifosize = 128 * 4, | |
88 | .fifohalfsize = 64 * 4, | |
89 | .datalength_bits = 16, | |
7d72a1d4 | 90 | .pwrreg_powerup = MCI_PWR_UP, |
768fbc18 PM |
91 | }; |
92 | ||
3a37298a PM |
93 | static struct variant_data variant_arm_extended_fifo_hwfc = { |
94 | .fifosize = 128 * 4, | |
95 | .fifohalfsize = 64 * 4, | |
96 | .clkreg_enable = MCI_ARM_HWFCEN, | |
97 | .datalength_bits = 16, | |
98 | .pwrreg_powerup = MCI_PWR_UP, | |
99 | }; | |
100 | ||
4956e109 | 101 | static struct variant_data variant_u300 = { |
8301bb68 RV |
102 | .fifosize = 16 * 4, |
103 | .fifohalfsize = 8 * 4, | |
49ac215e | 104 | .clkreg_enable = MCI_ST_U300_HWFCEN, |
08458ef6 | 105 | .datalength_bits = 16, |
34177802 | 106 | .sdio = true, |
7d72a1d4 | 107 | .pwrreg_powerup = MCI_PWR_ON, |
4d1a3a0d | 108 | .signal_direction = true, |
f4670dae | 109 | .pwrreg_clkgate = true, |
4956e109 RV |
110 | }; |
111 | ||
34fd4213 LW |
112 | static struct variant_data variant_nomadik = { |
113 | .fifosize = 16 * 4, | |
114 | .fifohalfsize = 8 * 4, | |
115 | .clkreg = MCI_CLK_ENABLE, | |
116 | .datalength_bits = 24, | |
117 | .sdio = true, | |
118 | .st_clkdiv = true, | |
119 | .pwrreg_powerup = MCI_PWR_ON, | |
120 | .signal_direction = true, | |
f4670dae | 121 | .pwrreg_clkgate = true, |
34fd4213 LW |
122 | }; |
123 | ||
4956e109 | 124 | static struct variant_data variant_ux500 = { |
8301bb68 RV |
125 | .fifosize = 30 * 4, |
126 | .fifohalfsize = 8 * 4, | |
4956e109 | 127 | .clkreg = MCI_CLK_ENABLE, |
49ac215e | 128 | .clkreg_enable = MCI_ST_UX500_HWFCEN, |
08458ef6 | 129 | .datalength_bits = 24, |
34177802 | 130 | .sdio = true, |
b70a67f9 | 131 | .st_clkdiv = true, |
7d72a1d4 | 132 | .pwrreg_powerup = MCI_PWR_ON, |
4d1a3a0d | 133 | .signal_direction = true, |
f4670dae | 134 | .pwrreg_clkgate = true, |
4956e109 | 135 | }; |
b70a67f9 | 136 | |
1784b157 PL |
137 | static struct variant_data variant_ux500v2 = { |
138 | .fifosize = 30 * 4, | |
139 | .fifohalfsize = 8 * 4, | |
140 | .clkreg = MCI_CLK_ENABLE, | |
141 | .clkreg_enable = MCI_ST_UX500_HWFCEN, | |
142 | .datalength_bits = 24, | |
143 | .sdio = true, | |
144 | .st_clkdiv = true, | |
145 | .blksz_datactrl16 = true, | |
7d72a1d4 | 146 | .pwrreg_powerup = MCI_PWR_ON, |
4d1a3a0d | 147 | .signal_direction = true, |
f4670dae | 148 | .pwrreg_clkgate = true, |
1784b157 PL |
149 | }; |
150 | ||
653a761e UH |
151 | /* |
152 | * Validate mmc prerequisites | |
153 | */ | |
154 | static int mmci_validate_data(struct mmci_host *host, | |
155 | struct mmc_data *data) | |
156 | { | |
157 | if (!data) | |
158 | return 0; | |
159 | ||
160 | if (!is_power_of_2(data->blksz)) { | |
161 | dev_err(mmc_dev(host->mmc), | |
162 | "unsupported block size (%d bytes)\n", data->blksz); | |
163 | return -EINVAL; | |
164 | } | |
165 | ||
166 | return 0; | |
167 | } | |
168 | ||
7437cfa5 UH |
169 | /* |
170 | * This must be called with host->lock held | |
171 | */ | |
172 | static void mmci_write_clkreg(struct mmci_host *host, u32 clk) | |
173 | { | |
174 | if (host->clk_reg != clk) { | |
175 | host->clk_reg = clk; | |
176 | writel(clk, host->base + MMCICLOCK); | |
177 | } | |
178 | } | |
179 | ||
180 | /* | |
181 | * This must be called with host->lock held | |
182 | */ | |
183 | static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) | |
184 | { | |
185 | if (host->pwr_reg != pwr) { | |
186 | host->pwr_reg = pwr; | |
187 | writel(pwr, host->base + MMCIPOWER); | |
188 | } | |
189 | } | |
190 | ||
a6a6464a LW |
191 | /* |
192 | * This must be called with host->lock held | |
193 | */ | |
194 | static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) | |
195 | { | |
4956e109 RV |
196 | struct variant_data *variant = host->variant; |
197 | u32 clk = variant->clkreg; | |
a6a6464a | 198 | |
c58a8509 UH |
199 | /* Make sure cclk reflects the current calculated clock */ |
200 | host->cclk = 0; | |
201 | ||
a6a6464a LW |
202 | if (desired) { |
203 | if (desired >= host->mclk) { | |
991a86e1 | 204 | clk = MCI_CLK_BYPASS; |
399bc486 LW |
205 | if (variant->st_clkdiv) |
206 | clk |= MCI_ST_UX500_NEG_EDGE; | |
a6a6464a | 207 | host->cclk = host->mclk; |
b70a67f9 LW |
208 | } else if (variant->st_clkdiv) { |
209 | /* | |
210 | * DB8500 TRM says f = mclk / (clkdiv + 2) | |
211 | * => clkdiv = (mclk / f) - 2 | |
212 | * Round the divider up so we don't exceed the max | |
213 | * frequency | |
214 | */ | |
215 | clk = DIV_ROUND_UP(host->mclk, desired) - 2; | |
216 | if (clk >= 256) | |
217 | clk = 255; | |
218 | host->cclk = host->mclk / (clk + 2); | |
a6a6464a | 219 | } else { |
b70a67f9 LW |
220 | /* |
221 | * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) | |
222 | * => clkdiv = mclk / (2 * f) - 1 | |
223 | */ | |
a6a6464a LW |
224 | clk = host->mclk / (2 * desired) - 1; |
225 | if (clk >= 256) | |
226 | clk = 255; | |
227 | host->cclk = host->mclk / (2 * (clk + 1)); | |
228 | } | |
4380c14f RV |
229 | |
230 | clk |= variant->clkreg_enable; | |
a6a6464a LW |
231 | clk |= MCI_CLK_ENABLE; |
232 | /* This hasn't proven to be worthwhile */ | |
233 | /* clk |= MCI_CLK_PWRSAVE; */ | |
234 | } | |
235 | ||
c58a8509 UH |
236 | /* Set actual clock for debug */ |
237 | host->mmc->actual_clock = host->cclk; | |
238 | ||
9e6c82cd | 239 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) |
771dc157 LW |
240 | clk |= MCI_4BIT_BUS; |
241 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) | |
242 | clk |= MCI_ST_8BIT_BUS; | |
9e6c82cd | 243 | |
6dbb6ee0 UH |
244 | if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) |
245 | clk |= MCI_ST_UX500_NEG_EDGE; | |
246 | ||
7437cfa5 | 247 | mmci_write_clkreg(host, clk); |
a6a6464a LW |
248 | } |
249 | ||
1da177e4 LT |
250 | static void |
251 | mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) | |
252 | { | |
253 | writel(0, host->base + MMCICOMMAND); | |
254 | ||
e47c222b RK |
255 | BUG_ON(host->data); |
256 | ||
1da177e4 LT |
257 | host->mrq = NULL; |
258 | host->cmd = NULL; | |
259 | ||
1da177e4 | 260 | mmc_request_done(host->mmc, mrq); |
2cd976c4 UH |
261 | |
262 | pm_runtime_mark_last_busy(mmc_dev(host->mmc)); | |
263 | pm_runtime_put_autosuspend(mmc_dev(host->mmc)); | |
1da177e4 LT |
264 | } |
265 | ||
2686b4b4 LW |
266 | static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) |
267 | { | |
268 | void __iomem *base = host->base; | |
269 | ||
270 | if (host->singleirq) { | |
271 | unsigned int mask0 = readl(base + MMCIMASK0); | |
272 | ||
273 | mask0 &= ~MCI_IRQ1MASK; | |
274 | mask0 |= mask; | |
275 | ||
276 | writel(mask0, base + MMCIMASK0); | |
277 | } | |
278 | ||
279 | writel(mask, base + MMCIMASK1); | |
280 | } | |
281 | ||
1da177e4 LT |
282 | static void mmci_stop_data(struct mmci_host *host) |
283 | { | |
284 | writel(0, host->base + MMCIDATACTRL); | |
2686b4b4 | 285 | mmci_set_mask1(host, 0); |
1da177e4 LT |
286 | host->data = NULL; |
287 | } | |
288 | ||
4ce1d6cb RV |
289 | static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) |
290 | { | |
291 | unsigned int flags = SG_MITER_ATOMIC; | |
292 | ||
293 | if (data->flags & MMC_DATA_READ) | |
294 | flags |= SG_MITER_TO_SG; | |
295 | else | |
296 | flags |= SG_MITER_FROM_SG; | |
297 | ||
298 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); | |
299 | } | |
300 | ||
c8ebae37 RK |
301 | /* |
302 | * All the DMA operation mode stuff goes inside this ifdef. | |
303 | * This assumes that you have a generic DMA device interface, | |
304 | * no custom DMA interfaces are supported. | |
305 | */ | |
306 | #ifdef CONFIG_DMA_ENGINE | |
c3be1efd | 307 | static void mmci_dma_setup(struct mmci_host *host) |
c8ebae37 RK |
308 | { |
309 | struct mmci_platform_data *plat = host->plat; | |
310 | const char *rxname, *txname; | |
311 | dma_cap_mask_t mask; | |
312 | ||
313 | if (!plat || !plat->dma_filter) { | |
314 | dev_info(mmc_dev(host->mmc), "no DMA platform data\n"); | |
315 | return; | |
316 | } | |
317 | ||
58c7ccbf PF |
318 | /* initialize pre request cookie */ |
319 | host->next_data.cookie = 1; | |
320 | ||
c8ebae37 RK |
321 | /* Try to acquire a generic DMA engine slave channel */ |
322 | dma_cap_zero(mask); | |
323 | dma_cap_set(DMA_SLAVE, mask); | |
324 | ||
325 | /* | |
326 | * If only an RX channel is specified, the driver will | |
327 | * attempt to use it bidirectionally, however if it is | |
328 | * is specified but cannot be located, DMA will be disabled. | |
329 | */ | |
330 | if (plat->dma_rx_param) { | |
331 | host->dma_rx_channel = dma_request_channel(mask, | |
332 | plat->dma_filter, | |
333 | plat->dma_rx_param); | |
334 | /* E.g if no DMA hardware is present */ | |
335 | if (!host->dma_rx_channel) | |
336 | dev_err(mmc_dev(host->mmc), "no RX DMA channel\n"); | |
337 | } | |
338 | ||
339 | if (plat->dma_tx_param) { | |
340 | host->dma_tx_channel = dma_request_channel(mask, | |
341 | plat->dma_filter, | |
342 | plat->dma_tx_param); | |
343 | if (!host->dma_tx_channel) | |
344 | dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n"); | |
345 | } else { | |
346 | host->dma_tx_channel = host->dma_rx_channel; | |
347 | } | |
348 | ||
349 | if (host->dma_rx_channel) | |
350 | rxname = dma_chan_name(host->dma_rx_channel); | |
351 | else | |
352 | rxname = "none"; | |
353 | ||
354 | if (host->dma_tx_channel) | |
355 | txname = dma_chan_name(host->dma_tx_channel); | |
356 | else | |
357 | txname = "none"; | |
358 | ||
359 | dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", | |
360 | rxname, txname); | |
361 | ||
362 | /* | |
363 | * Limit the maximum segment size in any SG entry according to | |
364 | * the parameters of the DMA engine device. | |
365 | */ | |
366 | if (host->dma_tx_channel) { | |
367 | struct device *dev = host->dma_tx_channel->device->dev; | |
368 | unsigned int max_seg_size = dma_get_max_seg_size(dev); | |
369 | ||
370 | if (max_seg_size < host->mmc->max_seg_size) | |
371 | host->mmc->max_seg_size = max_seg_size; | |
372 | } | |
373 | if (host->dma_rx_channel) { | |
374 | struct device *dev = host->dma_rx_channel->device->dev; | |
375 | unsigned int max_seg_size = dma_get_max_seg_size(dev); | |
376 | ||
377 | if (max_seg_size < host->mmc->max_seg_size) | |
378 | host->mmc->max_seg_size = max_seg_size; | |
379 | } | |
380 | } | |
381 | ||
382 | /* | |
6e0ee714 | 383 | * This is used in or so inline it |
c8ebae37 RK |
384 | * so it can be discarded. |
385 | */ | |
386 | static inline void mmci_dma_release(struct mmci_host *host) | |
387 | { | |
388 | struct mmci_platform_data *plat = host->plat; | |
389 | ||
390 | if (host->dma_rx_channel) | |
391 | dma_release_channel(host->dma_rx_channel); | |
392 | if (host->dma_tx_channel && plat->dma_tx_param) | |
393 | dma_release_channel(host->dma_tx_channel); | |
394 | host->dma_rx_channel = host->dma_tx_channel = NULL; | |
395 | } | |
396 | ||
653a761e UH |
397 | static void mmci_dma_data_error(struct mmci_host *host) |
398 | { | |
399 | dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); | |
400 | dmaengine_terminate_all(host->dma_current); | |
401 | host->dma_current = NULL; | |
402 | host->dma_desc_current = NULL; | |
403 | host->data->host_cookie = 0; | |
404 | } | |
405 | ||
c8ebae37 RK |
406 | static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) |
407 | { | |
653a761e | 408 | struct dma_chan *chan; |
c8ebae37 | 409 | enum dma_data_direction dir; |
653a761e UH |
410 | |
411 | if (data->flags & MMC_DATA_READ) { | |
412 | dir = DMA_FROM_DEVICE; | |
413 | chan = host->dma_rx_channel; | |
414 | } else { | |
415 | dir = DMA_TO_DEVICE; | |
416 | chan = host->dma_tx_channel; | |
417 | } | |
418 | ||
419 | dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); | |
420 | } | |
421 | ||
422 | static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) | |
423 | { | |
c8ebae37 RK |
424 | u32 status; |
425 | int i; | |
426 | ||
427 | /* Wait up to 1ms for the DMA to complete */ | |
428 | for (i = 0; ; i++) { | |
429 | status = readl(host->base + MMCISTATUS); | |
430 | if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) | |
431 | break; | |
432 | udelay(10); | |
433 | } | |
434 | ||
435 | /* | |
436 | * Check to see whether we still have some data left in the FIFO - | |
437 | * this catches DMA controllers which are unable to monitor the | |
438 | * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- | |
439 | * contiguous buffers. On TX, we'll get a FIFO underrun error. | |
440 | */ | |
441 | if (status & MCI_RXDATAAVLBLMASK) { | |
653a761e | 442 | mmci_dma_data_error(host); |
c8ebae37 RK |
443 | if (!data->error) |
444 | data->error = -EIO; | |
445 | } | |
446 | ||
58c7ccbf | 447 | if (!data->host_cookie) |
653a761e | 448 | mmci_dma_unmap(host, data); |
c8ebae37 RK |
449 | |
450 | /* | |
451 | * Use of DMA with scatter-gather is impossible. | |
452 | * Give up with DMA and switch back to PIO mode. | |
453 | */ | |
454 | if (status & MCI_RXDATAAVLBLMASK) { | |
455 | dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); | |
456 | mmci_dma_release(host); | |
457 | } | |
c8ebae37 | 458 | |
653a761e UH |
459 | host->dma_current = NULL; |
460 | host->dma_desc_current = NULL; | |
c8ebae37 RK |
461 | } |
462 | ||
653a761e UH |
463 | /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ |
464 | static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, | |
465 | struct dma_chan **dma_chan, | |
466 | struct dma_async_tx_descriptor **dma_desc) | |
c8ebae37 RK |
467 | { |
468 | struct variant_data *variant = host->variant; | |
469 | struct dma_slave_config conf = { | |
470 | .src_addr = host->phybase + MMCIFIFO, | |
471 | .dst_addr = host->phybase + MMCIFIFO, | |
472 | .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
473 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
474 | .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ | |
475 | .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ | |
258aea76 | 476 | .device_fc = false, |
c8ebae37 | 477 | }; |
c8ebae37 RK |
478 | struct dma_chan *chan; |
479 | struct dma_device *device; | |
480 | struct dma_async_tx_descriptor *desc; | |
05f5799c | 481 | enum dma_data_direction buffer_dirn; |
c8ebae37 RK |
482 | int nr_sg; |
483 | ||
c8ebae37 | 484 | if (data->flags & MMC_DATA_READ) { |
05f5799c VK |
485 | conf.direction = DMA_DEV_TO_MEM; |
486 | buffer_dirn = DMA_FROM_DEVICE; | |
c8ebae37 RK |
487 | chan = host->dma_rx_channel; |
488 | } else { | |
05f5799c VK |
489 | conf.direction = DMA_MEM_TO_DEV; |
490 | buffer_dirn = DMA_TO_DEVICE; | |
c8ebae37 RK |
491 | chan = host->dma_tx_channel; |
492 | } | |
493 | ||
494 | /* If there's no DMA channel, fall back to PIO */ | |
495 | if (!chan) | |
496 | return -EINVAL; | |
497 | ||
498 | /* If less than or equal to the fifo size, don't bother with DMA */ | |
58c7ccbf | 499 | if (data->blksz * data->blocks <= variant->fifosize) |
c8ebae37 RK |
500 | return -EINVAL; |
501 | ||
502 | device = chan->device; | |
05f5799c | 503 | nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); |
c8ebae37 RK |
504 | if (nr_sg == 0) |
505 | return -EINVAL; | |
506 | ||
507 | dmaengine_slave_config(chan, &conf); | |
16052827 | 508 | desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, |
c8ebae37 RK |
509 | conf.direction, DMA_CTRL_ACK); |
510 | if (!desc) | |
511 | goto unmap_exit; | |
512 | ||
653a761e UH |
513 | *dma_chan = chan; |
514 | *dma_desc = desc; | |
58c7ccbf PF |
515 | |
516 | return 0; | |
c8ebae37 | 517 | |
58c7ccbf | 518 | unmap_exit: |
05f5799c | 519 | dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); |
58c7ccbf PF |
520 | return -ENOMEM; |
521 | } | |
522 | ||
653a761e UH |
523 | static inline int mmci_dma_prep_data(struct mmci_host *host, |
524 | struct mmc_data *data) | |
525 | { | |
526 | /* Check if next job is already prepared. */ | |
527 | if (host->dma_current && host->dma_desc_current) | |
528 | return 0; | |
529 | ||
530 | /* No job were prepared thus do it now. */ | |
531 | return __mmci_dma_prep_data(host, data, &host->dma_current, | |
532 | &host->dma_desc_current); | |
533 | } | |
534 | ||
535 | static inline int mmci_dma_prep_next(struct mmci_host *host, | |
536 | struct mmc_data *data) | |
537 | { | |
538 | struct mmci_host_next *nd = &host->next_data; | |
539 | return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc); | |
540 | } | |
541 | ||
58c7ccbf PF |
542 | static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) |
543 | { | |
544 | int ret; | |
545 | struct mmc_data *data = host->data; | |
546 | ||
653a761e | 547 | ret = mmci_dma_prep_data(host, host->data); |
58c7ccbf PF |
548 | if (ret) |
549 | return ret; | |
550 | ||
551 | /* Okay, go for it. */ | |
c8ebae37 RK |
552 | dev_vdbg(mmc_dev(host->mmc), |
553 | "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", | |
554 | data->sg_len, data->blksz, data->blocks, data->flags); | |
58c7ccbf PF |
555 | dmaengine_submit(host->dma_desc_current); |
556 | dma_async_issue_pending(host->dma_current); | |
c8ebae37 RK |
557 | |
558 | datactrl |= MCI_DPSM_DMAENABLE; | |
559 | ||
560 | /* Trigger the DMA transfer */ | |
561 | writel(datactrl, host->base + MMCIDATACTRL); | |
562 | ||
563 | /* | |
564 | * Let the MMCI say when the data is ended and it's time | |
565 | * to fire next DMA request. When that happens, MMCI will | |
566 | * call mmci_data_end() | |
567 | */ | |
568 | writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, | |
569 | host->base + MMCIMASK0); | |
570 | return 0; | |
58c7ccbf | 571 | } |
c8ebae37 | 572 | |
58c7ccbf PF |
573 | static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) |
574 | { | |
575 | struct mmci_host_next *next = &host->next_data; | |
576 | ||
653a761e UH |
577 | WARN_ON(data->host_cookie && data->host_cookie != next->cookie); |
578 | WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan)); | |
58c7ccbf PF |
579 | |
580 | host->dma_desc_current = next->dma_desc; | |
581 | host->dma_current = next->dma_chan; | |
58c7ccbf PF |
582 | next->dma_desc = NULL; |
583 | next->dma_chan = NULL; | |
c8ebae37 | 584 | } |
58c7ccbf PF |
585 | |
586 | static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, | |
587 | bool is_first_req) | |
588 | { | |
589 | struct mmci_host *host = mmc_priv(mmc); | |
590 | struct mmc_data *data = mrq->data; | |
591 | struct mmci_host_next *nd = &host->next_data; | |
592 | ||
593 | if (!data) | |
594 | return; | |
595 | ||
653a761e UH |
596 | BUG_ON(data->host_cookie); |
597 | ||
598 | if (mmci_validate_data(host, data)) | |
58c7ccbf | 599 | return; |
58c7ccbf | 600 | |
653a761e UH |
601 | if (!mmci_dma_prep_next(host, data)) |
602 | data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; | |
58c7ccbf PF |
603 | } |
604 | ||
605 | static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, | |
606 | int err) | |
607 | { | |
608 | struct mmci_host *host = mmc_priv(mmc); | |
609 | struct mmc_data *data = mrq->data; | |
58c7ccbf | 610 | |
653a761e | 611 | if (!data || !data->host_cookie) |
58c7ccbf PF |
612 | return; |
613 | ||
653a761e | 614 | mmci_dma_unmap(host, data); |
58c7ccbf | 615 | |
653a761e UH |
616 | if (err) { |
617 | struct mmci_host_next *next = &host->next_data; | |
618 | struct dma_chan *chan; | |
619 | if (data->flags & MMC_DATA_READ) | |
620 | chan = host->dma_rx_channel; | |
621 | else | |
622 | chan = host->dma_tx_channel; | |
623 | dmaengine_terminate_all(chan); | |
58c7ccbf | 624 | |
653a761e UH |
625 | next->dma_desc = NULL; |
626 | next->dma_chan = NULL; | |
58c7ccbf PF |
627 | } |
628 | } | |
629 | ||
c8ebae37 RK |
630 | #else |
631 | /* Blank functions if the DMA engine is not available */ | |
58c7ccbf PF |
632 | static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) |
633 | { | |
634 | } | |
c8ebae37 RK |
635 | static inline void mmci_dma_setup(struct mmci_host *host) |
636 | { | |
637 | } | |
638 | ||
639 | static inline void mmci_dma_release(struct mmci_host *host) | |
640 | { | |
641 | } | |
642 | ||
643 | static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) | |
644 | { | |
645 | } | |
646 | ||
653a761e UH |
647 | static inline void mmci_dma_finalize(struct mmci_host *host, |
648 | struct mmc_data *data) | |
649 | { | |
650 | } | |
651 | ||
c8ebae37 RK |
652 | static inline void mmci_dma_data_error(struct mmci_host *host) |
653 | { | |
654 | } | |
655 | ||
656 | static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) | |
657 | { | |
658 | return -ENOSYS; | |
659 | } | |
58c7ccbf PF |
660 | |
661 | #define mmci_pre_request NULL | |
662 | #define mmci_post_request NULL | |
663 | ||
c8ebae37 RK |
664 | #endif |
665 | ||
1da177e4 LT |
666 | static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) |
667 | { | |
8301bb68 | 668 | struct variant_data *variant = host->variant; |
1da177e4 | 669 | unsigned int datactrl, timeout, irqmask; |
7b09cdac | 670 | unsigned long long clks; |
1da177e4 | 671 | void __iomem *base; |
3bc87f24 | 672 | int blksz_bits; |
1da177e4 | 673 | |
64de0289 LW |
674 | dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", |
675 | data->blksz, data->blocks, data->flags); | |
1da177e4 LT |
676 | |
677 | host->data = data; | |
528320db | 678 | host->size = data->blksz * data->blocks; |
51d4375d | 679 | data->bytes_xfered = 0; |
1da177e4 | 680 | |
7b09cdac RK |
681 | clks = (unsigned long long)data->timeout_ns * host->cclk; |
682 | do_div(clks, 1000000000UL); | |
683 | ||
684 | timeout = data->timeout_clks + (unsigned int)clks; | |
1da177e4 LT |
685 | |
686 | base = host->base; | |
687 | writel(timeout, base + MMCIDATATIMER); | |
688 | writel(host->size, base + MMCIDATALENGTH); | |
689 | ||
3bc87f24 RK |
690 | blksz_bits = ffs(data->blksz) - 1; |
691 | BUG_ON(1 << blksz_bits != data->blksz); | |
692 | ||
1784b157 PL |
693 | if (variant->blksz_datactrl16) |
694 | datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); | |
695 | else | |
696 | datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; | |
c8ebae37 RK |
697 | |
698 | if (data->flags & MMC_DATA_READ) | |
1da177e4 | 699 | datactrl |= MCI_DPSM_DIRECTION; |
c8ebae37 | 700 | |
7258db7e UH |
701 | /* The ST Micro variants has a special bit to enable SDIO */ |
702 | if (variant->sdio && host->mmc->card) | |
06c1a121 UH |
703 | if (mmc_card_sdio(host->mmc->card)) { |
704 | /* | |
705 | * The ST Micro variants has a special bit | |
706 | * to enable SDIO. | |
707 | */ | |
708 | u32 clk; | |
709 | ||
7258db7e UH |
710 | datactrl |= MCI_ST_DPSM_SDIOEN; |
711 | ||
06c1a121 | 712 | /* |
70ac0935 UH |
713 | * The ST Micro variant for SDIO small write transfers |
714 | * needs to have clock H/W flow control disabled, | |
715 | * otherwise the transfer will not start. The threshold | |
716 | * depends on the rate of MCLK. | |
06c1a121 | 717 | */ |
70ac0935 UH |
718 | if (data->flags & MMC_DATA_WRITE && |
719 | (host->size < 8 || | |
720 | (host->size <= 8 && host->mclk > 50000000))) | |
06c1a121 UH |
721 | clk = host->clk_reg & ~variant->clkreg_enable; |
722 | else | |
723 | clk = host->clk_reg | variant->clkreg_enable; | |
724 | ||
725 | mmci_write_clkreg(host, clk); | |
726 | } | |
727 | ||
6dbb6ee0 UH |
728 | if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) |
729 | datactrl |= MCI_ST_DPSM_DDRMODE; | |
730 | ||
c8ebae37 RK |
731 | /* |
732 | * Attempt to use DMA operation mode, if this | |
733 | * should fail, fall back to PIO mode | |
734 | */ | |
735 | if (!mmci_dma_start_data(host, datactrl)) | |
736 | return; | |
737 | ||
738 | /* IRQ mode, map the SG list for CPU reading/writing */ | |
739 | mmci_init_sg(host, data); | |
740 | ||
741 | if (data->flags & MMC_DATA_READ) { | |
1da177e4 | 742 | irqmask = MCI_RXFIFOHALFFULLMASK; |
0425a142 RK |
743 | |
744 | /* | |
c4d877c1 RK |
745 | * If we have less than the fifo 'half-full' threshold to |
746 | * transfer, trigger a PIO interrupt as soon as any data | |
747 | * is available. | |
0425a142 | 748 | */ |
c4d877c1 | 749 | if (host->size < variant->fifohalfsize) |
0425a142 | 750 | irqmask |= MCI_RXDATAAVLBLMASK; |
1da177e4 LT |
751 | } else { |
752 | /* | |
753 | * We don't actually need to include "FIFO empty" here | |
754 | * since its implicit in "FIFO half empty". | |
755 | */ | |
756 | irqmask = MCI_TXFIFOHALFEMPTYMASK; | |
757 | } | |
758 | ||
759 | writel(datactrl, base + MMCIDATACTRL); | |
760 | writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); | |
2686b4b4 | 761 | mmci_set_mask1(host, irqmask); |
1da177e4 LT |
762 | } |
763 | ||
764 | static void | |
765 | mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) | |
766 | { | |
767 | void __iomem *base = host->base; | |
768 | ||
64de0289 | 769 | dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", |
1da177e4 LT |
770 | cmd->opcode, cmd->arg, cmd->flags); |
771 | ||
772 | if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { | |
773 | writel(0, base + MMCICOMMAND); | |
774 | udelay(1); | |
775 | } | |
776 | ||
777 | c |= cmd->opcode | MCI_CPSM_ENABLE; | |
e9225176 RK |
778 | if (cmd->flags & MMC_RSP_PRESENT) { |
779 | if (cmd->flags & MMC_RSP_136) | |
780 | c |= MCI_CPSM_LONGRSP; | |
1da177e4 | 781 | c |= MCI_CPSM_RESPONSE; |
1da177e4 LT |
782 | } |
783 | if (/*interrupt*/0) | |
784 | c |= MCI_CPSM_INTERRUPT; | |
785 | ||
786 | host->cmd = cmd; | |
787 | ||
788 | writel(cmd->arg, base + MMCIARGUMENT); | |
789 | writel(c, base + MMCICOMMAND); | |
790 | } | |
791 | ||
792 | static void | |
793 | mmci_data_irq(struct mmci_host *host, struct mmc_data *data, | |
794 | unsigned int status) | |
795 | { | |
f20f8f21 | 796 | /* First check for errors */ |
b63038d6 UH |
797 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| |
798 | MCI_TXUNDERRUN|MCI_RXOVERRUN)) { | |
8cb28155 | 799 | u32 remain, success; |
f20f8f21 | 800 | |
c8ebae37 | 801 | /* Terminate the DMA transfer */ |
653a761e | 802 | if (dma_inprogress(host)) { |
c8ebae37 | 803 | mmci_dma_data_error(host); |
653a761e UH |
804 | mmci_dma_unmap(host, data); |
805 | } | |
e9c091b4 RK |
806 | |
807 | /* | |
c8afc9d5 RK |
808 | * Calculate how far we are into the transfer. Note that |
809 | * the data counter gives the number of bytes transferred | |
810 | * on the MMC bus, not on the host side. On reads, this | |
811 | * can be as much as a FIFO-worth of data ahead. This | |
812 | * matters for FIFO overruns only. | |
e9c091b4 | 813 | */ |
f5a106d9 | 814 | remain = readl(host->base + MMCIDATACNT); |
8cb28155 LW |
815 | success = data->blksz * data->blocks - remain; |
816 | ||
c8afc9d5 RK |
817 | dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", |
818 | status, success); | |
8cb28155 LW |
819 | if (status & MCI_DATACRCFAIL) { |
820 | /* Last block was not successful */ | |
c8afc9d5 | 821 | success -= 1; |
17b0429d | 822 | data->error = -EILSEQ; |
8cb28155 | 823 | } else if (status & MCI_DATATIMEOUT) { |
17b0429d | 824 | data->error = -ETIMEDOUT; |
757df746 LW |
825 | } else if (status & MCI_STARTBITERR) { |
826 | data->error = -ECOMM; | |
c8afc9d5 RK |
827 | } else if (status & MCI_TXUNDERRUN) { |
828 | data->error = -EIO; | |
829 | } else if (status & MCI_RXOVERRUN) { | |
830 | if (success > host->variant->fifosize) | |
831 | success -= host->variant->fifosize; | |
832 | else | |
833 | success = 0; | |
17b0429d | 834 | data->error = -EIO; |
4ce1d6cb | 835 | } |
51d4375d | 836 | data->bytes_xfered = round_down(success, data->blksz); |
1da177e4 | 837 | } |
f20f8f21 | 838 | |
8cb28155 LW |
839 | if (status & MCI_DATABLOCKEND) |
840 | dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); | |
f20f8f21 | 841 | |
ccff9b51 | 842 | if (status & MCI_DATAEND || data->error) { |
c8ebae37 | 843 | if (dma_inprogress(host)) |
653a761e | 844 | mmci_dma_finalize(host, data); |
1da177e4 LT |
845 | mmci_stop_data(host); |
846 | ||
8cb28155 LW |
847 | if (!data->error) |
848 | /* The error clause is handled above, success! */ | |
51d4375d | 849 | data->bytes_xfered = data->blksz * data->blocks; |
f20f8f21 | 850 | |
024629c6 | 851 | if (!data->stop || host->mrq->sbc) { |
1da177e4 LT |
852 | mmci_request_end(host, data->mrq); |
853 | } else { | |
854 | mmci_start_command(host, data->stop, 0); | |
855 | } | |
856 | } | |
857 | } | |
858 | ||
859 | static void | |
860 | mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, | |
861 | unsigned int status) | |
862 | { | |
863 | void __iomem *base = host->base; | |
024629c6 | 864 | bool sbc = (cmd == host->mrq->sbc); |
1da177e4 LT |
865 | |
866 | host->cmd = NULL; | |
867 | ||
1da177e4 | 868 | if (status & MCI_CMDTIMEOUT) { |
17b0429d | 869 | cmd->error = -ETIMEDOUT; |
1da177e4 | 870 | } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { |
17b0429d | 871 | cmd->error = -EILSEQ; |
9047b435 RKAL |
872 | } else { |
873 | cmd->resp[0] = readl(base + MMCIRESPONSE0); | |
874 | cmd->resp[1] = readl(base + MMCIRESPONSE1); | |
875 | cmd->resp[2] = readl(base + MMCIRESPONSE2); | |
876 | cmd->resp[3] = readl(base + MMCIRESPONSE3); | |
1da177e4 LT |
877 | } |
878 | ||
024629c6 | 879 | if ((!sbc && !cmd->data) || cmd->error) { |
3b6e3c73 UH |
880 | if (host->data) { |
881 | /* Terminate the DMA transfer */ | |
653a761e | 882 | if (dma_inprogress(host)) { |
3b6e3c73 | 883 | mmci_dma_data_error(host); |
653a761e UH |
884 | mmci_dma_unmap(host, host->data); |
885 | } | |
e47c222b | 886 | mmci_stop_data(host); |
3b6e3c73 | 887 | } |
024629c6 UH |
888 | mmci_request_end(host, host->mrq); |
889 | } else if (sbc) { | |
890 | mmci_start_command(host, host->mrq->cmd, 0); | |
1da177e4 LT |
891 | } else if (!(cmd->data->flags & MMC_DATA_READ)) { |
892 | mmci_start_data(host, cmd->data); | |
893 | } | |
894 | } | |
895 | ||
896 | static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) | |
897 | { | |
898 | void __iomem *base = host->base; | |
899 | char *ptr = buffer; | |
900 | u32 status; | |
26eed9a5 | 901 | int host_remain = host->size; |
1da177e4 LT |
902 | |
903 | do { | |
26eed9a5 | 904 | int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); |
1da177e4 LT |
905 | |
906 | if (count > remain) | |
907 | count = remain; | |
908 | ||
909 | if (count <= 0) | |
910 | break; | |
911 | ||
393e5e24 UH |
912 | /* |
913 | * SDIO especially may want to send something that is | |
914 | * not divisible by 4 (as opposed to card sectors | |
915 | * etc). Therefore make sure to always read the last bytes | |
916 | * while only doing full 32-bit reads towards the FIFO. | |
917 | */ | |
918 | if (unlikely(count & 0x3)) { | |
919 | if (count < 4) { | |
920 | unsigned char buf[4]; | |
4b85da08 | 921 | ioread32_rep(base + MMCIFIFO, buf, 1); |
393e5e24 UH |
922 | memcpy(ptr, buf, count); |
923 | } else { | |
4b85da08 | 924 | ioread32_rep(base + MMCIFIFO, ptr, count >> 2); |
393e5e24 UH |
925 | count &= ~0x3; |
926 | } | |
927 | } else { | |
4b85da08 | 928 | ioread32_rep(base + MMCIFIFO, ptr, count >> 2); |
393e5e24 | 929 | } |
1da177e4 LT |
930 | |
931 | ptr += count; | |
932 | remain -= count; | |
26eed9a5 | 933 | host_remain -= count; |
1da177e4 LT |
934 | |
935 | if (remain == 0) | |
936 | break; | |
937 | ||
938 | status = readl(base + MMCISTATUS); | |
939 | } while (status & MCI_RXDATAAVLBL); | |
940 | ||
941 | return ptr - buffer; | |
942 | } | |
943 | ||
944 | static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) | |
945 | { | |
8301bb68 | 946 | struct variant_data *variant = host->variant; |
1da177e4 LT |
947 | void __iomem *base = host->base; |
948 | char *ptr = buffer; | |
949 | ||
950 | do { | |
951 | unsigned int count, maxcnt; | |
952 | ||
8301bb68 RV |
953 | maxcnt = status & MCI_TXFIFOEMPTY ? |
954 | variant->fifosize : variant->fifohalfsize; | |
1da177e4 LT |
955 | count = min(remain, maxcnt); |
956 | ||
34177802 LW |
957 | /* |
958 | * SDIO especially may want to send something that is | |
959 | * not divisible by 4 (as opposed to card sectors | |
960 | * etc), and the FIFO only accept full 32-bit writes. | |
961 | * So compensate by adding +3 on the count, a single | |
962 | * byte become a 32bit write, 7 bytes will be two | |
963 | * 32bit writes etc. | |
964 | */ | |
4b85da08 | 965 | iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); |
1da177e4 LT |
966 | |
967 | ptr += count; | |
968 | remain -= count; | |
969 | ||
970 | if (remain == 0) | |
971 | break; | |
972 | ||
973 | status = readl(base + MMCISTATUS); | |
974 | } while (status & MCI_TXFIFOHALFEMPTY); | |
975 | ||
976 | return ptr - buffer; | |
977 | } | |
978 | ||
979 | /* | |
980 | * PIO data transfer IRQ handler. | |
981 | */ | |
7d12e780 | 982 | static irqreturn_t mmci_pio_irq(int irq, void *dev_id) |
1da177e4 LT |
983 | { |
984 | struct mmci_host *host = dev_id; | |
4ce1d6cb | 985 | struct sg_mapping_iter *sg_miter = &host->sg_miter; |
8301bb68 | 986 | struct variant_data *variant = host->variant; |
1da177e4 | 987 | void __iomem *base = host->base; |
4ce1d6cb | 988 | unsigned long flags; |
1da177e4 LT |
989 | u32 status; |
990 | ||
991 | status = readl(base + MMCISTATUS); | |
992 | ||
64de0289 | 993 | dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); |
1da177e4 | 994 | |
4ce1d6cb RV |
995 | local_irq_save(flags); |
996 | ||
1da177e4 | 997 | do { |
1da177e4 LT |
998 | unsigned int remain, len; |
999 | char *buffer; | |
1000 | ||
1001 | /* | |
1002 | * For write, we only need to test the half-empty flag | |
1003 | * here - if the FIFO is completely empty, then by | |
1004 | * definition it is more than half empty. | |
1005 | * | |
1006 | * For read, check for data available. | |
1007 | */ | |
1008 | if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) | |
1009 | break; | |
1010 | ||
4ce1d6cb RV |
1011 | if (!sg_miter_next(sg_miter)) |
1012 | break; | |
1013 | ||
1014 | buffer = sg_miter->addr; | |
1015 | remain = sg_miter->length; | |
1da177e4 LT |
1016 | |
1017 | len = 0; | |
1018 | if (status & MCI_RXACTIVE) | |
1019 | len = mmci_pio_read(host, buffer, remain); | |
1020 | if (status & MCI_TXACTIVE) | |
1021 | len = mmci_pio_write(host, buffer, remain, status); | |
1022 | ||
4ce1d6cb | 1023 | sg_miter->consumed = len; |
1da177e4 | 1024 | |
1da177e4 LT |
1025 | host->size -= len; |
1026 | remain -= len; | |
1027 | ||
1028 | if (remain) | |
1029 | break; | |
1030 | ||
1da177e4 LT |
1031 | status = readl(base + MMCISTATUS); |
1032 | } while (1); | |
1033 | ||
4ce1d6cb RV |
1034 | sg_miter_stop(sg_miter); |
1035 | ||
1036 | local_irq_restore(flags); | |
1037 | ||
1da177e4 | 1038 | /* |
c4d877c1 RK |
1039 | * If we have less than the fifo 'half-full' threshold to transfer, |
1040 | * trigger a PIO interrupt as soon as any data is available. | |
1da177e4 | 1041 | */ |
c4d877c1 | 1042 | if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) |
2686b4b4 | 1043 | mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); |
1da177e4 LT |
1044 | |
1045 | /* | |
1046 | * If we run out of data, disable the data IRQs; this | |
1047 | * prevents a race where the FIFO becomes empty before | |
1048 | * the chip itself has disabled the data path, and | |
1049 | * stops us racing with our data end IRQ. | |
1050 | */ | |
1051 | if (host->size == 0) { | |
2686b4b4 | 1052 | mmci_set_mask1(host, 0); |
1da177e4 LT |
1053 | writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); |
1054 | } | |
1055 | ||
1056 | return IRQ_HANDLED; | |
1057 | } | |
1058 | ||
1059 | /* | |
1060 | * Handle completion of command and data transfers. | |
1061 | */ | |
7d12e780 | 1062 | static irqreturn_t mmci_irq(int irq, void *dev_id) |
1da177e4 LT |
1063 | { |
1064 | struct mmci_host *host = dev_id; | |
1065 | u32 status; | |
1066 | int ret = 0; | |
1067 | ||
1068 | spin_lock(&host->lock); | |
1069 | ||
1070 | do { | |
1071 | struct mmc_command *cmd; | |
1072 | struct mmc_data *data; | |
1073 | ||
1074 | status = readl(host->base + MMCISTATUS); | |
2686b4b4 LW |
1075 | |
1076 | if (host->singleirq) { | |
1077 | if (status & readl(host->base + MMCIMASK1)) | |
1078 | mmci_pio_irq(irq, dev_id); | |
1079 | ||
1080 | status &= ~MCI_IRQ1MASK; | |
1081 | } | |
1082 | ||
1da177e4 LT |
1083 | status &= readl(host->base + MMCIMASK0); |
1084 | writel(status, host->base + MMCICLEAR); | |
1085 | ||
64de0289 | 1086 | dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); |
1da177e4 LT |
1087 | |
1088 | data = host->data; | |
b63038d6 UH |
1089 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| |
1090 | MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND| | |
1091 | MCI_DATABLOCKEND) && data) | |
1da177e4 LT |
1092 | mmci_data_irq(host, data, status); |
1093 | ||
1094 | cmd = host->cmd; | |
1095 | if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) | |
1096 | mmci_cmd_irq(host, cmd, status); | |
1097 | ||
1098 | ret = 1; | |
1099 | } while (status); | |
1100 | ||
1101 | spin_unlock(&host->lock); | |
1102 | ||
1103 | return IRQ_RETVAL(ret); | |
1104 | } | |
1105 | ||
1106 | static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
1107 | { | |
1108 | struct mmci_host *host = mmc_priv(mmc); | |
9e943021 | 1109 | unsigned long flags; |
1da177e4 LT |
1110 | |
1111 | WARN_ON(host->mrq != NULL); | |
1112 | ||
653a761e UH |
1113 | mrq->cmd->error = mmci_validate_data(host, mrq->data); |
1114 | if (mrq->cmd->error) { | |
255d01af PO |
1115 | mmc_request_done(mmc, mrq); |
1116 | return; | |
1117 | } | |
1118 | ||
1c3be369 RK |
1119 | pm_runtime_get_sync(mmc_dev(mmc)); |
1120 | ||
9e943021 | 1121 | spin_lock_irqsave(&host->lock, flags); |
1da177e4 LT |
1122 | |
1123 | host->mrq = mrq; | |
1124 | ||
58c7ccbf PF |
1125 | if (mrq->data) |
1126 | mmci_get_next_data(host, mrq->data); | |
1127 | ||
1da177e4 LT |
1128 | if (mrq->data && mrq->data->flags & MMC_DATA_READ) |
1129 | mmci_start_data(host, mrq->data); | |
1130 | ||
024629c6 UH |
1131 | if (mrq->sbc) |
1132 | mmci_start_command(host, mrq->sbc, 0); | |
1133 | else | |
1134 | mmci_start_command(host, mrq->cmd, 0); | |
1da177e4 | 1135 | |
9e943021 | 1136 | spin_unlock_irqrestore(&host->lock, flags); |
1da177e4 LT |
1137 | } |
1138 | ||
1139 | static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
1140 | { | |
1141 | struct mmci_host *host = mmc_priv(mmc); | |
7d72a1d4 | 1142 | struct variant_data *variant = host->variant; |
a6a6464a LW |
1143 | u32 pwr = 0; |
1144 | unsigned long flags; | |
db90f91f | 1145 | int ret; |
1da177e4 | 1146 | |
2cd976c4 UH |
1147 | pm_runtime_get_sync(mmc_dev(mmc)); |
1148 | ||
bc521818 UH |
1149 | if (host->plat->ios_handler && |
1150 | host->plat->ios_handler(mmc_dev(mmc), ios)) | |
1151 | dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); | |
1152 | ||
1da177e4 LT |
1153 | switch (ios->power_mode) { |
1154 | case MMC_POWER_OFF: | |
599c1d5c UH |
1155 | if (!IS_ERR(mmc->supply.vmmc)) |
1156 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); | |
237fb5e6 LJ |
1157 | |
1158 | if (!IS_ERR(mmc->supply.vqmmc) && | |
1159 | regulator_is_enabled(mmc->supply.vqmmc)) | |
1160 | regulator_disable(mmc->supply.vqmmc); | |
1161 | ||
1da177e4 LT |
1162 | break; |
1163 | case MMC_POWER_UP: | |
599c1d5c UH |
1164 | if (!IS_ERR(mmc->supply.vmmc)) |
1165 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); | |
1166 | ||
7d72a1d4 UH |
1167 | /* |
1168 | * The ST Micro variant doesn't have the PL180s MCI_PWR_UP | |
1169 | * and instead uses MCI_PWR_ON so apply whatever value is | |
1170 | * configured in the variant data. | |
1171 | */ | |
1172 | pwr |= variant->pwrreg_powerup; | |
1173 | ||
1174 | break; | |
1da177e4 | 1175 | case MMC_POWER_ON: |
237fb5e6 | 1176 | if (!IS_ERR(mmc->supply.vqmmc) && |
db90f91f LJ |
1177 | !regulator_is_enabled(mmc->supply.vqmmc)) { |
1178 | ret = regulator_enable(mmc->supply.vqmmc); | |
1179 | if (ret < 0) | |
1180 | dev_err(mmc_dev(mmc), | |
1181 | "failed to enable vqmmc regulator\n"); | |
1182 | } | |
237fb5e6 | 1183 | |
1da177e4 LT |
1184 | pwr |= MCI_PWR_ON; |
1185 | break; | |
1186 | } | |
1187 | ||
4d1a3a0d UH |
1188 | if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { |
1189 | /* | |
1190 | * The ST Micro variant has some additional bits | |
1191 | * indicating signal direction for the signals in | |
1192 | * the SD/MMC bus and feedback-clock usage. | |
1193 | */ | |
1194 | pwr |= host->plat->sigdir; | |
1195 | ||
1196 | if (ios->bus_width == MMC_BUS_WIDTH_4) | |
1197 | pwr &= ~MCI_ST_DATA74DIREN; | |
1198 | else if (ios->bus_width == MMC_BUS_WIDTH_1) | |
1199 | pwr &= (~MCI_ST_DATA74DIREN & | |
1200 | ~MCI_ST_DATA31DIREN & | |
1201 | ~MCI_ST_DATA2DIREN); | |
1202 | } | |
1203 | ||
cc30d60e | 1204 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { |
f17a1f06 | 1205 | if (host->hw_designer != AMBA_VENDOR_ST) |
cc30d60e LW |
1206 | pwr |= MCI_ROD; |
1207 | else { | |
1208 | /* | |
1209 | * The ST Micro variant use the ROD bit for something | |
1210 | * else and only has OD (Open Drain). | |
1211 | */ | |
1212 | pwr |= MCI_OD; | |
1213 | } | |
1214 | } | |
1da177e4 | 1215 | |
f4670dae UH |
1216 | /* |
1217 | * If clock = 0 and the variant requires the MMCIPOWER to be used for | |
1218 | * gating the clock, the MCI_PWR_ON bit is cleared. | |
1219 | */ | |
1220 | if (!ios->clock && variant->pwrreg_clkgate) | |
1221 | pwr &= ~MCI_PWR_ON; | |
1222 | ||
a6a6464a LW |
1223 | spin_lock_irqsave(&host->lock, flags); |
1224 | ||
1225 | mmci_set_clkreg(host, ios->clock); | |
7437cfa5 | 1226 | mmci_write_pwrreg(host, pwr); |
a6a6464a LW |
1227 | |
1228 | spin_unlock_irqrestore(&host->lock, flags); | |
2cd976c4 | 1229 | |
2cd976c4 UH |
1230 | pm_runtime_mark_last_busy(mmc_dev(mmc)); |
1231 | pm_runtime_put_autosuspend(mmc_dev(mmc)); | |
1da177e4 LT |
1232 | } |
1233 | ||
89001446 RK |
1234 | static int mmci_get_ro(struct mmc_host *mmc) |
1235 | { | |
1236 | struct mmci_host *host = mmc_priv(mmc); | |
1237 | ||
1238 | if (host->gpio_wp == -ENOSYS) | |
1239 | return -ENOSYS; | |
1240 | ||
18a06301 | 1241 | return gpio_get_value_cansleep(host->gpio_wp); |
89001446 RK |
1242 | } |
1243 | ||
1244 | static int mmci_get_cd(struct mmc_host *mmc) | |
1245 | { | |
1246 | struct mmci_host *host = mmc_priv(mmc); | |
29719445 | 1247 | struct mmci_platform_data *plat = host->plat; |
89001446 RK |
1248 | unsigned int status; |
1249 | ||
4b8caec0 RV |
1250 | if (host->gpio_cd == -ENOSYS) { |
1251 | if (!plat->status) | |
1252 | return 1; /* Assume always present */ | |
1253 | ||
29719445 | 1254 | status = plat->status(mmc_dev(host->mmc)); |
4b8caec0 | 1255 | } else |
18a06301 LW |
1256 | status = !!gpio_get_value_cansleep(host->gpio_cd) |
1257 | ^ plat->cd_invert; | |
89001446 | 1258 | |
74bc8093 RK |
1259 | /* |
1260 | * Use positive logic throughout - status is zero for no card, | |
1261 | * non-zero for card inserted. | |
1262 | */ | |
1263 | return status; | |
89001446 RK |
1264 | } |
1265 | ||
148b8b39 RV |
1266 | static irqreturn_t mmci_cd_irq(int irq, void *dev_id) |
1267 | { | |
1268 | struct mmci_host *host = dev_id; | |
1269 | ||
1270 | mmc_detect_change(host->mmc, msecs_to_jiffies(500)); | |
1271 | ||
1272 | return IRQ_HANDLED; | |
1273 | } | |
1274 | ||
ab7aefd0 | 1275 | static const struct mmc_host_ops mmci_ops = { |
1da177e4 | 1276 | .request = mmci_request, |
58c7ccbf PF |
1277 | .pre_req = mmci_pre_request, |
1278 | .post_req = mmci_post_request, | |
1da177e4 | 1279 | .set_ios = mmci_set_ios, |
89001446 RK |
1280 | .get_ro = mmci_get_ro, |
1281 | .get_cd = mmci_get_cd, | |
1da177e4 LT |
1282 | }; |
1283 | ||
000bc9d5 LJ |
1284 | #ifdef CONFIG_OF |
1285 | static void mmci_dt_populate_generic_pdata(struct device_node *np, | |
1286 | struct mmci_platform_data *pdata) | |
1287 | { | |
1288 | int bus_width = 0; | |
1289 | ||
9a597016 | 1290 | pdata->gpio_wp = of_get_named_gpio(np, "wp-gpios", 0); |
9a597016 | 1291 | pdata->gpio_cd = of_get_named_gpio(np, "cd-gpios", 0); |
000bc9d5 LJ |
1292 | |
1293 | if (of_get_property(np, "cd-inverted", NULL)) | |
1294 | pdata->cd_invert = true; | |
1295 | else | |
1296 | pdata->cd_invert = false; | |
1297 | ||
1298 | of_property_read_u32(np, "max-frequency", &pdata->f_max); | |
1299 | if (!pdata->f_max) | |
1300 | pr_warn("%s has no 'max-frequency' property\n", np->full_name); | |
1301 | ||
1302 | if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) | |
1303 | pdata->capabilities |= MMC_CAP_MMC_HIGHSPEED; | |
1304 | if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) | |
1305 | pdata->capabilities |= MMC_CAP_SD_HIGHSPEED; | |
1306 | ||
1307 | of_property_read_u32(np, "bus-width", &bus_width); | |
1308 | switch (bus_width) { | |
1309 | case 0 : | |
1310 | /* No bus-width supplied. */ | |
1311 | break; | |
1312 | case 4 : | |
1313 | pdata->capabilities |= MMC_CAP_4_BIT_DATA; | |
1314 | break; | |
1315 | case 8 : | |
1316 | pdata->capabilities |= MMC_CAP_8_BIT_DATA; | |
1317 | break; | |
1318 | default : | |
1319 | pr_warn("%s: Unsupported bus width\n", np->full_name); | |
1320 | } | |
1321 | } | |
c0a120a4 LJ |
1322 | #else |
1323 | static void mmci_dt_populate_generic_pdata(struct device_node *np, | |
1324 | struct mmci_platform_data *pdata) | |
1325 | { | |
1326 | return; | |
1327 | } | |
000bc9d5 LJ |
1328 | #endif |
1329 | ||
c3be1efd | 1330 | static int mmci_probe(struct amba_device *dev, |
aa25afad | 1331 | const struct amba_id *id) |
1da177e4 | 1332 | { |
6ef297f8 | 1333 | struct mmci_platform_data *plat = dev->dev.platform_data; |
000bc9d5 | 1334 | struct device_node *np = dev->dev.of_node; |
4956e109 | 1335 | struct variant_data *variant = id->data; |
1da177e4 LT |
1336 | struct mmci_host *host; |
1337 | struct mmc_host *mmc; | |
1338 | int ret; | |
1339 | ||
000bc9d5 LJ |
1340 | /* Must have platform data or Device Tree. */ |
1341 | if (!plat && !np) { | |
1342 | dev_err(&dev->dev, "No plat data or DT found\n"); | |
1343 | return -EINVAL; | |
1da177e4 LT |
1344 | } |
1345 | ||
b9b52918 LJ |
1346 | if (!plat) { |
1347 | plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); | |
1348 | if (!plat) | |
1349 | return -ENOMEM; | |
1350 | } | |
1351 | ||
000bc9d5 LJ |
1352 | if (np) |
1353 | mmci_dt_populate_generic_pdata(np, plat); | |
1354 | ||
1da177e4 LT |
1355 | ret = amba_request_regions(dev, DRIVER_NAME); |
1356 | if (ret) | |
1357 | goto out; | |
1358 | ||
1359 | mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); | |
1360 | if (!mmc) { | |
1361 | ret = -ENOMEM; | |
1362 | goto rel_regions; | |
1363 | } | |
1364 | ||
1365 | host = mmc_priv(mmc); | |
4ea580f1 | 1366 | host->mmc = mmc; |
012b7d33 | 1367 | |
89001446 RK |
1368 | host->gpio_wp = -ENOSYS; |
1369 | host->gpio_cd = -ENOSYS; | |
148b8b39 | 1370 | host->gpio_cd_irq = -1; |
89001446 | 1371 | |
012b7d33 RK |
1372 | host->hw_designer = amba_manf(dev); |
1373 | host->hw_revision = amba_rev(dev); | |
64de0289 LW |
1374 | dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); |
1375 | dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); | |
012b7d33 | 1376 | |
665ba56f | 1377 | host->clk = devm_clk_get(&dev->dev, NULL); |
1da177e4 LT |
1378 | if (IS_ERR(host->clk)) { |
1379 | ret = PTR_ERR(host->clk); | |
1da177e4 LT |
1380 | goto host_free; |
1381 | } | |
1382 | ||
ac940938 | 1383 | ret = clk_prepare_enable(host->clk); |
1da177e4 | 1384 | if (ret) |
665ba56f | 1385 | goto host_free; |
1da177e4 LT |
1386 | |
1387 | host->plat = plat; | |
4956e109 | 1388 | host->variant = variant; |
1da177e4 | 1389 | host->mclk = clk_get_rate(host->clk); |
c8df9a53 LW |
1390 | /* |
1391 | * According to the spec, mclk is max 100 MHz, | |
1392 | * so we try to adjust the clock down to this, | |
1393 | * (if possible). | |
1394 | */ | |
1395 | if (host->mclk > 100000000) { | |
1396 | ret = clk_set_rate(host->clk, 100000000); | |
1397 | if (ret < 0) | |
1398 | goto clk_disable; | |
1399 | host->mclk = clk_get_rate(host->clk); | |
64de0289 LW |
1400 | dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", |
1401 | host->mclk); | |
c8df9a53 | 1402 | } |
c8ebae37 | 1403 | host->phybase = dev->res.start; |
dc890c2d | 1404 | host->base = ioremap(dev->res.start, resource_size(&dev->res)); |
1da177e4 LT |
1405 | if (!host->base) { |
1406 | ret = -ENOMEM; | |
1407 | goto clk_disable; | |
1408 | } | |
1409 | ||
1410 | mmc->ops = &mmci_ops; | |
7f294e49 LW |
1411 | /* |
1412 | * The ARM and ST versions of the block have slightly different | |
1413 | * clock divider equations which means that the minimum divider | |
1414 | * differs too. | |
1415 | */ | |
1416 | if (variant->st_clkdiv) | |
1417 | mmc->f_min = DIV_ROUND_UP(host->mclk, 257); | |
1418 | else | |
1419 | mmc->f_min = DIV_ROUND_UP(host->mclk, 512); | |
808d97cc LW |
1420 | /* |
1421 | * If the platform data supplies a maximum operating | |
1422 | * frequency, this takes precedence. Else, we fall back | |
1423 | * to using the module parameter, which has a (low) | |
1424 | * default value in case it is not specified. Either | |
1425 | * value must not exceed the clock rate into the block, | |
1426 | * of course. | |
1427 | */ | |
1428 | if (plat->f_max) | |
1429 | mmc->f_max = min(host->mclk, plat->f_max); | |
1430 | else | |
1431 | mmc->f_max = min(host->mclk, fmax); | |
64de0289 LW |
1432 | dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); |
1433 | ||
a9a83785 LW |
1434 | host->pinctrl = devm_pinctrl_get(&dev->dev); |
1435 | if (IS_ERR(host->pinctrl)) { | |
1436 | ret = PTR_ERR(host->pinctrl); | |
1437 | goto clk_disable; | |
1438 | } | |
1439 | ||
1440 | host->pins_default = pinctrl_lookup_state(host->pinctrl, | |
1441 | PINCTRL_STATE_DEFAULT); | |
1442 | ||
1443 | /* enable pins to be muxed in and configured */ | |
1444 | if (!IS_ERR(host->pins_default)) { | |
1445 | ret = pinctrl_select_state(host->pinctrl, host->pins_default); | |
1446 | if (ret) | |
1447 | dev_warn(&dev->dev, "could not set default pins\n"); | |
1448 | } else | |
1449 | dev_warn(&dev->dev, "could not get default pinstate\n"); | |
1450 | ||
599c1d5c UH |
1451 | /* Get regulators and the supported OCR mask */ |
1452 | mmc_regulator_get_supply(mmc); | |
1453 | if (!mmc->ocr_avail) | |
34e84f39 | 1454 | mmc->ocr_avail = plat->ocr_mask; |
599c1d5c UH |
1455 | else if (plat->ocr_mask) |
1456 | dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); | |
1457 | ||
9e6c82cd | 1458 | mmc->caps = plat->capabilities; |
5a092627 | 1459 | mmc->caps2 = plat->capabilities2; |
1da177e4 | 1460 | |
70be208f UH |
1461 | /* We support these PM capabilities. */ |
1462 | mmc->pm_caps = MMC_PM_KEEP_POWER; | |
1463 | ||
1da177e4 LT |
1464 | /* |
1465 | * We can do SGIO | |
1466 | */ | |
a36274e0 | 1467 | mmc->max_segs = NR_SG; |
1da177e4 LT |
1468 | |
1469 | /* | |
08458ef6 RV |
1470 | * Since only a certain number of bits are valid in the data length |
1471 | * register, we must ensure that we don't exceed 2^num-1 bytes in a | |
1472 | * single request. | |
1da177e4 | 1473 | */ |
08458ef6 | 1474 | mmc->max_req_size = (1 << variant->datalength_bits) - 1; |
1da177e4 LT |
1475 | |
1476 | /* | |
1477 | * Set the maximum segment size. Since we aren't doing DMA | |
1478 | * (yet) we are only limited by the data length register. | |
1479 | */ | |
55db890a | 1480 | mmc->max_seg_size = mmc->max_req_size; |
1da177e4 | 1481 | |
fe4a3c7a PO |
1482 | /* |
1483 | * Block size can be up to 2048 bytes, but must be a power of two. | |
1484 | */ | |
8f7f6b7e | 1485 | mmc->max_blk_size = 1 << 11; |
fe4a3c7a | 1486 | |
55db890a | 1487 | /* |
8f7f6b7e WD |
1488 | * Limit the number of blocks transferred so that we don't overflow |
1489 | * the maximum request size. | |
55db890a | 1490 | */ |
8f7f6b7e | 1491 | mmc->max_blk_count = mmc->max_req_size >> 11; |
55db890a | 1492 | |
1da177e4 LT |
1493 | spin_lock_init(&host->lock); |
1494 | ||
1495 | writel(0, host->base + MMCIMASK0); | |
1496 | writel(0, host->base + MMCIMASK1); | |
1497 | writel(0xfff, host->base + MMCICLEAR); | |
1498 | ||
2805b9ab RS |
1499 | if (plat->gpio_cd == -EPROBE_DEFER) { |
1500 | ret = -EPROBE_DEFER; | |
1501 | goto err_gpio_cd; | |
1502 | } | |
89001446 RK |
1503 | if (gpio_is_valid(plat->gpio_cd)) { |
1504 | ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); | |
1505 | if (ret == 0) | |
1506 | ret = gpio_direction_input(plat->gpio_cd); | |
1507 | if (ret == 0) | |
1508 | host->gpio_cd = plat->gpio_cd; | |
1509 | else if (ret != -ENOSYS) | |
1510 | goto err_gpio_cd; | |
148b8b39 | 1511 | |
17ee083b LW |
1512 | /* |
1513 | * A gpio pin that will detect cards when inserted and removed | |
1514 | * will most likely want to trigger on the edges if it is | |
1515 | * 0 when ejected and 1 when inserted (or mutatis mutandis | |
1516 | * for the inverted case) so we request triggers on both | |
1517 | * edges. | |
1518 | */ | |
148b8b39 | 1519 | ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), |
17ee083b LW |
1520 | mmci_cd_irq, |
1521 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, | |
1522 | DRIVER_NAME " (cd)", host); | |
148b8b39 RV |
1523 | if (ret >= 0) |
1524 | host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); | |
89001446 | 1525 | } |
2805b9ab RS |
1526 | if (plat->gpio_wp == -EPROBE_DEFER) { |
1527 | ret = -EPROBE_DEFER; | |
1528 | goto err_gpio_wp; | |
1529 | } | |
89001446 RK |
1530 | if (gpio_is_valid(plat->gpio_wp)) { |
1531 | ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); | |
1532 | if (ret == 0) | |
1533 | ret = gpio_direction_input(plat->gpio_wp); | |
1534 | if (ret == 0) | |
1535 | host->gpio_wp = plat->gpio_wp; | |
1536 | else if (ret != -ENOSYS) | |
1537 | goto err_gpio_wp; | |
1538 | } | |
1539 | ||
4b8caec0 RV |
1540 | if ((host->plat->status || host->gpio_cd != -ENOSYS) |
1541 | && host->gpio_cd_irq < 0) | |
148b8b39 RV |
1542 | mmc->caps |= MMC_CAP_NEEDS_POLL; |
1543 | ||
dace1453 | 1544 | ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); |
1da177e4 LT |
1545 | if (ret) |
1546 | goto unmap; | |
1547 | ||
dfb85185 | 1548 | if (!dev->irq[1]) |
2686b4b4 LW |
1549 | host->singleirq = true; |
1550 | else { | |
1551 | ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, | |
1552 | DRIVER_NAME " (pio)", host); | |
1553 | if (ret) | |
1554 | goto irq0_free; | |
1555 | } | |
1da177e4 | 1556 | |
8cb28155 | 1557 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); |
1da177e4 LT |
1558 | |
1559 | amba_set_drvdata(dev, mmc); | |
1560 | ||
c8ebae37 RK |
1561 | dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", |
1562 | mmc_hostname(mmc), amba_part(dev), amba_manf(dev), | |
1563 | amba_rev(dev), (unsigned long long)dev->res.start, | |
1564 | dev->irq[0], dev->irq[1]); | |
1565 | ||
1566 | mmci_dma_setup(host); | |
1da177e4 | 1567 | |
2cd976c4 UH |
1568 | pm_runtime_set_autosuspend_delay(&dev->dev, 50); |
1569 | pm_runtime_use_autosuspend(&dev->dev); | |
1c3be369 RK |
1570 | pm_runtime_put(&dev->dev); |
1571 | ||
8c11a94d RK |
1572 | mmc_add_host(mmc); |
1573 | ||
1da177e4 LT |
1574 | return 0; |
1575 | ||
1576 | irq0_free: | |
1577 | free_irq(dev->irq[0], host); | |
1578 | unmap: | |
89001446 RK |
1579 | if (host->gpio_wp != -ENOSYS) |
1580 | gpio_free(host->gpio_wp); | |
1581 | err_gpio_wp: | |
148b8b39 RV |
1582 | if (host->gpio_cd_irq >= 0) |
1583 | free_irq(host->gpio_cd_irq, host); | |
89001446 RK |
1584 | if (host->gpio_cd != -ENOSYS) |
1585 | gpio_free(host->gpio_cd); | |
1586 | err_gpio_cd: | |
1da177e4 LT |
1587 | iounmap(host->base); |
1588 | clk_disable: | |
ac940938 | 1589 | clk_disable_unprepare(host->clk); |
1da177e4 LT |
1590 | host_free: |
1591 | mmc_free_host(mmc); | |
1592 | rel_regions: | |
1593 | amba_release_regions(dev); | |
1594 | out: | |
1595 | return ret; | |
1596 | } | |
1597 | ||
6e0ee714 | 1598 | static int mmci_remove(struct amba_device *dev) |
1da177e4 LT |
1599 | { |
1600 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
1601 | ||
1602 | amba_set_drvdata(dev, NULL); | |
1603 | ||
1604 | if (mmc) { | |
1605 | struct mmci_host *host = mmc_priv(mmc); | |
1606 | ||
1c3be369 RK |
1607 | /* |
1608 | * Undo pm_runtime_put() in probe. We use the _sync | |
1609 | * version here so that we can access the primecell. | |
1610 | */ | |
1611 | pm_runtime_get_sync(&dev->dev); | |
1612 | ||
1da177e4 LT |
1613 | mmc_remove_host(mmc); |
1614 | ||
1615 | writel(0, host->base + MMCIMASK0); | |
1616 | writel(0, host->base + MMCIMASK1); | |
1617 | ||
1618 | writel(0, host->base + MMCICOMMAND); | |
1619 | writel(0, host->base + MMCIDATACTRL); | |
1620 | ||
c8ebae37 | 1621 | mmci_dma_release(host); |
1da177e4 | 1622 | free_irq(dev->irq[0], host); |
2686b4b4 LW |
1623 | if (!host->singleirq) |
1624 | free_irq(dev->irq[1], host); | |
1da177e4 | 1625 | |
89001446 RK |
1626 | if (host->gpio_wp != -ENOSYS) |
1627 | gpio_free(host->gpio_wp); | |
148b8b39 RV |
1628 | if (host->gpio_cd_irq >= 0) |
1629 | free_irq(host->gpio_cd_irq, host); | |
89001446 RK |
1630 | if (host->gpio_cd != -ENOSYS) |
1631 | gpio_free(host->gpio_cd); | |
1632 | ||
1da177e4 | 1633 | iounmap(host->base); |
ac940938 | 1634 | clk_disable_unprepare(host->clk); |
1da177e4 LT |
1635 | |
1636 | mmc_free_host(mmc); | |
1637 | ||
1638 | amba_release_regions(dev); | |
1639 | } | |
1640 | ||
1641 | return 0; | |
1642 | } | |
1643 | ||
48fa7003 UH |
1644 | #ifdef CONFIG_SUSPEND |
1645 | static int mmci_suspend(struct device *dev) | |
1da177e4 | 1646 | { |
48fa7003 UH |
1647 | struct amba_device *adev = to_amba_device(dev); |
1648 | struct mmc_host *mmc = amba_get_drvdata(adev); | |
1da177e4 LT |
1649 | int ret = 0; |
1650 | ||
1651 | if (mmc) { | |
1652 | struct mmci_host *host = mmc_priv(mmc); | |
1653 | ||
1a13f8fa | 1654 | ret = mmc_suspend_host(mmc); |
2cd976c4 UH |
1655 | if (ret == 0) { |
1656 | pm_runtime_get_sync(dev); | |
1da177e4 | 1657 | writel(0, host->base + MMCIMASK0); |
2cd976c4 | 1658 | } |
1da177e4 LT |
1659 | } |
1660 | ||
1661 | return ret; | |
1662 | } | |
1663 | ||
48fa7003 | 1664 | static int mmci_resume(struct device *dev) |
1da177e4 | 1665 | { |
48fa7003 UH |
1666 | struct amba_device *adev = to_amba_device(dev); |
1667 | struct mmc_host *mmc = amba_get_drvdata(adev); | |
1da177e4 LT |
1668 | int ret = 0; |
1669 | ||
1670 | if (mmc) { | |
1671 | struct mmci_host *host = mmc_priv(mmc); | |
1672 | ||
1673 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); | |
2cd976c4 | 1674 | pm_runtime_put(dev); |
1da177e4 LT |
1675 | |
1676 | ret = mmc_resume_host(mmc); | |
1677 | } | |
1678 | ||
1679 | return ret; | |
1680 | } | |
1da177e4 LT |
1681 | #endif |
1682 | ||
8259293a UH |
1683 | #ifdef CONFIG_PM_RUNTIME |
1684 | static int mmci_runtime_suspend(struct device *dev) | |
1685 | { | |
1686 | struct amba_device *adev = to_amba_device(dev); | |
1687 | struct mmc_host *mmc = amba_get_drvdata(adev); | |
1688 | ||
1689 | if (mmc) { | |
1690 | struct mmci_host *host = mmc_priv(mmc); | |
1691 | clk_disable_unprepare(host->clk); | |
1692 | } | |
1693 | ||
1694 | return 0; | |
1695 | } | |
1696 | ||
1697 | static int mmci_runtime_resume(struct device *dev) | |
1698 | { | |
1699 | struct amba_device *adev = to_amba_device(dev); | |
1700 | struct mmc_host *mmc = amba_get_drvdata(adev); | |
1701 | ||
1702 | if (mmc) { | |
1703 | struct mmci_host *host = mmc_priv(mmc); | |
1704 | clk_prepare_enable(host->clk); | |
1705 | } | |
1706 | ||
1707 | return 0; | |
1708 | } | |
1709 | #endif | |
1710 | ||
48fa7003 UH |
1711 | static const struct dev_pm_ops mmci_dev_pm_ops = { |
1712 | SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume) | |
8259293a | 1713 | SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) |
48fa7003 UH |
1714 | }; |
1715 | ||
1da177e4 LT |
1716 | static struct amba_id mmci_ids[] = { |
1717 | { | |
1718 | .id = 0x00041180, | |
768fbc18 | 1719 | .mask = 0xff0fffff, |
4956e109 | 1720 | .data = &variant_arm, |
1da177e4 | 1721 | }, |
768fbc18 PM |
1722 | { |
1723 | .id = 0x01041180, | |
1724 | .mask = 0xff0fffff, | |
1725 | .data = &variant_arm_extended_fifo, | |
1726 | }, | |
3a37298a PM |
1727 | { |
1728 | .id = 0x02041180, | |
1729 | .mask = 0xff0fffff, | |
1730 | .data = &variant_arm_extended_fifo_hwfc, | |
1731 | }, | |
1da177e4 LT |
1732 | { |
1733 | .id = 0x00041181, | |
1734 | .mask = 0x000fffff, | |
4956e109 | 1735 | .data = &variant_arm, |
1da177e4 | 1736 | }, |
cc30d60e LW |
1737 | /* ST Micro variants */ |
1738 | { | |
1739 | .id = 0x00180180, | |
1740 | .mask = 0x00ffffff, | |
4956e109 | 1741 | .data = &variant_u300, |
cc30d60e | 1742 | }, |
34fd4213 LW |
1743 | { |
1744 | .id = 0x10180180, | |
1745 | .mask = 0xf0ffffff, | |
1746 | .data = &variant_nomadik, | |
1747 | }, | |
cc30d60e LW |
1748 | { |
1749 | .id = 0x00280180, | |
1750 | .mask = 0x00ffffff, | |
4956e109 RV |
1751 | .data = &variant_u300, |
1752 | }, | |
1753 | { | |
1754 | .id = 0x00480180, | |
1784b157 | 1755 | .mask = 0xf0ffffff, |
4956e109 | 1756 | .data = &variant_ux500, |
cc30d60e | 1757 | }, |
1784b157 PL |
1758 | { |
1759 | .id = 0x10480180, | |
1760 | .mask = 0xf0ffffff, | |
1761 | .data = &variant_ux500v2, | |
1762 | }, | |
1da177e4 LT |
1763 | { 0, 0 }, |
1764 | }; | |
1765 | ||
9f99835f DM |
1766 | MODULE_DEVICE_TABLE(amba, mmci_ids); |
1767 | ||
1da177e4 LT |
1768 | static struct amba_driver mmci_driver = { |
1769 | .drv = { | |
1770 | .name = DRIVER_NAME, | |
48fa7003 | 1771 | .pm = &mmci_dev_pm_ops, |
1da177e4 LT |
1772 | }, |
1773 | .probe = mmci_probe, | |
0433c143 | 1774 | .remove = mmci_remove, |
1da177e4 LT |
1775 | .id_table = mmci_ids, |
1776 | }; | |
1777 | ||
9e5ed094 | 1778 | module_amba_driver(mmci_driver); |
1da177e4 | 1779 | |
1da177e4 LT |
1780 | module_param(fmax, uint, 0444); |
1781 | ||
1782 | MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); | |
1783 | MODULE_LICENSE("GPL"); |