Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. | |
64de0289 | 5 | * Copyright (C) 2010 ST-Ericsson AB. |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/highmem.h> | |
019a5f56 | 20 | #include <linux/log2.h> |
1da177e4 | 21 | #include <linux/mmc/host.h> |
a62c80e5 | 22 | #include <linux/amba/bus.h> |
f8ce2547 | 23 | #include <linux/clk.h> |
bd6dee6f | 24 | #include <linux/scatterlist.h> |
89001446 | 25 | #include <linux/gpio.h> |
6ef297f8 | 26 | #include <linux/amba/mmci.h> |
34e84f39 | 27 | #include <linux/regulator/consumer.h> |
1da177e4 | 28 | |
7b09cdac | 29 | #include <asm/div64.h> |
1da177e4 | 30 | #include <asm/io.h> |
c6b8fdad | 31 | #include <asm/sizes.h> |
1da177e4 LT |
32 | |
33 | #include "mmci.h" | |
34 | ||
35 | #define DRIVER_NAME "mmci-pl18x" | |
36 | ||
1da177e4 LT |
37 | static unsigned int fmax = 515633; |
38 | ||
4956e109 RV |
39 | /** |
40 | * struct variant_data - MMCI variant-specific quirks | |
41 | * @clkreg: default value for MCICLOCK register | |
4380c14f | 42 | * @clkreg_enable: enable value for MMCICLOCK register |
08458ef6 | 43 | * @datalength_bits: number of bits in the MMCIDATALENGTH register |
4956e109 RV |
44 | */ |
45 | struct variant_data { | |
46 | unsigned int clkreg; | |
4380c14f | 47 | unsigned int clkreg_enable; |
08458ef6 | 48 | unsigned int datalength_bits; |
4956e109 RV |
49 | }; |
50 | ||
51 | static struct variant_data variant_arm = { | |
08458ef6 | 52 | .datalength_bits = 16, |
4956e109 RV |
53 | }; |
54 | ||
55 | static struct variant_data variant_u300 = { | |
4380c14f | 56 | .clkreg_enable = 1 << 13, /* HWFCEN */ |
08458ef6 | 57 | .datalength_bits = 16, |
4956e109 RV |
58 | }; |
59 | ||
60 | static struct variant_data variant_ux500 = { | |
61 | .clkreg = MCI_CLK_ENABLE, | |
4380c14f | 62 | .clkreg_enable = 1 << 14, /* HWFCEN */ |
08458ef6 | 63 | .datalength_bits = 24, |
4956e109 | 64 | }; |
a6a6464a LW |
65 | /* |
66 | * This must be called with host->lock held | |
67 | */ | |
68 | static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) | |
69 | { | |
4956e109 RV |
70 | struct variant_data *variant = host->variant; |
71 | u32 clk = variant->clkreg; | |
a6a6464a LW |
72 | |
73 | if (desired) { | |
74 | if (desired >= host->mclk) { | |
75 | clk = MCI_CLK_BYPASS; | |
76 | host->cclk = host->mclk; | |
77 | } else { | |
78 | clk = host->mclk / (2 * desired) - 1; | |
79 | if (clk >= 256) | |
80 | clk = 255; | |
81 | host->cclk = host->mclk / (2 * (clk + 1)); | |
82 | } | |
4380c14f RV |
83 | |
84 | clk |= variant->clkreg_enable; | |
a6a6464a LW |
85 | clk |= MCI_CLK_ENABLE; |
86 | /* This hasn't proven to be worthwhile */ | |
87 | /* clk |= MCI_CLK_PWRSAVE; */ | |
88 | } | |
89 | ||
9e6c82cd | 90 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) |
771dc157 LW |
91 | clk |= MCI_4BIT_BUS; |
92 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) | |
93 | clk |= MCI_ST_8BIT_BUS; | |
9e6c82cd | 94 | |
a6a6464a LW |
95 | writel(clk, host->base + MMCICLOCK); |
96 | } | |
97 | ||
1da177e4 LT |
98 | static void |
99 | mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) | |
100 | { | |
101 | writel(0, host->base + MMCICOMMAND); | |
102 | ||
e47c222b RK |
103 | BUG_ON(host->data); |
104 | ||
1da177e4 LT |
105 | host->mrq = NULL; |
106 | host->cmd = NULL; | |
107 | ||
108 | if (mrq->data) | |
109 | mrq->data->bytes_xfered = host->data_xfered; | |
110 | ||
111 | /* | |
112 | * Need to drop the host lock here; mmc_request_done may call | |
113 | * back into the driver... | |
114 | */ | |
115 | spin_unlock(&host->lock); | |
116 | mmc_request_done(host->mmc, mrq); | |
117 | spin_lock(&host->lock); | |
118 | } | |
119 | ||
120 | static void mmci_stop_data(struct mmci_host *host) | |
121 | { | |
122 | writel(0, host->base + MMCIDATACTRL); | |
123 | writel(0, host->base + MMCIMASK1); | |
124 | host->data = NULL; | |
125 | } | |
126 | ||
4ce1d6cb RV |
127 | static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) |
128 | { | |
129 | unsigned int flags = SG_MITER_ATOMIC; | |
130 | ||
131 | if (data->flags & MMC_DATA_READ) | |
132 | flags |= SG_MITER_TO_SG; | |
133 | else | |
134 | flags |= SG_MITER_FROM_SG; | |
135 | ||
136 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); | |
137 | } | |
138 | ||
1da177e4 LT |
139 | static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) |
140 | { | |
141 | unsigned int datactrl, timeout, irqmask; | |
7b09cdac | 142 | unsigned long long clks; |
1da177e4 | 143 | void __iomem *base; |
3bc87f24 | 144 | int blksz_bits; |
1da177e4 | 145 | |
64de0289 LW |
146 | dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", |
147 | data->blksz, data->blocks, data->flags); | |
1da177e4 LT |
148 | |
149 | host->data = data; | |
528320db | 150 | host->size = data->blksz * data->blocks; |
1da177e4 LT |
151 | host->data_xfered = 0; |
152 | ||
153 | mmci_init_sg(host, data); | |
154 | ||
7b09cdac RK |
155 | clks = (unsigned long long)data->timeout_ns * host->cclk; |
156 | do_div(clks, 1000000000UL); | |
157 | ||
158 | timeout = data->timeout_clks + (unsigned int)clks; | |
1da177e4 LT |
159 | |
160 | base = host->base; | |
161 | writel(timeout, base + MMCIDATATIMER); | |
162 | writel(host->size, base + MMCIDATALENGTH); | |
163 | ||
3bc87f24 RK |
164 | blksz_bits = ffs(data->blksz) - 1; |
165 | BUG_ON(1 << blksz_bits != data->blksz); | |
166 | ||
167 | datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; | |
1da177e4 LT |
168 | if (data->flags & MMC_DATA_READ) { |
169 | datactrl |= MCI_DPSM_DIRECTION; | |
170 | irqmask = MCI_RXFIFOHALFFULLMASK; | |
0425a142 RK |
171 | |
172 | /* | |
173 | * If we have less than a FIFOSIZE of bytes to transfer, | |
174 | * trigger a PIO interrupt as soon as any data is available. | |
175 | */ | |
176 | if (host->size < MCI_FIFOSIZE) | |
177 | irqmask |= MCI_RXDATAAVLBLMASK; | |
1da177e4 LT |
178 | } else { |
179 | /* | |
180 | * We don't actually need to include "FIFO empty" here | |
181 | * since its implicit in "FIFO half empty". | |
182 | */ | |
183 | irqmask = MCI_TXFIFOHALFEMPTYMASK; | |
184 | } | |
185 | ||
186 | writel(datactrl, base + MMCIDATACTRL); | |
187 | writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); | |
188 | writel(irqmask, base + MMCIMASK1); | |
189 | } | |
190 | ||
191 | static void | |
192 | mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) | |
193 | { | |
194 | void __iomem *base = host->base; | |
195 | ||
64de0289 | 196 | dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", |
1da177e4 LT |
197 | cmd->opcode, cmd->arg, cmd->flags); |
198 | ||
199 | if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { | |
200 | writel(0, base + MMCICOMMAND); | |
201 | udelay(1); | |
202 | } | |
203 | ||
204 | c |= cmd->opcode | MCI_CPSM_ENABLE; | |
e9225176 RK |
205 | if (cmd->flags & MMC_RSP_PRESENT) { |
206 | if (cmd->flags & MMC_RSP_136) | |
207 | c |= MCI_CPSM_LONGRSP; | |
1da177e4 | 208 | c |= MCI_CPSM_RESPONSE; |
1da177e4 LT |
209 | } |
210 | if (/*interrupt*/0) | |
211 | c |= MCI_CPSM_INTERRUPT; | |
212 | ||
213 | host->cmd = cmd; | |
214 | ||
215 | writel(cmd->arg, base + MMCIARGUMENT); | |
216 | writel(c, base + MMCICOMMAND); | |
217 | } | |
218 | ||
219 | static void | |
220 | mmci_data_irq(struct mmci_host *host, struct mmc_data *data, | |
221 | unsigned int status) | |
222 | { | |
223 | if (status & MCI_DATABLOCKEND) { | |
3bc87f24 | 224 | host->data_xfered += data->blksz; |
f28e8a4d LW |
225 | #ifdef CONFIG_ARCH_U300 |
226 | /* | |
227 | * On the U300 some signal or other is | |
228 | * badly routed so that a data write does | |
229 | * not properly terminate with a MCI_DATAEND | |
230 | * status flag. This quirk will make writes | |
231 | * work again. | |
232 | */ | |
233 | if (data->flags & MMC_DATA_WRITE) | |
234 | status |= MCI_DATAEND; | |
235 | #endif | |
1da177e4 LT |
236 | } |
237 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) { | |
64de0289 | 238 | dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ (status %08x)\n", status); |
1da177e4 | 239 | if (status & MCI_DATACRCFAIL) |
17b0429d | 240 | data->error = -EILSEQ; |
1da177e4 | 241 | else if (status & MCI_DATATIMEOUT) |
17b0429d | 242 | data->error = -ETIMEDOUT; |
1da177e4 | 243 | else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN)) |
17b0429d | 244 | data->error = -EIO; |
1da177e4 | 245 | status |= MCI_DATAEND; |
e9c091b4 RK |
246 | |
247 | /* | |
248 | * We hit an error condition. Ensure that any data | |
249 | * partially written to a page is properly coherent. | |
250 | */ | |
4ce1d6cb RV |
251 | if (data->flags & MMC_DATA_READ) { |
252 | struct sg_mapping_iter *sg_miter = &host->sg_miter; | |
253 | unsigned long flags; | |
254 | ||
255 | local_irq_save(flags); | |
256 | if (sg_miter_next(sg_miter)) { | |
257 | flush_dcache_page(sg_miter->page); | |
258 | sg_miter_stop(sg_miter); | |
259 | } | |
260 | local_irq_restore(flags); | |
261 | } | |
1da177e4 LT |
262 | } |
263 | if (status & MCI_DATAEND) { | |
264 | mmci_stop_data(host); | |
265 | ||
266 | if (!data->stop) { | |
267 | mmci_request_end(host, data->mrq); | |
268 | } else { | |
269 | mmci_start_command(host, data->stop, 0); | |
270 | } | |
271 | } | |
272 | } | |
273 | ||
274 | static void | |
275 | mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, | |
276 | unsigned int status) | |
277 | { | |
278 | void __iomem *base = host->base; | |
279 | ||
280 | host->cmd = NULL; | |
281 | ||
282 | cmd->resp[0] = readl(base + MMCIRESPONSE0); | |
283 | cmd->resp[1] = readl(base + MMCIRESPONSE1); | |
284 | cmd->resp[2] = readl(base + MMCIRESPONSE2); | |
285 | cmd->resp[3] = readl(base + MMCIRESPONSE3); | |
286 | ||
287 | if (status & MCI_CMDTIMEOUT) { | |
17b0429d | 288 | cmd->error = -ETIMEDOUT; |
1da177e4 | 289 | } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { |
17b0429d | 290 | cmd->error = -EILSEQ; |
1da177e4 LT |
291 | } |
292 | ||
17b0429d | 293 | if (!cmd->data || cmd->error) { |
e47c222b RK |
294 | if (host->data) |
295 | mmci_stop_data(host); | |
1da177e4 LT |
296 | mmci_request_end(host, cmd->mrq); |
297 | } else if (!(cmd->data->flags & MMC_DATA_READ)) { | |
298 | mmci_start_data(host, cmd->data); | |
299 | } | |
300 | } | |
301 | ||
302 | static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) | |
303 | { | |
304 | void __iomem *base = host->base; | |
305 | char *ptr = buffer; | |
306 | u32 status; | |
26eed9a5 | 307 | int host_remain = host->size; |
1da177e4 LT |
308 | |
309 | do { | |
26eed9a5 | 310 | int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); |
1da177e4 LT |
311 | |
312 | if (count > remain) | |
313 | count = remain; | |
314 | ||
315 | if (count <= 0) | |
316 | break; | |
317 | ||
318 | readsl(base + MMCIFIFO, ptr, count >> 2); | |
319 | ||
320 | ptr += count; | |
321 | remain -= count; | |
26eed9a5 | 322 | host_remain -= count; |
1da177e4 LT |
323 | |
324 | if (remain == 0) | |
325 | break; | |
326 | ||
327 | status = readl(base + MMCISTATUS); | |
328 | } while (status & MCI_RXDATAAVLBL); | |
329 | ||
330 | return ptr - buffer; | |
331 | } | |
332 | ||
333 | static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) | |
334 | { | |
335 | void __iomem *base = host->base; | |
336 | char *ptr = buffer; | |
337 | ||
338 | do { | |
339 | unsigned int count, maxcnt; | |
340 | ||
341 | maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE; | |
342 | count = min(remain, maxcnt); | |
343 | ||
344 | writesl(base + MMCIFIFO, ptr, count >> 2); | |
345 | ||
346 | ptr += count; | |
347 | remain -= count; | |
348 | ||
349 | if (remain == 0) | |
350 | break; | |
351 | ||
352 | status = readl(base + MMCISTATUS); | |
353 | } while (status & MCI_TXFIFOHALFEMPTY); | |
354 | ||
355 | return ptr - buffer; | |
356 | } | |
357 | ||
358 | /* | |
359 | * PIO data transfer IRQ handler. | |
360 | */ | |
7d12e780 | 361 | static irqreturn_t mmci_pio_irq(int irq, void *dev_id) |
1da177e4 LT |
362 | { |
363 | struct mmci_host *host = dev_id; | |
4ce1d6cb | 364 | struct sg_mapping_iter *sg_miter = &host->sg_miter; |
1da177e4 | 365 | void __iomem *base = host->base; |
4ce1d6cb | 366 | unsigned long flags; |
1da177e4 LT |
367 | u32 status; |
368 | ||
369 | status = readl(base + MMCISTATUS); | |
370 | ||
64de0289 | 371 | dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); |
1da177e4 | 372 | |
4ce1d6cb RV |
373 | local_irq_save(flags); |
374 | ||
1da177e4 | 375 | do { |
1da177e4 LT |
376 | unsigned int remain, len; |
377 | char *buffer; | |
378 | ||
379 | /* | |
380 | * For write, we only need to test the half-empty flag | |
381 | * here - if the FIFO is completely empty, then by | |
382 | * definition it is more than half empty. | |
383 | * | |
384 | * For read, check for data available. | |
385 | */ | |
386 | if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) | |
387 | break; | |
388 | ||
4ce1d6cb RV |
389 | if (!sg_miter_next(sg_miter)) |
390 | break; | |
391 | ||
392 | buffer = sg_miter->addr; | |
393 | remain = sg_miter->length; | |
1da177e4 LT |
394 | |
395 | len = 0; | |
396 | if (status & MCI_RXACTIVE) | |
397 | len = mmci_pio_read(host, buffer, remain); | |
398 | if (status & MCI_TXACTIVE) | |
399 | len = mmci_pio_write(host, buffer, remain, status); | |
400 | ||
4ce1d6cb | 401 | sg_miter->consumed = len; |
1da177e4 | 402 | |
1da177e4 LT |
403 | host->size -= len; |
404 | remain -= len; | |
405 | ||
406 | if (remain) | |
407 | break; | |
408 | ||
e9c091b4 | 409 | if (status & MCI_RXACTIVE) |
4ce1d6cb | 410 | flush_dcache_page(sg_miter->page); |
1da177e4 LT |
411 | |
412 | status = readl(base + MMCISTATUS); | |
413 | } while (1); | |
414 | ||
4ce1d6cb RV |
415 | sg_miter_stop(sg_miter); |
416 | ||
417 | local_irq_restore(flags); | |
418 | ||
1da177e4 LT |
419 | /* |
420 | * If we're nearing the end of the read, switch to | |
421 | * "any data available" mode. | |
422 | */ | |
423 | if (status & MCI_RXACTIVE && host->size < MCI_FIFOSIZE) | |
424 | writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1); | |
425 | ||
426 | /* | |
427 | * If we run out of data, disable the data IRQs; this | |
428 | * prevents a race where the FIFO becomes empty before | |
429 | * the chip itself has disabled the data path, and | |
430 | * stops us racing with our data end IRQ. | |
431 | */ | |
432 | if (host->size == 0) { | |
433 | writel(0, base + MMCIMASK1); | |
434 | writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); | |
435 | } | |
436 | ||
437 | return IRQ_HANDLED; | |
438 | } | |
439 | ||
440 | /* | |
441 | * Handle completion of command and data transfers. | |
442 | */ | |
7d12e780 | 443 | static irqreturn_t mmci_irq(int irq, void *dev_id) |
1da177e4 LT |
444 | { |
445 | struct mmci_host *host = dev_id; | |
446 | u32 status; | |
447 | int ret = 0; | |
448 | ||
449 | spin_lock(&host->lock); | |
450 | ||
451 | do { | |
452 | struct mmc_command *cmd; | |
453 | struct mmc_data *data; | |
454 | ||
455 | status = readl(host->base + MMCISTATUS); | |
456 | status &= readl(host->base + MMCIMASK0); | |
457 | writel(status, host->base + MMCICLEAR); | |
458 | ||
64de0289 | 459 | dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); |
1da177e4 LT |
460 | |
461 | data = host->data; | |
462 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN| | |
463 | MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data) | |
464 | mmci_data_irq(host, data, status); | |
465 | ||
466 | cmd = host->cmd; | |
467 | if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) | |
468 | mmci_cmd_irq(host, cmd, status); | |
469 | ||
470 | ret = 1; | |
471 | } while (status); | |
472 | ||
473 | spin_unlock(&host->lock); | |
474 | ||
475 | return IRQ_RETVAL(ret); | |
476 | } | |
477 | ||
478 | static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
479 | { | |
480 | struct mmci_host *host = mmc_priv(mmc); | |
9e943021 | 481 | unsigned long flags; |
1da177e4 LT |
482 | |
483 | WARN_ON(host->mrq != NULL); | |
484 | ||
019a5f56 | 485 | if (mrq->data && !is_power_of_2(mrq->data->blksz)) { |
64de0289 LW |
486 | dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", |
487 | mrq->data->blksz); | |
255d01af PO |
488 | mrq->cmd->error = -EINVAL; |
489 | mmc_request_done(mmc, mrq); | |
490 | return; | |
491 | } | |
492 | ||
9e943021 | 493 | spin_lock_irqsave(&host->lock, flags); |
1da177e4 LT |
494 | |
495 | host->mrq = mrq; | |
496 | ||
497 | if (mrq->data && mrq->data->flags & MMC_DATA_READ) | |
498 | mmci_start_data(host, mrq->data); | |
499 | ||
500 | mmci_start_command(host, mrq->cmd, 0); | |
501 | ||
9e943021 | 502 | spin_unlock_irqrestore(&host->lock, flags); |
1da177e4 LT |
503 | } |
504 | ||
505 | static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
506 | { | |
507 | struct mmci_host *host = mmc_priv(mmc); | |
a6a6464a LW |
508 | u32 pwr = 0; |
509 | unsigned long flags; | |
1da177e4 | 510 | |
1da177e4 LT |
511 | switch (ios->power_mode) { |
512 | case MMC_POWER_OFF: | |
34e84f39 LW |
513 | if(host->vcc && |
514 | regulator_is_enabled(host->vcc)) | |
515 | regulator_disable(host->vcc); | |
1da177e4 LT |
516 | break; |
517 | case MMC_POWER_UP: | |
34e84f39 LW |
518 | #ifdef CONFIG_REGULATOR |
519 | if (host->vcc) | |
520 | /* This implicitly enables the regulator */ | |
521 | mmc_regulator_set_ocr(host->vcc, ios->vdd); | |
522 | #endif | |
bb8f563c RV |
523 | if (host->plat->vdd_handler) |
524 | pwr |= host->plat->vdd_handler(mmc_dev(mmc), ios->vdd, | |
525 | ios->power_mode); | |
cc30d60e | 526 | /* The ST version does not have this, fall through to POWER_ON */ |
f17a1f06 | 527 | if (host->hw_designer != AMBA_VENDOR_ST) { |
cc30d60e LW |
528 | pwr |= MCI_PWR_UP; |
529 | break; | |
530 | } | |
1da177e4 LT |
531 | case MMC_POWER_ON: |
532 | pwr |= MCI_PWR_ON; | |
533 | break; | |
534 | } | |
535 | ||
cc30d60e | 536 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { |
f17a1f06 | 537 | if (host->hw_designer != AMBA_VENDOR_ST) |
cc30d60e LW |
538 | pwr |= MCI_ROD; |
539 | else { | |
540 | /* | |
541 | * The ST Micro variant use the ROD bit for something | |
542 | * else and only has OD (Open Drain). | |
543 | */ | |
544 | pwr |= MCI_OD; | |
545 | } | |
546 | } | |
1da177e4 | 547 | |
a6a6464a LW |
548 | spin_lock_irqsave(&host->lock, flags); |
549 | ||
550 | mmci_set_clkreg(host, ios->clock); | |
1da177e4 LT |
551 | |
552 | if (host->pwr != pwr) { | |
553 | host->pwr = pwr; | |
554 | writel(pwr, host->base + MMCIPOWER); | |
555 | } | |
a6a6464a LW |
556 | |
557 | spin_unlock_irqrestore(&host->lock, flags); | |
1da177e4 LT |
558 | } |
559 | ||
89001446 RK |
560 | static int mmci_get_ro(struct mmc_host *mmc) |
561 | { | |
562 | struct mmci_host *host = mmc_priv(mmc); | |
563 | ||
564 | if (host->gpio_wp == -ENOSYS) | |
565 | return -ENOSYS; | |
566 | ||
567 | return gpio_get_value(host->gpio_wp); | |
568 | } | |
569 | ||
570 | static int mmci_get_cd(struct mmc_host *mmc) | |
571 | { | |
572 | struct mmci_host *host = mmc_priv(mmc); | |
29719445 | 573 | struct mmci_platform_data *plat = host->plat; |
89001446 RK |
574 | unsigned int status; |
575 | ||
576 | if (host->gpio_cd == -ENOSYS) | |
29719445 | 577 | status = plat->status(mmc_dev(host->mmc)); |
89001446 | 578 | else |
29719445 | 579 | status = !!gpio_get_value(host->gpio_cd) ^ plat->cd_invert; |
89001446 | 580 | |
74bc8093 RK |
581 | /* |
582 | * Use positive logic throughout - status is zero for no card, | |
583 | * non-zero for card inserted. | |
584 | */ | |
585 | return status; | |
89001446 RK |
586 | } |
587 | ||
ab7aefd0 | 588 | static const struct mmc_host_ops mmci_ops = { |
1da177e4 LT |
589 | .request = mmci_request, |
590 | .set_ios = mmci_set_ios, | |
89001446 RK |
591 | .get_ro = mmci_get_ro, |
592 | .get_cd = mmci_get_cd, | |
1da177e4 LT |
593 | }; |
594 | ||
03fbdb15 | 595 | static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) |
1da177e4 | 596 | { |
6ef297f8 | 597 | struct mmci_platform_data *plat = dev->dev.platform_data; |
4956e109 | 598 | struct variant_data *variant = id->data; |
1da177e4 LT |
599 | struct mmci_host *host; |
600 | struct mmc_host *mmc; | |
601 | int ret; | |
602 | ||
603 | /* must have platform data */ | |
604 | if (!plat) { | |
605 | ret = -EINVAL; | |
606 | goto out; | |
607 | } | |
608 | ||
609 | ret = amba_request_regions(dev, DRIVER_NAME); | |
610 | if (ret) | |
611 | goto out; | |
612 | ||
613 | mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); | |
614 | if (!mmc) { | |
615 | ret = -ENOMEM; | |
616 | goto rel_regions; | |
617 | } | |
618 | ||
619 | host = mmc_priv(mmc); | |
4ea580f1 | 620 | host->mmc = mmc; |
012b7d33 | 621 | |
89001446 RK |
622 | host->gpio_wp = -ENOSYS; |
623 | host->gpio_cd = -ENOSYS; | |
624 | ||
012b7d33 RK |
625 | host->hw_designer = amba_manf(dev); |
626 | host->hw_revision = amba_rev(dev); | |
64de0289 LW |
627 | dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); |
628 | dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); | |
012b7d33 | 629 | |
ee569c43 | 630 | host->clk = clk_get(&dev->dev, NULL); |
1da177e4 LT |
631 | if (IS_ERR(host->clk)) { |
632 | ret = PTR_ERR(host->clk); | |
633 | host->clk = NULL; | |
634 | goto host_free; | |
635 | } | |
636 | ||
1da177e4 LT |
637 | ret = clk_enable(host->clk); |
638 | if (ret) | |
a8d3584a | 639 | goto clk_free; |
1da177e4 LT |
640 | |
641 | host->plat = plat; | |
4956e109 | 642 | host->variant = variant; |
1da177e4 | 643 | host->mclk = clk_get_rate(host->clk); |
c8df9a53 LW |
644 | /* |
645 | * According to the spec, mclk is max 100 MHz, | |
646 | * so we try to adjust the clock down to this, | |
647 | * (if possible). | |
648 | */ | |
649 | if (host->mclk > 100000000) { | |
650 | ret = clk_set_rate(host->clk, 100000000); | |
651 | if (ret < 0) | |
652 | goto clk_disable; | |
653 | host->mclk = clk_get_rate(host->clk); | |
64de0289 LW |
654 | dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", |
655 | host->mclk); | |
c8df9a53 | 656 | } |
dc890c2d | 657 | host->base = ioremap(dev->res.start, resource_size(&dev->res)); |
1da177e4 LT |
658 | if (!host->base) { |
659 | ret = -ENOMEM; | |
660 | goto clk_disable; | |
661 | } | |
662 | ||
663 | mmc->ops = &mmci_ops; | |
664 | mmc->f_min = (host->mclk + 511) / 512; | |
808d97cc LW |
665 | /* |
666 | * If the platform data supplies a maximum operating | |
667 | * frequency, this takes precedence. Else, we fall back | |
668 | * to using the module parameter, which has a (low) | |
669 | * default value in case it is not specified. Either | |
670 | * value must not exceed the clock rate into the block, | |
671 | * of course. | |
672 | */ | |
673 | if (plat->f_max) | |
674 | mmc->f_max = min(host->mclk, plat->f_max); | |
675 | else | |
676 | mmc->f_max = min(host->mclk, fmax); | |
64de0289 LW |
677 | dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); |
678 | ||
34e84f39 LW |
679 | #ifdef CONFIG_REGULATOR |
680 | /* If we're using the regulator framework, try to fetch a regulator */ | |
681 | host->vcc = regulator_get(&dev->dev, "vmmc"); | |
682 | if (IS_ERR(host->vcc)) | |
683 | host->vcc = NULL; | |
684 | else { | |
685 | int mask = mmc_regulator_get_ocrmask(host->vcc); | |
686 | ||
687 | if (mask < 0) | |
688 | dev_err(&dev->dev, "error getting OCR mask (%d)\n", | |
689 | mask); | |
690 | else { | |
691 | host->mmc->ocr_avail = (u32) mask; | |
692 | if (plat->ocr_mask) | |
693 | dev_warn(&dev->dev, | |
694 | "Provided ocr_mask/setpower will not be used " | |
695 | "(using regulator instead)\n"); | |
696 | } | |
697 | } | |
698 | #endif | |
699 | /* Fall back to platform data if no regulator is found */ | |
700 | if (host->vcc == NULL) | |
701 | mmc->ocr_avail = plat->ocr_mask; | |
9e6c82cd | 702 | mmc->caps = plat->capabilities; |
f5e2574e | 703 | mmc->caps |= MMC_CAP_NEEDS_POLL; |
1da177e4 LT |
704 | |
705 | /* | |
706 | * We can do SGIO | |
707 | */ | |
708 | mmc->max_hw_segs = 16; | |
709 | mmc->max_phys_segs = NR_SG; | |
710 | ||
711 | /* | |
08458ef6 RV |
712 | * Since only a certain number of bits are valid in the data length |
713 | * register, we must ensure that we don't exceed 2^num-1 bytes in a | |
714 | * single request. | |
1da177e4 | 715 | */ |
08458ef6 | 716 | mmc->max_req_size = (1 << variant->datalength_bits) - 1; |
1da177e4 LT |
717 | |
718 | /* | |
719 | * Set the maximum segment size. Since we aren't doing DMA | |
720 | * (yet) we are only limited by the data length register. | |
721 | */ | |
55db890a | 722 | mmc->max_seg_size = mmc->max_req_size; |
1da177e4 | 723 | |
fe4a3c7a PO |
724 | /* |
725 | * Block size can be up to 2048 bytes, but must be a power of two. | |
726 | */ | |
727 | mmc->max_blk_size = 2048; | |
728 | ||
55db890a PO |
729 | /* |
730 | * No limit on the number of blocks transferred. | |
731 | */ | |
732 | mmc->max_blk_count = mmc->max_req_size; | |
733 | ||
1da177e4 LT |
734 | spin_lock_init(&host->lock); |
735 | ||
736 | writel(0, host->base + MMCIMASK0); | |
737 | writel(0, host->base + MMCIMASK1); | |
738 | writel(0xfff, host->base + MMCICLEAR); | |
739 | ||
89001446 RK |
740 | if (gpio_is_valid(plat->gpio_cd)) { |
741 | ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); | |
742 | if (ret == 0) | |
743 | ret = gpio_direction_input(plat->gpio_cd); | |
744 | if (ret == 0) | |
745 | host->gpio_cd = plat->gpio_cd; | |
746 | else if (ret != -ENOSYS) | |
747 | goto err_gpio_cd; | |
748 | } | |
749 | if (gpio_is_valid(plat->gpio_wp)) { | |
750 | ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); | |
751 | if (ret == 0) | |
752 | ret = gpio_direction_input(plat->gpio_wp); | |
753 | if (ret == 0) | |
754 | host->gpio_wp = plat->gpio_wp; | |
755 | else if (ret != -ENOSYS) | |
756 | goto err_gpio_wp; | |
757 | } | |
758 | ||
dace1453 | 759 | ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); |
1da177e4 LT |
760 | if (ret) |
761 | goto unmap; | |
762 | ||
dace1453 | 763 | ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, DRIVER_NAME " (pio)", host); |
1da177e4 LT |
764 | if (ret) |
765 | goto irq0_free; | |
766 | ||
767 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); | |
768 | ||
769 | amba_set_drvdata(dev, mmc); | |
770 | ||
771 | mmc_add_host(mmc); | |
772 | ||
64de0289 | 773 | dev_info(&dev->dev, "%s: MMCI rev %x cfg %02x at 0x%016llx irq %d,%d\n", |
d366b643 | 774 | mmc_hostname(mmc), amba_rev(dev), amba_config(dev), |
e29419ff | 775 | (unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]); |
1da177e4 | 776 | |
1da177e4 LT |
777 | return 0; |
778 | ||
779 | irq0_free: | |
780 | free_irq(dev->irq[0], host); | |
781 | unmap: | |
89001446 RK |
782 | if (host->gpio_wp != -ENOSYS) |
783 | gpio_free(host->gpio_wp); | |
784 | err_gpio_wp: | |
785 | if (host->gpio_cd != -ENOSYS) | |
786 | gpio_free(host->gpio_cd); | |
787 | err_gpio_cd: | |
1da177e4 LT |
788 | iounmap(host->base); |
789 | clk_disable: | |
790 | clk_disable(host->clk); | |
1da177e4 LT |
791 | clk_free: |
792 | clk_put(host->clk); | |
793 | host_free: | |
794 | mmc_free_host(mmc); | |
795 | rel_regions: | |
796 | amba_release_regions(dev); | |
797 | out: | |
798 | return ret; | |
799 | } | |
800 | ||
6dc4a47a | 801 | static int __devexit mmci_remove(struct amba_device *dev) |
1da177e4 LT |
802 | { |
803 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
804 | ||
805 | amba_set_drvdata(dev, NULL); | |
806 | ||
807 | if (mmc) { | |
808 | struct mmci_host *host = mmc_priv(mmc); | |
809 | ||
1da177e4 LT |
810 | mmc_remove_host(mmc); |
811 | ||
812 | writel(0, host->base + MMCIMASK0); | |
813 | writel(0, host->base + MMCIMASK1); | |
814 | ||
815 | writel(0, host->base + MMCICOMMAND); | |
816 | writel(0, host->base + MMCIDATACTRL); | |
817 | ||
818 | free_irq(dev->irq[0], host); | |
819 | free_irq(dev->irq[1], host); | |
820 | ||
89001446 RK |
821 | if (host->gpio_wp != -ENOSYS) |
822 | gpio_free(host->gpio_wp); | |
823 | if (host->gpio_cd != -ENOSYS) | |
824 | gpio_free(host->gpio_cd); | |
825 | ||
1da177e4 LT |
826 | iounmap(host->base); |
827 | clk_disable(host->clk); | |
1da177e4 LT |
828 | clk_put(host->clk); |
829 | ||
34e84f39 LW |
830 | if (regulator_is_enabled(host->vcc)) |
831 | regulator_disable(host->vcc); | |
832 | regulator_put(host->vcc); | |
833 | ||
1da177e4 LT |
834 | mmc_free_host(mmc); |
835 | ||
836 | amba_release_regions(dev); | |
837 | } | |
838 | ||
839 | return 0; | |
840 | } | |
841 | ||
842 | #ifdef CONFIG_PM | |
e5378ca8 | 843 | static int mmci_suspend(struct amba_device *dev, pm_message_t state) |
1da177e4 LT |
844 | { |
845 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
846 | int ret = 0; | |
847 | ||
848 | if (mmc) { | |
849 | struct mmci_host *host = mmc_priv(mmc); | |
850 | ||
1a13f8fa | 851 | ret = mmc_suspend_host(mmc); |
1da177e4 LT |
852 | if (ret == 0) |
853 | writel(0, host->base + MMCIMASK0); | |
854 | } | |
855 | ||
856 | return ret; | |
857 | } | |
858 | ||
859 | static int mmci_resume(struct amba_device *dev) | |
860 | { | |
861 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
862 | int ret = 0; | |
863 | ||
864 | if (mmc) { | |
865 | struct mmci_host *host = mmc_priv(mmc); | |
866 | ||
867 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); | |
868 | ||
869 | ret = mmc_resume_host(mmc); | |
870 | } | |
871 | ||
872 | return ret; | |
873 | } | |
874 | #else | |
875 | #define mmci_suspend NULL | |
876 | #define mmci_resume NULL | |
877 | #endif | |
878 | ||
879 | static struct amba_id mmci_ids[] = { | |
880 | { | |
881 | .id = 0x00041180, | |
882 | .mask = 0x000fffff, | |
4956e109 | 883 | .data = &variant_arm, |
1da177e4 LT |
884 | }, |
885 | { | |
886 | .id = 0x00041181, | |
887 | .mask = 0x000fffff, | |
4956e109 | 888 | .data = &variant_arm, |
1da177e4 | 889 | }, |
cc30d60e LW |
890 | /* ST Micro variants */ |
891 | { | |
892 | .id = 0x00180180, | |
893 | .mask = 0x00ffffff, | |
4956e109 | 894 | .data = &variant_u300, |
cc30d60e LW |
895 | }, |
896 | { | |
897 | .id = 0x00280180, | |
898 | .mask = 0x00ffffff, | |
4956e109 RV |
899 | .data = &variant_u300, |
900 | }, | |
901 | { | |
902 | .id = 0x00480180, | |
903 | .mask = 0x00ffffff, | |
904 | .data = &variant_ux500, | |
cc30d60e | 905 | }, |
1da177e4 LT |
906 | { 0, 0 }, |
907 | }; | |
908 | ||
909 | static struct amba_driver mmci_driver = { | |
910 | .drv = { | |
911 | .name = DRIVER_NAME, | |
912 | }, | |
913 | .probe = mmci_probe, | |
6dc4a47a | 914 | .remove = __devexit_p(mmci_remove), |
1da177e4 LT |
915 | .suspend = mmci_suspend, |
916 | .resume = mmci_resume, | |
917 | .id_table = mmci_ids, | |
918 | }; | |
919 | ||
920 | static int __init mmci_init(void) | |
921 | { | |
922 | return amba_driver_register(&mmci_driver); | |
923 | } | |
924 | ||
925 | static void __exit mmci_exit(void) | |
926 | { | |
927 | amba_driver_unregister(&mmci_driver); | |
928 | } | |
929 | ||
930 | module_init(mmci_init); | |
931 | module_exit(mmci_exit); | |
932 | module_param(fmax, uint, 0444); | |
933 | ||
934 | MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); | |
935 | MODULE_LICENSE("GPL"); |