Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. | |
c8ebae37 | 5 | * Copyright (C) 2010 ST-Ericsson SA |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/interrupt.h> | |
613b152c | 17 | #include <linux/kernel.h> |
1da177e4 LT |
18 | #include <linux/delay.h> |
19 | #include <linux/err.h> | |
20 | #include <linux/highmem.h> | |
019a5f56 | 21 | #include <linux/log2.h> |
1da177e4 | 22 | #include <linux/mmc/host.h> |
34177802 | 23 | #include <linux/mmc/card.h> |
a62c80e5 | 24 | #include <linux/amba/bus.h> |
f8ce2547 | 25 | #include <linux/clk.h> |
bd6dee6f | 26 | #include <linux/scatterlist.h> |
89001446 | 27 | #include <linux/gpio.h> |
34e84f39 | 28 | #include <linux/regulator/consumer.h> |
c8ebae37 RK |
29 | #include <linux/dmaengine.h> |
30 | #include <linux/dma-mapping.h> | |
31 | #include <linux/amba/mmci.h> | |
1c3be369 | 32 | #include <linux/pm_runtime.h> |
1da177e4 | 33 | |
7b09cdac | 34 | #include <asm/div64.h> |
1da177e4 | 35 | #include <asm/io.h> |
c6b8fdad | 36 | #include <asm/sizes.h> |
1da177e4 LT |
37 | |
38 | #include "mmci.h" | |
39 | ||
40 | #define DRIVER_NAME "mmci-pl18x" | |
41 | ||
1da177e4 LT |
42 | static unsigned int fmax = 515633; |
43 | ||
4956e109 RV |
44 | /** |
45 | * struct variant_data - MMCI variant-specific quirks | |
46 | * @clkreg: default value for MCICLOCK register | |
4380c14f | 47 | * @clkreg_enable: enable value for MMCICLOCK register |
08458ef6 | 48 | * @datalength_bits: number of bits in the MMCIDATALENGTH register |
8301bb68 RV |
49 | * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY |
50 | * is asserted (likewise for RX) | |
51 | * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY | |
52 | * is asserted (likewise for RX) | |
34177802 | 53 | * @sdio: variant supports SDIO |
b70a67f9 | 54 | * @st_clkdiv: true if using a ST-specific clock divider algorithm |
1784b157 | 55 | * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register |
7d72a1d4 | 56 | * @pwrreg_powerup: power up value for MMCIPOWER register |
4d1a3a0d | 57 | * @signal_direction: input/out direction of bus signals can be indicated |
4956e109 RV |
58 | */ |
59 | struct variant_data { | |
60 | unsigned int clkreg; | |
4380c14f | 61 | unsigned int clkreg_enable; |
08458ef6 | 62 | unsigned int datalength_bits; |
8301bb68 RV |
63 | unsigned int fifosize; |
64 | unsigned int fifohalfsize; | |
34177802 | 65 | bool sdio; |
b70a67f9 | 66 | bool st_clkdiv; |
1784b157 | 67 | bool blksz_datactrl16; |
7d72a1d4 | 68 | u32 pwrreg_powerup; |
4d1a3a0d | 69 | bool signal_direction; |
4956e109 RV |
70 | }; |
71 | ||
72 | static struct variant_data variant_arm = { | |
8301bb68 RV |
73 | .fifosize = 16 * 4, |
74 | .fifohalfsize = 8 * 4, | |
08458ef6 | 75 | .datalength_bits = 16, |
7d72a1d4 | 76 | .pwrreg_powerup = MCI_PWR_UP, |
4956e109 RV |
77 | }; |
78 | ||
768fbc18 PM |
79 | static struct variant_data variant_arm_extended_fifo = { |
80 | .fifosize = 128 * 4, | |
81 | .fifohalfsize = 64 * 4, | |
82 | .datalength_bits = 16, | |
7d72a1d4 | 83 | .pwrreg_powerup = MCI_PWR_UP, |
768fbc18 PM |
84 | }; |
85 | ||
4956e109 | 86 | static struct variant_data variant_u300 = { |
8301bb68 RV |
87 | .fifosize = 16 * 4, |
88 | .fifohalfsize = 8 * 4, | |
49ac215e | 89 | .clkreg_enable = MCI_ST_U300_HWFCEN, |
08458ef6 | 90 | .datalength_bits = 16, |
34177802 | 91 | .sdio = true, |
7d72a1d4 | 92 | .pwrreg_powerup = MCI_PWR_ON, |
4d1a3a0d | 93 | .signal_direction = true, |
4956e109 RV |
94 | }; |
95 | ||
96 | static struct variant_data variant_ux500 = { | |
8301bb68 RV |
97 | .fifosize = 30 * 4, |
98 | .fifohalfsize = 8 * 4, | |
4956e109 | 99 | .clkreg = MCI_CLK_ENABLE, |
49ac215e | 100 | .clkreg_enable = MCI_ST_UX500_HWFCEN, |
08458ef6 | 101 | .datalength_bits = 24, |
34177802 | 102 | .sdio = true, |
b70a67f9 | 103 | .st_clkdiv = true, |
7d72a1d4 | 104 | .pwrreg_powerup = MCI_PWR_ON, |
4d1a3a0d | 105 | .signal_direction = true, |
4956e109 | 106 | }; |
b70a67f9 | 107 | |
1784b157 PL |
108 | static struct variant_data variant_ux500v2 = { |
109 | .fifosize = 30 * 4, | |
110 | .fifohalfsize = 8 * 4, | |
111 | .clkreg = MCI_CLK_ENABLE, | |
112 | .clkreg_enable = MCI_ST_UX500_HWFCEN, | |
113 | .datalength_bits = 24, | |
114 | .sdio = true, | |
115 | .st_clkdiv = true, | |
116 | .blksz_datactrl16 = true, | |
7d72a1d4 | 117 | .pwrreg_powerup = MCI_PWR_ON, |
4d1a3a0d | 118 | .signal_direction = true, |
1784b157 PL |
119 | }; |
120 | ||
a6a6464a LW |
121 | /* |
122 | * This must be called with host->lock held | |
123 | */ | |
124 | static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) | |
125 | { | |
4956e109 RV |
126 | struct variant_data *variant = host->variant; |
127 | u32 clk = variant->clkreg; | |
a6a6464a LW |
128 | |
129 | if (desired) { | |
130 | if (desired >= host->mclk) { | |
991a86e1 | 131 | clk = MCI_CLK_BYPASS; |
399bc486 LW |
132 | if (variant->st_clkdiv) |
133 | clk |= MCI_ST_UX500_NEG_EDGE; | |
a6a6464a | 134 | host->cclk = host->mclk; |
b70a67f9 LW |
135 | } else if (variant->st_clkdiv) { |
136 | /* | |
137 | * DB8500 TRM says f = mclk / (clkdiv + 2) | |
138 | * => clkdiv = (mclk / f) - 2 | |
139 | * Round the divider up so we don't exceed the max | |
140 | * frequency | |
141 | */ | |
142 | clk = DIV_ROUND_UP(host->mclk, desired) - 2; | |
143 | if (clk >= 256) | |
144 | clk = 255; | |
145 | host->cclk = host->mclk / (clk + 2); | |
a6a6464a | 146 | } else { |
b70a67f9 LW |
147 | /* |
148 | * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) | |
149 | * => clkdiv = mclk / (2 * f) - 1 | |
150 | */ | |
a6a6464a LW |
151 | clk = host->mclk / (2 * desired) - 1; |
152 | if (clk >= 256) | |
153 | clk = 255; | |
154 | host->cclk = host->mclk / (2 * (clk + 1)); | |
155 | } | |
4380c14f RV |
156 | |
157 | clk |= variant->clkreg_enable; | |
a6a6464a LW |
158 | clk |= MCI_CLK_ENABLE; |
159 | /* This hasn't proven to be worthwhile */ | |
160 | /* clk |= MCI_CLK_PWRSAVE; */ | |
161 | } | |
162 | ||
9e6c82cd | 163 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) |
771dc157 LW |
164 | clk |= MCI_4BIT_BUS; |
165 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) | |
166 | clk |= MCI_ST_8BIT_BUS; | |
9e6c82cd | 167 | |
a6a6464a LW |
168 | writel(clk, host->base + MMCICLOCK); |
169 | } | |
170 | ||
1da177e4 LT |
171 | static void |
172 | mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) | |
173 | { | |
174 | writel(0, host->base + MMCICOMMAND); | |
175 | ||
e47c222b RK |
176 | BUG_ON(host->data); |
177 | ||
1da177e4 LT |
178 | host->mrq = NULL; |
179 | host->cmd = NULL; | |
180 | ||
1c3be369 | 181 | pm_runtime_put(mmc_dev(host->mmc)); |
1da177e4 | 182 | mmc_request_done(host->mmc, mrq); |
1da177e4 LT |
183 | } |
184 | ||
2686b4b4 LW |
185 | static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) |
186 | { | |
187 | void __iomem *base = host->base; | |
188 | ||
189 | if (host->singleirq) { | |
190 | unsigned int mask0 = readl(base + MMCIMASK0); | |
191 | ||
192 | mask0 &= ~MCI_IRQ1MASK; | |
193 | mask0 |= mask; | |
194 | ||
195 | writel(mask0, base + MMCIMASK0); | |
196 | } | |
197 | ||
198 | writel(mask, base + MMCIMASK1); | |
199 | } | |
200 | ||
1da177e4 LT |
201 | static void mmci_stop_data(struct mmci_host *host) |
202 | { | |
203 | writel(0, host->base + MMCIDATACTRL); | |
2686b4b4 | 204 | mmci_set_mask1(host, 0); |
1da177e4 LT |
205 | host->data = NULL; |
206 | } | |
207 | ||
4ce1d6cb RV |
208 | static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) |
209 | { | |
210 | unsigned int flags = SG_MITER_ATOMIC; | |
211 | ||
212 | if (data->flags & MMC_DATA_READ) | |
213 | flags |= SG_MITER_TO_SG; | |
214 | else | |
215 | flags |= SG_MITER_FROM_SG; | |
216 | ||
217 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); | |
218 | } | |
219 | ||
c8ebae37 RK |
220 | /* |
221 | * All the DMA operation mode stuff goes inside this ifdef. | |
222 | * This assumes that you have a generic DMA device interface, | |
223 | * no custom DMA interfaces are supported. | |
224 | */ | |
225 | #ifdef CONFIG_DMA_ENGINE | |
226 | static void __devinit mmci_dma_setup(struct mmci_host *host) | |
227 | { | |
228 | struct mmci_platform_data *plat = host->plat; | |
229 | const char *rxname, *txname; | |
230 | dma_cap_mask_t mask; | |
231 | ||
232 | if (!plat || !plat->dma_filter) { | |
233 | dev_info(mmc_dev(host->mmc), "no DMA platform data\n"); | |
234 | return; | |
235 | } | |
236 | ||
58c7ccbf PF |
237 | /* initialize pre request cookie */ |
238 | host->next_data.cookie = 1; | |
239 | ||
c8ebae37 RK |
240 | /* Try to acquire a generic DMA engine slave channel */ |
241 | dma_cap_zero(mask); | |
242 | dma_cap_set(DMA_SLAVE, mask); | |
243 | ||
244 | /* | |
245 | * If only an RX channel is specified, the driver will | |
246 | * attempt to use it bidirectionally, however if it is | |
247 | * is specified but cannot be located, DMA will be disabled. | |
248 | */ | |
249 | if (plat->dma_rx_param) { | |
250 | host->dma_rx_channel = dma_request_channel(mask, | |
251 | plat->dma_filter, | |
252 | plat->dma_rx_param); | |
253 | /* E.g if no DMA hardware is present */ | |
254 | if (!host->dma_rx_channel) | |
255 | dev_err(mmc_dev(host->mmc), "no RX DMA channel\n"); | |
256 | } | |
257 | ||
258 | if (plat->dma_tx_param) { | |
259 | host->dma_tx_channel = dma_request_channel(mask, | |
260 | plat->dma_filter, | |
261 | plat->dma_tx_param); | |
262 | if (!host->dma_tx_channel) | |
263 | dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n"); | |
264 | } else { | |
265 | host->dma_tx_channel = host->dma_rx_channel; | |
266 | } | |
267 | ||
268 | if (host->dma_rx_channel) | |
269 | rxname = dma_chan_name(host->dma_rx_channel); | |
270 | else | |
271 | rxname = "none"; | |
272 | ||
273 | if (host->dma_tx_channel) | |
274 | txname = dma_chan_name(host->dma_tx_channel); | |
275 | else | |
276 | txname = "none"; | |
277 | ||
278 | dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", | |
279 | rxname, txname); | |
280 | ||
281 | /* | |
282 | * Limit the maximum segment size in any SG entry according to | |
283 | * the parameters of the DMA engine device. | |
284 | */ | |
285 | if (host->dma_tx_channel) { | |
286 | struct device *dev = host->dma_tx_channel->device->dev; | |
287 | unsigned int max_seg_size = dma_get_max_seg_size(dev); | |
288 | ||
289 | if (max_seg_size < host->mmc->max_seg_size) | |
290 | host->mmc->max_seg_size = max_seg_size; | |
291 | } | |
292 | if (host->dma_rx_channel) { | |
293 | struct device *dev = host->dma_rx_channel->device->dev; | |
294 | unsigned int max_seg_size = dma_get_max_seg_size(dev); | |
295 | ||
296 | if (max_seg_size < host->mmc->max_seg_size) | |
297 | host->mmc->max_seg_size = max_seg_size; | |
298 | } | |
299 | } | |
300 | ||
301 | /* | |
302 | * This is used in __devinit or __devexit so inline it | |
303 | * so it can be discarded. | |
304 | */ | |
305 | static inline void mmci_dma_release(struct mmci_host *host) | |
306 | { | |
307 | struct mmci_platform_data *plat = host->plat; | |
308 | ||
309 | if (host->dma_rx_channel) | |
310 | dma_release_channel(host->dma_rx_channel); | |
311 | if (host->dma_tx_channel && plat->dma_tx_param) | |
312 | dma_release_channel(host->dma_tx_channel); | |
313 | host->dma_rx_channel = host->dma_tx_channel = NULL; | |
314 | } | |
315 | ||
316 | static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) | |
317 | { | |
318 | struct dma_chan *chan = host->dma_current; | |
319 | enum dma_data_direction dir; | |
320 | u32 status; | |
321 | int i; | |
322 | ||
323 | /* Wait up to 1ms for the DMA to complete */ | |
324 | for (i = 0; ; i++) { | |
325 | status = readl(host->base + MMCISTATUS); | |
326 | if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) | |
327 | break; | |
328 | udelay(10); | |
329 | } | |
330 | ||
331 | /* | |
332 | * Check to see whether we still have some data left in the FIFO - | |
333 | * this catches DMA controllers which are unable to monitor the | |
334 | * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- | |
335 | * contiguous buffers. On TX, we'll get a FIFO underrun error. | |
336 | */ | |
337 | if (status & MCI_RXDATAAVLBLMASK) { | |
338 | dmaengine_terminate_all(chan); | |
339 | if (!data->error) | |
340 | data->error = -EIO; | |
341 | } | |
342 | ||
343 | if (data->flags & MMC_DATA_WRITE) { | |
344 | dir = DMA_TO_DEVICE; | |
345 | } else { | |
346 | dir = DMA_FROM_DEVICE; | |
347 | } | |
348 | ||
58c7ccbf PF |
349 | if (!data->host_cookie) |
350 | dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); | |
c8ebae37 RK |
351 | |
352 | /* | |
353 | * Use of DMA with scatter-gather is impossible. | |
354 | * Give up with DMA and switch back to PIO mode. | |
355 | */ | |
356 | if (status & MCI_RXDATAAVLBLMASK) { | |
357 | dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); | |
358 | mmci_dma_release(host); | |
359 | } | |
360 | } | |
361 | ||
362 | static void mmci_dma_data_error(struct mmci_host *host) | |
363 | { | |
364 | dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); | |
365 | dmaengine_terminate_all(host->dma_current); | |
366 | } | |
367 | ||
58c7ccbf PF |
368 | static int mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, |
369 | struct mmci_host_next *next) | |
c8ebae37 RK |
370 | { |
371 | struct variant_data *variant = host->variant; | |
372 | struct dma_slave_config conf = { | |
373 | .src_addr = host->phybase + MMCIFIFO, | |
374 | .dst_addr = host->phybase + MMCIFIFO, | |
375 | .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
376 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
377 | .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ | |
378 | .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ | |
379 | }; | |
c8ebae37 RK |
380 | struct dma_chan *chan; |
381 | struct dma_device *device; | |
382 | struct dma_async_tx_descriptor *desc; | |
05f5799c | 383 | enum dma_data_direction buffer_dirn; |
c8ebae37 RK |
384 | int nr_sg; |
385 | ||
58c7ccbf PF |
386 | /* Check if next job is already prepared */ |
387 | if (data->host_cookie && !next && | |
388 | host->dma_current && host->dma_desc_current) | |
389 | return 0; | |
390 | ||
391 | if (!next) { | |
392 | host->dma_current = NULL; | |
393 | host->dma_desc_current = NULL; | |
394 | } | |
c8ebae37 RK |
395 | |
396 | if (data->flags & MMC_DATA_READ) { | |
05f5799c VK |
397 | conf.direction = DMA_DEV_TO_MEM; |
398 | buffer_dirn = DMA_FROM_DEVICE; | |
c8ebae37 RK |
399 | chan = host->dma_rx_channel; |
400 | } else { | |
05f5799c VK |
401 | conf.direction = DMA_MEM_TO_DEV; |
402 | buffer_dirn = DMA_TO_DEVICE; | |
c8ebae37 RK |
403 | chan = host->dma_tx_channel; |
404 | } | |
405 | ||
406 | /* If there's no DMA channel, fall back to PIO */ | |
407 | if (!chan) | |
408 | return -EINVAL; | |
409 | ||
410 | /* If less than or equal to the fifo size, don't bother with DMA */ | |
58c7ccbf | 411 | if (data->blksz * data->blocks <= variant->fifosize) |
c8ebae37 RK |
412 | return -EINVAL; |
413 | ||
414 | device = chan->device; | |
05f5799c | 415 | nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); |
c8ebae37 RK |
416 | if (nr_sg == 0) |
417 | return -EINVAL; | |
418 | ||
419 | dmaengine_slave_config(chan, &conf); | |
420 | desc = device->device_prep_slave_sg(chan, data->sg, nr_sg, | |
421 | conf.direction, DMA_CTRL_ACK); | |
422 | if (!desc) | |
423 | goto unmap_exit; | |
424 | ||
58c7ccbf PF |
425 | if (next) { |
426 | next->dma_chan = chan; | |
427 | next->dma_desc = desc; | |
428 | } else { | |
429 | host->dma_current = chan; | |
430 | host->dma_desc_current = desc; | |
431 | } | |
432 | ||
433 | return 0; | |
c8ebae37 | 434 | |
58c7ccbf PF |
435 | unmap_exit: |
436 | if (!next) | |
437 | dmaengine_terminate_all(chan); | |
05f5799c | 438 | dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); |
58c7ccbf PF |
439 | return -ENOMEM; |
440 | } | |
441 | ||
442 | static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) | |
443 | { | |
444 | int ret; | |
445 | struct mmc_data *data = host->data; | |
446 | ||
447 | ret = mmci_dma_prep_data(host, host->data, NULL); | |
448 | if (ret) | |
449 | return ret; | |
450 | ||
451 | /* Okay, go for it. */ | |
c8ebae37 RK |
452 | dev_vdbg(mmc_dev(host->mmc), |
453 | "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", | |
454 | data->sg_len, data->blksz, data->blocks, data->flags); | |
58c7ccbf PF |
455 | dmaengine_submit(host->dma_desc_current); |
456 | dma_async_issue_pending(host->dma_current); | |
c8ebae37 RK |
457 | |
458 | datactrl |= MCI_DPSM_DMAENABLE; | |
459 | ||
460 | /* Trigger the DMA transfer */ | |
461 | writel(datactrl, host->base + MMCIDATACTRL); | |
462 | ||
463 | /* | |
464 | * Let the MMCI say when the data is ended and it's time | |
465 | * to fire next DMA request. When that happens, MMCI will | |
466 | * call mmci_data_end() | |
467 | */ | |
468 | writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, | |
469 | host->base + MMCIMASK0); | |
470 | return 0; | |
58c7ccbf | 471 | } |
c8ebae37 | 472 | |
58c7ccbf PF |
473 | static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) |
474 | { | |
475 | struct mmci_host_next *next = &host->next_data; | |
476 | ||
477 | if (data->host_cookie && data->host_cookie != next->cookie) { | |
a3c76eb9 | 478 | pr_warning("[%s] invalid cookie: data->host_cookie %d" |
58c7ccbf PF |
479 | " host->next_data.cookie %d\n", |
480 | __func__, data->host_cookie, host->next_data.cookie); | |
481 | data->host_cookie = 0; | |
482 | } | |
483 | ||
484 | if (!data->host_cookie) | |
485 | return; | |
486 | ||
487 | host->dma_desc_current = next->dma_desc; | |
488 | host->dma_current = next->dma_chan; | |
489 | ||
490 | next->dma_desc = NULL; | |
491 | next->dma_chan = NULL; | |
c8ebae37 | 492 | } |
58c7ccbf PF |
493 | |
494 | static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, | |
495 | bool is_first_req) | |
496 | { | |
497 | struct mmci_host *host = mmc_priv(mmc); | |
498 | struct mmc_data *data = mrq->data; | |
499 | struct mmci_host_next *nd = &host->next_data; | |
500 | ||
501 | if (!data) | |
502 | return; | |
503 | ||
504 | if (data->host_cookie) { | |
505 | data->host_cookie = 0; | |
506 | return; | |
507 | } | |
508 | ||
509 | /* if config for dma */ | |
510 | if (((data->flags & MMC_DATA_WRITE) && host->dma_tx_channel) || | |
511 | ((data->flags & MMC_DATA_READ) && host->dma_rx_channel)) { | |
512 | if (mmci_dma_prep_data(host, data, nd)) | |
513 | data->host_cookie = 0; | |
514 | else | |
515 | data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; | |
516 | } | |
517 | } | |
518 | ||
519 | static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, | |
520 | int err) | |
521 | { | |
522 | struct mmci_host *host = mmc_priv(mmc); | |
523 | struct mmc_data *data = mrq->data; | |
524 | struct dma_chan *chan; | |
525 | enum dma_data_direction dir; | |
526 | ||
527 | if (!data) | |
528 | return; | |
529 | ||
530 | if (data->flags & MMC_DATA_READ) { | |
531 | dir = DMA_FROM_DEVICE; | |
532 | chan = host->dma_rx_channel; | |
533 | } else { | |
534 | dir = DMA_TO_DEVICE; | |
535 | chan = host->dma_tx_channel; | |
536 | } | |
537 | ||
538 | ||
539 | /* if config for dma */ | |
540 | if (chan) { | |
541 | if (err) | |
542 | dmaengine_terminate_all(chan); | |
8e3336b1 | 543 | if (data->host_cookie) |
58c7ccbf PF |
544 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, |
545 | data->sg_len, dir); | |
546 | mrq->data->host_cookie = 0; | |
547 | } | |
548 | } | |
549 | ||
c8ebae37 RK |
550 | #else |
551 | /* Blank functions if the DMA engine is not available */ | |
58c7ccbf PF |
552 | static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) |
553 | { | |
554 | } | |
c8ebae37 RK |
555 | static inline void mmci_dma_setup(struct mmci_host *host) |
556 | { | |
557 | } | |
558 | ||
559 | static inline void mmci_dma_release(struct mmci_host *host) | |
560 | { | |
561 | } | |
562 | ||
563 | static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) | |
564 | { | |
565 | } | |
566 | ||
567 | static inline void mmci_dma_data_error(struct mmci_host *host) | |
568 | { | |
569 | } | |
570 | ||
571 | static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) | |
572 | { | |
573 | return -ENOSYS; | |
574 | } | |
58c7ccbf PF |
575 | |
576 | #define mmci_pre_request NULL | |
577 | #define mmci_post_request NULL | |
578 | ||
c8ebae37 RK |
579 | #endif |
580 | ||
1da177e4 LT |
581 | static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) |
582 | { | |
8301bb68 | 583 | struct variant_data *variant = host->variant; |
1da177e4 | 584 | unsigned int datactrl, timeout, irqmask; |
7b09cdac | 585 | unsigned long long clks; |
1da177e4 | 586 | void __iomem *base; |
3bc87f24 | 587 | int blksz_bits; |
1da177e4 | 588 | |
64de0289 LW |
589 | dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", |
590 | data->blksz, data->blocks, data->flags); | |
1da177e4 LT |
591 | |
592 | host->data = data; | |
528320db | 593 | host->size = data->blksz * data->blocks; |
51d4375d | 594 | data->bytes_xfered = 0; |
1da177e4 | 595 | |
7b09cdac RK |
596 | clks = (unsigned long long)data->timeout_ns * host->cclk; |
597 | do_div(clks, 1000000000UL); | |
598 | ||
599 | timeout = data->timeout_clks + (unsigned int)clks; | |
1da177e4 LT |
600 | |
601 | base = host->base; | |
602 | writel(timeout, base + MMCIDATATIMER); | |
603 | writel(host->size, base + MMCIDATALENGTH); | |
604 | ||
3bc87f24 RK |
605 | blksz_bits = ffs(data->blksz) - 1; |
606 | BUG_ON(1 << blksz_bits != data->blksz); | |
607 | ||
1784b157 PL |
608 | if (variant->blksz_datactrl16) |
609 | datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); | |
610 | else | |
611 | datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; | |
c8ebae37 RK |
612 | |
613 | if (data->flags & MMC_DATA_READ) | |
1da177e4 | 614 | datactrl |= MCI_DPSM_DIRECTION; |
c8ebae37 RK |
615 | |
616 | /* | |
617 | * Attempt to use DMA operation mode, if this | |
618 | * should fail, fall back to PIO mode | |
619 | */ | |
620 | if (!mmci_dma_start_data(host, datactrl)) | |
621 | return; | |
622 | ||
623 | /* IRQ mode, map the SG list for CPU reading/writing */ | |
624 | mmci_init_sg(host, data); | |
625 | ||
626 | if (data->flags & MMC_DATA_READ) { | |
1da177e4 | 627 | irqmask = MCI_RXFIFOHALFFULLMASK; |
0425a142 RK |
628 | |
629 | /* | |
c4d877c1 RK |
630 | * If we have less than the fifo 'half-full' threshold to |
631 | * transfer, trigger a PIO interrupt as soon as any data | |
632 | * is available. | |
0425a142 | 633 | */ |
c4d877c1 | 634 | if (host->size < variant->fifohalfsize) |
0425a142 | 635 | irqmask |= MCI_RXDATAAVLBLMASK; |
1da177e4 LT |
636 | } else { |
637 | /* | |
638 | * We don't actually need to include "FIFO empty" here | |
639 | * since its implicit in "FIFO half empty". | |
640 | */ | |
641 | irqmask = MCI_TXFIFOHALFEMPTYMASK; | |
642 | } | |
643 | ||
34177802 LW |
644 | /* The ST Micro variants has a special bit to enable SDIO */ |
645 | if (variant->sdio && host->mmc->card) | |
646 | if (mmc_card_sdio(host->mmc->card)) | |
647 | datactrl |= MCI_ST_DPSM_SDIOEN; | |
648 | ||
1da177e4 LT |
649 | writel(datactrl, base + MMCIDATACTRL); |
650 | writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); | |
2686b4b4 | 651 | mmci_set_mask1(host, irqmask); |
1da177e4 LT |
652 | } |
653 | ||
654 | static void | |
655 | mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) | |
656 | { | |
657 | void __iomem *base = host->base; | |
658 | ||
64de0289 | 659 | dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", |
1da177e4 LT |
660 | cmd->opcode, cmd->arg, cmd->flags); |
661 | ||
662 | if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { | |
663 | writel(0, base + MMCICOMMAND); | |
664 | udelay(1); | |
665 | } | |
666 | ||
667 | c |= cmd->opcode | MCI_CPSM_ENABLE; | |
e9225176 RK |
668 | if (cmd->flags & MMC_RSP_PRESENT) { |
669 | if (cmd->flags & MMC_RSP_136) | |
670 | c |= MCI_CPSM_LONGRSP; | |
1da177e4 | 671 | c |= MCI_CPSM_RESPONSE; |
1da177e4 LT |
672 | } |
673 | if (/*interrupt*/0) | |
674 | c |= MCI_CPSM_INTERRUPT; | |
675 | ||
676 | host->cmd = cmd; | |
677 | ||
678 | writel(cmd->arg, base + MMCIARGUMENT); | |
679 | writel(c, base + MMCICOMMAND); | |
680 | } | |
681 | ||
682 | static void | |
683 | mmci_data_irq(struct mmci_host *host, struct mmc_data *data, | |
684 | unsigned int status) | |
685 | { | |
f20f8f21 | 686 | /* First check for errors */ |
b63038d6 UH |
687 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| |
688 | MCI_TXUNDERRUN|MCI_RXOVERRUN)) { | |
8cb28155 | 689 | u32 remain, success; |
f20f8f21 | 690 | |
c8ebae37 RK |
691 | /* Terminate the DMA transfer */ |
692 | if (dma_inprogress(host)) | |
693 | mmci_dma_data_error(host); | |
e9c091b4 RK |
694 | |
695 | /* | |
c8afc9d5 RK |
696 | * Calculate how far we are into the transfer. Note that |
697 | * the data counter gives the number of bytes transferred | |
698 | * on the MMC bus, not on the host side. On reads, this | |
699 | * can be as much as a FIFO-worth of data ahead. This | |
700 | * matters for FIFO overruns only. | |
e9c091b4 | 701 | */ |
f5a106d9 | 702 | remain = readl(host->base + MMCIDATACNT); |
8cb28155 LW |
703 | success = data->blksz * data->blocks - remain; |
704 | ||
c8afc9d5 RK |
705 | dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", |
706 | status, success); | |
8cb28155 LW |
707 | if (status & MCI_DATACRCFAIL) { |
708 | /* Last block was not successful */ | |
c8afc9d5 | 709 | success -= 1; |
17b0429d | 710 | data->error = -EILSEQ; |
8cb28155 | 711 | } else if (status & MCI_DATATIMEOUT) { |
17b0429d | 712 | data->error = -ETIMEDOUT; |
757df746 LW |
713 | } else if (status & MCI_STARTBITERR) { |
714 | data->error = -ECOMM; | |
c8afc9d5 RK |
715 | } else if (status & MCI_TXUNDERRUN) { |
716 | data->error = -EIO; | |
717 | } else if (status & MCI_RXOVERRUN) { | |
718 | if (success > host->variant->fifosize) | |
719 | success -= host->variant->fifosize; | |
720 | else | |
721 | success = 0; | |
17b0429d | 722 | data->error = -EIO; |
4ce1d6cb | 723 | } |
51d4375d | 724 | data->bytes_xfered = round_down(success, data->blksz); |
1da177e4 | 725 | } |
f20f8f21 | 726 | |
8cb28155 LW |
727 | if (status & MCI_DATABLOCKEND) |
728 | dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); | |
f20f8f21 | 729 | |
ccff9b51 | 730 | if (status & MCI_DATAEND || data->error) { |
c8ebae37 RK |
731 | if (dma_inprogress(host)) |
732 | mmci_dma_unmap(host, data); | |
1da177e4 LT |
733 | mmci_stop_data(host); |
734 | ||
8cb28155 LW |
735 | if (!data->error) |
736 | /* The error clause is handled above, success! */ | |
51d4375d | 737 | data->bytes_xfered = data->blksz * data->blocks; |
f20f8f21 | 738 | |
1da177e4 LT |
739 | if (!data->stop) { |
740 | mmci_request_end(host, data->mrq); | |
741 | } else { | |
742 | mmci_start_command(host, data->stop, 0); | |
743 | } | |
744 | } | |
745 | } | |
746 | ||
747 | static void | |
748 | mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, | |
749 | unsigned int status) | |
750 | { | |
751 | void __iomem *base = host->base; | |
752 | ||
753 | host->cmd = NULL; | |
754 | ||
1da177e4 | 755 | if (status & MCI_CMDTIMEOUT) { |
17b0429d | 756 | cmd->error = -ETIMEDOUT; |
1da177e4 | 757 | } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { |
17b0429d | 758 | cmd->error = -EILSEQ; |
9047b435 RKAL |
759 | } else { |
760 | cmd->resp[0] = readl(base + MMCIRESPONSE0); | |
761 | cmd->resp[1] = readl(base + MMCIRESPONSE1); | |
762 | cmd->resp[2] = readl(base + MMCIRESPONSE2); | |
763 | cmd->resp[3] = readl(base + MMCIRESPONSE3); | |
1da177e4 LT |
764 | } |
765 | ||
17b0429d | 766 | if (!cmd->data || cmd->error) { |
3b6e3c73 UH |
767 | if (host->data) { |
768 | /* Terminate the DMA transfer */ | |
769 | if (dma_inprogress(host)) | |
770 | mmci_dma_data_error(host); | |
e47c222b | 771 | mmci_stop_data(host); |
3b6e3c73 | 772 | } |
1da177e4 LT |
773 | mmci_request_end(host, cmd->mrq); |
774 | } else if (!(cmd->data->flags & MMC_DATA_READ)) { | |
775 | mmci_start_data(host, cmd->data); | |
776 | } | |
777 | } | |
778 | ||
779 | static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) | |
780 | { | |
781 | void __iomem *base = host->base; | |
782 | char *ptr = buffer; | |
783 | u32 status; | |
26eed9a5 | 784 | int host_remain = host->size; |
1da177e4 LT |
785 | |
786 | do { | |
26eed9a5 | 787 | int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); |
1da177e4 LT |
788 | |
789 | if (count > remain) | |
790 | count = remain; | |
791 | ||
792 | if (count <= 0) | |
793 | break; | |
794 | ||
795 | readsl(base + MMCIFIFO, ptr, count >> 2); | |
796 | ||
797 | ptr += count; | |
798 | remain -= count; | |
26eed9a5 | 799 | host_remain -= count; |
1da177e4 LT |
800 | |
801 | if (remain == 0) | |
802 | break; | |
803 | ||
804 | status = readl(base + MMCISTATUS); | |
805 | } while (status & MCI_RXDATAAVLBL); | |
806 | ||
807 | return ptr - buffer; | |
808 | } | |
809 | ||
810 | static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) | |
811 | { | |
8301bb68 | 812 | struct variant_data *variant = host->variant; |
1da177e4 LT |
813 | void __iomem *base = host->base; |
814 | char *ptr = buffer; | |
815 | ||
816 | do { | |
817 | unsigned int count, maxcnt; | |
818 | ||
8301bb68 RV |
819 | maxcnt = status & MCI_TXFIFOEMPTY ? |
820 | variant->fifosize : variant->fifohalfsize; | |
1da177e4 LT |
821 | count = min(remain, maxcnt); |
822 | ||
34177802 LW |
823 | /* |
824 | * The ST Micro variant for SDIO transfer sizes | |
825 | * less then 8 bytes should have clock H/W flow | |
826 | * control disabled. | |
827 | */ | |
828 | if (variant->sdio && | |
829 | mmc_card_sdio(host->mmc->card)) { | |
830 | if (count < 8) | |
831 | writel(readl(host->base + MMCICLOCK) & | |
832 | ~variant->clkreg_enable, | |
833 | host->base + MMCICLOCK); | |
834 | else | |
835 | writel(readl(host->base + MMCICLOCK) | | |
836 | variant->clkreg_enable, | |
837 | host->base + MMCICLOCK); | |
838 | } | |
839 | ||
840 | /* | |
841 | * SDIO especially may want to send something that is | |
842 | * not divisible by 4 (as opposed to card sectors | |
843 | * etc), and the FIFO only accept full 32-bit writes. | |
844 | * So compensate by adding +3 on the count, a single | |
845 | * byte become a 32bit write, 7 bytes will be two | |
846 | * 32bit writes etc. | |
847 | */ | |
848 | writesl(base + MMCIFIFO, ptr, (count + 3) >> 2); | |
1da177e4 LT |
849 | |
850 | ptr += count; | |
851 | remain -= count; | |
852 | ||
853 | if (remain == 0) | |
854 | break; | |
855 | ||
856 | status = readl(base + MMCISTATUS); | |
857 | } while (status & MCI_TXFIFOHALFEMPTY); | |
858 | ||
859 | return ptr - buffer; | |
860 | } | |
861 | ||
862 | /* | |
863 | * PIO data transfer IRQ handler. | |
864 | */ | |
7d12e780 | 865 | static irqreturn_t mmci_pio_irq(int irq, void *dev_id) |
1da177e4 LT |
866 | { |
867 | struct mmci_host *host = dev_id; | |
4ce1d6cb | 868 | struct sg_mapping_iter *sg_miter = &host->sg_miter; |
8301bb68 | 869 | struct variant_data *variant = host->variant; |
1da177e4 | 870 | void __iomem *base = host->base; |
4ce1d6cb | 871 | unsigned long flags; |
1da177e4 LT |
872 | u32 status; |
873 | ||
874 | status = readl(base + MMCISTATUS); | |
875 | ||
64de0289 | 876 | dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); |
1da177e4 | 877 | |
4ce1d6cb RV |
878 | local_irq_save(flags); |
879 | ||
1da177e4 | 880 | do { |
1da177e4 LT |
881 | unsigned int remain, len; |
882 | char *buffer; | |
883 | ||
884 | /* | |
885 | * For write, we only need to test the half-empty flag | |
886 | * here - if the FIFO is completely empty, then by | |
887 | * definition it is more than half empty. | |
888 | * | |
889 | * For read, check for data available. | |
890 | */ | |
891 | if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) | |
892 | break; | |
893 | ||
4ce1d6cb RV |
894 | if (!sg_miter_next(sg_miter)) |
895 | break; | |
896 | ||
897 | buffer = sg_miter->addr; | |
898 | remain = sg_miter->length; | |
1da177e4 LT |
899 | |
900 | len = 0; | |
901 | if (status & MCI_RXACTIVE) | |
902 | len = mmci_pio_read(host, buffer, remain); | |
903 | if (status & MCI_TXACTIVE) | |
904 | len = mmci_pio_write(host, buffer, remain, status); | |
905 | ||
4ce1d6cb | 906 | sg_miter->consumed = len; |
1da177e4 | 907 | |
1da177e4 LT |
908 | host->size -= len; |
909 | remain -= len; | |
910 | ||
911 | if (remain) | |
912 | break; | |
913 | ||
1da177e4 LT |
914 | status = readl(base + MMCISTATUS); |
915 | } while (1); | |
916 | ||
4ce1d6cb RV |
917 | sg_miter_stop(sg_miter); |
918 | ||
919 | local_irq_restore(flags); | |
920 | ||
1da177e4 | 921 | /* |
c4d877c1 RK |
922 | * If we have less than the fifo 'half-full' threshold to transfer, |
923 | * trigger a PIO interrupt as soon as any data is available. | |
1da177e4 | 924 | */ |
c4d877c1 | 925 | if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) |
2686b4b4 | 926 | mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); |
1da177e4 LT |
927 | |
928 | /* | |
929 | * If we run out of data, disable the data IRQs; this | |
930 | * prevents a race where the FIFO becomes empty before | |
931 | * the chip itself has disabled the data path, and | |
932 | * stops us racing with our data end IRQ. | |
933 | */ | |
934 | if (host->size == 0) { | |
2686b4b4 | 935 | mmci_set_mask1(host, 0); |
1da177e4 LT |
936 | writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); |
937 | } | |
938 | ||
939 | return IRQ_HANDLED; | |
940 | } | |
941 | ||
942 | /* | |
943 | * Handle completion of command and data transfers. | |
944 | */ | |
7d12e780 | 945 | static irqreturn_t mmci_irq(int irq, void *dev_id) |
1da177e4 LT |
946 | { |
947 | struct mmci_host *host = dev_id; | |
948 | u32 status; | |
949 | int ret = 0; | |
950 | ||
951 | spin_lock(&host->lock); | |
952 | ||
953 | do { | |
954 | struct mmc_command *cmd; | |
955 | struct mmc_data *data; | |
956 | ||
957 | status = readl(host->base + MMCISTATUS); | |
2686b4b4 LW |
958 | |
959 | if (host->singleirq) { | |
960 | if (status & readl(host->base + MMCIMASK1)) | |
961 | mmci_pio_irq(irq, dev_id); | |
962 | ||
963 | status &= ~MCI_IRQ1MASK; | |
964 | } | |
965 | ||
1da177e4 LT |
966 | status &= readl(host->base + MMCIMASK0); |
967 | writel(status, host->base + MMCICLEAR); | |
968 | ||
64de0289 | 969 | dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); |
1da177e4 LT |
970 | |
971 | data = host->data; | |
b63038d6 UH |
972 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| |
973 | MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND| | |
974 | MCI_DATABLOCKEND) && data) | |
1da177e4 LT |
975 | mmci_data_irq(host, data, status); |
976 | ||
977 | cmd = host->cmd; | |
978 | if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) | |
979 | mmci_cmd_irq(host, cmd, status); | |
980 | ||
981 | ret = 1; | |
982 | } while (status); | |
983 | ||
984 | spin_unlock(&host->lock); | |
985 | ||
986 | return IRQ_RETVAL(ret); | |
987 | } | |
988 | ||
989 | static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
990 | { | |
991 | struct mmci_host *host = mmc_priv(mmc); | |
9e943021 | 992 | unsigned long flags; |
1da177e4 LT |
993 | |
994 | WARN_ON(host->mrq != NULL); | |
995 | ||
019a5f56 | 996 | if (mrq->data && !is_power_of_2(mrq->data->blksz)) { |
64de0289 LW |
997 | dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", |
998 | mrq->data->blksz); | |
255d01af PO |
999 | mrq->cmd->error = -EINVAL; |
1000 | mmc_request_done(mmc, mrq); | |
1001 | return; | |
1002 | } | |
1003 | ||
1c3be369 RK |
1004 | pm_runtime_get_sync(mmc_dev(mmc)); |
1005 | ||
9e943021 | 1006 | spin_lock_irqsave(&host->lock, flags); |
1da177e4 LT |
1007 | |
1008 | host->mrq = mrq; | |
1009 | ||
58c7ccbf PF |
1010 | if (mrq->data) |
1011 | mmci_get_next_data(host, mrq->data); | |
1012 | ||
1da177e4 LT |
1013 | if (mrq->data && mrq->data->flags & MMC_DATA_READ) |
1014 | mmci_start_data(host, mrq->data); | |
1015 | ||
1016 | mmci_start_command(host, mrq->cmd, 0); | |
1017 | ||
9e943021 | 1018 | spin_unlock_irqrestore(&host->lock, flags); |
1da177e4 LT |
1019 | } |
1020 | ||
1021 | static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
1022 | { | |
1023 | struct mmci_host *host = mmc_priv(mmc); | |
7d72a1d4 | 1024 | struct variant_data *variant = host->variant; |
a6a6464a LW |
1025 | u32 pwr = 0; |
1026 | unsigned long flags; | |
99fc5131 | 1027 | int ret; |
1da177e4 | 1028 | |
bc521818 UH |
1029 | if (host->plat->ios_handler && |
1030 | host->plat->ios_handler(mmc_dev(mmc), ios)) | |
1031 | dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); | |
1032 | ||
1da177e4 LT |
1033 | switch (ios->power_mode) { |
1034 | case MMC_POWER_OFF: | |
99fc5131 LW |
1035 | if (host->vcc) |
1036 | ret = mmc_regulator_set_ocr(mmc, host->vcc, 0); | |
1da177e4 LT |
1037 | break; |
1038 | case MMC_POWER_UP: | |
99fc5131 LW |
1039 | if (host->vcc) { |
1040 | ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd); | |
1041 | if (ret) { | |
1042 | dev_err(mmc_dev(mmc), "unable to set OCR\n"); | |
1043 | /* | |
1044 | * The .set_ios() function in the mmc_host_ops | |
1045 | * struct return void, and failing to set the | |
1046 | * power should be rare so we print an error | |
1047 | * and return here. | |
1048 | */ | |
1049 | return; | |
1050 | } | |
1051 | } | |
7d72a1d4 UH |
1052 | /* |
1053 | * The ST Micro variant doesn't have the PL180s MCI_PWR_UP | |
1054 | * and instead uses MCI_PWR_ON so apply whatever value is | |
1055 | * configured in the variant data. | |
1056 | */ | |
1057 | pwr |= variant->pwrreg_powerup; | |
1058 | ||
1059 | break; | |
1da177e4 LT |
1060 | case MMC_POWER_ON: |
1061 | pwr |= MCI_PWR_ON; | |
1062 | break; | |
1063 | } | |
1064 | ||
4d1a3a0d UH |
1065 | if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { |
1066 | /* | |
1067 | * The ST Micro variant has some additional bits | |
1068 | * indicating signal direction for the signals in | |
1069 | * the SD/MMC bus and feedback-clock usage. | |
1070 | */ | |
1071 | pwr |= host->plat->sigdir; | |
1072 | ||
1073 | if (ios->bus_width == MMC_BUS_WIDTH_4) | |
1074 | pwr &= ~MCI_ST_DATA74DIREN; | |
1075 | else if (ios->bus_width == MMC_BUS_WIDTH_1) | |
1076 | pwr &= (~MCI_ST_DATA74DIREN & | |
1077 | ~MCI_ST_DATA31DIREN & | |
1078 | ~MCI_ST_DATA2DIREN); | |
1079 | } | |
1080 | ||
cc30d60e | 1081 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { |
f17a1f06 | 1082 | if (host->hw_designer != AMBA_VENDOR_ST) |
cc30d60e LW |
1083 | pwr |= MCI_ROD; |
1084 | else { | |
1085 | /* | |
1086 | * The ST Micro variant use the ROD bit for something | |
1087 | * else and only has OD (Open Drain). | |
1088 | */ | |
1089 | pwr |= MCI_OD; | |
1090 | } | |
1091 | } | |
1da177e4 | 1092 | |
a6a6464a LW |
1093 | spin_lock_irqsave(&host->lock, flags); |
1094 | ||
1095 | mmci_set_clkreg(host, ios->clock); | |
1da177e4 LT |
1096 | |
1097 | if (host->pwr != pwr) { | |
1098 | host->pwr = pwr; | |
1099 | writel(pwr, host->base + MMCIPOWER); | |
1100 | } | |
a6a6464a LW |
1101 | |
1102 | spin_unlock_irqrestore(&host->lock, flags); | |
1da177e4 LT |
1103 | } |
1104 | ||
89001446 RK |
1105 | static int mmci_get_ro(struct mmc_host *mmc) |
1106 | { | |
1107 | struct mmci_host *host = mmc_priv(mmc); | |
1108 | ||
1109 | if (host->gpio_wp == -ENOSYS) | |
1110 | return -ENOSYS; | |
1111 | ||
18a06301 | 1112 | return gpio_get_value_cansleep(host->gpio_wp); |
89001446 RK |
1113 | } |
1114 | ||
1115 | static int mmci_get_cd(struct mmc_host *mmc) | |
1116 | { | |
1117 | struct mmci_host *host = mmc_priv(mmc); | |
29719445 | 1118 | struct mmci_platform_data *plat = host->plat; |
89001446 RK |
1119 | unsigned int status; |
1120 | ||
4b8caec0 RV |
1121 | if (host->gpio_cd == -ENOSYS) { |
1122 | if (!plat->status) | |
1123 | return 1; /* Assume always present */ | |
1124 | ||
29719445 | 1125 | status = plat->status(mmc_dev(host->mmc)); |
4b8caec0 | 1126 | } else |
18a06301 LW |
1127 | status = !!gpio_get_value_cansleep(host->gpio_cd) |
1128 | ^ plat->cd_invert; | |
89001446 | 1129 | |
74bc8093 RK |
1130 | /* |
1131 | * Use positive logic throughout - status is zero for no card, | |
1132 | * non-zero for card inserted. | |
1133 | */ | |
1134 | return status; | |
89001446 RK |
1135 | } |
1136 | ||
148b8b39 RV |
1137 | static irqreturn_t mmci_cd_irq(int irq, void *dev_id) |
1138 | { | |
1139 | struct mmci_host *host = dev_id; | |
1140 | ||
1141 | mmc_detect_change(host->mmc, msecs_to_jiffies(500)); | |
1142 | ||
1143 | return IRQ_HANDLED; | |
1144 | } | |
1145 | ||
ab7aefd0 | 1146 | static const struct mmc_host_ops mmci_ops = { |
1da177e4 | 1147 | .request = mmci_request, |
58c7ccbf PF |
1148 | .pre_req = mmci_pre_request, |
1149 | .post_req = mmci_post_request, | |
1da177e4 | 1150 | .set_ios = mmci_set_ios, |
89001446 RK |
1151 | .get_ro = mmci_get_ro, |
1152 | .get_cd = mmci_get_cd, | |
1da177e4 LT |
1153 | }; |
1154 | ||
aa25afad RK |
1155 | static int __devinit mmci_probe(struct amba_device *dev, |
1156 | const struct amba_id *id) | |
1da177e4 | 1157 | { |
6ef297f8 | 1158 | struct mmci_platform_data *plat = dev->dev.platform_data; |
4956e109 | 1159 | struct variant_data *variant = id->data; |
1da177e4 LT |
1160 | struct mmci_host *host; |
1161 | struct mmc_host *mmc; | |
1162 | int ret; | |
1163 | ||
1164 | /* must have platform data */ | |
1165 | if (!plat) { | |
1166 | ret = -EINVAL; | |
1167 | goto out; | |
1168 | } | |
1169 | ||
1170 | ret = amba_request_regions(dev, DRIVER_NAME); | |
1171 | if (ret) | |
1172 | goto out; | |
1173 | ||
1174 | mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); | |
1175 | if (!mmc) { | |
1176 | ret = -ENOMEM; | |
1177 | goto rel_regions; | |
1178 | } | |
1179 | ||
1180 | host = mmc_priv(mmc); | |
4ea580f1 | 1181 | host->mmc = mmc; |
012b7d33 | 1182 | |
89001446 RK |
1183 | host->gpio_wp = -ENOSYS; |
1184 | host->gpio_cd = -ENOSYS; | |
148b8b39 | 1185 | host->gpio_cd_irq = -1; |
89001446 | 1186 | |
012b7d33 RK |
1187 | host->hw_designer = amba_manf(dev); |
1188 | host->hw_revision = amba_rev(dev); | |
64de0289 LW |
1189 | dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); |
1190 | dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); | |
012b7d33 | 1191 | |
ee569c43 | 1192 | host->clk = clk_get(&dev->dev, NULL); |
1da177e4 LT |
1193 | if (IS_ERR(host->clk)) { |
1194 | ret = PTR_ERR(host->clk); | |
1195 | host->clk = NULL; | |
1196 | goto host_free; | |
1197 | } | |
1198 | ||
52ca0f3a | 1199 | ret = clk_prepare(host->clk); |
1da177e4 | 1200 | if (ret) |
a8d3584a | 1201 | goto clk_free; |
1da177e4 | 1202 | |
52ca0f3a RK |
1203 | ret = clk_enable(host->clk); |
1204 | if (ret) | |
1205 | goto clk_unprep; | |
1206 | ||
1da177e4 | 1207 | host->plat = plat; |
4956e109 | 1208 | host->variant = variant; |
1da177e4 | 1209 | host->mclk = clk_get_rate(host->clk); |
c8df9a53 LW |
1210 | /* |
1211 | * According to the spec, mclk is max 100 MHz, | |
1212 | * so we try to adjust the clock down to this, | |
1213 | * (if possible). | |
1214 | */ | |
1215 | if (host->mclk > 100000000) { | |
1216 | ret = clk_set_rate(host->clk, 100000000); | |
1217 | if (ret < 0) | |
1218 | goto clk_disable; | |
1219 | host->mclk = clk_get_rate(host->clk); | |
64de0289 LW |
1220 | dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", |
1221 | host->mclk); | |
c8df9a53 | 1222 | } |
c8ebae37 | 1223 | host->phybase = dev->res.start; |
dc890c2d | 1224 | host->base = ioremap(dev->res.start, resource_size(&dev->res)); |
1da177e4 LT |
1225 | if (!host->base) { |
1226 | ret = -ENOMEM; | |
1227 | goto clk_disable; | |
1228 | } | |
1229 | ||
1230 | mmc->ops = &mmci_ops; | |
7f294e49 LW |
1231 | /* |
1232 | * The ARM and ST versions of the block have slightly different | |
1233 | * clock divider equations which means that the minimum divider | |
1234 | * differs too. | |
1235 | */ | |
1236 | if (variant->st_clkdiv) | |
1237 | mmc->f_min = DIV_ROUND_UP(host->mclk, 257); | |
1238 | else | |
1239 | mmc->f_min = DIV_ROUND_UP(host->mclk, 512); | |
808d97cc LW |
1240 | /* |
1241 | * If the platform data supplies a maximum operating | |
1242 | * frequency, this takes precedence. Else, we fall back | |
1243 | * to using the module parameter, which has a (low) | |
1244 | * default value in case it is not specified. Either | |
1245 | * value must not exceed the clock rate into the block, | |
1246 | * of course. | |
1247 | */ | |
1248 | if (plat->f_max) | |
1249 | mmc->f_max = min(host->mclk, plat->f_max); | |
1250 | else | |
1251 | mmc->f_max = min(host->mclk, fmax); | |
64de0289 LW |
1252 | dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); |
1253 | ||
34e84f39 LW |
1254 | #ifdef CONFIG_REGULATOR |
1255 | /* If we're using the regulator framework, try to fetch a regulator */ | |
1256 | host->vcc = regulator_get(&dev->dev, "vmmc"); | |
1257 | if (IS_ERR(host->vcc)) | |
1258 | host->vcc = NULL; | |
1259 | else { | |
1260 | int mask = mmc_regulator_get_ocrmask(host->vcc); | |
1261 | ||
1262 | if (mask < 0) | |
1263 | dev_err(&dev->dev, "error getting OCR mask (%d)\n", | |
1264 | mask); | |
1265 | else { | |
1266 | host->mmc->ocr_avail = (u32) mask; | |
1267 | if (plat->ocr_mask) | |
1268 | dev_warn(&dev->dev, | |
1269 | "Provided ocr_mask/setpower will not be used " | |
1270 | "(using regulator instead)\n"); | |
1271 | } | |
1272 | } | |
1273 | #endif | |
1274 | /* Fall back to platform data if no regulator is found */ | |
1275 | if (host->vcc == NULL) | |
1276 | mmc->ocr_avail = plat->ocr_mask; | |
9e6c82cd | 1277 | mmc->caps = plat->capabilities; |
5a092627 | 1278 | mmc->caps2 = plat->capabilities2; |
1da177e4 LT |
1279 | |
1280 | /* | |
1281 | * We can do SGIO | |
1282 | */ | |
a36274e0 | 1283 | mmc->max_segs = NR_SG; |
1da177e4 LT |
1284 | |
1285 | /* | |
08458ef6 RV |
1286 | * Since only a certain number of bits are valid in the data length |
1287 | * register, we must ensure that we don't exceed 2^num-1 bytes in a | |
1288 | * single request. | |
1da177e4 | 1289 | */ |
08458ef6 | 1290 | mmc->max_req_size = (1 << variant->datalength_bits) - 1; |
1da177e4 LT |
1291 | |
1292 | /* | |
1293 | * Set the maximum segment size. Since we aren't doing DMA | |
1294 | * (yet) we are only limited by the data length register. | |
1295 | */ | |
55db890a | 1296 | mmc->max_seg_size = mmc->max_req_size; |
1da177e4 | 1297 | |
fe4a3c7a PO |
1298 | /* |
1299 | * Block size can be up to 2048 bytes, but must be a power of two. | |
1300 | */ | |
1301 | mmc->max_blk_size = 2048; | |
1302 | ||
55db890a PO |
1303 | /* |
1304 | * No limit on the number of blocks transferred. | |
1305 | */ | |
1306 | mmc->max_blk_count = mmc->max_req_size; | |
1307 | ||
1da177e4 LT |
1308 | spin_lock_init(&host->lock); |
1309 | ||
1310 | writel(0, host->base + MMCIMASK0); | |
1311 | writel(0, host->base + MMCIMASK1); | |
1312 | writel(0xfff, host->base + MMCICLEAR); | |
1313 | ||
89001446 RK |
1314 | if (gpio_is_valid(plat->gpio_cd)) { |
1315 | ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); | |
1316 | if (ret == 0) | |
1317 | ret = gpio_direction_input(plat->gpio_cd); | |
1318 | if (ret == 0) | |
1319 | host->gpio_cd = plat->gpio_cd; | |
1320 | else if (ret != -ENOSYS) | |
1321 | goto err_gpio_cd; | |
148b8b39 | 1322 | |
17ee083b LW |
1323 | /* |
1324 | * A gpio pin that will detect cards when inserted and removed | |
1325 | * will most likely want to trigger on the edges if it is | |
1326 | * 0 when ejected and 1 when inserted (or mutatis mutandis | |
1327 | * for the inverted case) so we request triggers on both | |
1328 | * edges. | |
1329 | */ | |
148b8b39 | 1330 | ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), |
17ee083b LW |
1331 | mmci_cd_irq, |
1332 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, | |
1333 | DRIVER_NAME " (cd)", host); | |
148b8b39 RV |
1334 | if (ret >= 0) |
1335 | host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); | |
89001446 RK |
1336 | } |
1337 | if (gpio_is_valid(plat->gpio_wp)) { | |
1338 | ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); | |
1339 | if (ret == 0) | |
1340 | ret = gpio_direction_input(plat->gpio_wp); | |
1341 | if (ret == 0) | |
1342 | host->gpio_wp = plat->gpio_wp; | |
1343 | else if (ret != -ENOSYS) | |
1344 | goto err_gpio_wp; | |
1345 | } | |
1346 | ||
4b8caec0 RV |
1347 | if ((host->plat->status || host->gpio_cd != -ENOSYS) |
1348 | && host->gpio_cd_irq < 0) | |
148b8b39 RV |
1349 | mmc->caps |= MMC_CAP_NEEDS_POLL; |
1350 | ||
dace1453 | 1351 | ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); |
1da177e4 LT |
1352 | if (ret) |
1353 | goto unmap; | |
1354 | ||
2686b4b4 LW |
1355 | if (dev->irq[1] == NO_IRQ) |
1356 | host->singleirq = true; | |
1357 | else { | |
1358 | ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, | |
1359 | DRIVER_NAME " (pio)", host); | |
1360 | if (ret) | |
1361 | goto irq0_free; | |
1362 | } | |
1da177e4 | 1363 | |
8cb28155 | 1364 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); |
1da177e4 LT |
1365 | |
1366 | amba_set_drvdata(dev, mmc); | |
1367 | ||
c8ebae37 RK |
1368 | dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", |
1369 | mmc_hostname(mmc), amba_part(dev), amba_manf(dev), | |
1370 | amba_rev(dev), (unsigned long long)dev->res.start, | |
1371 | dev->irq[0], dev->irq[1]); | |
1372 | ||
1373 | mmci_dma_setup(host); | |
1da177e4 | 1374 | |
1c3be369 RK |
1375 | pm_runtime_put(&dev->dev); |
1376 | ||
8c11a94d RK |
1377 | mmc_add_host(mmc); |
1378 | ||
1da177e4 LT |
1379 | return 0; |
1380 | ||
1381 | irq0_free: | |
1382 | free_irq(dev->irq[0], host); | |
1383 | unmap: | |
89001446 RK |
1384 | if (host->gpio_wp != -ENOSYS) |
1385 | gpio_free(host->gpio_wp); | |
1386 | err_gpio_wp: | |
148b8b39 RV |
1387 | if (host->gpio_cd_irq >= 0) |
1388 | free_irq(host->gpio_cd_irq, host); | |
89001446 RK |
1389 | if (host->gpio_cd != -ENOSYS) |
1390 | gpio_free(host->gpio_cd); | |
1391 | err_gpio_cd: | |
1da177e4 LT |
1392 | iounmap(host->base); |
1393 | clk_disable: | |
1394 | clk_disable(host->clk); | |
52ca0f3a RK |
1395 | clk_unprep: |
1396 | clk_unprepare(host->clk); | |
1da177e4 LT |
1397 | clk_free: |
1398 | clk_put(host->clk); | |
1399 | host_free: | |
1400 | mmc_free_host(mmc); | |
1401 | rel_regions: | |
1402 | amba_release_regions(dev); | |
1403 | out: | |
1404 | return ret; | |
1405 | } | |
1406 | ||
6dc4a47a | 1407 | static int __devexit mmci_remove(struct amba_device *dev) |
1da177e4 LT |
1408 | { |
1409 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
1410 | ||
1411 | amba_set_drvdata(dev, NULL); | |
1412 | ||
1413 | if (mmc) { | |
1414 | struct mmci_host *host = mmc_priv(mmc); | |
1415 | ||
1c3be369 RK |
1416 | /* |
1417 | * Undo pm_runtime_put() in probe. We use the _sync | |
1418 | * version here so that we can access the primecell. | |
1419 | */ | |
1420 | pm_runtime_get_sync(&dev->dev); | |
1421 | ||
1da177e4 LT |
1422 | mmc_remove_host(mmc); |
1423 | ||
1424 | writel(0, host->base + MMCIMASK0); | |
1425 | writel(0, host->base + MMCIMASK1); | |
1426 | ||
1427 | writel(0, host->base + MMCICOMMAND); | |
1428 | writel(0, host->base + MMCIDATACTRL); | |
1429 | ||
c8ebae37 | 1430 | mmci_dma_release(host); |
1da177e4 | 1431 | free_irq(dev->irq[0], host); |
2686b4b4 LW |
1432 | if (!host->singleirq) |
1433 | free_irq(dev->irq[1], host); | |
1da177e4 | 1434 | |
89001446 RK |
1435 | if (host->gpio_wp != -ENOSYS) |
1436 | gpio_free(host->gpio_wp); | |
148b8b39 RV |
1437 | if (host->gpio_cd_irq >= 0) |
1438 | free_irq(host->gpio_cd_irq, host); | |
89001446 RK |
1439 | if (host->gpio_cd != -ENOSYS) |
1440 | gpio_free(host->gpio_cd); | |
1441 | ||
1da177e4 LT |
1442 | iounmap(host->base); |
1443 | clk_disable(host->clk); | |
52ca0f3a | 1444 | clk_unprepare(host->clk); |
1da177e4 LT |
1445 | clk_put(host->clk); |
1446 | ||
99fc5131 LW |
1447 | if (host->vcc) |
1448 | mmc_regulator_set_ocr(mmc, host->vcc, 0); | |
34e84f39 LW |
1449 | regulator_put(host->vcc); |
1450 | ||
1da177e4 LT |
1451 | mmc_free_host(mmc); |
1452 | ||
1453 | amba_release_regions(dev); | |
1454 | } | |
1455 | ||
1456 | return 0; | |
1457 | } | |
1458 | ||
48fa7003 UH |
1459 | #ifdef CONFIG_SUSPEND |
1460 | static int mmci_suspend(struct device *dev) | |
1da177e4 | 1461 | { |
48fa7003 UH |
1462 | struct amba_device *adev = to_amba_device(dev); |
1463 | struct mmc_host *mmc = amba_get_drvdata(adev); | |
1da177e4 LT |
1464 | int ret = 0; |
1465 | ||
1466 | if (mmc) { | |
1467 | struct mmci_host *host = mmc_priv(mmc); | |
1468 | ||
1a13f8fa | 1469 | ret = mmc_suspend_host(mmc); |
1da177e4 LT |
1470 | if (ret == 0) |
1471 | writel(0, host->base + MMCIMASK0); | |
1472 | } | |
1473 | ||
1474 | return ret; | |
1475 | } | |
1476 | ||
48fa7003 | 1477 | static int mmci_resume(struct device *dev) |
1da177e4 | 1478 | { |
48fa7003 UH |
1479 | struct amba_device *adev = to_amba_device(dev); |
1480 | struct mmc_host *mmc = amba_get_drvdata(adev); | |
1da177e4 LT |
1481 | int ret = 0; |
1482 | ||
1483 | if (mmc) { | |
1484 | struct mmci_host *host = mmc_priv(mmc); | |
1485 | ||
1486 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); | |
1487 | ||
1488 | ret = mmc_resume_host(mmc); | |
1489 | } | |
1490 | ||
1491 | return ret; | |
1492 | } | |
1da177e4 LT |
1493 | #endif |
1494 | ||
48fa7003 UH |
1495 | static const struct dev_pm_ops mmci_dev_pm_ops = { |
1496 | SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume) | |
1497 | }; | |
1498 | ||
1da177e4 LT |
1499 | static struct amba_id mmci_ids[] = { |
1500 | { | |
1501 | .id = 0x00041180, | |
768fbc18 | 1502 | .mask = 0xff0fffff, |
4956e109 | 1503 | .data = &variant_arm, |
1da177e4 | 1504 | }, |
768fbc18 PM |
1505 | { |
1506 | .id = 0x01041180, | |
1507 | .mask = 0xff0fffff, | |
1508 | .data = &variant_arm_extended_fifo, | |
1509 | }, | |
1da177e4 LT |
1510 | { |
1511 | .id = 0x00041181, | |
1512 | .mask = 0x000fffff, | |
4956e109 | 1513 | .data = &variant_arm, |
1da177e4 | 1514 | }, |
cc30d60e LW |
1515 | /* ST Micro variants */ |
1516 | { | |
1517 | .id = 0x00180180, | |
1518 | .mask = 0x00ffffff, | |
4956e109 | 1519 | .data = &variant_u300, |
cc30d60e LW |
1520 | }, |
1521 | { | |
1522 | .id = 0x00280180, | |
1523 | .mask = 0x00ffffff, | |
4956e109 RV |
1524 | .data = &variant_u300, |
1525 | }, | |
1526 | { | |
1527 | .id = 0x00480180, | |
1784b157 | 1528 | .mask = 0xf0ffffff, |
4956e109 | 1529 | .data = &variant_ux500, |
cc30d60e | 1530 | }, |
1784b157 PL |
1531 | { |
1532 | .id = 0x10480180, | |
1533 | .mask = 0xf0ffffff, | |
1534 | .data = &variant_ux500v2, | |
1535 | }, | |
1da177e4 LT |
1536 | { 0, 0 }, |
1537 | }; | |
1538 | ||
9f99835f DM |
1539 | MODULE_DEVICE_TABLE(amba, mmci_ids); |
1540 | ||
1da177e4 LT |
1541 | static struct amba_driver mmci_driver = { |
1542 | .drv = { | |
1543 | .name = DRIVER_NAME, | |
48fa7003 | 1544 | .pm = &mmci_dev_pm_ops, |
1da177e4 LT |
1545 | }, |
1546 | .probe = mmci_probe, | |
6dc4a47a | 1547 | .remove = __devexit_p(mmci_remove), |
1da177e4 LT |
1548 | .id_table = mmci_ids, |
1549 | }; | |
1550 | ||
1551 | static int __init mmci_init(void) | |
1552 | { | |
1553 | return amba_driver_register(&mmci_driver); | |
1554 | } | |
1555 | ||
1556 | static void __exit mmci_exit(void) | |
1557 | { | |
1558 | amba_driver_unregister(&mmci_driver); | |
1559 | } | |
1560 | ||
1561 | module_init(mmci_init); | |
1562 | module_exit(mmci_exit); | |
1563 | module_param(fmax, uint, 0444); | |
1564 | ||
1565 | MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); | |
1566 | MODULE_LICENSE("GPL"); |