Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. | |
64de0289 | 5 | * Copyright (C) 2010 ST-Ericsson AB. |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/highmem.h> | |
019a5f56 | 20 | #include <linux/log2.h> |
1da177e4 | 21 | #include <linux/mmc/host.h> |
a62c80e5 | 22 | #include <linux/amba/bus.h> |
f8ce2547 | 23 | #include <linux/clk.h> |
bd6dee6f | 24 | #include <linux/scatterlist.h> |
89001446 | 25 | #include <linux/gpio.h> |
6ef297f8 | 26 | #include <linux/amba/mmci.h> |
34e84f39 | 27 | #include <linux/regulator/consumer.h> |
1da177e4 | 28 | |
7b09cdac | 29 | #include <asm/div64.h> |
1da177e4 | 30 | #include <asm/io.h> |
c6b8fdad | 31 | #include <asm/sizes.h> |
1da177e4 LT |
32 | |
33 | #include "mmci.h" | |
34 | ||
35 | #define DRIVER_NAME "mmci-pl18x" | |
36 | ||
1da177e4 LT |
37 | static unsigned int fmax = 515633; |
38 | ||
4956e109 RV |
39 | /** |
40 | * struct variant_data - MMCI variant-specific quirks | |
41 | * @clkreg: default value for MCICLOCK register | |
42 | */ | |
43 | struct variant_data { | |
44 | unsigned int clkreg; | |
45 | }; | |
46 | ||
47 | static struct variant_data variant_arm = { | |
48 | }; | |
49 | ||
50 | static struct variant_data variant_u300 = { | |
51 | }; | |
52 | ||
53 | static struct variant_data variant_ux500 = { | |
54 | .clkreg = MCI_CLK_ENABLE, | |
55 | }; | |
a6a6464a LW |
56 | /* |
57 | * This must be called with host->lock held | |
58 | */ | |
59 | static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) | |
60 | { | |
4956e109 RV |
61 | struct variant_data *variant = host->variant; |
62 | u32 clk = variant->clkreg; | |
a6a6464a LW |
63 | |
64 | if (desired) { | |
65 | if (desired >= host->mclk) { | |
66 | clk = MCI_CLK_BYPASS; | |
67 | host->cclk = host->mclk; | |
68 | } else { | |
69 | clk = host->mclk / (2 * desired) - 1; | |
70 | if (clk >= 256) | |
71 | clk = 255; | |
72 | host->cclk = host->mclk / (2 * (clk + 1)); | |
73 | } | |
b43149c1 | 74 | if (host->hw_designer == AMBA_VENDOR_ST) |
771dc157 | 75 | clk |= MCI_ST_FCEN; /* Bug fix in ST IP block */ |
a6a6464a LW |
76 | clk |= MCI_CLK_ENABLE; |
77 | /* This hasn't proven to be worthwhile */ | |
78 | /* clk |= MCI_CLK_PWRSAVE; */ | |
79 | } | |
80 | ||
9e6c82cd | 81 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) |
771dc157 LW |
82 | clk |= MCI_4BIT_BUS; |
83 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) | |
84 | clk |= MCI_ST_8BIT_BUS; | |
9e6c82cd | 85 | |
a6a6464a LW |
86 | writel(clk, host->base + MMCICLOCK); |
87 | } | |
88 | ||
1da177e4 LT |
89 | static void |
90 | mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) | |
91 | { | |
92 | writel(0, host->base + MMCICOMMAND); | |
93 | ||
e47c222b RK |
94 | BUG_ON(host->data); |
95 | ||
1da177e4 LT |
96 | host->mrq = NULL; |
97 | host->cmd = NULL; | |
98 | ||
99 | if (mrq->data) | |
100 | mrq->data->bytes_xfered = host->data_xfered; | |
101 | ||
102 | /* | |
103 | * Need to drop the host lock here; mmc_request_done may call | |
104 | * back into the driver... | |
105 | */ | |
106 | spin_unlock(&host->lock); | |
107 | mmc_request_done(host->mmc, mrq); | |
108 | spin_lock(&host->lock); | |
109 | } | |
110 | ||
111 | static void mmci_stop_data(struct mmci_host *host) | |
112 | { | |
113 | writel(0, host->base + MMCIDATACTRL); | |
114 | writel(0, host->base + MMCIMASK1); | |
115 | host->data = NULL; | |
116 | } | |
117 | ||
4ce1d6cb RV |
118 | static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) |
119 | { | |
120 | unsigned int flags = SG_MITER_ATOMIC; | |
121 | ||
122 | if (data->flags & MMC_DATA_READ) | |
123 | flags |= SG_MITER_TO_SG; | |
124 | else | |
125 | flags |= SG_MITER_FROM_SG; | |
126 | ||
127 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); | |
128 | } | |
129 | ||
1da177e4 LT |
130 | static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) |
131 | { | |
132 | unsigned int datactrl, timeout, irqmask; | |
7b09cdac | 133 | unsigned long long clks; |
1da177e4 | 134 | void __iomem *base; |
3bc87f24 | 135 | int blksz_bits; |
1da177e4 | 136 | |
64de0289 LW |
137 | dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", |
138 | data->blksz, data->blocks, data->flags); | |
1da177e4 LT |
139 | |
140 | host->data = data; | |
528320db | 141 | host->size = data->blksz * data->blocks; |
1da177e4 LT |
142 | host->data_xfered = 0; |
143 | ||
144 | mmci_init_sg(host, data); | |
145 | ||
7b09cdac RK |
146 | clks = (unsigned long long)data->timeout_ns * host->cclk; |
147 | do_div(clks, 1000000000UL); | |
148 | ||
149 | timeout = data->timeout_clks + (unsigned int)clks; | |
1da177e4 LT |
150 | |
151 | base = host->base; | |
152 | writel(timeout, base + MMCIDATATIMER); | |
153 | writel(host->size, base + MMCIDATALENGTH); | |
154 | ||
3bc87f24 RK |
155 | blksz_bits = ffs(data->blksz) - 1; |
156 | BUG_ON(1 << blksz_bits != data->blksz); | |
157 | ||
158 | datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; | |
1da177e4 LT |
159 | if (data->flags & MMC_DATA_READ) { |
160 | datactrl |= MCI_DPSM_DIRECTION; | |
161 | irqmask = MCI_RXFIFOHALFFULLMASK; | |
0425a142 RK |
162 | |
163 | /* | |
164 | * If we have less than a FIFOSIZE of bytes to transfer, | |
165 | * trigger a PIO interrupt as soon as any data is available. | |
166 | */ | |
167 | if (host->size < MCI_FIFOSIZE) | |
168 | irqmask |= MCI_RXDATAAVLBLMASK; | |
1da177e4 LT |
169 | } else { |
170 | /* | |
171 | * We don't actually need to include "FIFO empty" here | |
172 | * since its implicit in "FIFO half empty". | |
173 | */ | |
174 | irqmask = MCI_TXFIFOHALFEMPTYMASK; | |
175 | } | |
176 | ||
177 | writel(datactrl, base + MMCIDATACTRL); | |
178 | writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); | |
179 | writel(irqmask, base + MMCIMASK1); | |
180 | } | |
181 | ||
182 | static void | |
183 | mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) | |
184 | { | |
185 | void __iomem *base = host->base; | |
186 | ||
64de0289 | 187 | dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", |
1da177e4 LT |
188 | cmd->opcode, cmd->arg, cmd->flags); |
189 | ||
190 | if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { | |
191 | writel(0, base + MMCICOMMAND); | |
192 | udelay(1); | |
193 | } | |
194 | ||
195 | c |= cmd->opcode | MCI_CPSM_ENABLE; | |
e9225176 RK |
196 | if (cmd->flags & MMC_RSP_PRESENT) { |
197 | if (cmd->flags & MMC_RSP_136) | |
198 | c |= MCI_CPSM_LONGRSP; | |
1da177e4 | 199 | c |= MCI_CPSM_RESPONSE; |
1da177e4 LT |
200 | } |
201 | if (/*interrupt*/0) | |
202 | c |= MCI_CPSM_INTERRUPT; | |
203 | ||
204 | host->cmd = cmd; | |
205 | ||
206 | writel(cmd->arg, base + MMCIARGUMENT); | |
207 | writel(c, base + MMCICOMMAND); | |
208 | } | |
209 | ||
210 | static void | |
211 | mmci_data_irq(struct mmci_host *host, struct mmc_data *data, | |
212 | unsigned int status) | |
213 | { | |
214 | if (status & MCI_DATABLOCKEND) { | |
3bc87f24 | 215 | host->data_xfered += data->blksz; |
f28e8a4d LW |
216 | #ifdef CONFIG_ARCH_U300 |
217 | /* | |
218 | * On the U300 some signal or other is | |
219 | * badly routed so that a data write does | |
220 | * not properly terminate with a MCI_DATAEND | |
221 | * status flag. This quirk will make writes | |
222 | * work again. | |
223 | */ | |
224 | if (data->flags & MMC_DATA_WRITE) | |
225 | status |= MCI_DATAEND; | |
226 | #endif | |
1da177e4 LT |
227 | } |
228 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) { | |
64de0289 | 229 | dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ (status %08x)\n", status); |
1da177e4 | 230 | if (status & MCI_DATACRCFAIL) |
17b0429d | 231 | data->error = -EILSEQ; |
1da177e4 | 232 | else if (status & MCI_DATATIMEOUT) |
17b0429d | 233 | data->error = -ETIMEDOUT; |
1da177e4 | 234 | else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN)) |
17b0429d | 235 | data->error = -EIO; |
1da177e4 | 236 | status |= MCI_DATAEND; |
e9c091b4 RK |
237 | |
238 | /* | |
239 | * We hit an error condition. Ensure that any data | |
240 | * partially written to a page is properly coherent. | |
241 | */ | |
4ce1d6cb RV |
242 | if (data->flags & MMC_DATA_READ) { |
243 | struct sg_mapping_iter *sg_miter = &host->sg_miter; | |
244 | unsigned long flags; | |
245 | ||
246 | local_irq_save(flags); | |
247 | if (sg_miter_next(sg_miter)) { | |
248 | flush_dcache_page(sg_miter->page); | |
249 | sg_miter_stop(sg_miter); | |
250 | } | |
251 | local_irq_restore(flags); | |
252 | } | |
1da177e4 LT |
253 | } |
254 | if (status & MCI_DATAEND) { | |
255 | mmci_stop_data(host); | |
256 | ||
257 | if (!data->stop) { | |
258 | mmci_request_end(host, data->mrq); | |
259 | } else { | |
260 | mmci_start_command(host, data->stop, 0); | |
261 | } | |
262 | } | |
263 | } | |
264 | ||
265 | static void | |
266 | mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, | |
267 | unsigned int status) | |
268 | { | |
269 | void __iomem *base = host->base; | |
270 | ||
271 | host->cmd = NULL; | |
272 | ||
273 | cmd->resp[0] = readl(base + MMCIRESPONSE0); | |
274 | cmd->resp[1] = readl(base + MMCIRESPONSE1); | |
275 | cmd->resp[2] = readl(base + MMCIRESPONSE2); | |
276 | cmd->resp[3] = readl(base + MMCIRESPONSE3); | |
277 | ||
278 | if (status & MCI_CMDTIMEOUT) { | |
17b0429d | 279 | cmd->error = -ETIMEDOUT; |
1da177e4 | 280 | } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { |
17b0429d | 281 | cmd->error = -EILSEQ; |
1da177e4 LT |
282 | } |
283 | ||
17b0429d | 284 | if (!cmd->data || cmd->error) { |
e47c222b RK |
285 | if (host->data) |
286 | mmci_stop_data(host); | |
1da177e4 LT |
287 | mmci_request_end(host, cmd->mrq); |
288 | } else if (!(cmd->data->flags & MMC_DATA_READ)) { | |
289 | mmci_start_data(host, cmd->data); | |
290 | } | |
291 | } | |
292 | ||
293 | static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) | |
294 | { | |
295 | void __iomem *base = host->base; | |
296 | char *ptr = buffer; | |
297 | u32 status; | |
26eed9a5 | 298 | int host_remain = host->size; |
1da177e4 LT |
299 | |
300 | do { | |
26eed9a5 | 301 | int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); |
1da177e4 LT |
302 | |
303 | if (count > remain) | |
304 | count = remain; | |
305 | ||
306 | if (count <= 0) | |
307 | break; | |
308 | ||
309 | readsl(base + MMCIFIFO, ptr, count >> 2); | |
310 | ||
311 | ptr += count; | |
312 | remain -= count; | |
26eed9a5 | 313 | host_remain -= count; |
1da177e4 LT |
314 | |
315 | if (remain == 0) | |
316 | break; | |
317 | ||
318 | status = readl(base + MMCISTATUS); | |
319 | } while (status & MCI_RXDATAAVLBL); | |
320 | ||
321 | return ptr - buffer; | |
322 | } | |
323 | ||
324 | static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) | |
325 | { | |
326 | void __iomem *base = host->base; | |
327 | char *ptr = buffer; | |
328 | ||
329 | do { | |
330 | unsigned int count, maxcnt; | |
331 | ||
332 | maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE; | |
333 | count = min(remain, maxcnt); | |
334 | ||
335 | writesl(base + MMCIFIFO, ptr, count >> 2); | |
336 | ||
337 | ptr += count; | |
338 | remain -= count; | |
339 | ||
340 | if (remain == 0) | |
341 | break; | |
342 | ||
343 | status = readl(base + MMCISTATUS); | |
344 | } while (status & MCI_TXFIFOHALFEMPTY); | |
345 | ||
346 | return ptr - buffer; | |
347 | } | |
348 | ||
349 | /* | |
350 | * PIO data transfer IRQ handler. | |
351 | */ | |
7d12e780 | 352 | static irqreturn_t mmci_pio_irq(int irq, void *dev_id) |
1da177e4 LT |
353 | { |
354 | struct mmci_host *host = dev_id; | |
4ce1d6cb | 355 | struct sg_mapping_iter *sg_miter = &host->sg_miter; |
1da177e4 | 356 | void __iomem *base = host->base; |
4ce1d6cb | 357 | unsigned long flags; |
1da177e4 LT |
358 | u32 status; |
359 | ||
360 | status = readl(base + MMCISTATUS); | |
361 | ||
64de0289 | 362 | dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); |
1da177e4 | 363 | |
4ce1d6cb RV |
364 | local_irq_save(flags); |
365 | ||
1da177e4 | 366 | do { |
1da177e4 LT |
367 | unsigned int remain, len; |
368 | char *buffer; | |
369 | ||
370 | /* | |
371 | * For write, we only need to test the half-empty flag | |
372 | * here - if the FIFO is completely empty, then by | |
373 | * definition it is more than half empty. | |
374 | * | |
375 | * For read, check for data available. | |
376 | */ | |
377 | if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) | |
378 | break; | |
379 | ||
4ce1d6cb RV |
380 | if (!sg_miter_next(sg_miter)) |
381 | break; | |
382 | ||
383 | buffer = sg_miter->addr; | |
384 | remain = sg_miter->length; | |
1da177e4 LT |
385 | |
386 | len = 0; | |
387 | if (status & MCI_RXACTIVE) | |
388 | len = mmci_pio_read(host, buffer, remain); | |
389 | if (status & MCI_TXACTIVE) | |
390 | len = mmci_pio_write(host, buffer, remain, status); | |
391 | ||
4ce1d6cb | 392 | sg_miter->consumed = len; |
1da177e4 | 393 | |
1da177e4 LT |
394 | host->size -= len; |
395 | remain -= len; | |
396 | ||
397 | if (remain) | |
398 | break; | |
399 | ||
e9c091b4 | 400 | if (status & MCI_RXACTIVE) |
4ce1d6cb | 401 | flush_dcache_page(sg_miter->page); |
1da177e4 LT |
402 | |
403 | status = readl(base + MMCISTATUS); | |
404 | } while (1); | |
405 | ||
4ce1d6cb RV |
406 | sg_miter_stop(sg_miter); |
407 | ||
408 | local_irq_restore(flags); | |
409 | ||
1da177e4 LT |
410 | /* |
411 | * If we're nearing the end of the read, switch to | |
412 | * "any data available" mode. | |
413 | */ | |
414 | if (status & MCI_RXACTIVE && host->size < MCI_FIFOSIZE) | |
415 | writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1); | |
416 | ||
417 | /* | |
418 | * If we run out of data, disable the data IRQs; this | |
419 | * prevents a race where the FIFO becomes empty before | |
420 | * the chip itself has disabled the data path, and | |
421 | * stops us racing with our data end IRQ. | |
422 | */ | |
423 | if (host->size == 0) { | |
424 | writel(0, base + MMCIMASK1); | |
425 | writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); | |
426 | } | |
427 | ||
428 | return IRQ_HANDLED; | |
429 | } | |
430 | ||
431 | /* | |
432 | * Handle completion of command and data transfers. | |
433 | */ | |
7d12e780 | 434 | static irqreturn_t mmci_irq(int irq, void *dev_id) |
1da177e4 LT |
435 | { |
436 | struct mmci_host *host = dev_id; | |
437 | u32 status; | |
438 | int ret = 0; | |
439 | ||
440 | spin_lock(&host->lock); | |
441 | ||
442 | do { | |
443 | struct mmc_command *cmd; | |
444 | struct mmc_data *data; | |
445 | ||
446 | status = readl(host->base + MMCISTATUS); | |
447 | status &= readl(host->base + MMCIMASK0); | |
448 | writel(status, host->base + MMCICLEAR); | |
449 | ||
64de0289 | 450 | dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); |
1da177e4 LT |
451 | |
452 | data = host->data; | |
453 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN| | |
454 | MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data) | |
455 | mmci_data_irq(host, data, status); | |
456 | ||
457 | cmd = host->cmd; | |
458 | if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) | |
459 | mmci_cmd_irq(host, cmd, status); | |
460 | ||
461 | ret = 1; | |
462 | } while (status); | |
463 | ||
464 | spin_unlock(&host->lock); | |
465 | ||
466 | return IRQ_RETVAL(ret); | |
467 | } | |
468 | ||
469 | static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
470 | { | |
471 | struct mmci_host *host = mmc_priv(mmc); | |
9e943021 | 472 | unsigned long flags; |
1da177e4 LT |
473 | |
474 | WARN_ON(host->mrq != NULL); | |
475 | ||
019a5f56 | 476 | if (mrq->data && !is_power_of_2(mrq->data->blksz)) { |
64de0289 LW |
477 | dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", |
478 | mrq->data->blksz); | |
255d01af PO |
479 | mrq->cmd->error = -EINVAL; |
480 | mmc_request_done(mmc, mrq); | |
481 | return; | |
482 | } | |
483 | ||
9e943021 | 484 | spin_lock_irqsave(&host->lock, flags); |
1da177e4 LT |
485 | |
486 | host->mrq = mrq; | |
487 | ||
488 | if (mrq->data && mrq->data->flags & MMC_DATA_READ) | |
489 | mmci_start_data(host, mrq->data); | |
490 | ||
491 | mmci_start_command(host, mrq->cmd, 0); | |
492 | ||
9e943021 | 493 | spin_unlock_irqrestore(&host->lock, flags); |
1da177e4 LT |
494 | } |
495 | ||
496 | static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
497 | { | |
498 | struct mmci_host *host = mmc_priv(mmc); | |
a6a6464a LW |
499 | u32 pwr = 0; |
500 | unsigned long flags; | |
1da177e4 | 501 | |
1da177e4 LT |
502 | switch (ios->power_mode) { |
503 | case MMC_POWER_OFF: | |
34e84f39 LW |
504 | if(host->vcc && |
505 | regulator_is_enabled(host->vcc)) | |
506 | regulator_disable(host->vcc); | |
1da177e4 LT |
507 | break; |
508 | case MMC_POWER_UP: | |
34e84f39 LW |
509 | #ifdef CONFIG_REGULATOR |
510 | if (host->vcc) | |
511 | /* This implicitly enables the regulator */ | |
512 | mmc_regulator_set_ocr(host->vcc, ios->vdd); | |
513 | #endif | |
bb8f563c RV |
514 | if (host->plat->vdd_handler) |
515 | pwr |= host->plat->vdd_handler(mmc_dev(mmc), ios->vdd, | |
516 | ios->power_mode); | |
cc30d60e | 517 | /* The ST version does not have this, fall through to POWER_ON */ |
f17a1f06 | 518 | if (host->hw_designer != AMBA_VENDOR_ST) { |
cc30d60e LW |
519 | pwr |= MCI_PWR_UP; |
520 | break; | |
521 | } | |
1da177e4 LT |
522 | case MMC_POWER_ON: |
523 | pwr |= MCI_PWR_ON; | |
524 | break; | |
525 | } | |
526 | ||
cc30d60e | 527 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { |
f17a1f06 | 528 | if (host->hw_designer != AMBA_VENDOR_ST) |
cc30d60e LW |
529 | pwr |= MCI_ROD; |
530 | else { | |
531 | /* | |
532 | * The ST Micro variant use the ROD bit for something | |
533 | * else and only has OD (Open Drain). | |
534 | */ | |
535 | pwr |= MCI_OD; | |
536 | } | |
537 | } | |
1da177e4 | 538 | |
a6a6464a LW |
539 | spin_lock_irqsave(&host->lock, flags); |
540 | ||
541 | mmci_set_clkreg(host, ios->clock); | |
1da177e4 LT |
542 | |
543 | if (host->pwr != pwr) { | |
544 | host->pwr = pwr; | |
545 | writel(pwr, host->base + MMCIPOWER); | |
546 | } | |
a6a6464a LW |
547 | |
548 | spin_unlock_irqrestore(&host->lock, flags); | |
1da177e4 LT |
549 | } |
550 | ||
89001446 RK |
551 | static int mmci_get_ro(struct mmc_host *mmc) |
552 | { | |
553 | struct mmci_host *host = mmc_priv(mmc); | |
554 | ||
555 | if (host->gpio_wp == -ENOSYS) | |
556 | return -ENOSYS; | |
557 | ||
558 | return gpio_get_value(host->gpio_wp); | |
559 | } | |
560 | ||
561 | static int mmci_get_cd(struct mmc_host *mmc) | |
562 | { | |
563 | struct mmci_host *host = mmc_priv(mmc); | |
564 | unsigned int status; | |
565 | ||
566 | if (host->gpio_cd == -ENOSYS) | |
567 | status = host->plat->status(mmc_dev(host->mmc)); | |
568 | else | |
569 | status = gpio_get_value(host->gpio_cd); | |
570 | ||
571 | return !status; | |
572 | } | |
573 | ||
ab7aefd0 | 574 | static const struct mmc_host_ops mmci_ops = { |
1da177e4 LT |
575 | .request = mmci_request, |
576 | .set_ios = mmci_set_ios, | |
89001446 RK |
577 | .get_ro = mmci_get_ro, |
578 | .get_cd = mmci_get_cd, | |
1da177e4 LT |
579 | }; |
580 | ||
03fbdb15 | 581 | static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) |
1da177e4 | 582 | { |
6ef297f8 | 583 | struct mmci_platform_data *plat = dev->dev.platform_data; |
4956e109 | 584 | struct variant_data *variant = id->data; |
1da177e4 LT |
585 | struct mmci_host *host; |
586 | struct mmc_host *mmc; | |
587 | int ret; | |
588 | ||
589 | /* must have platform data */ | |
590 | if (!plat) { | |
591 | ret = -EINVAL; | |
592 | goto out; | |
593 | } | |
594 | ||
595 | ret = amba_request_regions(dev, DRIVER_NAME); | |
596 | if (ret) | |
597 | goto out; | |
598 | ||
599 | mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); | |
600 | if (!mmc) { | |
601 | ret = -ENOMEM; | |
602 | goto rel_regions; | |
603 | } | |
604 | ||
605 | host = mmc_priv(mmc); | |
4ea580f1 | 606 | host->mmc = mmc; |
012b7d33 | 607 | |
89001446 RK |
608 | host->gpio_wp = -ENOSYS; |
609 | host->gpio_cd = -ENOSYS; | |
610 | ||
012b7d33 RK |
611 | host->hw_designer = amba_manf(dev); |
612 | host->hw_revision = amba_rev(dev); | |
64de0289 LW |
613 | dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); |
614 | dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); | |
012b7d33 | 615 | |
ee569c43 | 616 | host->clk = clk_get(&dev->dev, NULL); |
1da177e4 LT |
617 | if (IS_ERR(host->clk)) { |
618 | ret = PTR_ERR(host->clk); | |
619 | host->clk = NULL; | |
620 | goto host_free; | |
621 | } | |
622 | ||
1da177e4 LT |
623 | ret = clk_enable(host->clk); |
624 | if (ret) | |
a8d3584a | 625 | goto clk_free; |
1da177e4 LT |
626 | |
627 | host->plat = plat; | |
4956e109 | 628 | host->variant = variant; |
1da177e4 | 629 | host->mclk = clk_get_rate(host->clk); |
c8df9a53 LW |
630 | /* |
631 | * According to the spec, mclk is max 100 MHz, | |
632 | * so we try to adjust the clock down to this, | |
633 | * (if possible). | |
634 | */ | |
635 | if (host->mclk > 100000000) { | |
636 | ret = clk_set_rate(host->clk, 100000000); | |
637 | if (ret < 0) | |
638 | goto clk_disable; | |
639 | host->mclk = clk_get_rate(host->clk); | |
64de0289 LW |
640 | dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", |
641 | host->mclk); | |
c8df9a53 | 642 | } |
dc890c2d | 643 | host->base = ioremap(dev->res.start, resource_size(&dev->res)); |
1da177e4 LT |
644 | if (!host->base) { |
645 | ret = -ENOMEM; | |
646 | goto clk_disable; | |
647 | } | |
648 | ||
649 | mmc->ops = &mmci_ops; | |
650 | mmc->f_min = (host->mclk + 511) / 512; | |
808d97cc LW |
651 | /* |
652 | * If the platform data supplies a maximum operating | |
653 | * frequency, this takes precedence. Else, we fall back | |
654 | * to using the module parameter, which has a (low) | |
655 | * default value in case it is not specified. Either | |
656 | * value must not exceed the clock rate into the block, | |
657 | * of course. | |
658 | */ | |
659 | if (plat->f_max) | |
660 | mmc->f_max = min(host->mclk, plat->f_max); | |
661 | else | |
662 | mmc->f_max = min(host->mclk, fmax); | |
64de0289 LW |
663 | dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); |
664 | ||
34e84f39 LW |
665 | #ifdef CONFIG_REGULATOR |
666 | /* If we're using the regulator framework, try to fetch a regulator */ | |
667 | host->vcc = regulator_get(&dev->dev, "vmmc"); | |
668 | if (IS_ERR(host->vcc)) | |
669 | host->vcc = NULL; | |
670 | else { | |
671 | int mask = mmc_regulator_get_ocrmask(host->vcc); | |
672 | ||
673 | if (mask < 0) | |
674 | dev_err(&dev->dev, "error getting OCR mask (%d)\n", | |
675 | mask); | |
676 | else { | |
677 | host->mmc->ocr_avail = (u32) mask; | |
678 | if (plat->ocr_mask) | |
679 | dev_warn(&dev->dev, | |
680 | "Provided ocr_mask/setpower will not be used " | |
681 | "(using regulator instead)\n"); | |
682 | } | |
683 | } | |
684 | #endif | |
685 | /* Fall back to platform data if no regulator is found */ | |
686 | if (host->vcc == NULL) | |
687 | mmc->ocr_avail = plat->ocr_mask; | |
9e6c82cd | 688 | mmc->caps = plat->capabilities; |
f5e2574e | 689 | mmc->caps |= MMC_CAP_NEEDS_POLL; |
1da177e4 LT |
690 | |
691 | /* | |
692 | * We can do SGIO | |
693 | */ | |
694 | mmc->max_hw_segs = 16; | |
695 | mmc->max_phys_segs = NR_SG; | |
696 | ||
697 | /* | |
698 | * Since we only have a 16-bit data length register, we must | |
699 | * ensure that we don't exceed 2^16-1 bytes in a single request. | |
1da177e4 | 700 | */ |
55db890a | 701 | mmc->max_req_size = 65535; |
1da177e4 LT |
702 | |
703 | /* | |
704 | * Set the maximum segment size. Since we aren't doing DMA | |
705 | * (yet) we are only limited by the data length register. | |
706 | */ | |
55db890a | 707 | mmc->max_seg_size = mmc->max_req_size; |
1da177e4 | 708 | |
fe4a3c7a PO |
709 | /* |
710 | * Block size can be up to 2048 bytes, but must be a power of two. | |
711 | */ | |
712 | mmc->max_blk_size = 2048; | |
713 | ||
55db890a PO |
714 | /* |
715 | * No limit on the number of blocks transferred. | |
716 | */ | |
717 | mmc->max_blk_count = mmc->max_req_size; | |
718 | ||
1da177e4 LT |
719 | spin_lock_init(&host->lock); |
720 | ||
721 | writel(0, host->base + MMCIMASK0); | |
722 | writel(0, host->base + MMCIMASK1); | |
723 | writel(0xfff, host->base + MMCICLEAR); | |
724 | ||
89001446 RK |
725 | if (gpio_is_valid(plat->gpio_cd)) { |
726 | ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); | |
727 | if (ret == 0) | |
728 | ret = gpio_direction_input(plat->gpio_cd); | |
729 | if (ret == 0) | |
730 | host->gpio_cd = plat->gpio_cd; | |
731 | else if (ret != -ENOSYS) | |
732 | goto err_gpio_cd; | |
733 | } | |
734 | if (gpio_is_valid(plat->gpio_wp)) { | |
735 | ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); | |
736 | if (ret == 0) | |
737 | ret = gpio_direction_input(plat->gpio_wp); | |
738 | if (ret == 0) | |
739 | host->gpio_wp = plat->gpio_wp; | |
740 | else if (ret != -ENOSYS) | |
741 | goto err_gpio_wp; | |
742 | } | |
743 | ||
dace1453 | 744 | ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); |
1da177e4 LT |
745 | if (ret) |
746 | goto unmap; | |
747 | ||
dace1453 | 748 | ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, DRIVER_NAME " (pio)", host); |
1da177e4 LT |
749 | if (ret) |
750 | goto irq0_free; | |
751 | ||
752 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); | |
753 | ||
754 | amba_set_drvdata(dev, mmc); | |
755 | ||
756 | mmc_add_host(mmc); | |
757 | ||
64de0289 | 758 | dev_info(&dev->dev, "%s: MMCI rev %x cfg %02x at 0x%016llx irq %d,%d\n", |
d366b643 | 759 | mmc_hostname(mmc), amba_rev(dev), amba_config(dev), |
e29419ff | 760 | (unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]); |
1da177e4 | 761 | |
1da177e4 LT |
762 | return 0; |
763 | ||
764 | irq0_free: | |
765 | free_irq(dev->irq[0], host); | |
766 | unmap: | |
89001446 RK |
767 | if (host->gpio_wp != -ENOSYS) |
768 | gpio_free(host->gpio_wp); | |
769 | err_gpio_wp: | |
770 | if (host->gpio_cd != -ENOSYS) | |
771 | gpio_free(host->gpio_cd); | |
772 | err_gpio_cd: | |
1da177e4 LT |
773 | iounmap(host->base); |
774 | clk_disable: | |
775 | clk_disable(host->clk); | |
1da177e4 LT |
776 | clk_free: |
777 | clk_put(host->clk); | |
778 | host_free: | |
779 | mmc_free_host(mmc); | |
780 | rel_regions: | |
781 | amba_release_regions(dev); | |
782 | out: | |
783 | return ret; | |
784 | } | |
785 | ||
6dc4a47a | 786 | static int __devexit mmci_remove(struct amba_device *dev) |
1da177e4 LT |
787 | { |
788 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
789 | ||
790 | amba_set_drvdata(dev, NULL); | |
791 | ||
792 | if (mmc) { | |
793 | struct mmci_host *host = mmc_priv(mmc); | |
794 | ||
1da177e4 LT |
795 | mmc_remove_host(mmc); |
796 | ||
797 | writel(0, host->base + MMCIMASK0); | |
798 | writel(0, host->base + MMCIMASK1); | |
799 | ||
800 | writel(0, host->base + MMCICOMMAND); | |
801 | writel(0, host->base + MMCIDATACTRL); | |
802 | ||
803 | free_irq(dev->irq[0], host); | |
804 | free_irq(dev->irq[1], host); | |
805 | ||
89001446 RK |
806 | if (host->gpio_wp != -ENOSYS) |
807 | gpio_free(host->gpio_wp); | |
808 | if (host->gpio_cd != -ENOSYS) | |
809 | gpio_free(host->gpio_cd); | |
810 | ||
1da177e4 LT |
811 | iounmap(host->base); |
812 | clk_disable(host->clk); | |
1da177e4 LT |
813 | clk_put(host->clk); |
814 | ||
34e84f39 LW |
815 | if (regulator_is_enabled(host->vcc)) |
816 | regulator_disable(host->vcc); | |
817 | regulator_put(host->vcc); | |
818 | ||
1da177e4 LT |
819 | mmc_free_host(mmc); |
820 | ||
821 | amba_release_regions(dev); | |
822 | } | |
823 | ||
824 | return 0; | |
825 | } | |
826 | ||
827 | #ifdef CONFIG_PM | |
e5378ca8 | 828 | static int mmci_suspend(struct amba_device *dev, pm_message_t state) |
1da177e4 LT |
829 | { |
830 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
831 | int ret = 0; | |
832 | ||
833 | if (mmc) { | |
834 | struct mmci_host *host = mmc_priv(mmc); | |
835 | ||
1a13f8fa | 836 | ret = mmc_suspend_host(mmc); |
1da177e4 LT |
837 | if (ret == 0) |
838 | writel(0, host->base + MMCIMASK0); | |
839 | } | |
840 | ||
841 | return ret; | |
842 | } | |
843 | ||
844 | static int mmci_resume(struct amba_device *dev) | |
845 | { | |
846 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
847 | int ret = 0; | |
848 | ||
849 | if (mmc) { | |
850 | struct mmci_host *host = mmc_priv(mmc); | |
851 | ||
852 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); | |
853 | ||
854 | ret = mmc_resume_host(mmc); | |
855 | } | |
856 | ||
857 | return ret; | |
858 | } | |
859 | #else | |
860 | #define mmci_suspend NULL | |
861 | #define mmci_resume NULL | |
862 | #endif | |
863 | ||
864 | static struct amba_id mmci_ids[] = { | |
865 | { | |
866 | .id = 0x00041180, | |
867 | .mask = 0x000fffff, | |
4956e109 | 868 | .data = &variant_arm, |
1da177e4 LT |
869 | }, |
870 | { | |
871 | .id = 0x00041181, | |
872 | .mask = 0x000fffff, | |
4956e109 | 873 | .data = &variant_arm, |
1da177e4 | 874 | }, |
cc30d60e LW |
875 | /* ST Micro variants */ |
876 | { | |
877 | .id = 0x00180180, | |
878 | .mask = 0x00ffffff, | |
4956e109 | 879 | .data = &variant_u300, |
cc30d60e LW |
880 | }, |
881 | { | |
882 | .id = 0x00280180, | |
883 | .mask = 0x00ffffff, | |
4956e109 RV |
884 | .data = &variant_u300, |
885 | }, | |
886 | { | |
887 | .id = 0x00480180, | |
888 | .mask = 0x00ffffff, | |
889 | .data = &variant_ux500, | |
cc30d60e | 890 | }, |
1da177e4 LT |
891 | { 0, 0 }, |
892 | }; | |
893 | ||
894 | static struct amba_driver mmci_driver = { | |
895 | .drv = { | |
896 | .name = DRIVER_NAME, | |
897 | }, | |
898 | .probe = mmci_probe, | |
6dc4a47a | 899 | .remove = __devexit_p(mmci_remove), |
1da177e4 LT |
900 | .suspend = mmci_suspend, |
901 | .resume = mmci_resume, | |
902 | .id_table = mmci_ids, | |
903 | }; | |
904 | ||
905 | static int __init mmci_init(void) | |
906 | { | |
907 | return amba_driver_register(&mmci_driver); | |
908 | } | |
909 | ||
910 | static void __exit mmci_exit(void) | |
911 | { | |
912 | amba_driver_unregister(&mmci_driver); | |
913 | } | |
914 | ||
915 | module_init(mmci_init); | |
916 | module_exit(mmci_exit); | |
917 | module_param(fmax, uint, 0444); | |
918 | ||
919 | MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); | |
920 | MODULE_LICENSE("GPL"); |