Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. | |
c8ebae37 | 5 | * Copyright (C) 2010 ST-Ericsson SA |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/interrupt.h> | |
613b152c | 17 | #include <linux/kernel.h> |
000bc9d5 | 18 | #include <linux/slab.h> |
1da177e4 LT |
19 | #include <linux/delay.h> |
20 | #include <linux/err.h> | |
21 | #include <linux/highmem.h> | |
019a5f56 | 22 | #include <linux/log2.h> |
1da177e4 | 23 | #include <linux/mmc/host.h> |
34177802 | 24 | #include <linux/mmc/card.h> |
a62c80e5 | 25 | #include <linux/amba/bus.h> |
f8ce2547 | 26 | #include <linux/clk.h> |
bd6dee6f | 27 | #include <linux/scatterlist.h> |
89001446 | 28 | #include <linux/gpio.h> |
9a597016 | 29 | #include <linux/of_gpio.h> |
34e84f39 | 30 | #include <linux/regulator/consumer.h> |
c8ebae37 RK |
31 | #include <linux/dmaengine.h> |
32 | #include <linux/dma-mapping.h> | |
33 | #include <linux/amba/mmci.h> | |
1c3be369 | 34 | #include <linux/pm_runtime.h> |
258aea76 | 35 | #include <linux/types.h> |
1da177e4 | 36 | |
7b09cdac | 37 | #include <asm/div64.h> |
1da177e4 | 38 | #include <asm/io.h> |
c6b8fdad | 39 | #include <asm/sizes.h> |
1da177e4 LT |
40 | |
41 | #include "mmci.h" | |
42 | ||
43 | #define DRIVER_NAME "mmci-pl18x" | |
44 | ||
1da177e4 LT |
45 | static unsigned int fmax = 515633; |
46 | ||
4956e109 RV |
47 | /** |
48 | * struct variant_data - MMCI variant-specific quirks | |
49 | * @clkreg: default value for MCICLOCK register | |
4380c14f | 50 | * @clkreg_enable: enable value for MMCICLOCK register |
08458ef6 | 51 | * @datalength_bits: number of bits in the MMCIDATALENGTH register |
8301bb68 RV |
52 | * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY |
53 | * is asserted (likewise for RX) | |
54 | * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY | |
55 | * is asserted (likewise for RX) | |
34177802 | 56 | * @sdio: variant supports SDIO |
b70a67f9 | 57 | * @st_clkdiv: true if using a ST-specific clock divider algorithm |
1784b157 | 58 | * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register |
7d72a1d4 | 59 | * @pwrreg_powerup: power up value for MMCIPOWER register |
4d1a3a0d | 60 | * @signal_direction: input/out direction of bus signals can be indicated |
4956e109 RV |
61 | */ |
62 | struct variant_data { | |
63 | unsigned int clkreg; | |
4380c14f | 64 | unsigned int clkreg_enable; |
08458ef6 | 65 | unsigned int datalength_bits; |
8301bb68 RV |
66 | unsigned int fifosize; |
67 | unsigned int fifohalfsize; | |
34177802 | 68 | bool sdio; |
b70a67f9 | 69 | bool st_clkdiv; |
1784b157 | 70 | bool blksz_datactrl16; |
7d72a1d4 | 71 | u32 pwrreg_powerup; |
4d1a3a0d | 72 | bool signal_direction; |
4956e109 RV |
73 | }; |
74 | ||
75 | static struct variant_data variant_arm = { | |
8301bb68 RV |
76 | .fifosize = 16 * 4, |
77 | .fifohalfsize = 8 * 4, | |
08458ef6 | 78 | .datalength_bits = 16, |
7d72a1d4 | 79 | .pwrreg_powerup = MCI_PWR_UP, |
4956e109 RV |
80 | }; |
81 | ||
768fbc18 PM |
82 | static struct variant_data variant_arm_extended_fifo = { |
83 | .fifosize = 128 * 4, | |
84 | .fifohalfsize = 64 * 4, | |
85 | .datalength_bits = 16, | |
7d72a1d4 | 86 | .pwrreg_powerup = MCI_PWR_UP, |
768fbc18 PM |
87 | }; |
88 | ||
4956e109 | 89 | static struct variant_data variant_u300 = { |
8301bb68 RV |
90 | .fifosize = 16 * 4, |
91 | .fifohalfsize = 8 * 4, | |
49ac215e | 92 | .clkreg_enable = MCI_ST_U300_HWFCEN, |
08458ef6 | 93 | .datalength_bits = 16, |
34177802 | 94 | .sdio = true, |
7d72a1d4 | 95 | .pwrreg_powerup = MCI_PWR_ON, |
4d1a3a0d | 96 | .signal_direction = true, |
4956e109 RV |
97 | }; |
98 | ||
34fd4213 LW |
99 | static struct variant_data variant_nomadik = { |
100 | .fifosize = 16 * 4, | |
101 | .fifohalfsize = 8 * 4, | |
102 | .clkreg = MCI_CLK_ENABLE, | |
103 | .datalength_bits = 24, | |
104 | .sdio = true, | |
105 | .st_clkdiv = true, | |
106 | .pwrreg_powerup = MCI_PWR_ON, | |
107 | .signal_direction = true, | |
108 | }; | |
109 | ||
4956e109 | 110 | static struct variant_data variant_ux500 = { |
8301bb68 RV |
111 | .fifosize = 30 * 4, |
112 | .fifohalfsize = 8 * 4, | |
4956e109 | 113 | .clkreg = MCI_CLK_ENABLE, |
49ac215e | 114 | .clkreg_enable = MCI_ST_UX500_HWFCEN, |
08458ef6 | 115 | .datalength_bits = 24, |
34177802 | 116 | .sdio = true, |
b70a67f9 | 117 | .st_clkdiv = true, |
7d72a1d4 | 118 | .pwrreg_powerup = MCI_PWR_ON, |
4d1a3a0d | 119 | .signal_direction = true, |
4956e109 | 120 | }; |
b70a67f9 | 121 | |
1784b157 PL |
122 | static struct variant_data variant_ux500v2 = { |
123 | .fifosize = 30 * 4, | |
124 | .fifohalfsize = 8 * 4, | |
125 | .clkreg = MCI_CLK_ENABLE, | |
126 | .clkreg_enable = MCI_ST_UX500_HWFCEN, | |
127 | .datalength_bits = 24, | |
128 | .sdio = true, | |
129 | .st_clkdiv = true, | |
130 | .blksz_datactrl16 = true, | |
7d72a1d4 | 131 | .pwrreg_powerup = MCI_PWR_ON, |
4d1a3a0d | 132 | .signal_direction = true, |
1784b157 PL |
133 | }; |
134 | ||
7437cfa5 UH |
135 | /* |
136 | * This must be called with host->lock held | |
137 | */ | |
138 | static void mmci_write_clkreg(struct mmci_host *host, u32 clk) | |
139 | { | |
140 | if (host->clk_reg != clk) { | |
141 | host->clk_reg = clk; | |
142 | writel(clk, host->base + MMCICLOCK); | |
143 | } | |
144 | } | |
145 | ||
146 | /* | |
147 | * This must be called with host->lock held | |
148 | */ | |
149 | static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) | |
150 | { | |
151 | if (host->pwr_reg != pwr) { | |
152 | host->pwr_reg = pwr; | |
153 | writel(pwr, host->base + MMCIPOWER); | |
154 | } | |
155 | } | |
156 | ||
a6a6464a LW |
157 | /* |
158 | * This must be called with host->lock held | |
159 | */ | |
160 | static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) | |
161 | { | |
4956e109 RV |
162 | struct variant_data *variant = host->variant; |
163 | u32 clk = variant->clkreg; | |
a6a6464a LW |
164 | |
165 | if (desired) { | |
166 | if (desired >= host->mclk) { | |
991a86e1 | 167 | clk = MCI_CLK_BYPASS; |
399bc486 LW |
168 | if (variant->st_clkdiv) |
169 | clk |= MCI_ST_UX500_NEG_EDGE; | |
a6a6464a | 170 | host->cclk = host->mclk; |
b70a67f9 LW |
171 | } else if (variant->st_clkdiv) { |
172 | /* | |
173 | * DB8500 TRM says f = mclk / (clkdiv + 2) | |
174 | * => clkdiv = (mclk / f) - 2 | |
175 | * Round the divider up so we don't exceed the max | |
176 | * frequency | |
177 | */ | |
178 | clk = DIV_ROUND_UP(host->mclk, desired) - 2; | |
179 | if (clk >= 256) | |
180 | clk = 255; | |
181 | host->cclk = host->mclk / (clk + 2); | |
a6a6464a | 182 | } else { |
b70a67f9 LW |
183 | /* |
184 | * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) | |
185 | * => clkdiv = mclk / (2 * f) - 1 | |
186 | */ | |
a6a6464a LW |
187 | clk = host->mclk / (2 * desired) - 1; |
188 | if (clk >= 256) | |
189 | clk = 255; | |
190 | host->cclk = host->mclk / (2 * (clk + 1)); | |
191 | } | |
4380c14f RV |
192 | |
193 | clk |= variant->clkreg_enable; | |
a6a6464a LW |
194 | clk |= MCI_CLK_ENABLE; |
195 | /* This hasn't proven to be worthwhile */ | |
196 | /* clk |= MCI_CLK_PWRSAVE; */ | |
197 | } | |
198 | ||
9e6c82cd | 199 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) |
771dc157 LW |
200 | clk |= MCI_4BIT_BUS; |
201 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) | |
202 | clk |= MCI_ST_8BIT_BUS; | |
9e6c82cd | 203 | |
7437cfa5 | 204 | mmci_write_clkreg(host, clk); |
a6a6464a LW |
205 | } |
206 | ||
1da177e4 LT |
207 | static void |
208 | mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) | |
209 | { | |
210 | writel(0, host->base + MMCICOMMAND); | |
211 | ||
e47c222b RK |
212 | BUG_ON(host->data); |
213 | ||
1da177e4 LT |
214 | host->mrq = NULL; |
215 | host->cmd = NULL; | |
216 | ||
1da177e4 | 217 | mmc_request_done(host->mmc, mrq); |
2cd976c4 UH |
218 | |
219 | pm_runtime_mark_last_busy(mmc_dev(host->mmc)); | |
220 | pm_runtime_put_autosuspend(mmc_dev(host->mmc)); | |
1da177e4 LT |
221 | } |
222 | ||
2686b4b4 LW |
223 | static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) |
224 | { | |
225 | void __iomem *base = host->base; | |
226 | ||
227 | if (host->singleirq) { | |
228 | unsigned int mask0 = readl(base + MMCIMASK0); | |
229 | ||
230 | mask0 &= ~MCI_IRQ1MASK; | |
231 | mask0 |= mask; | |
232 | ||
233 | writel(mask0, base + MMCIMASK0); | |
234 | } | |
235 | ||
236 | writel(mask, base + MMCIMASK1); | |
237 | } | |
238 | ||
1da177e4 LT |
239 | static void mmci_stop_data(struct mmci_host *host) |
240 | { | |
241 | writel(0, host->base + MMCIDATACTRL); | |
2686b4b4 | 242 | mmci_set_mask1(host, 0); |
1da177e4 LT |
243 | host->data = NULL; |
244 | } | |
245 | ||
4ce1d6cb RV |
246 | static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) |
247 | { | |
248 | unsigned int flags = SG_MITER_ATOMIC; | |
249 | ||
250 | if (data->flags & MMC_DATA_READ) | |
251 | flags |= SG_MITER_TO_SG; | |
252 | else | |
253 | flags |= SG_MITER_FROM_SG; | |
254 | ||
255 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); | |
256 | } | |
257 | ||
c8ebae37 RK |
258 | /* |
259 | * All the DMA operation mode stuff goes inside this ifdef. | |
260 | * This assumes that you have a generic DMA device interface, | |
261 | * no custom DMA interfaces are supported. | |
262 | */ | |
263 | #ifdef CONFIG_DMA_ENGINE | |
264 | static void __devinit mmci_dma_setup(struct mmci_host *host) | |
265 | { | |
266 | struct mmci_platform_data *plat = host->plat; | |
267 | const char *rxname, *txname; | |
268 | dma_cap_mask_t mask; | |
269 | ||
270 | if (!plat || !plat->dma_filter) { | |
271 | dev_info(mmc_dev(host->mmc), "no DMA platform data\n"); | |
272 | return; | |
273 | } | |
274 | ||
58c7ccbf PF |
275 | /* initialize pre request cookie */ |
276 | host->next_data.cookie = 1; | |
277 | ||
c8ebae37 RK |
278 | /* Try to acquire a generic DMA engine slave channel */ |
279 | dma_cap_zero(mask); | |
280 | dma_cap_set(DMA_SLAVE, mask); | |
281 | ||
282 | /* | |
283 | * If only an RX channel is specified, the driver will | |
284 | * attempt to use it bidirectionally, however if it is | |
285 | * is specified but cannot be located, DMA will be disabled. | |
286 | */ | |
287 | if (plat->dma_rx_param) { | |
288 | host->dma_rx_channel = dma_request_channel(mask, | |
289 | plat->dma_filter, | |
290 | plat->dma_rx_param); | |
291 | /* E.g if no DMA hardware is present */ | |
292 | if (!host->dma_rx_channel) | |
293 | dev_err(mmc_dev(host->mmc), "no RX DMA channel\n"); | |
294 | } | |
295 | ||
296 | if (plat->dma_tx_param) { | |
297 | host->dma_tx_channel = dma_request_channel(mask, | |
298 | plat->dma_filter, | |
299 | plat->dma_tx_param); | |
300 | if (!host->dma_tx_channel) | |
301 | dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n"); | |
302 | } else { | |
303 | host->dma_tx_channel = host->dma_rx_channel; | |
304 | } | |
305 | ||
306 | if (host->dma_rx_channel) | |
307 | rxname = dma_chan_name(host->dma_rx_channel); | |
308 | else | |
309 | rxname = "none"; | |
310 | ||
311 | if (host->dma_tx_channel) | |
312 | txname = dma_chan_name(host->dma_tx_channel); | |
313 | else | |
314 | txname = "none"; | |
315 | ||
316 | dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", | |
317 | rxname, txname); | |
318 | ||
319 | /* | |
320 | * Limit the maximum segment size in any SG entry according to | |
321 | * the parameters of the DMA engine device. | |
322 | */ | |
323 | if (host->dma_tx_channel) { | |
324 | struct device *dev = host->dma_tx_channel->device->dev; | |
325 | unsigned int max_seg_size = dma_get_max_seg_size(dev); | |
326 | ||
327 | if (max_seg_size < host->mmc->max_seg_size) | |
328 | host->mmc->max_seg_size = max_seg_size; | |
329 | } | |
330 | if (host->dma_rx_channel) { | |
331 | struct device *dev = host->dma_rx_channel->device->dev; | |
332 | unsigned int max_seg_size = dma_get_max_seg_size(dev); | |
333 | ||
334 | if (max_seg_size < host->mmc->max_seg_size) | |
335 | host->mmc->max_seg_size = max_seg_size; | |
336 | } | |
337 | } | |
338 | ||
339 | /* | |
340 | * This is used in __devinit or __devexit so inline it | |
341 | * so it can be discarded. | |
342 | */ | |
343 | static inline void mmci_dma_release(struct mmci_host *host) | |
344 | { | |
345 | struct mmci_platform_data *plat = host->plat; | |
346 | ||
347 | if (host->dma_rx_channel) | |
348 | dma_release_channel(host->dma_rx_channel); | |
349 | if (host->dma_tx_channel && plat->dma_tx_param) | |
350 | dma_release_channel(host->dma_tx_channel); | |
351 | host->dma_rx_channel = host->dma_tx_channel = NULL; | |
352 | } | |
353 | ||
354 | static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) | |
355 | { | |
356 | struct dma_chan *chan = host->dma_current; | |
357 | enum dma_data_direction dir; | |
358 | u32 status; | |
359 | int i; | |
360 | ||
361 | /* Wait up to 1ms for the DMA to complete */ | |
362 | for (i = 0; ; i++) { | |
363 | status = readl(host->base + MMCISTATUS); | |
364 | if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) | |
365 | break; | |
366 | udelay(10); | |
367 | } | |
368 | ||
369 | /* | |
370 | * Check to see whether we still have some data left in the FIFO - | |
371 | * this catches DMA controllers which are unable to monitor the | |
372 | * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- | |
373 | * contiguous buffers. On TX, we'll get a FIFO underrun error. | |
374 | */ | |
375 | if (status & MCI_RXDATAAVLBLMASK) { | |
376 | dmaengine_terminate_all(chan); | |
377 | if (!data->error) | |
378 | data->error = -EIO; | |
379 | } | |
380 | ||
381 | if (data->flags & MMC_DATA_WRITE) { | |
382 | dir = DMA_TO_DEVICE; | |
383 | } else { | |
384 | dir = DMA_FROM_DEVICE; | |
385 | } | |
386 | ||
58c7ccbf PF |
387 | if (!data->host_cookie) |
388 | dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); | |
c8ebae37 RK |
389 | |
390 | /* | |
391 | * Use of DMA with scatter-gather is impossible. | |
392 | * Give up with DMA and switch back to PIO mode. | |
393 | */ | |
394 | if (status & MCI_RXDATAAVLBLMASK) { | |
395 | dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); | |
396 | mmci_dma_release(host); | |
397 | } | |
398 | } | |
399 | ||
400 | static void mmci_dma_data_error(struct mmci_host *host) | |
401 | { | |
402 | dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); | |
403 | dmaengine_terminate_all(host->dma_current); | |
404 | } | |
405 | ||
58c7ccbf PF |
406 | static int mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, |
407 | struct mmci_host_next *next) | |
c8ebae37 RK |
408 | { |
409 | struct variant_data *variant = host->variant; | |
410 | struct dma_slave_config conf = { | |
411 | .src_addr = host->phybase + MMCIFIFO, | |
412 | .dst_addr = host->phybase + MMCIFIFO, | |
413 | .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
414 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
415 | .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ | |
416 | .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ | |
258aea76 | 417 | .device_fc = false, |
c8ebae37 | 418 | }; |
c8ebae37 RK |
419 | struct dma_chan *chan; |
420 | struct dma_device *device; | |
421 | struct dma_async_tx_descriptor *desc; | |
05f5799c | 422 | enum dma_data_direction buffer_dirn; |
c8ebae37 RK |
423 | int nr_sg; |
424 | ||
58c7ccbf PF |
425 | /* Check if next job is already prepared */ |
426 | if (data->host_cookie && !next && | |
427 | host->dma_current && host->dma_desc_current) | |
428 | return 0; | |
429 | ||
430 | if (!next) { | |
431 | host->dma_current = NULL; | |
432 | host->dma_desc_current = NULL; | |
433 | } | |
c8ebae37 RK |
434 | |
435 | if (data->flags & MMC_DATA_READ) { | |
05f5799c VK |
436 | conf.direction = DMA_DEV_TO_MEM; |
437 | buffer_dirn = DMA_FROM_DEVICE; | |
c8ebae37 RK |
438 | chan = host->dma_rx_channel; |
439 | } else { | |
05f5799c VK |
440 | conf.direction = DMA_MEM_TO_DEV; |
441 | buffer_dirn = DMA_TO_DEVICE; | |
c8ebae37 RK |
442 | chan = host->dma_tx_channel; |
443 | } | |
444 | ||
445 | /* If there's no DMA channel, fall back to PIO */ | |
446 | if (!chan) | |
447 | return -EINVAL; | |
448 | ||
449 | /* If less than or equal to the fifo size, don't bother with DMA */ | |
58c7ccbf | 450 | if (data->blksz * data->blocks <= variant->fifosize) |
c8ebae37 RK |
451 | return -EINVAL; |
452 | ||
453 | device = chan->device; | |
05f5799c | 454 | nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); |
c8ebae37 RK |
455 | if (nr_sg == 0) |
456 | return -EINVAL; | |
457 | ||
458 | dmaengine_slave_config(chan, &conf); | |
16052827 | 459 | desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, |
c8ebae37 RK |
460 | conf.direction, DMA_CTRL_ACK); |
461 | if (!desc) | |
462 | goto unmap_exit; | |
463 | ||
58c7ccbf PF |
464 | if (next) { |
465 | next->dma_chan = chan; | |
466 | next->dma_desc = desc; | |
467 | } else { | |
468 | host->dma_current = chan; | |
469 | host->dma_desc_current = desc; | |
470 | } | |
471 | ||
472 | return 0; | |
c8ebae37 | 473 | |
58c7ccbf PF |
474 | unmap_exit: |
475 | if (!next) | |
476 | dmaengine_terminate_all(chan); | |
05f5799c | 477 | dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); |
58c7ccbf PF |
478 | return -ENOMEM; |
479 | } | |
480 | ||
481 | static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) | |
482 | { | |
483 | int ret; | |
484 | struct mmc_data *data = host->data; | |
485 | ||
486 | ret = mmci_dma_prep_data(host, host->data, NULL); | |
487 | if (ret) | |
488 | return ret; | |
489 | ||
490 | /* Okay, go for it. */ | |
c8ebae37 RK |
491 | dev_vdbg(mmc_dev(host->mmc), |
492 | "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", | |
493 | data->sg_len, data->blksz, data->blocks, data->flags); | |
58c7ccbf PF |
494 | dmaengine_submit(host->dma_desc_current); |
495 | dma_async_issue_pending(host->dma_current); | |
c8ebae37 RK |
496 | |
497 | datactrl |= MCI_DPSM_DMAENABLE; | |
498 | ||
499 | /* Trigger the DMA transfer */ | |
500 | writel(datactrl, host->base + MMCIDATACTRL); | |
501 | ||
502 | /* | |
503 | * Let the MMCI say when the data is ended and it's time | |
504 | * to fire next DMA request. When that happens, MMCI will | |
505 | * call mmci_data_end() | |
506 | */ | |
507 | writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, | |
508 | host->base + MMCIMASK0); | |
509 | return 0; | |
58c7ccbf | 510 | } |
c8ebae37 | 511 | |
58c7ccbf PF |
512 | static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) |
513 | { | |
514 | struct mmci_host_next *next = &host->next_data; | |
515 | ||
516 | if (data->host_cookie && data->host_cookie != next->cookie) { | |
a3c76eb9 | 517 | pr_warning("[%s] invalid cookie: data->host_cookie %d" |
58c7ccbf PF |
518 | " host->next_data.cookie %d\n", |
519 | __func__, data->host_cookie, host->next_data.cookie); | |
520 | data->host_cookie = 0; | |
521 | } | |
522 | ||
523 | if (!data->host_cookie) | |
524 | return; | |
525 | ||
526 | host->dma_desc_current = next->dma_desc; | |
527 | host->dma_current = next->dma_chan; | |
528 | ||
529 | next->dma_desc = NULL; | |
530 | next->dma_chan = NULL; | |
c8ebae37 | 531 | } |
58c7ccbf PF |
532 | |
533 | static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, | |
534 | bool is_first_req) | |
535 | { | |
536 | struct mmci_host *host = mmc_priv(mmc); | |
537 | struct mmc_data *data = mrq->data; | |
538 | struct mmci_host_next *nd = &host->next_data; | |
539 | ||
540 | if (!data) | |
541 | return; | |
542 | ||
543 | if (data->host_cookie) { | |
544 | data->host_cookie = 0; | |
545 | return; | |
546 | } | |
547 | ||
548 | /* if config for dma */ | |
549 | if (((data->flags & MMC_DATA_WRITE) && host->dma_tx_channel) || | |
550 | ((data->flags & MMC_DATA_READ) && host->dma_rx_channel)) { | |
551 | if (mmci_dma_prep_data(host, data, nd)) | |
552 | data->host_cookie = 0; | |
553 | else | |
554 | data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; | |
555 | } | |
556 | } | |
557 | ||
558 | static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, | |
559 | int err) | |
560 | { | |
561 | struct mmci_host *host = mmc_priv(mmc); | |
562 | struct mmc_data *data = mrq->data; | |
563 | struct dma_chan *chan; | |
564 | enum dma_data_direction dir; | |
565 | ||
566 | if (!data) | |
567 | return; | |
568 | ||
569 | if (data->flags & MMC_DATA_READ) { | |
570 | dir = DMA_FROM_DEVICE; | |
571 | chan = host->dma_rx_channel; | |
572 | } else { | |
573 | dir = DMA_TO_DEVICE; | |
574 | chan = host->dma_tx_channel; | |
575 | } | |
576 | ||
577 | ||
578 | /* if config for dma */ | |
579 | if (chan) { | |
580 | if (err) | |
581 | dmaengine_terminate_all(chan); | |
8e3336b1 | 582 | if (data->host_cookie) |
58c7ccbf PF |
583 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, |
584 | data->sg_len, dir); | |
585 | mrq->data->host_cookie = 0; | |
586 | } | |
587 | } | |
588 | ||
c8ebae37 RK |
589 | #else |
590 | /* Blank functions if the DMA engine is not available */ | |
58c7ccbf PF |
591 | static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) |
592 | { | |
593 | } | |
c8ebae37 RK |
594 | static inline void mmci_dma_setup(struct mmci_host *host) |
595 | { | |
596 | } | |
597 | ||
598 | static inline void mmci_dma_release(struct mmci_host *host) | |
599 | { | |
600 | } | |
601 | ||
602 | static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) | |
603 | { | |
604 | } | |
605 | ||
606 | static inline void mmci_dma_data_error(struct mmci_host *host) | |
607 | { | |
608 | } | |
609 | ||
610 | static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) | |
611 | { | |
612 | return -ENOSYS; | |
613 | } | |
58c7ccbf PF |
614 | |
615 | #define mmci_pre_request NULL | |
616 | #define mmci_post_request NULL | |
617 | ||
c8ebae37 RK |
618 | #endif |
619 | ||
1da177e4 LT |
620 | static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) |
621 | { | |
8301bb68 | 622 | struct variant_data *variant = host->variant; |
1da177e4 | 623 | unsigned int datactrl, timeout, irqmask; |
7b09cdac | 624 | unsigned long long clks; |
1da177e4 | 625 | void __iomem *base; |
3bc87f24 | 626 | int blksz_bits; |
1da177e4 | 627 | |
64de0289 LW |
628 | dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", |
629 | data->blksz, data->blocks, data->flags); | |
1da177e4 LT |
630 | |
631 | host->data = data; | |
528320db | 632 | host->size = data->blksz * data->blocks; |
51d4375d | 633 | data->bytes_xfered = 0; |
1da177e4 | 634 | |
7b09cdac RK |
635 | clks = (unsigned long long)data->timeout_ns * host->cclk; |
636 | do_div(clks, 1000000000UL); | |
637 | ||
638 | timeout = data->timeout_clks + (unsigned int)clks; | |
1da177e4 LT |
639 | |
640 | base = host->base; | |
641 | writel(timeout, base + MMCIDATATIMER); | |
642 | writel(host->size, base + MMCIDATALENGTH); | |
643 | ||
3bc87f24 RK |
644 | blksz_bits = ffs(data->blksz) - 1; |
645 | BUG_ON(1 << blksz_bits != data->blksz); | |
646 | ||
1784b157 PL |
647 | if (variant->blksz_datactrl16) |
648 | datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); | |
649 | else | |
650 | datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; | |
c8ebae37 RK |
651 | |
652 | if (data->flags & MMC_DATA_READ) | |
1da177e4 | 653 | datactrl |= MCI_DPSM_DIRECTION; |
c8ebae37 | 654 | |
7258db7e UH |
655 | /* The ST Micro variants has a special bit to enable SDIO */ |
656 | if (variant->sdio && host->mmc->card) | |
657 | if (mmc_card_sdio(host->mmc->card)) | |
658 | datactrl |= MCI_ST_DPSM_SDIOEN; | |
659 | ||
c8ebae37 RK |
660 | /* |
661 | * Attempt to use DMA operation mode, if this | |
662 | * should fail, fall back to PIO mode | |
663 | */ | |
664 | if (!mmci_dma_start_data(host, datactrl)) | |
665 | return; | |
666 | ||
667 | /* IRQ mode, map the SG list for CPU reading/writing */ | |
668 | mmci_init_sg(host, data); | |
669 | ||
670 | if (data->flags & MMC_DATA_READ) { | |
1da177e4 | 671 | irqmask = MCI_RXFIFOHALFFULLMASK; |
0425a142 RK |
672 | |
673 | /* | |
c4d877c1 RK |
674 | * If we have less than the fifo 'half-full' threshold to |
675 | * transfer, trigger a PIO interrupt as soon as any data | |
676 | * is available. | |
0425a142 | 677 | */ |
c4d877c1 | 678 | if (host->size < variant->fifohalfsize) |
0425a142 | 679 | irqmask |= MCI_RXDATAAVLBLMASK; |
1da177e4 LT |
680 | } else { |
681 | /* | |
682 | * We don't actually need to include "FIFO empty" here | |
683 | * since its implicit in "FIFO half empty". | |
684 | */ | |
685 | irqmask = MCI_TXFIFOHALFEMPTYMASK; | |
686 | } | |
687 | ||
688 | writel(datactrl, base + MMCIDATACTRL); | |
689 | writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); | |
2686b4b4 | 690 | mmci_set_mask1(host, irqmask); |
1da177e4 LT |
691 | } |
692 | ||
693 | static void | |
694 | mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) | |
695 | { | |
696 | void __iomem *base = host->base; | |
697 | ||
64de0289 | 698 | dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", |
1da177e4 LT |
699 | cmd->opcode, cmd->arg, cmd->flags); |
700 | ||
701 | if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { | |
702 | writel(0, base + MMCICOMMAND); | |
703 | udelay(1); | |
704 | } | |
705 | ||
706 | c |= cmd->opcode | MCI_CPSM_ENABLE; | |
e9225176 RK |
707 | if (cmd->flags & MMC_RSP_PRESENT) { |
708 | if (cmd->flags & MMC_RSP_136) | |
709 | c |= MCI_CPSM_LONGRSP; | |
1da177e4 | 710 | c |= MCI_CPSM_RESPONSE; |
1da177e4 LT |
711 | } |
712 | if (/*interrupt*/0) | |
713 | c |= MCI_CPSM_INTERRUPT; | |
714 | ||
715 | host->cmd = cmd; | |
716 | ||
717 | writel(cmd->arg, base + MMCIARGUMENT); | |
718 | writel(c, base + MMCICOMMAND); | |
719 | } | |
720 | ||
721 | static void | |
722 | mmci_data_irq(struct mmci_host *host, struct mmc_data *data, | |
723 | unsigned int status) | |
724 | { | |
f20f8f21 | 725 | /* First check for errors */ |
b63038d6 UH |
726 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| |
727 | MCI_TXUNDERRUN|MCI_RXOVERRUN)) { | |
8cb28155 | 728 | u32 remain, success; |
f20f8f21 | 729 | |
c8ebae37 RK |
730 | /* Terminate the DMA transfer */ |
731 | if (dma_inprogress(host)) | |
732 | mmci_dma_data_error(host); | |
e9c091b4 RK |
733 | |
734 | /* | |
c8afc9d5 RK |
735 | * Calculate how far we are into the transfer. Note that |
736 | * the data counter gives the number of bytes transferred | |
737 | * on the MMC bus, not on the host side. On reads, this | |
738 | * can be as much as a FIFO-worth of data ahead. This | |
739 | * matters for FIFO overruns only. | |
e9c091b4 | 740 | */ |
f5a106d9 | 741 | remain = readl(host->base + MMCIDATACNT); |
8cb28155 LW |
742 | success = data->blksz * data->blocks - remain; |
743 | ||
c8afc9d5 RK |
744 | dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", |
745 | status, success); | |
8cb28155 LW |
746 | if (status & MCI_DATACRCFAIL) { |
747 | /* Last block was not successful */ | |
c8afc9d5 | 748 | success -= 1; |
17b0429d | 749 | data->error = -EILSEQ; |
8cb28155 | 750 | } else if (status & MCI_DATATIMEOUT) { |
17b0429d | 751 | data->error = -ETIMEDOUT; |
757df746 LW |
752 | } else if (status & MCI_STARTBITERR) { |
753 | data->error = -ECOMM; | |
c8afc9d5 RK |
754 | } else if (status & MCI_TXUNDERRUN) { |
755 | data->error = -EIO; | |
756 | } else if (status & MCI_RXOVERRUN) { | |
757 | if (success > host->variant->fifosize) | |
758 | success -= host->variant->fifosize; | |
759 | else | |
760 | success = 0; | |
17b0429d | 761 | data->error = -EIO; |
4ce1d6cb | 762 | } |
51d4375d | 763 | data->bytes_xfered = round_down(success, data->blksz); |
1da177e4 | 764 | } |
f20f8f21 | 765 | |
8cb28155 LW |
766 | if (status & MCI_DATABLOCKEND) |
767 | dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); | |
f20f8f21 | 768 | |
ccff9b51 | 769 | if (status & MCI_DATAEND || data->error) { |
c8ebae37 RK |
770 | if (dma_inprogress(host)) |
771 | mmci_dma_unmap(host, data); | |
1da177e4 LT |
772 | mmci_stop_data(host); |
773 | ||
8cb28155 LW |
774 | if (!data->error) |
775 | /* The error clause is handled above, success! */ | |
51d4375d | 776 | data->bytes_xfered = data->blksz * data->blocks; |
f20f8f21 | 777 | |
1da177e4 LT |
778 | if (!data->stop) { |
779 | mmci_request_end(host, data->mrq); | |
780 | } else { | |
781 | mmci_start_command(host, data->stop, 0); | |
782 | } | |
783 | } | |
784 | } | |
785 | ||
786 | static void | |
787 | mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, | |
788 | unsigned int status) | |
789 | { | |
790 | void __iomem *base = host->base; | |
791 | ||
792 | host->cmd = NULL; | |
793 | ||
1da177e4 | 794 | if (status & MCI_CMDTIMEOUT) { |
17b0429d | 795 | cmd->error = -ETIMEDOUT; |
1da177e4 | 796 | } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { |
17b0429d | 797 | cmd->error = -EILSEQ; |
9047b435 RKAL |
798 | } else { |
799 | cmd->resp[0] = readl(base + MMCIRESPONSE0); | |
800 | cmd->resp[1] = readl(base + MMCIRESPONSE1); | |
801 | cmd->resp[2] = readl(base + MMCIRESPONSE2); | |
802 | cmd->resp[3] = readl(base + MMCIRESPONSE3); | |
1da177e4 LT |
803 | } |
804 | ||
17b0429d | 805 | if (!cmd->data || cmd->error) { |
3b6e3c73 UH |
806 | if (host->data) { |
807 | /* Terminate the DMA transfer */ | |
808 | if (dma_inprogress(host)) | |
809 | mmci_dma_data_error(host); | |
e47c222b | 810 | mmci_stop_data(host); |
3b6e3c73 | 811 | } |
1da177e4 LT |
812 | mmci_request_end(host, cmd->mrq); |
813 | } else if (!(cmd->data->flags & MMC_DATA_READ)) { | |
814 | mmci_start_data(host, cmd->data); | |
815 | } | |
816 | } | |
817 | ||
818 | static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) | |
819 | { | |
820 | void __iomem *base = host->base; | |
821 | char *ptr = buffer; | |
822 | u32 status; | |
26eed9a5 | 823 | int host_remain = host->size; |
1da177e4 LT |
824 | |
825 | do { | |
26eed9a5 | 826 | int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); |
1da177e4 LT |
827 | |
828 | if (count > remain) | |
829 | count = remain; | |
830 | ||
831 | if (count <= 0) | |
832 | break; | |
833 | ||
393e5e24 UH |
834 | /* |
835 | * SDIO especially may want to send something that is | |
836 | * not divisible by 4 (as opposed to card sectors | |
837 | * etc). Therefore make sure to always read the last bytes | |
838 | * while only doing full 32-bit reads towards the FIFO. | |
839 | */ | |
840 | if (unlikely(count & 0x3)) { | |
841 | if (count < 4) { | |
842 | unsigned char buf[4]; | |
843 | readsl(base + MMCIFIFO, buf, 1); | |
844 | memcpy(ptr, buf, count); | |
845 | } else { | |
846 | readsl(base + MMCIFIFO, ptr, count >> 2); | |
847 | count &= ~0x3; | |
848 | } | |
849 | } else { | |
850 | readsl(base + MMCIFIFO, ptr, count >> 2); | |
851 | } | |
1da177e4 LT |
852 | |
853 | ptr += count; | |
854 | remain -= count; | |
26eed9a5 | 855 | host_remain -= count; |
1da177e4 LT |
856 | |
857 | if (remain == 0) | |
858 | break; | |
859 | ||
860 | status = readl(base + MMCISTATUS); | |
861 | } while (status & MCI_RXDATAAVLBL); | |
862 | ||
863 | return ptr - buffer; | |
864 | } | |
865 | ||
866 | static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) | |
867 | { | |
8301bb68 | 868 | struct variant_data *variant = host->variant; |
1da177e4 LT |
869 | void __iomem *base = host->base; |
870 | char *ptr = buffer; | |
871 | ||
872 | do { | |
873 | unsigned int count, maxcnt; | |
874 | ||
8301bb68 RV |
875 | maxcnt = status & MCI_TXFIFOEMPTY ? |
876 | variant->fifosize : variant->fifohalfsize; | |
1da177e4 LT |
877 | count = min(remain, maxcnt); |
878 | ||
34177802 LW |
879 | /* |
880 | * The ST Micro variant for SDIO transfer sizes | |
881 | * less then 8 bytes should have clock H/W flow | |
882 | * control disabled. | |
883 | */ | |
884 | if (variant->sdio && | |
885 | mmc_card_sdio(host->mmc->card)) { | |
7437cfa5 | 886 | u32 clk; |
34177802 | 887 | if (count < 8) |
7437cfa5 | 888 | clk = host->clk_reg & ~variant->clkreg_enable; |
34177802 | 889 | else |
7437cfa5 UH |
890 | clk = host->clk_reg | variant->clkreg_enable; |
891 | ||
892 | mmci_write_clkreg(host, clk); | |
34177802 LW |
893 | } |
894 | ||
895 | /* | |
896 | * SDIO especially may want to send something that is | |
897 | * not divisible by 4 (as opposed to card sectors | |
898 | * etc), and the FIFO only accept full 32-bit writes. | |
899 | * So compensate by adding +3 on the count, a single | |
900 | * byte become a 32bit write, 7 bytes will be two | |
901 | * 32bit writes etc. | |
902 | */ | |
903 | writesl(base + MMCIFIFO, ptr, (count + 3) >> 2); | |
1da177e4 LT |
904 | |
905 | ptr += count; | |
906 | remain -= count; | |
907 | ||
908 | if (remain == 0) | |
909 | break; | |
910 | ||
911 | status = readl(base + MMCISTATUS); | |
912 | } while (status & MCI_TXFIFOHALFEMPTY); | |
913 | ||
914 | return ptr - buffer; | |
915 | } | |
916 | ||
917 | /* | |
918 | * PIO data transfer IRQ handler. | |
919 | */ | |
7d12e780 | 920 | static irqreturn_t mmci_pio_irq(int irq, void *dev_id) |
1da177e4 LT |
921 | { |
922 | struct mmci_host *host = dev_id; | |
4ce1d6cb | 923 | struct sg_mapping_iter *sg_miter = &host->sg_miter; |
8301bb68 | 924 | struct variant_data *variant = host->variant; |
1da177e4 | 925 | void __iomem *base = host->base; |
4ce1d6cb | 926 | unsigned long flags; |
1da177e4 LT |
927 | u32 status; |
928 | ||
929 | status = readl(base + MMCISTATUS); | |
930 | ||
64de0289 | 931 | dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); |
1da177e4 | 932 | |
4ce1d6cb RV |
933 | local_irq_save(flags); |
934 | ||
1da177e4 | 935 | do { |
1da177e4 LT |
936 | unsigned int remain, len; |
937 | char *buffer; | |
938 | ||
939 | /* | |
940 | * For write, we only need to test the half-empty flag | |
941 | * here - if the FIFO is completely empty, then by | |
942 | * definition it is more than half empty. | |
943 | * | |
944 | * For read, check for data available. | |
945 | */ | |
946 | if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) | |
947 | break; | |
948 | ||
4ce1d6cb RV |
949 | if (!sg_miter_next(sg_miter)) |
950 | break; | |
951 | ||
952 | buffer = sg_miter->addr; | |
953 | remain = sg_miter->length; | |
1da177e4 LT |
954 | |
955 | len = 0; | |
956 | if (status & MCI_RXACTIVE) | |
957 | len = mmci_pio_read(host, buffer, remain); | |
958 | if (status & MCI_TXACTIVE) | |
959 | len = mmci_pio_write(host, buffer, remain, status); | |
960 | ||
4ce1d6cb | 961 | sg_miter->consumed = len; |
1da177e4 | 962 | |
1da177e4 LT |
963 | host->size -= len; |
964 | remain -= len; | |
965 | ||
966 | if (remain) | |
967 | break; | |
968 | ||
1da177e4 LT |
969 | status = readl(base + MMCISTATUS); |
970 | } while (1); | |
971 | ||
4ce1d6cb RV |
972 | sg_miter_stop(sg_miter); |
973 | ||
974 | local_irq_restore(flags); | |
975 | ||
1da177e4 | 976 | /* |
c4d877c1 RK |
977 | * If we have less than the fifo 'half-full' threshold to transfer, |
978 | * trigger a PIO interrupt as soon as any data is available. | |
1da177e4 | 979 | */ |
c4d877c1 | 980 | if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) |
2686b4b4 | 981 | mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); |
1da177e4 LT |
982 | |
983 | /* | |
984 | * If we run out of data, disable the data IRQs; this | |
985 | * prevents a race where the FIFO becomes empty before | |
986 | * the chip itself has disabled the data path, and | |
987 | * stops us racing with our data end IRQ. | |
988 | */ | |
989 | if (host->size == 0) { | |
2686b4b4 | 990 | mmci_set_mask1(host, 0); |
1da177e4 LT |
991 | writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); |
992 | } | |
993 | ||
994 | return IRQ_HANDLED; | |
995 | } | |
996 | ||
997 | /* | |
998 | * Handle completion of command and data transfers. | |
999 | */ | |
7d12e780 | 1000 | static irqreturn_t mmci_irq(int irq, void *dev_id) |
1da177e4 LT |
1001 | { |
1002 | struct mmci_host *host = dev_id; | |
1003 | u32 status; | |
1004 | int ret = 0; | |
1005 | ||
1006 | spin_lock(&host->lock); | |
1007 | ||
1008 | do { | |
1009 | struct mmc_command *cmd; | |
1010 | struct mmc_data *data; | |
1011 | ||
1012 | status = readl(host->base + MMCISTATUS); | |
2686b4b4 LW |
1013 | |
1014 | if (host->singleirq) { | |
1015 | if (status & readl(host->base + MMCIMASK1)) | |
1016 | mmci_pio_irq(irq, dev_id); | |
1017 | ||
1018 | status &= ~MCI_IRQ1MASK; | |
1019 | } | |
1020 | ||
1da177e4 LT |
1021 | status &= readl(host->base + MMCIMASK0); |
1022 | writel(status, host->base + MMCICLEAR); | |
1023 | ||
64de0289 | 1024 | dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); |
1da177e4 LT |
1025 | |
1026 | data = host->data; | |
b63038d6 UH |
1027 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| |
1028 | MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND| | |
1029 | MCI_DATABLOCKEND) && data) | |
1da177e4 LT |
1030 | mmci_data_irq(host, data, status); |
1031 | ||
1032 | cmd = host->cmd; | |
1033 | if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) | |
1034 | mmci_cmd_irq(host, cmd, status); | |
1035 | ||
1036 | ret = 1; | |
1037 | } while (status); | |
1038 | ||
1039 | spin_unlock(&host->lock); | |
1040 | ||
1041 | return IRQ_RETVAL(ret); | |
1042 | } | |
1043 | ||
1044 | static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
1045 | { | |
1046 | struct mmci_host *host = mmc_priv(mmc); | |
9e943021 | 1047 | unsigned long flags; |
1da177e4 LT |
1048 | |
1049 | WARN_ON(host->mrq != NULL); | |
1050 | ||
019a5f56 | 1051 | if (mrq->data && !is_power_of_2(mrq->data->blksz)) { |
64de0289 LW |
1052 | dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", |
1053 | mrq->data->blksz); | |
255d01af PO |
1054 | mrq->cmd->error = -EINVAL; |
1055 | mmc_request_done(mmc, mrq); | |
1056 | return; | |
1057 | } | |
1058 | ||
1c3be369 RK |
1059 | pm_runtime_get_sync(mmc_dev(mmc)); |
1060 | ||
9e943021 | 1061 | spin_lock_irqsave(&host->lock, flags); |
1da177e4 LT |
1062 | |
1063 | host->mrq = mrq; | |
1064 | ||
58c7ccbf PF |
1065 | if (mrq->data) |
1066 | mmci_get_next_data(host, mrq->data); | |
1067 | ||
1da177e4 LT |
1068 | if (mrq->data && mrq->data->flags & MMC_DATA_READ) |
1069 | mmci_start_data(host, mrq->data); | |
1070 | ||
1071 | mmci_start_command(host, mrq->cmd, 0); | |
1072 | ||
9e943021 | 1073 | spin_unlock_irqrestore(&host->lock, flags); |
1da177e4 LT |
1074 | } |
1075 | ||
1076 | static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
1077 | { | |
1078 | struct mmci_host *host = mmc_priv(mmc); | |
7d72a1d4 | 1079 | struct variant_data *variant = host->variant; |
a6a6464a LW |
1080 | u32 pwr = 0; |
1081 | unsigned long flags; | |
99fc5131 | 1082 | int ret; |
1da177e4 | 1083 | |
2cd976c4 UH |
1084 | pm_runtime_get_sync(mmc_dev(mmc)); |
1085 | ||
bc521818 UH |
1086 | if (host->plat->ios_handler && |
1087 | host->plat->ios_handler(mmc_dev(mmc), ios)) | |
1088 | dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); | |
1089 | ||
1da177e4 LT |
1090 | switch (ios->power_mode) { |
1091 | case MMC_POWER_OFF: | |
99fc5131 LW |
1092 | if (host->vcc) |
1093 | ret = mmc_regulator_set_ocr(mmc, host->vcc, 0); | |
1da177e4 LT |
1094 | break; |
1095 | case MMC_POWER_UP: | |
99fc5131 LW |
1096 | if (host->vcc) { |
1097 | ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd); | |
1098 | if (ret) { | |
1099 | dev_err(mmc_dev(mmc), "unable to set OCR\n"); | |
1100 | /* | |
1101 | * The .set_ios() function in the mmc_host_ops | |
1102 | * struct return void, and failing to set the | |
1103 | * power should be rare so we print an error | |
1104 | * and return here. | |
1105 | */ | |
2cd976c4 | 1106 | goto out; |
99fc5131 LW |
1107 | } |
1108 | } | |
7d72a1d4 UH |
1109 | /* |
1110 | * The ST Micro variant doesn't have the PL180s MCI_PWR_UP | |
1111 | * and instead uses MCI_PWR_ON so apply whatever value is | |
1112 | * configured in the variant data. | |
1113 | */ | |
1114 | pwr |= variant->pwrreg_powerup; | |
1115 | ||
1116 | break; | |
1da177e4 LT |
1117 | case MMC_POWER_ON: |
1118 | pwr |= MCI_PWR_ON; | |
1119 | break; | |
1120 | } | |
1121 | ||
4d1a3a0d UH |
1122 | if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { |
1123 | /* | |
1124 | * The ST Micro variant has some additional bits | |
1125 | * indicating signal direction for the signals in | |
1126 | * the SD/MMC bus and feedback-clock usage. | |
1127 | */ | |
1128 | pwr |= host->plat->sigdir; | |
1129 | ||
1130 | if (ios->bus_width == MMC_BUS_WIDTH_4) | |
1131 | pwr &= ~MCI_ST_DATA74DIREN; | |
1132 | else if (ios->bus_width == MMC_BUS_WIDTH_1) | |
1133 | pwr &= (~MCI_ST_DATA74DIREN & | |
1134 | ~MCI_ST_DATA31DIREN & | |
1135 | ~MCI_ST_DATA2DIREN); | |
1136 | } | |
1137 | ||
cc30d60e | 1138 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { |
f17a1f06 | 1139 | if (host->hw_designer != AMBA_VENDOR_ST) |
cc30d60e LW |
1140 | pwr |= MCI_ROD; |
1141 | else { | |
1142 | /* | |
1143 | * The ST Micro variant use the ROD bit for something | |
1144 | * else and only has OD (Open Drain). | |
1145 | */ | |
1146 | pwr |= MCI_OD; | |
1147 | } | |
1148 | } | |
1da177e4 | 1149 | |
a6a6464a LW |
1150 | spin_lock_irqsave(&host->lock, flags); |
1151 | ||
1152 | mmci_set_clkreg(host, ios->clock); | |
7437cfa5 | 1153 | mmci_write_pwrreg(host, pwr); |
a6a6464a LW |
1154 | |
1155 | spin_unlock_irqrestore(&host->lock, flags); | |
2cd976c4 UH |
1156 | |
1157 | out: | |
1158 | pm_runtime_mark_last_busy(mmc_dev(mmc)); | |
1159 | pm_runtime_put_autosuspend(mmc_dev(mmc)); | |
1da177e4 LT |
1160 | } |
1161 | ||
89001446 RK |
1162 | static int mmci_get_ro(struct mmc_host *mmc) |
1163 | { | |
1164 | struct mmci_host *host = mmc_priv(mmc); | |
1165 | ||
1166 | if (host->gpio_wp == -ENOSYS) | |
1167 | return -ENOSYS; | |
1168 | ||
18a06301 | 1169 | return gpio_get_value_cansleep(host->gpio_wp); |
89001446 RK |
1170 | } |
1171 | ||
1172 | static int mmci_get_cd(struct mmc_host *mmc) | |
1173 | { | |
1174 | struct mmci_host *host = mmc_priv(mmc); | |
29719445 | 1175 | struct mmci_platform_data *plat = host->plat; |
89001446 RK |
1176 | unsigned int status; |
1177 | ||
4b8caec0 RV |
1178 | if (host->gpio_cd == -ENOSYS) { |
1179 | if (!plat->status) | |
1180 | return 1; /* Assume always present */ | |
1181 | ||
29719445 | 1182 | status = plat->status(mmc_dev(host->mmc)); |
4b8caec0 | 1183 | } else |
18a06301 LW |
1184 | status = !!gpio_get_value_cansleep(host->gpio_cd) |
1185 | ^ plat->cd_invert; | |
89001446 | 1186 | |
74bc8093 RK |
1187 | /* |
1188 | * Use positive logic throughout - status is zero for no card, | |
1189 | * non-zero for card inserted. | |
1190 | */ | |
1191 | return status; | |
89001446 RK |
1192 | } |
1193 | ||
148b8b39 RV |
1194 | static irqreturn_t mmci_cd_irq(int irq, void *dev_id) |
1195 | { | |
1196 | struct mmci_host *host = dev_id; | |
1197 | ||
1198 | mmc_detect_change(host->mmc, msecs_to_jiffies(500)); | |
1199 | ||
1200 | return IRQ_HANDLED; | |
1201 | } | |
1202 | ||
ab7aefd0 | 1203 | static const struct mmc_host_ops mmci_ops = { |
1da177e4 | 1204 | .request = mmci_request, |
58c7ccbf PF |
1205 | .pre_req = mmci_pre_request, |
1206 | .post_req = mmci_post_request, | |
1da177e4 | 1207 | .set_ios = mmci_set_ios, |
89001446 RK |
1208 | .get_ro = mmci_get_ro, |
1209 | .get_cd = mmci_get_cd, | |
1da177e4 LT |
1210 | }; |
1211 | ||
000bc9d5 LJ |
1212 | #ifdef CONFIG_OF |
1213 | static void mmci_dt_populate_generic_pdata(struct device_node *np, | |
1214 | struct mmci_platform_data *pdata) | |
1215 | { | |
1216 | int bus_width = 0; | |
1217 | ||
9a597016 | 1218 | pdata->gpio_wp = of_get_named_gpio(np, "wp-gpios", 0); |
9a597016 | 1219 | pdata->gpio_cd = of_get_named_gpio(np, "cd-gpios", 0); |
000bc9d5 LJ |
1220 | |
1221 | if (of_get_property(np, "cd-inverted", NULL)) | |
1222 | pdata->cd_invert = true; | |
1223 | else | |
1224 | pdata->cd_invert = false; | |
1225 | ||
1226 | of_property_read_u32(np, "max-frequency", &pdata->f_max); | |
1227 | if (!pdata->f_max) | |
1228 | pr_warn("%s has no 'max-frequency' property\n", np->full_name); | |
1229 | ||
1230 | if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) | |
1231 | pdata->capabilities |= MMC_CAP_MMC_HIGHSPEED; | |
1232 | if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) | |
1233 | pdata->capabilities |= MMC_CAP_SD_HIGHSPEED; | |
1234 | ||
1235 | of_property_read_u32(np, "bus-width", &bus_width); | |
1236 | switch (bus_width) { | |
1237 | case 0 : | |
1238 | /* No bus-width supplied. */ | |
1239 | break; | |
1240 | case 4 : | |
1241 | pdata->capabilities |= MMC_CAP_4_BIT_DATA; | |
1242 | break; | |
1243 | case 8 : | |
1244 | pdata->capabilities |= MMC_CAP_8_BIT_DATA; | |
1245 | break; | |
1246 | default : | |
1247 | pr_warn("%s: Unsupported bus width\n", np->full_name); | |
1248 | } | |
1249 | } | |
c0a120a4 LJ |
1250 | #else |
1251 | static void mmci_dt_populate_generic_pdata(struct device_node *np, | |
1252 | struct mmci_platform_data *pdata) | |
1253 | { | |
1254 | return; | |
1255 | } | |
000bc9d5 LJ |
1256 | #endif |
1257 | ||
aa25afad RK |
1258 | static int __devinit mmci_probe(struct amba_device *dev, |
1259 | const struct amba_id *id) | |
1da177e4 | 1260 | { |
6ef297f8 | 1261 | struct mmci_platform_data *plat = dev->dev.platform_data; |
000bc9d5 | 1262 | struct device_node *np = dev->dev.of_node; |
4956e109 | 1263 | struct variant_data *variant = id->data; |
1da177e4 LT |
1264 | struct mmci_host *host; |
1265 | struct mmc_host *mmc; | |
1266 | int ret; | |
1267 | ||
000bc9d5 LJ |
1268 | /* Must have platform data or Device Tree. */ |
1269 | if (!plat && !np) { | |
1270 | dev_err(&dev->dev, "No plat data or DT found\n"); | |
1271 | return -EINVAL; | |
1da177e4 LT |
1272 | } |
1273 | ||
b9b52918 LJ |
1274 | if (!plat) { |
1275 | plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); | |
1276 | if (!plat) | |
1277 | return -ENOMEM; | |
1278 | } | |
1279 | ||
000bc9d5 LJ |
1280 | if (np) |
1281 | mmci_dt_populate_generic_pdata(np, plat); | |
1282 | ||
1da177e4 LT |
1283 | ret = amba_request_regions(dev, DRIVER_NAME); |
1284 | if (ret) | |
1285 | goto out; | |
1286 | ||
1287 | mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); | |
1288 | if (!mmc) { | |
1289 | ret = -ENOMEM; | |
1290 | goto rel_regions; | |
1291 | } | |
1292 | ||
1293 | host = mmc_priv(mmc); | |
4ea580f1 | 1294 | host->mmc = mmc; |
012b7d33 | 1295 | |
89001446 RK |
1296 | host->gpio_wp = -ENOSYS; |
1297 | host->gpio_cd = -ENOSYS; | |
148b8b39 | 1298 | host->gpio_cd_irq = -1; |
89001446 | 1299 | |
012b7d33 RK |
1300 | host->hw_designer = amba_manf(dev); |
1301 | host->hw_revision = amba_rev(dev); | |
64de0289 LW |
1302 | dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); |
1303 | dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); | |
012b7d33 | 1304 | |
ee569c43 | 1305 | host->clk = clk_get(&dev->dev, NULL); |
1da177e4 LT |
1306 | if (IS_ERR(host->clk)) { |
1307 | ret = PTR_ERR(host->clk); | |
1308 | host->clk = NULL; | |
1309 | goto host_free; | |
1310 | } | |
1311 | ||
52ca0f3a | 1312 | ret = clk_prepare(host->clk); |
1da177e4 | 1313 | if (ret) |
a8d3584a | 1314 | goto clk_free; |
1da177e4 | 1315 | |
52ca0f3a RK |
1316 | ret = clk_enable(host->clk); |
1317 | if (ret) | |
1318 | goto clk_unprep; | |
1319 | ||
1da177e4 | 1320 | host->plat = plat; |
4956e109 | 1321 | host->variant = variant; |
1da177e4 | 1322 | host->mclk = clk_get_rate(host->clk); |
c8df9a53 LW |
1323 | /* |
1324 | * According to the spec, mclk is max 100 MHz, | |
1325 | * so we try to adjust the clock down to this, | |
1326 | * (if possible). | |
1327 | */ | |
1328 | if (host->mclk > 100000000) { | |
1329 | ret = clk_set_rate(host->clk, 100000000); | |
1330 | if (ret < 0) | |
1331 | goto clk_disable; | |
1332 | host->mclk = clk_get_rate(host->clk); | |
64de0289 LW |
1333 | dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", |
1334 | host->mclk); | |
c8df9a53 | 1335 | } |
c8ebae37 | 1336 | host->phybase = dev->res.start; |
dc890c2d | 1337 | host->base = ioremap(dev->res.start, resource_size(&dev->res)); |
1da177e4 LT |
1338 | if (!host->base) { |
1339 | ret = -ENOMEM; | |
1340 | goto clk_disable; | |
1341 | } | |
1342 | ||
1343 | mmc->ops = &mmci_ops; | |
7f294e49 LW |
1344 | /* |
1345 | * The ARM and ST versions of the block have slightly different | |
1346 | * clock divider equations which means that the minimum divider | |
1347 | * differs too. | |
1348 | */ | |
1349 | if (variant->st_clkdiv) | |
1350 | mmc->f_min = DIV_ROUND_UP(host->mclk, 257); | |
1351 | else | |
1352 | mmc->f_min = DIV_ROUND_UP(host->mclk, 512); | |
808d97cc LW |
1353 | /* |
1354 | * If the platform data supplies a maximum operating | |
1355 | * frequency, this takes precedence. Else, we fall back | |
1356 | * to using the module parameter, which has a (low) | |
1357 | * default value in case it is not specified. Either | |
1358 | * value must not exceed the clock rate into the block, | |
1359 | * of course. | |
1360 | */ | |
1361 | if (plat->f_max) | |
1362 | mmc->f_max = min(host->mclk, plat->f_max); | |
1363 | else | |
1364 | mmc->f_max = min(host->mclk, fmax); | |
64de0289 LW |
1365 | dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); |
1366 | ||
34e84f39 LW |
1367 | #ifdef CONFIG_REGULATOR |
1368 | /* If we're using the regulator framework, try to fetch a regulator */ | |
1369 | host->vcc = regulator_get(&dev->dev, "vmmc"); | |
1370 | if (IS_ERR(host->vcc)) | |
1371 | host->vcc = NULL; | |
1372 | else { | |
1373 | int mask = mmc_regulator_get_ocrmask(host->vcc); | |
1374 | ||
1375 | if (mask < 0) | |
1376 | dev_err(&dev->dev, "error getting OCR mask (%d)\n", | |
1377 | mask); | |
1378 | else { | |
1379 | host->mmc->ocr_avail = (u32) mask; | |
1380 | if (plat->ocr_mask) | |
1381 | dev_warn(&dev->dev, | |
1382 | "Provided ocr_mask/setpower will not be used " | |
1383 | "(using regulator instead)\n"); | |
1384 | } | |
1385 | } | |
1386 | #endif | |
1387 | /* Fall back to platform data if no regulator is found */ | |
1388 | if (host->vcc == NULL) | |
1389 | mmc->ocr_avail = plat->ocr_mask; | |
9e6c82cd | 1390 | mmc->caps = plat->capabilities; |
5a092627 | 1391 | mmc->caps2 = plat->capabilities2; |
1da177e4 LT |
1392 | |
1393 | /* | |
1394 | * We can do SGIO | |
1395 | */ | |
a36274e0 | 1396 | mmc->max_segs = NR_SG; |
1da177e4 LT |
1397 | |
1398 | /* | |
08458ef6 RV |
1399 | * Since only a certain number of bits are valid in the data length |
1400 | * register, we must ensure that we don't exceed 2^num-1 bytes in a | |
1401 | * single request. | |
1da177e4 | 1402 | */ |
08458ef6 | 1403 | mmc->max_req_size = (1 << variant->datalength_bits) - 1; |
1da177e4 LT |
1404 | |
1405 | /* | |
1406 | * Set the maximum segment size. Since we aren't doing DMA | |
1407 | * (yet) we are only limited by the data length register. | |
1408 | */ | |
55db890a | 1409 | mmc->max_seg_size = mmc->max_req_size; |
1da177e4 | 1410 | |
fe4a3c7a PO |
1411 | /* |
1412 | * Block size can be up to 2048 bytes, but must be a power of two. | |
1413 | */ | |
8f7f6b7e | 1414 | mmc->max_blk_size = 1 << 11; |
fe4a3c7a | 1415 | |
55db890a | 1416 | /* |
8f7f6b7e WD |
1417 | * Limit the number of blocks transferred so that we don't overflow |
1418 | * the maximum request size. | |
55db890a | 1419 | */ |
8f7f6b7e | 1420 | mmc->max_blk_count = mmc->max_req_size >> 11; |
55db890a | 1421 | |
1da177e4 LT |
1422 | spin_lock_init(&host->lock); |
1423 | ||
1424 | writel(0, host->base + MMCIMASK0); | |
1425 | writel(0, host->base + MMCIMASK1); | |
1426 | writel(0xfff, host->base + MMCICLEAR); | |
1427 | ||
2805b9ab RS |
1428 | if (plat->gpio_cd == -EPROBE_DEFER) { |
1429 | ret = -EPROBE_DEFER; | |
1430 | goto err_gpio_cd; | |
1431 | } | |
89001446 RK |
1432 | if (gpio_is_valid(plat->gpio_cd)) { |
1433 | ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); | |
1434 | if (ret == 0) | |
1435 | ret = gpio_direction_input(plat->gpio_cd); | |
1436 | if (ret == 0) | |
1437 | host->gpio_cd = plat->gpio_cd; | |
1438 | else if (ret != -ENOSYS) | |
1439 | goto err_gpio_cd; | |
148b8b39 | 1440 | |
17ee083b LW |
1441 | /* |
1442 | * A gpio pin that will detect cards when inserted and removed | |
1443 | * will most likely want to trigger on the edges if it is | |
1444 | * 0 when ejected and 1 when inserted (or mutatis mutandis | |
1445 | * for the inverted case) so we request triggers on both | |
1446 | * edges. | |
1447 | */ | |
148b8b39 | 1448 | ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), |
17ee083b LW |
1449 | mmci_cd_irq, |
1450 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, | |
1451 | DRIVER_NAME " (cd)", host); | |
148b8b39 RV |
1452 | if (ret >= 0) |
1453 | host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); | |
89001446 | 1454 | } |
2805b9ab RS |
1455 | if (plat->gpio_wp == -EPROBE_DEFER) { |
1456 | ret = -EPROBE_DEFER; | |
1457 | goto err_gpio_wp; | |
1458 | } | |
89001446 RK |
1459 | if (gpio_is_valid(plat->gpio_wp)) { |
1460 | ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); | |
1461 | if (ret == 0) | |
1462 | ret = gpio_direction_input(plat->gpio_wp); | |
1463 | if (ret == 0) | |
1464 | host->gpio_wp = plat->gpio_wp; | |
1465 | else if (ret != -ENOSYS) | |
1466 | goto err_gpio_wp; | |
1467 | } | |
1468 | ||
4b8caec0 RV |
1469 | if ((host->plat->status || host->gpio_cd != -ENOSYS) |
1470 | && host->gpio_cd_irq < 0) | |
148b8b39 RV |
1471 | mmc->caps |= MMC_CAP_NEEDS_POLL; |
1472 | ||
dace1453 | 1473 | ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); |
1da177e4 LT |
1474 | if (ret) |
1475 | goto unmap; | |
1476 | ||
dfb85185 | 1477 | if (!dev->irq[1]) |
2686b4b4 LW |
1478 | host->singleirq = true; |
1479 | else { | |
1480 | ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, | |
1481 | DRIVER_NAME " (pio)", host); | |
1482 | if (ret) | |
1483 | goto irq0_free; | |
1484 | } | |
1da177e4 | 1485 | |
8cb28155 | 1486 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); |
1da177e4 LT |
1487 | |
1488 | amba_set_drvdata(dev, mmc); | |
1489 | ||
c8ebae37 RK |
1490 | dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", |
1491 | mmc_hostname(mmc), amba_part(dev), amba_manf(dev), | |
1492 | amba_rev(dev), (unsigned long long)dev->res.start, | |
1493 | dev->irq[0], dev->irq[1]); | |
1494 | ||
1495 | mmci_dma_setup(host); | |
1da177e4 | 1496 | |
2cd976c4 UH |
1497 | pm_runtime_set_autosuspend_delay(&dev->dev, 50); |
1498 | pm_runtime_use_autosuspend(&dev->dev); | |
1c3be369 RK |
1499 | pm_runtime_put(&dev->dev); |
1500 | ||
8c11a94d RK |
1501 | mmc_add_host(mmc); |
1502 | ||
1da177e4 LT |
1503 | return 0; |
1504 | ||
1505 | irq0_free: | |
1506 | free_irq(dev->irq[0], host); | |
1507 | unmap: | |
89001446 RK |
1508 | if (host->gpio_wp != -ENOSYS) |
1509 | gpio_free(host->gpio_wp); | |
1510 | err_gpio_wp: | |
148b8b39 RV |
1511 | if (host->gpio_cd_irq >= 0) |
1512 | free_irq(host->gpio_cd_irq, host); | |
89001446 RK |
1513 | if (host->gpio_cd != -ENOSYS) |
1514 | gpio_free(host->gpio_cd); | |
1515 | err_gpio_cd: | |
1da177e4 LT |
1516 | iounmap(host->base); |
1517 | clk_disable: | |
1518 | clk_disable(host->clk); | |
52ca0f3a RK |
1519 | clk_unprep: |
1520 | clk_unprepare(host->clk); | |
1da177e4 LT |
1521 | clk_free: |
1522 | clk_put(host->clk); | |
1523 | host_free: | |
1524 | mmc_free_host(mmc); | |
1525 | rel_regions: | |
1526 | amba_release_regions(dev); | |
1527 | out: | |
1528 | return ret; | |
1529 | } | |
1530 | ||
6dc4a47a | 1531 | static int __devexit mmci_remove(struct amba_device *dev) |
1da177e4 LT |
1532 | { |
1533 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
1534 | ||
1535 | amba_set_drvdata(dev, NULL); | |
1536 | ||
1537 | if (mmc) { | |
1538 | struct mmci_host *host = mmc_priv(mmc); | |
1539 | ||
1c3be369 RK |
1540 | /* |
1541 | * Undo pm_runtime_put() in probe. We use the _sync | |
1542 | * version here so that we can access the primecell. | |
1543 | */ | |
1544 | pm_runtime_get_sync(&dev->dev); | |
1545 | ||
1da177e4 LT |
1546 | mmc_remove_host(mmc); |
1547 | ||
1548 | writel(0, host->base + MMCIMASK0); | |
1549 | writel(0, host->base + MMCIMASK1); | |
1550 | ||
1551 | writel(0, host->base + MMCICOMMAND); | |
1552 | writel(0, host->base + MMCIDATACTRL); | |
1553 | ||
c8ebae37 | 1554 | mmci_dma_release(host); |
1da177e4 | 1555 | free_irq(dev->irq[0], host); |
2686b4b4 LW |
1556 | if (!host->singleirq) |
1557 | free_irq(dev->irq[1], host); | |
1da177e4 | 1558 | |
89001446 RK |
1559 | if (host->gpio_wp != -ENOSYS) |
1560 | gpio_free(host->gpio_wp); | |
148b8b39 RV |
1561 | if (host->gpio_cd_irq >= 0) |
1562 | free_irq(host->gpio_cd_irq, host); | |
89001446 RK |
1563 | if (host->gpio_cd != -ENOSYS) |
1564 | gpio_free(host->gpio_cd); | |
1565 | ||
1da177e4 LT |
1566 | iounmap(host->base); |
1567 | clk_disable(host->clk); | |
52ca0f3a | 1568 | clk_unprepare(host->clk); |
1da177e4 LT |
1569 | clk_put(host->clk); |
1570 | ||
99fc5131 LW |
1571 | if (host->vcc) |
1572 | mmc_regulator_set_ocr(mmc, host->vcc, 0); | |
34e84f39 LW |
1573 | regulator_put(host->vcc); |
1574 | ||
1da177e4 LT |
1575 | mmc_free_host(mmc); |
1576 | ||
1577 | amba_release_regions(dev); | |
1578 | } | |
1579 | ||
1580 | return 0; | |
1581 | } | |
1582 | ||
48fa7003 UH |
1583 | #ifdef CONFIG_SUSPEND |
1584 | static int mmci_suspend(struct device *dev) | |
1da177e4 | 1585 | { |
48fa7003 UH |
1586 | struct amba_device *adev = to_amba_device(dev); |
1587 | struct mmc_host *mmc = amba_get_drvdata(adev); | |
1da177e4 LT |
1588 | int ret = 0; |
1589 | ||
1590 | if (mmc) { | |
1591 | struct mmci_host *host = mmc_priv(mmc); | |
1592 | ||
1a13f8fa | 1593 | ret = mmc_suspend_host(mmc); |
2cd976c4 UH |
1594 | if (ret == 0) { |
1595 | pm_runtime_get_sync(dev); | |
1da177e4 | 1596 | writel(0, host->base + MMCIMASK0); |
2cd976c4 | 1597 | } |
1da177e4 LT |
1598 | } |
1599 | ||
1600 | return ret; | |
1601 | } | |
1602 | ||
48fa7003 | 1603 | static int mmci_resume(struct device *dev) |
1da177e4 | 1604 | { |
48fa7003 UH |
1605 | struct amba_device *adev = to_amba_device(dev); |
1606 | struct mmc_host *mmc = amba_get_drvdata(adev); | |
1da177e4 LT |
1607 | int ret = 0; |
1608 | ||
1609 | if (mmc) { | |
1610 | struct mmci_host *host = mmc_priv(mmc); | |
1611 | ||
1612 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); | |
2cd976c4 | 1613 | pm_runtime_put(dev); |
1da177e4 LT |
1614 | |
1615 | ret = mmc_resume_host(mmc); | |
1616 | } | |
1617 | ||
1618 | return ret; | |
1619 | } | |
1da177e4 LT |
1620 | #endif |
1621 | ||
48fa7003 UH |
1622 | static const struct dev_pm_ops mmci_dev_pm_ops = { |
1623 | SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume) | |
1624 | }; | |
1625 | ||
1da177e4 LT |
1626 | static struct amba_id mmci_ids[] = { |
1627 | { | |
1628 | .id = 0x00041180, | |
768fbc18 | 1629 | .mask = 0xff0fffff, |
4956e109 | 1630 | .data = &variant_arm, |
1da177e4 | 1631 | }, |
768fbc18 PM |
1632 | { |
1633 | .id = 0x01041180, | |
1634 | .mask = 0xff0fffff, | |
1635 | .data = &variant_arm_extended_fifo, | |
1636 | }, | |
1da177e4 LT |
1637 | { |
1638 | .id = 0x00041181, | |
1639 | .mask = 0x000fffff, | |
4956e109 | 1640 | .data = &variant_arm, |
1da177e4 | 1641 | }, |
cc30d60e LW |
1642 | /* ST Micro variants */ |
1643 | { | |
1644 | .id = 0x00180180, | |
1645 | .mask = 0x00ffffff, | |
4956e109 | 1646 | .data = &variant_u300, |
cc30d60e | 1647 | }, |
34fd4213 LW |
1648 | { |
1649 | .id = 0x10180180, | |
1650 | .mask = 0xf0ffffff, | |
1651 | .data = &variant_nomadik, | |
1652 | }, | |
cc30d60e LW |
1653 | { |
1654 | .id = 0x00280180, | |
1655 | .mask = 0x00ffffff, | |
4956e109 RV |
1656 | .data = &variant_u300, |
1657 | }, | |
1658 | { | |
1659 | .id = 0x00480180, | |
1784b157 | 1660 | .mask = 0xf0ffffff, |
4956e109 | 1661 | .data = &variant_ux500, |
cc30d60e | 1662 | }, |
1784b157 PL |
1663 | { |
1664 | .id = 0x10480180, | |
1665 | .mask = 0xf0ffffff, | |
1666 | .data = &variant_ux500v2, | |
1667 | }, | |
1da177e4 LT |
1668 | { 0, 0 }, |
1669 | }; | |
1670 | ||
9f99835f DM |
1671 | MODULE_DEVICE_TABLE(amba, mmci_ids); |
1672 | ||
1da177e4 LT |
1673 | static struct amba_driver mmci_driver = { |
1674 | .drv = { | |
1675 | .name = DRIVER_NAME, | |
48fa7003 | 1676 | .pm = &mmci_dev_pm_ops, |
1da177e4 LT |
1677 | }, |
1678 | .probe = mmci_probe, | |
6dc4a47a | 1679 | .remove = __devexit_p(mmci_remove), |
1da177e4 LT |
1680 | .id_table = mmci_ids, |
1681 | }; | |
1682 | ||
9e5ed094 | 1683 | module_amba_driver(mmci_driver); |
1da177e4 | 1684 | |
1da177e4 LT |
1685 | module_param(fmax, uint, 0444); |
1686 | ||
1687 | MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); | |
1688 | MODULE_LICENSE("GPL"); |