Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. | |
c8ebae37 | 5 | * Copyright (C) 2010 ST-Ericsson SA |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/interrupt.h> | |
613b152c | 17 | #include <linux/kernel.h> |
1da177e4 LT |
18 | #include <linux/delay.h> |
19 | #include <linux/err.h> | |
20 | #include <linux/highmem.h> | |
019a5f56 | 21 | #include <linux/log2.h> |
1da177e4 | 22 | #include <linux/mmc/host.h> |
34177802 | 23 | #include <linux/mmc/card.h> |
a62c80e5 | 24 | #include <linux/amba/bus.h> |
f8ce2547 | 25 | #include <linux/clk.h> |
bd6dee6f | 26 | #include <linux/scatterlist.h> |
89001446 | 27 | #include <linux/gpio.h> |
34e84f39 | 28 | #include <linux/regulator/consumer.h> |
c8ebae37 RK |
29 | #include <linux/dmaengine.h> |
30 | #include <linux/dma-mapping.h> | |
31 | #include <linux/amba/mmci.h> | |
1da177e4 | 32 | |
7b09cdac | 33 | #include <asm/div64.h> |
1da177e4 | 34 | #include <asm/io.h> |
c6b8fdad | 35 | #include <asm/sizes.h> |
1da177e4 LT |
36 | |
37 | #include "mmci.h" | |
38 | ||
39 | #define DRIVER_NAME "mmci-pl18x" | |
40 | ||
1da177e4 LT |
41 | static unsigned int fmax = 515633; |
42 | ||
4956e109 RV |
43 | /** |
44 | * struct variant_data - MMCI variant-specific quirks | |
45 | * @clkreg: default value for MCICLOCK register | |
4380c14f | 46 | * @clkreg_enable: enable value for MMCICLOCK register |
08458ef6 | 47 | * @datalength_bits: number of bits in the MMCIDATALENGTH register |
8301bb68 RV |
48 | * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY |
49 | * is asserted (likewise for RX) | |
50 | * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY | |
51 | * is asserted (likewise for RX) | |
34177802 | 52 | * @sdio: variant supports SDIO |
b70a67f9 | 53 | * @st_clkdiv: true if using a ST-specific clock divider algorithm |
1784b157 | 54 | * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register |
4956e109 RV |
55 | */ |
56 | struct variant_data { | |
57 | unsigned int clkreg; | |
4380c14f | 58 | unsigned int clkreg_enable; |
08458ef6 | 59 | unsigned int datalength_bits; |
8301bb68 RV |
60 | unsigned int fifosize; |
61 | unsigned int fifohalfsize; | |
34177802 | 62 | bool sdio; |
b70a67f9 | 63 | bool st_clkdiv; |
1784b157 | 64 | bool blksz_datactrl16; |
4956e109 RV |
65 | }; |
66 | ||
67 | static struct variant_data variant_arm = { | |
8301bb68 RV |
68 | .fifosize = 16 * 4, |
69 | .fifohalfsize = 8 * 4, | |
08458ef6 | 70 | .datalength_bits = 16, |
4956e109 RV |
71 | }; |
72 | ||
768fbc18 PM |
73 | static struct variant_data variant_arm_extended_fifo = { |
74 | .fifosize = 128 * 4, | |
75 | .fifohalfsize = 64 * 4, | |
76 | .datalength_bits = 16, | |
77 | }; | |
78 | ||
4956e109 | 79 | static struct variant_data variant_u300 = { |
8301bb68 RV |
80 | .fifosize = 16 * 4, |
81 | .fifohalfsize = 8 * 4, | |
49ac215e | 82 | .clkreg_enable = MCI_ST_U300_HWFCEN, |
08458ef6 | 83 | .datalength_bits = 16, |
34177802 | 84 | .sdio = true, |
4956e109 RV |
85 | }; |
86 | ||
87 | static struct variant_data variant_ux500 = { | |
8301bb68 RV |
88 | .fifosize = 30 * 4, |
89 | .fifohalfsize = 8 * 4, | |
4956e109 | 90 | .clkreg = MCI_CLK_ENABLE, |
49ac215e | 91 | .clkreg_enable = MCI_ST_UX500_HWFCEN, |
08458ef6 | 92 | .datalength_bits = 24, |
34177802 | 93 | .sdio = true, |
b70a67f9 | 94 | .st_clkdiv = true, |
4956e109 | 95 | }; |
b70a67f9 | 96 | |
1784b157 PL |
97 | static struct variant_data variant_ux500v2 = { |
98 | .fifosize = 30 * 4, | |
99 | .fifohalfsize = 8 * 4, | |
100 | .clkreg = MCI_CLK_ENABLE, | |
101 | .clkreg_enable = MCI_ST_UX500_HWFCEN, | |
102 | .datalength_bits = 24, | |
103 | .sdio = true, | |
104 | .st_clkdiv = true, | |
105 | .blksz_datactrl16 = true, | |
106 | }; | |
107 | ||
a6a6464a LW |
108 | /* |
109 | * This must be called with host->lock held | |
110 | */ | |
111 | static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) | |
112 | { | |
4956e109 RV |
113 | struct variant_data *variant = host->variant; |
114 | u32 clk = variant->clkreg; | |
a6a6464a LW |
115 | |
116 | if (desired) { | |
117 | if (desired >= host->mclk) { | |
991a86e1 | 118 | clk = MCI_CLK_BYPASS; |
399bc486 LW |
119 | if (variant->st_clkdiv) |
120 | clk |= MCI_ST_UX500_NEG_EDGE; | |
a6a6464a | 121 | host->cclk = host->mclk; |
b70a67f9 LW |
122 | } else if (variant->st_clkdiv) { |
123 | /* | |
124 | * DB8500 TRM says f = mclk / (clkdiv + 2) | |
125 | * => clkdiv = (mclk / f) - 2 | |
126 | * Round the divider up so we don't exceed the max | |
127 | * frequency | |
128 | */ | |
129 | clk = DIV_ROUND_UP(host->mclk, desired) - 2; | |
130 | if (clk >= 256) | |
131 | clk = 255; | |
132 | host->cclk = host->mclk / (clk + 2); | |
a6a6464a | 133 | } else { |
b70a67f9 LW |
134 | /* |
135 | * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) | |
136 | * => clkdiv = mclk / (2 * f) - 1 | |
137 | */ | |
a6a6464a LW |
138 | clk = host->mclk / (2 * desired) - 1; |
139 | if (clk >= 256) | |
140 | clk = 255; | |
141 | host->cclk = host->mclk / (2 * (clk + 1)); | |
142 | } | |
4380c14f RV |
143 | |
144 | clk |= variant->clkreg_enable; | |
a6a6464a LW |
145 | clk |= MCI_CLK_ENABLE; |
146 | /* This hasn't proven to be worthwhile */ | |
147 | /* clk |= MCI_CLK_PWRSAVE; */ | |
148 | } | |
149 | ||
9e6c82cd | 150 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) |
771dc157 LW |
151 | clk |= MCI_4BIT_BUS; |
152 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) | |
153 | clk |= MCI_ST_8BIT_BUS; | |
9e6c82cd | 154 | |
a6a6464a LW |
155 | writel(clk, host->base + MMCICLOCK); |
156 | } | |
157 | ||
1da177e4 LT |
158 | static void |
159 | mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) | |
160 | { | |
161 | writel(0, host->base + MMCICOMMAND); | |
162 | ||
e47c222b RK |
163 | BUG_ON(host->data); |
164 | ||
1da177e4 LT |
165 | host->mrq = NULL; |
166 | host->cmd = NULL; | |
167 | ||
1da177e4 LT |
168 | /* |
169 | * Need to drop the host lock here; mmc_request_done may call | |
170 | * back into the driver... | |
171 | */ | |
172 | spin_unlock(&host->lock); | |
173 | mmc_request_done(host->mmc, mrq); | |
174 | spin_lock(&host->lock); | |
175 | } | |
176 | ||
2686b4b4 LW |
177 | static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) |
178 | { | |
179 | void __iomem *base = host->base; | |
180 | ||
181 | if (host->singleirq) { | |
182 | unsigned int mask0 = readl(base + MMCIMASK0); | |
183 | ||
184 | mask0 &= ~MCI_IRQ1MASK; | |
185 | mask0 |= mask; | |
186 | ||
187 | writel(mask0, base + MMCIMASK0); | |
188 | } | |
189 | ||
190 | writel(mask, base + MMCIMASK1); | |
191 | } | |
192 | ||
1da177e4 LT |
193 | static void mmci_stop_data(struct mmci_host *host) |
194 | { | |
195 | writel(0, host->base + MMCIDATACTRL); | |
2686b4b4 | 196 | mmci_set_mask1(host, 0); |
1da177e4 LT |
197 | host->data = NULL; |
198 | } | |
199 | ||
4ce1d6cb RV |
200 | static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) |
201 | { | |
202 | unsigned int flags = SG_MITER_ATOMIC; | |
203 | ||
204 | if (data->flags & MMC_DATA_READ) | |
205 | flags |= SG_MITER_TO_SG; | |
206 | else | |
207 | flags |= SG_MITER_FROM_SG; | |
208 | ||
209 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); | |
210 | } | |
211 | ||
c8ebae37 RK |
212 | /* |
213 | * All the DMA operation mode stuff goes inside this ifdef. | |
214 | * This assumes that you have a generic DMA device interface, | |
215 | * no custom DMA interfaces are supported. | |
216 | */ | |
217 | #ifdef CONFIG_DMA_ENGINE | |
218 | static void __devinit mmci_dma_setup(struct mmci_host *host) | |
219 | { | |
220 | struct mmci_platform_data *plat = host->plat; | |
221 | const char *rxname, *txname; | |
222 | dma_cap_mask_t mask; | |
223 | ||
224 | if (!plat || !plat->dma_filter) { | |
225 | dev_info(mmc_dev(host->mmc), "no DMA platform data\n"); | |
226 | return; | |
227 | } | |
228 | ||
58c7ccbf PF |
229 | /* initialize pre request cookie */ |
230 | host->next_data.cookie = 1; | |
231 | ||
c8ebae37 RK |
232 | /* Try to acquire a generic DMA engine slave channel */ |
233 | dma_cap_zero(mask); | |
234 | dma_cap_set(DMA_SLAVE, mask); | |
235 | ||
236 | /* | |
237 | * If only an RX channel is specified, the driver will | |
238 | * attempt to use it bidirectionally, however if it is | |
239 | * is specified but cannot be located, DMA will be disabled. | |
240 | */ | |
241 | if (plat->dma_rx_param) { | |
242 | host->dma_rx_channel = dma_request_channel(mask, | |
243 | plat->dma_filter, | |
244 | plat->dma_rx_param); | |
245 | /* E.g if no DMA hardware is present */ | |
246 | if (!host->dma_rx_channel) | |
247 | dev_err(mmc_dev(host->mmc), "no RX DMA channel\n"); | |
248 | } | |
249 | ||
250 | if (plat->dma_tx_param) { | |
251 | host->dma_tx_channel = dma_request_channel(mask, | |
252 | plat->dma_filter, | |
253 | plat->dma_tx_param); | |
254 | if (!host->dma_tx_channel) | |
255 | dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n"); | |
256 | } else { | |
257 | host->dma_tx_channel = host->dma_rx_channel; | |
258 | } | |
259 | ||
260 | if (host->dma_rx_channel) | |
261 | rxname = dma_chan_name(host->dma_rx_channel); | |
262 | else | |
263 | rxname = "none"; | |
264 | ||
265 | if (host->dma_tx_channel) | |
266 | txname = dma_chan_name(host->dma_tx_channel); | |
267 | else | |
268 | txname = "none"; | |
269 | ||
270 | dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", | |
271 | rxname, txname); | |
272 | ||
273 | /* | |
274 | * Limit the maximum segment size in any SG entry according to | |
275 | * the parameters of the DMA engine device. | |
276 | */ | |
277 | if (host->dma_tx_channel) { | |
278 | struct device *dev = host->dma_tx_channel->device->dev; | |
279 | unsigned int max_seg_size = dma_get_max_seg_size(dev); | |
280 | ||
281 | if (max_seg_size < host->mmc->max_seg_size) | |
282 | host->mmc->max_seg_size = max_seg_size; | |
283 | } | |
284 | if (host->dma_rx_channel) { | |
285 | struct device *dev = host->dma_rx_channel->device->dev; | |
286 | unsigned int max_seg_size = dma_get_max_seg_size(dev); | |
287 | ||
288 | if (max_seg_size < host->mmc->max_seg_size) | |
289 | host->mmc->max_seg_size = max_seg_size; | |
290 | } | |
291 | } | |
292 | ||
293 | /* | |
294 | * This is used in __devinit or __devexit so inline it | |
295 | * so it can be discarded. | |
296 | */ | |
297 | static inline void mmci_dma_release(struct mmci_host *host) | |
298 | { | |
299 | struct mmci_platform_data *plat = host->plat; | |
300 | ||
301 | if (host->dma_rx_channel) | |
302 | dma_release_channel(host->dma_rx_channel); | |
303 | if (host->dma_tx_channel && plat->dma_tx_param) | |
304 | dma_release_channel(host->dma_tx_channel); | |
305 | host->dma_rx_channel = host->dma_tx_channel = NULL; | |
306 | } | |
307 | ||
308 | static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) | |
309 | { | |
310 | struct dma_chan *chan = host->dma_current; | |
311 | enum dma_data_direction dir; | |
312 | u32 status; | |
313 | int i; | |
314 | ||
315 | /* Wait up to 1ms for the DMA to complete */ | |
316 | for (i = 0; ; i++) { | |
317 | status = readl(host->base + MMCISTATUS); | |
318 | if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) | |
319 | break; | |
320 | udelay(10); | |
321 | } | |
322 | ||
323 | /* | |
324 | * Check to see whether we still have some data left in the FIFO - | |
325 | * this catches DMA controllers which are unable to monitor the | |
326 | * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- | |
327 | * contiguous buffers. On TX, we'll get a FIFO underrun error. | |
328 | */ | |
329 | if (status & MCI_RXDATAAVLBLMASK) { | |
330 | dmaengine_terminate_all(chan); | |
331 | if (!data->error) | |
332 | data->error = -EIO; | |
333 | } | |
334 | ||
335 | if (data->flags & MMC_DATA_WRITE) { | |
336 | dir = DMA_TO_DEVICE; | |
337 | } else { | |
338 | dir = DMA_FROM_DEVICE; | |
339 | } | |
340 | ||
58c7ccbf PF |
341 | if (!data->host_cookie) |
342 | dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); | |
c8ebae37 RK |
343 | |
344 | /* | |
345 | * Use of DMA with scatter-gather is impossible. | |
346 | * Give up with DMA and switch back to PIO mode. | |
347 | */ | |
348 | if (status & MCI_RXDATAAVLBLMASK) { | |
349 | dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); | |
350 | mmci_dma_release(host); | |
351 | } | |
352 | } | |
353 | ||
354 | static void mmci_dma_data_error(struct mmci_host *host) | |
355 | { | |
356 | dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); | |
357 | dmaengine_terminate_all(host->dma_current); | |
358 | } | |
359 | ||
58c7ccbf PF |
360 | static int mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, |
361 | struct mmci_host_next *next) | |
c8ebae37 RK |
362 | { |
363 | struct variant_data *variant = host->variant; | |
364 | struct dma_slave_config conf = { | |
365 | .src_addr = host->phybase + MMCIFIFO, | |
366 | .dst_addr = host->phybase + MMCIFIFO, | |
367 | .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
368 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
369 | .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ | |
370 | .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ | |
371 | }; | |
c8ebae37 RK |
372 | struct dma_chan *chan; |
373 | struct dma_device *device; | |
374 | struct dma_async_tx_descriptor *desc; | |
375 | int nr_sg; | |
376 | ||
58c7ccbf PF |
377 | /* Check if next job is already prepared */ |
378 | if (data->host_cookie && !next && | |
379 | host->dma_current && host->dma_desc_current) | |
380 | return 0; | |
381 | ||
382 | if (!next) { | |
383 | host->dma_current = NULL; | |
384 | host->dma_desc_current = NULL; | |
385 | } | |
c8ebae37 RK |
386 | |
387 | if (data->flags & MMC_DATA_READ) { | |
388 | conf.direction = DMA_FROM_DEVICE; | |
389 | chan = host->dma_rx_channel; | |
390 | } else { | |
391 | conf.direction = DMA_TO_DEVICE; | |
392 | chan = host->dma_tx_channel; | |
393 | } | |
394 | ||
395 | /* If there's no DMA channel, fall back to PIO */ | |
396 | if (!chan) | |
397 | return -EINVAL; | |
398 | ||
399 | /* If less than or equal to the fifo size, don't bother with DMA */ | |
58c7ccbf | 400 | if (data->blksz * data->blocks <= variant->fifosize) |
c8ebae37 RK |
401 | return -EINVAL; |
402 | ||
403 | device = chan->device; | |
404 | nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, conf.direction); | |
405 | if (nr_sg == 0) | |
406 | return -EINVAL; | |
407 | ||
408 | dmaengine_slave_config(chan, &conf); | |
409 | desc = device->device_prep_slave_sg(chan, data->sg, nr_sg, | |
410 | conf.direction, DMA_CTRL_ACK); | |
411 | if (!desc) | |
412 | goto unmap_exit; | |
413 | ||
58c7ccbf PF |
414 | if (next) { |
415 | next->dma_chan = chan; | |
416 | next->dma_desc = desc; | |
417 | } else { | |
418 | host->dma_current = chan; | |
419 | host->dma_desc_current = desc; | |
420 | } | |
421 | ||
422 | return 0; | |
c8ebae37 | 423 | |
58c7ccbf PF |
424 | unmap_exit: |
425 | if (!next) | |
426 | dmaengine_terminate_all(chan); | |
427 | dma_unmap_sg(device->dev, data->sg, data->sg_len, conf.direction); | |
428 | return -ENOMEM; | |
429 | } | |
430 | ||
431 | static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) | |
432 | { | |
433 | int ret; | |
434 | struct mmc_data *data = host->data; | |
435 | ||
436 | ret = mmci_dma_prep_data(host, host->data, NULL); | |
437 | if (ret) | |
438 | return ret; | |
439 | ||
440 | /* Okay, go for it. */ | |
c8ebae37 RK |
441 | dev_vdbg(mmc_dev(host->mmc), |
442 | "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", | |
443 | data->sg_len, data->blksz, data->blocks, data->flags); | |
58c7ccbf PF |
444 | dmaengine_submit(host->dma_desc_current); |
445 | dma_async_issue_pending(host->dma_current); | |
c8ebae37 RK |
446 | |
447 | datactrl |= MCI_DPSM_DMAENABLE; | |
448 | ||
449 | /* Trigger the DMA transfer */ | |
450 | writel(datactrl, host->base + MMCIDATACTRL); | |
451 | ||
452 | /* | |
453 | * Let the MMCI say when the data is ended and it's time | |
454 | * to fire next DMA request. When that happens, MMCI will | |
455 | * call mmci_data_end() | |
456 | */ | |
457 | writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, | |
458 | host->base + MMCIMASK0); | |
459 | return 0; | |
58c7ccbf | 460 | } |
c8ebae37 | 461 | |
58c7ccbf PF |
462 | static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) |
463 | { | |
464 | struct mmci_host_next *next = &host->next_data; | |
465 | ||
466 | if (data->host_cookie && data->host_cookie != next->cookie) { | |
467 | printk(KERN_WARNING "[%s] invalid cookie: data->host_cookie %d" | |
468 | " host->next_data.cookie %d\n", | |
469 | __func__, data->host_cookie, host->next_data.cookie); | |
470 | data->host_cookie = 0; | |
471 | } | |
472 | ||
473 | if (!data->host_cookie) | |
474 | return; | |
475 | ||
476 | host->dma_desc_current = next->dma_desc; | |
477 | host->dma_current = next->dma_chan; | |
478 | ||
479 | next->dma_desc = NULL; | |
480 | next->dma_chan = NULL; | |
c8ebae37 | 481 | } |
58c7ccbf PF |
482 | |
483 | static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, | |
484 | bool is_first_req) | |
485 | { | |
486 | struct mmci_host *host = mmc_priv(mmc); | |
487 | struct mmc_data *data = mrq->data; | |
488 | struct mmci_host_next *nd = &host->next_data; | |
489 | ||
490 | if (!data) | |
491 | return; | |
492 | ||
493 | if (data->host_cookie) { | |
494 | data->host_cookie = 0; | |
495 | return; | |
496 | } | |
497 | ||
498 | /* if config for dma */ | |
499 | if (((data->flags & MMC_DATA_WRITE) && host->dma_tx_channel) || | |
500 | ((data->flags & MMC_DATA_READ) && host->dma_rx_channel)) { | |
501 | if (mmci_dma_prep_data(host, data, nd)) | |
502 | data->host_cookie = 0; | |
503 | else | |
504 | data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; | |
505 | } | |
506 | } | |
507 | ||
508 | static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, | |
509 | int err) | |
510 | { | |
511 | struct mmci_host *host = mmc_priv(mmc); | |
512 | struct mmc_data *data = mrq->data; | |
513 | struct dma_chan *chan; | |
514 | enum dma_data_direction dir; | |
515 | ||
516 | if (!data) | |
517 | return; | |
518 | ||
519 | if (data->flags & MMC_DATA_READ) { | |
520 | dir = DMA_FROM_DEVICE; | |
521 | chan = host->dma_rx_channel; | |
522 | } else { | |
523 | dir = DMA_TO_DEVICE; | |
524 | chan = host->dma_tx_channel; | |
525 | } | |
526 | ||
527 | ||
528 | /* if config for dma */ | |
529 | if (chan) { | |
530 | if (err) | |
531 | dmaengine_terminate_all(chan); | |
8e3336b1 | 532 | if (data->host_cookie) |
58c7ccbf PF |
533 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, |
534 | data->sg_len, dir); | |
535 | mrq->data->host_cookie = 0; | |
536 | } | |
537 | } | |
538 | ||
c8ebae37 RK |
539 | #else |
540 | /* Blank functions if the DMA engine is not available */ | |
58c7ccbf PF |
541 | static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) |
542 | { | |
543 | } | |
c8ebae37 RK |
544 | static inline void mmci_dma_setup(struct mmci_host *host) |
545 | { | |
546 | } | |
547 | ||
548 | static inline void mmci_dma_release(struct mmci_host *host) | |
549 | { | |
550 | } | |
551 | ||
552 | static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) | |
553 | { | |
554 | } | |
555 | ||
556 | static inline void mmci_dma_data_error(struct mmci_host *host) | |
557 | { | |
558 | } | |
559 | ||
560 | static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) | |
561 | { | |
562 | return -ENOSYS; | |
563 | } | |
58c7ccbf PF |
564 | |
565 | #define mmci_pre_request NULL | |
566 | #define mmci_post_request NULL | |
567 | ||
c8ebae37 RK |
568 | #endif |
569 | ||
1da177e4 LT |
570 | static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) |
571 | { | |
8301bb68 | 572 | struct variant_data *variant = host->variant; |
1da177e4 | 573 | unsigned int datactrl, timeout, irqmask; |
7b09cdac | 574 | unsigned long long clks; |
1da177e4 | 575 | void __iomem *base; |
3bc87f24 | 576 | int blksz_bits; |
1da177e4 | 577 | |
64de0289 LW |
578 | dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", |
579 | data->blksz, data->blocks, data->flags); | |
1da177e4 LT |
580 | |
581 | host->data = data; | |
528320db | 582 | host->size = data->blksz * data->blocks; |
51d4375d | 583 | data->bytes_xfered = 0; |
1da177e4 | 584 | |
7b09cdac RK |
585 | clks = (unsigned long long)data->timeout_ns * host->cclk; |
586 | do_div(clks, 1000000000UL); | |
587 | ||
588 | timeout = data->timeout_clks + (unsigned int)clks; | |
1da177e4 LT |
589 | |
590 | base = host->base; | |
591 | writel(timeout, base + MMCIDATATIMER); | |
592 | writel(host->size, base + MMCIDATALENGTH); | |
593 | ||
3bc87f24 RK |
594 | blksz_bits = ffs(data->blksz) - 1; |
595 | BUG_ON(1 << blksz_bits != data->blksz); | |
596 | ||
1784b157 PL |
597 | if (variant->blksz_datactrl16) |
598 | datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); | |
599 | else | |
600 | datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; | |
c8ebae37 RK |
601 | |
602 | if (data->flags & MMC_DATA_READ) | |
1da177e4 | 603 | datactrl |= MCI_DPSM_DIRECTION; |
c8ebae37 RK |
604 | |
605 | /* | |
606 | * Attempt to use DMA operation mode, if this | |
607 | * should fail, fall back to PIO mode | |
608 | */ | |
609 | if (!mmci_dma_start_data(host, datactrl)) | |
610 | return; | |
611 | ||
612 | /* IRQ mode, map the SG list for CPU reading/writing */ | |
613 | mmci_init_sg(host, data); | |
614 | ||
615 | if (data->flags & MMC_DATA_READ) { | |
1da177e4 | 616 | irqmask = MCI_RXFIFOHALFFULLMASK; |
0425a142 RK |
617 | |
618 | /* | |
c4d877c1 RK |
619 | * If we have less than the fifo 'half-full' threshold to |
620 | * transfer, trigger a PIO interrupt as soon as any data | |
621 | * is available. | |
0425a142 | 622 | */ |
c4d877c1 | 623 | if (host->size < variant->fifohalfsize) |
0425a142 | 624 | irqmask |= MCI_RXDATAAVLBLMASK; |
1da177e4 LT |
625 | } else { |
626 | /* | |
627 | * We don't actually need to include "FIFO empty" here | |
628 | * since its implicit in "FIFO half empty". | |
629 | */ | |
630 | irqmask = MCI_TXFIFOHALFEMPTYMASK; | |
631 | } | |
632 | ||
34177802 LW |
633 | /* The ST Micro variants has a special bit to enable SDIO */ |
634 | if (variant->sdio && host->mmc->card) | |
635 | if (mmc_card_sdio(host->mmc->card)) | |
636 | datactrl |= MCI_ST_DPSM_SDIOEN; | |
637 | ||
1da177e4 LT |
638 | writel(datactrl, base + MMCIDATACTRL); |
639 | writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); | |
2686b4b4 | 640 | mmci_set_mask1(host, irqmask); |
1da177e4 LT |
641 | } |
642 | ||
643 | static void | |
644 | mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) | |
645 | { | |
646 | void __iomem *base = host->base; | |
647 | ||
64de0289 | 648 | dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", |
1da177e4 LT |
649 | cmd->opcode, cmd->arg, cmd->flags); |
650 | ||
651 | if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { | |
652 | writel(0, base + MMCICOMMAND); | |
653 | udelay(1); | |
654 | } | |
655 | ||
656 | c |= cmd->opcode | MCI_CPSM_ENABLE; | |
e9225176 RK |
657 | if (cmd->flags & MMC_RSP_PRESENT) { |
658 | if (cmd->flags & MMC_RSP_136) | |
659 | c |= MCI_CPSM_LONGRSP; | |
1da177e4 | 660 | c |= MCI_CPSM_RESPONSE; |
1da177e4 LT |
661 | } |
662 | if (/*interrupt*/0) | |
663 | c |= MCI_CPSM_INTERRUPT; | |
664 | ||
665 | host->cmd = cmd; | |
666 | ||
667 | writel(cmd->arg, base + MMCIARGUMENT); | |
668 | writel(c, base + MMCICOMMAND); | |
669 | } | |
670 | ||
671 | static void | |
672 | mmci_data_irq(struct mmci_host *host, struct mmc_data *data, | |
673 | unsigned int status) | |
674 | { | |
f20f8f21 | 675 | /* First check for errors */ |
1da177e4 | 676 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) { |
8cb28155 | 677 | u32 remain, success; |
f20f8f21 | 678 | |
c8ebae37 RK |
679 | /* Terminate the DMA transfer */ |
680 | if (dma_inprogress(host)) | |
681 | mmci_dma_data_error(host); | |
e9c091b4 RK |
682 | |
683 | /* | |
c8afc9d5 RK |
684 | * Calculate how far we are into the transfer. Note that |
685 | * the data counter gives the number of bytes transferred | |
686 | * on the MMC bus, not on the host side. On reads, this | |
687 | * can be as much as a FIFO-worth of data ahead. This | |
688 | * matters for FIFO overruns only. | |
e9c091b4 | 689 | */ |
f5a106d9 | 690 | remain = readl(host->base + MMCIDATACNT); |
8cb28155 LW |
691 | success = data->blksz * data->blocks - remain; |
692 | ||
c8afc9d5 RK |
693 | dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", |
694 | status, success); | |
8cb28155 LW |
695 | if (status & MCI_DATACRCFAIL) { |
696 | /* Last block was not successful */ | |
c8afc9d5 | 697 | success -= 1; |
17b0429d | 698 | data->error = -EILSEQ; |
8cb28155 | 699 | } else if (status & MCI_DATATIMEOUT) { |
17b0429d | 700 | data->error = -ETIMEDOUT; |
757df746 LW |
701 | } else if (status & MCI_STARTBITERR) { |
702 | data->error = -ECOMM; | |
c8afc9d5 RK |
703 | } else if (status & MCI_TXUNDERRUN) { |
704 | data->error = -EIO; | |
705 | } else if (status & MCI_RXOVERRUN) { | |
706 | if (success > host->variant->fifosize) | |
707 | success -= host->variant->fifosize; | |
708 | else | |
709 | success = 0; | |
17b0429d | 710 | data->error = -EIO; |
4ce1d6cb | 711 | } |
51d4375d | 712 | data->bytes_xfered = round_down(success, data->blksz); |
1da177e4 | 713 | } |
f20f8f21 | 714 | |
8cb28155 LW |
715 | if (status & MCI_DATABLOCKEND) |
716 | dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); | |
f20f8f21 | 717 | |
ccff9b51 | 718 | if (status & MCI_DATAEND || data->error) { |
c8ebae37 RK |
719 | if (dma_inprogress(host)) |
720 | mmci_dma_unmap(host, data); | |
1da177e4 LT |
721 | mmci_stop_data(host); |
722 | ||
8cb28155 LW |
723 | if (!data->error) |
724 | /* The error clause is handled above, success! */ | |
51d4375d | 725 | data->bytes_xfered = data->blksz * data->blocks; |
f20f8f21 | 726 | |
1da177e4 LT |
727 | if (!data->stop) { |
728 | mmci_request_end(host, data->mrq); | |
729 | } else { | |
730 | mmci_start_command(host, data->stop, 0); | |
731 | } | |
732 | } | |
733 | } | |
734 | ||
735 | static void | |
736 | mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, | |
737 | unsigned int status) | |
738 | { | |
739 | void __iomem *base = host->base; | |
740 | ||
741 | host->cmd = NULL; | |
742 | ||
1da177e4 | 743 | if (status & MCI_CMDTIMEOUT) { |
17b0429d | 744 | cmd->error = -ETIMEDOUT; |
1da177e4 | 745 | } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { |
17b0429d | 746 | cmd->error = -EILSEQ; |
9047b435 RKAL |
747 | } else { |
748 | cmd->resp[0] = readl(base + MMCIRESPONSE0); | |
749 | cmd->resp[1] = readl(base + MMCIRESPONSE1); | |
750 | cmd->resp[2] = readl(base + MMCIRESPONSE2); | |
751 | cmd->resp[3] = readl(base + MMCIRESPONSE3); | |
1da177e4 LT |
752 | } |
753 | ||
17b0429d | 754 | if (!cmd->data || cmd->error) { |
e47c222b RK |
755 | if (host->data) |
756 | mmci_stop_data(host); | |
1da177e4 LT |
757 | mmci_request_end(host, cmd->mrq); |
758 | } else if (!(cmd->data->flags & MMC_DATA_READ)) { | |
759 | mmci_start_data(host, cmd->data); | |
760 | } | |
761 | } | |
762 | ||
763 | static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) | |
764 | { | |
765 | void __iomem *base = host->base; | |
766 | char *ptr = buffer; | |
767 | u32 status; | |
26eed9a5 | 768 | int host_remain = host->size; |
1da177e4 LT |
769 | |
770 | do { | |
26eed9a5 | 771 | int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); |
1da177e4 LT |
772 | |
773 | if (count > remain) | |
774 | count = remain; | |
775 | ||
776 | if (count <= 0) | |
777 | break; | |
778 | ||
779 | readsl(base + MMCIFIFO, ptr, count >> 2); | |
780 | ||
781 | ptr += count; | |
782 | remain -= count; | |
26eed9a5 | 783 | host_remain -= count; |
1da177e4 LT |
784 | |
785 | if (remain == 0) | |
786 | break; | |
787 | ||
788 | status = readl(base + MMCISTATUS); | |
789 | } while (status & MCI_RXDATAAVLBL); | |
790 | ||
791 | return ptr - buffer; | |
792 | } | |
793 | ||
794 | static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) | |
795 | { | |
8301bb68 | 796 | struct variant_data *variant = host->variant; |
1da177e4 LT |
797 | void __iomem *base = host->base; |
798 | char *ptr = buffer; | |
799 | ||
800 | do { | |
801 | unsigned int count, maxcnt; | |
802 | ||
8301bb68 RV |
803 | maxcnt = status & MCI_TXFIFOEMPTY ? |
804 | variant->fifosize : variant->fifohalfsize; | |
1da177e4 LT |
805 | count = min(remain, maxcnt); |
806 | ||
34177802 LW |
807 | /* |
808 | * The ST Micro variant for SDIO transfer sizes | |
809 | * less then 8 bytes should have clock H/W flow | |
810 | * control disabled. | |
811 | */ | |
812 | if (variant->sdio && | |
813 | mmc_card_sdio(host->mmc->card)) { | |
814 | if (count < 8) | |
815 | writel(readl(host->base + MMCICLOCK) & | |
816 | ~variant->clkreg_enable, | |
817 | host->base + MMCICLOCK); | |
818 | else | |
819 | writel(readl(host->base + MMCICLOCK) | | |
820 | variant->clkreg_enable, | |
821 | host->base + MMCICLOCK); | |
822 | } | |
823 | ||
824 | /* | |
825 | * SDIO especially may want to send something that is | |
826 | * not divisible by 4 (as opposed to card sectors | |
827 | * etc), and the FIFO only accept full 32-bit writes. | |
828 | * So compensate by adding +3 on the count, a single | |
829 | * byte become a 32bit write, 7 bytes will be two | |
830 | * 32bit writes etc. | |
831 | */ | |
832 | writesl(base + MMCIFIFO, ptr, (count + 3) >> 2); | |
1da177e4 LT |
833 | |
834 | ptr += count; | |
835 | remain -= count; | |
836 | ||
837 | if (remain == 0) | |
838 | break; | |
839 | ||
840 | status = readl(base + MMCISTATUS); | |
841 | } while (status & MCI_TXFIFOHALFEMPTY); | |
842 | ||
843 | return ptr - buffer; | |
844 | } | |
845 | ||
846 | /* | |
847 | * PIO data transfer IRQ handler. | |
848 | */ | |
7d12e780 | 849 | static irqreturn_t mmci_pio_irq(int irq, void *dev_id) |
1da177e4 LT |
850 | { |
851 | struct mmci_host *host = dev_id; | |
4ce1d6cb | 852 | struct sg_mapping_iter *sg_miter = &host->sg_miter; |
8301bb68 | 853 | struct variant_data *variant = host->variant; |
1da177e4 | 854 | void __iomem *base = host->base; |
4ce1d6cb | 855 | unsigned long flags; |
1da177e4 LT |
856 | u32 status; |
857 | ||
858 | status = readl(base + MMCISTATUS); | |
859 | ||
64de0289 | 860 | dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); |
1da177e4 | 861 | |
4ce1d6cb RV |
862 | local_irq_save(flags); |
863 | ||
1da177e4 | 864 | do { |
1da177e4 LT |
865 | unsigned int remain, len; |
866 | char *buffer; | |
867 | ||
868 | /* | |
869 | * For write, we only need to test the half-empty flag | |
870 | * here - if the FIFO is completely empty, then by | |
871 | * definition it is more than half empty. | |
872 | * | |
873 | * For read, check for data available. | |
874 | */ | |
875 | if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) | |
876 | break; | |
877 | ||
4ce1d6cb RV |
878 | if (!sg_miter_next(sg_miter)) |
879 | break; | |
880 | ||
881 | buffer = sg_miter->addr; | |
882 | remain = sg_miter->length; | |
1da177e4 LT |
883 | |
884 | len = 0; | |
885 | if (status & MCI_RXACTIVE) | |
886 | len = mmci_pio_read(host, buffer, remain); | |
887 | if (status & MCI_TXACTIVE) | |
888 | len = mmci_pio_write(host, buffer, remain, status); | |
889 | ||
4ce1d6cb | 890 | sg_miter->consumed = len; |
1da177e4 | 891 | |
1da177e4 LT |
892 | host->size -= len; |
893 | remain -= len; | |
894 | ||
895 | if (remain) | |
896 | break; | |
897 | ||
1da177e4 LT |
898 | status = readl(base + MMCISTATUS); |
899 | } while (1); | |
900 | ||
4ce1d6cb RV |
901 | sg_miter_stop(sg_miter); |
902 | ||
903 | local_irq_restore(flags); | |
904 | ||
1da177e4 | 905 | /* |
c4d877c1 RK |
906 | * If we have less than the fifo 'half-full' threshold to transfer, |
907 | * trigger a PIO interrupt as soon as any data is available. | |
1da177e4 | 908 | */ |
c4d877c1 | 909 | if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) |
2686b4b4 | 910 | mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); |
1da177e4 LT |
911 | |
912 | /* | |
913 | * If we run out of data, disable the data IRQs; this | |
914 | * prevents a race where the FIFO becomes empty before | |
915 | * the chip itself has disabled the data path, and | |
916 | * stops us racing with our data end IRQ. | |
917 | */ | |
918 | if (host->size == 0) { | |
2686b4b4 | 919 | mmci_set_mask1(host, 0); |
1da177e4 LT |
920 | writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); |
921 | } | |
922 | ||
923 | return IRQ_HANDLED; | |
924 | } | |
925 | ||
926 | /* | |
927 | * Handle completion of command and data transfers. | |
928 | */ | |
7d12e780 | 929 | static irqreturn_t mmci_irq(int irq, void *dev_id) |
1da177e4 LT |
930 | { |
931 | struct mmci_host *host = dev_id; | |
932 | u32 status; | |
933 | int ret = 0; | |
934 | ||
935 | spin_lock(&host->lock); | |
936 | ||
937 | do { | |
938 | struct mmc_command *cmd; | |
939 | struct mmc_data *data; | |
940 | ||
941 | status = readl(host->base + MMCISTATUS); | |
2686b4b4 LW |
942 | |
943 | if (host->singleirq) { | |
944 | if (status & readl(host->base + MMCIMASK1)) | |
945 | mmci_pio_irq(irq, dev_id); | |
946 | ||
947 | status &= ~MCI_IRQ1MASK; | |
948 | } | |
949 | ||
1da177e4 LT |
950 | status &= readl(host->base + MMCIMASK0); |
951 | writel(status, host->base + MMCICLEAR); | |
952 | ||
64de0289 | 953 | dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); |
1da177e4 LT |
954 | |
955 | data = host->data; | |
956 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN| | |
957 | MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data) | |
958 | mmci_data_irq(host, data, status); | |
959 | ||
960 | cmd = host->cmd; | |
961 | if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) | |
962 | mmci_cmd_irq(host, cmd, status); | |
963 | ||
964 | ret = 1; | |
965 | } while (status); | |
966 | ||
967 | spin_unlock(&host->lock); | |
968 | ||
969 | return IRQ_RETVAL(ret); | |
970 | } | |
971 | ||
972 | static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
973 | { | |
974 | struct mmci_host *host = mmc_priv(mmc); | |
9e943021 | 975 | unsigned long flags; |
1da177e4 LT |
976 | |
977 | WARN_ON(host->mrq != NULL); | |
978 | ||
019a5f56 | 979 | if (mrq->data && !is_power_of_2(mrq->data->blksz)) { |
64de0289 LW |
980 | dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", |
981 | mrq->data->blksz); | |
255d01af PO |
982 | mrq->cmd->error = -EINVAL; |
983 | mmc_request_done(mmc, mrq); | |
984 | return; | |
985 | } | |
986 | ||
9e943021 | 987 | spin_lock_irqsave(&host->lock, flags); |
1da177e4 LT |
988 | |
989 | host->mrq = mrq; | |
990 | ||
58c7ccbf PF |
991 | if (mrq->data) |
992 | mmci_get_next_data(host, mrq->data); | |
993 | ||
1da177e4 LT |
994 | if (mrq->data && mrq->data->flags & MMC_DATA_READ) |
995 | mmci_start_data(host, mrq->data); | |
996 | ||
997 | mmci_start_command(host, mrq->cmd, 0); | |
998 | ||
9e943021 | 999 | spin_unlock_irqrestore(&host->lock, flags); |
1da177e4 LT |
1000 | } |
1001 | ||
1002 | static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
1003 | { | |
1004 | struct mmci_host *host = mmc_priv(mmc); | |
a6a6464a LW |
1005 | u32 pwr = 0; |
1006 | unsigned long flags; | |
99fc5131 | 1007 | int ret; |
1da177e4 | 1008 | |
1da177e4 LT |
1009 | switch (ios->power_mode) { |
1010 | case MMC_POWER_OFF: | |
99fc5131 LW |
1011 | if (host->vcc) |
1012 | ret = mmc_regulator_set_ocr(mmc, host->vcc, 0); | |
1da177e4 LT |
1013 | break; |
1014 | case MMC_POWER_UP: | |
99fc5131 LW |
1015 | if (host->vcc) { |
1016 | ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd); | |
1017 | if (ret) { | |
1018 | dev_err(mmc_dev(mmc), "unable to set OCR\n"); | |
1019 | /* | |
1020 | * The .set_ios() function in the mmc_host_ops | |
1021 | * struct return void, and failing to set the | |
1022 | * power should be rare so we print an error | |
1023 | * and return here. | |
1024 | */ | |
1025 | return; | |
1026 | } | |
1027 | } | |
bb8f563c RV |
1028 | if (host->plat->vdd_handler) |
1029 | pwr |= host->plat->vdd_handler(mmc_dev(mmc), ios->vdd, | |
1030 | ios->power_mode); | |
cc30d60e | 1031 | /* The ST version does not have this, fall through to POWER_ON */ |
f17a1f06 | 1032 | if (host->hw_designer != AMBA_VENDOR_ST) { |
cc30d60e LW |
1033 | pwr |= MCI_PWR_UP; |
1034 | break; | |
1035 | } | |
1da177e4 LT |
1036 | case MMC_POWER_ON: |
1037 | pwr |= MCI_PWR_ON; | |
1038 | break; | |
1039 | } | |
1040 | ||
cc30d60e | 1041 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { |
f17a1f06 | 1042 | if (host->hw_designer != AMBA_VENDOR_ST) |
cc30d60e LW |
1043 | pwr |= MCI_ROD; |
1044 | else { | |
1045 | /* | |
1046 | * The ST Micro variant use the ROD bit for something | |
1047 | * else and only has OD (Open Drain). | |
1048 | */ | |
1049 | pwr |= MCI_OD; | |
1050 | } | |
1051 | } | |
1da177e4 | 1052 | |
a6a6464a LW |
1053 | spin_lock_irqsave(&host->lock, flags); |
1054 | ||
1055 | mmci_set_clkreg(host, ios->clock); | |
1da177e4 LT |
1056 | |
1057 | if (host->pwr != pwr) { | |
1058 | host->pwr = pwr; | |
1059 | writel(pwr, host->base + MMCIPOWER); | |
1060 | } | |
a6a6464a LW |
1061 | |
1062 | spin_unlock_irqrestore(&host->lock, flags); | |
1da177e4 LT |
1063 | } |
1064 | ||
89001446 RK |
1065 | static int mmci_get_ro(struct mmc_host *mmc) |
1066 | { | |
1067 | struct mmci_host *host = mmc_priv(mmc); | |
1068 | ||
1069 | if (host->gpio_wp == -ENOSYS) | |
1070 | return -ENOSYS; | |
1071 | ||
18a06301 | 1072 | return gpio_get_value_cansleep(host->gpio_wp); |
89001446 RK |
1073 | } |
1074 | ||
1075 | static int mmci_get_cd(struct mmc_host *mmc) | |
1076 | { | |
1077 | struct mmci_host *host = mmc_priv(mmc); | |
29719445 | 1078 | struct mmci_platform_data *plat = host->plat; |
89001446 RK |
1079 | unsigned int status; |
1080 | ||
4b8caec0 RV |
1081 | if (host->gpio_cd == -ENOSYS) { |
1082 | if (!plat->status) | |
1083 | return 1; /* Assume always present */ | |
1084 | ||
29719445 | 1085 | status = plat->status(mmc_dev(host->mmc)); |
4b8caec0 | 1086 | } else |
18a06301 LW |
1087 | status = !!gpio_get_value_cansleep(host->gpio_cd) |
1088 | ^ plat->cd_invert; | |
89001446 | 1089 | |
74bc8093 RK |
1090 | /* |
1091 | * Use positive logic throughout - status is zero for no card, | |
1092 | * non-zero for card inserted. | |
1093 | */ | |
1094 | return status; | |
89001446 RK |
1095 | } |
1096 | ||
148b8b39 RV |
1097 | static irqreturn_t mmci_cd_irq(int irq, void *dev_id) |
1098 | { | |
1099 | struct mmci_host *host = dev_id; | |
1100 | ||
1101 | mmc_detect_change(host->mmc, msecs_to_jiffies(500)); | |
1102 | ||
1103 | return IRQ_HANDLED; | |
1104 | } | |
1105 | ||
ab7aefd0 | 1106 | static const struct mmc_host_ops mmci_ops = { |
1da177e4 | 1107 | .request = mmci_request, |
58c7ccbf PF |
1108 | .pre_req = mmci_pre_request, |
1109 | .post_req = mmci_post_request, | |
1da177e4 | 1110 | .set_ios = mmci_set_ios, |
89001446 RK |
1111 | .get_ro = mmci_get_ro, |
1112 | .get_cd = mmci_get_cd, | |
1da177e4 LT |
1113 | }; |
1114 | ||
aa25afad RK |
1115 | static int __devinit mmci_probe(struct amba_device *dev, |
1116 | const struct amba_id *id) | |
1da177e4 | 1117 | { |
6ef297f8 | 1118 | struct mmci_platform_data *plat = dev->dev.platform_data; |
4956e109 | 1119 | struct variant_data *variant = id->data; |
1da177e4 LT |
1120 | struct mmci_host *host; |
1121 | struct mmc_host *mmc; | |
1122 | int ret; | |
1123 | ||
1124 | /* must have platform data */ | |
1125 | if (!plat) { | |
1126 | ret = -EINVAL; | |
1127 | goto out; | |
1128 | } | |
1129 | ||
1130 | ret = amba_request_regions(dev, DRIVER_NAME); | |
1131 | if (ret) | |
1132 | goto out; | |
1133 | ||
1134 | mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); | |
1135 | if (!mmc) { | |
1136 | ret = -ENOMEM; | |
1137 | goto rel_regions; | |
1138 | } | |
1139 | ||
1140 | host = mmc_priv(mmc); | |
4ea580f1 | 1141 | host->mmc = mmc; |
012b7d33 | 1142 | |
89001446 RK |
1143 | host->gpio_wp = -ENOSYS; |
1144 | host->gpio_cd = -ENOSYS; | |
148b8b39 | 1145 | host->gpio_cd_irq = -1; |
89001446 | 1146 | |
012b7d33 RK |
1147 | host->hw_designer = amba_manf(dev); |
1148 | host->hw_revision = amba_rev(dev); | |
64de0289 LW |
1149 | dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); |
1150 | dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); | |
012b7d33 | 1151 | |
ee569c43 | 1152 | host->clk = clk_get(&dev->dev, NULL); |
1da177e4 LT |
1153 | if (IS_ERR(host->clk)) { |
1154 | ret = PTR_ERR(host->clk); | |
1155 | host->clk = NULL; | |
1156 | goto host_free; | |
1157 | } | |
1158 | ||
1da177e4 LT |
1159 | ret = clk_enable(host->clk); |
1160 | if (ret) | |
a8d3584a | 1161 | goto clk_free; |
1da177e4 LT |
1162 | |
1163 | host->plat = plat; | |
4956e109 | 1164 | host->variant = variant; |
1da177e4 | 1165 | host->mclk = clk_get_rate(host->clk); |
c8df9a53 LW |
1166 | /* |
1167 | * According to the spec, mclk is max 100 MHz, | |
1168 | * so we try to adjust the clock down to this, | |
1169 | * (if possible). | |
1170 | */ | |
1171 | if (host->mclk > 100000000) { | |
1172 | ret = clk_set_rate(host->clk, 100000000); | |
1173 | if (ret < 0) | |
1174 | goto clk_disable; | |
1175 | host->mclk = clk_get_rate(host->clk); | |
64de0289 LW |
1176 | dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", |
1177 | host->mclk); | |
c8df9a53 | 1178 | } |
c8ebae37 | 1179 | host->phybase = dev->res.start; |
dc890c2d | 1180 | host->base = ioremap(dev->res.start, resource_size(&dev->res)); |
1da177e4 LT |
1181 | if (!host->base) { |
1182 | ret = -ENOMEM; | |
1183 | goto clk_disable; | |
1184 | } | |
1185 | ||
1186 | mmc->ops = &mmci_ops; | |
7f294e49 LW |
1187 | /* |
1188 | * The ARM and ST versions of the block have slightly different | |
1189 | * clock divider equations which means that the minimum divider | |
1190 | * differs too. | |
1191 | */ | |
1192 | if (variant->st_clkdiv) | |
1193 | mmc->f_min = DIV_ROUND_UP(host->mclk, 257); | |
1194 | else | |
1195 | mmc->f_min = DIV_ROUND_UP(host->mclk, 512); | |
808d97cc LW |
1196 | /* |
1197 | * If the platform data supplies a maximum operating | |
1198 | * frequency, this takes precedence. Else, we fall back | |
1199 | * to using the module parameter, which has a (low) | |
1200 | * default value in case it is not specified. Either | |
1201 | * value must not exceed the clock rate into the block, | |
1202 | * of course. | |
1203 | */ | |
1204 | if (plat->f_max) | |
1205 | mmc->f_max = min(host->mclk, plat->f_max); | |
1206 | else | |
1207 | mmc->f_max = min(host->mclk, fmax); | |
64de0289 LW |
1208 | dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); |
1209 | ||
34e84f39 LW |
1210 | #ifdef CONFIG_REGULATOR |
1211 | /* If we're using the regulator framework, try to fetch a regulator */ | |
1212 | host->vcc = regulator_get(&dev->dev, "vmmc"); | |
1213 | if (IS_ERR(host->vcc)) | |
1214 | host->vcc = NULL; | |
1215 | else { | |
1216 | int mask = mmc_regulator_get_ocrmask(host->vcc); | |
1217 | ||
1218 | if (mask < 0) | |
1219 | dev_err(&dev->dev, "error getting OCR mask (%d)\n", | |
1220 | mask); | |
1221 | else { | |
1222 | host->mmc->ocr_avail = (u32) mask; | |
1223 | if (plat->ocr_mask) | |
1224 | dev_warn(&dev->dev, | |
1225 | "Provided ocr_mask/setpower will not be used " | |
1226 | "(using regulator instead)\n"); | |
1227 | } | |
1228 | } | |
1229 | #endif | |
1230 | /* Fall back to platform data if no regulator is found */ | |
1231 | if (host->vcc == NULL) | |
1232 | mmc->ocr_avail = plat->ocr_mask; | |
9e6c82cd | 1233 | mmc->caps = plat->capabilities; |
1da177e4 LT |
1234 | |
1235 | /* | |
1236 | * We can do SGIO | |
1237 | */ | |
a36274e0 | 1238 | mmc->max_segs = NR_SG; |
1da177e4 LT |
1239 | |
1240 | /* | |
08458ef6 RV |
1241 | * Since only a certain number of bits are valid in the data length |
1242 | * register, we must ensure that we don't exceed 2^num-1 bytes in a | |
1243 | * single request. | |
1da177e4 | 1244 | */ |
08458ef6 | 1245 | mmc->max_req_size = (1 << variant->datalength_bits) - 1; |
1da177e4 LT |
1246 | |
1247 | /* | |
1248 | * Set the maximum segment size. Since we aren't doing DMA | |
1249 | * (yet) we are only limited by the data length register. | |
1250 | */ | |
55db890a | 1251 | mmc->max_seg_size = mmc->max_req_size; |
1da177e4 | 1252 | |
fe4a3c7a PO |
1253 | /* |
1254 | * Block size can be up to 2048 bytes, but must be a power of two. | |
1255 | */ | |
1256 | mmc->max_blk_size = 2048; | |
1257 | ||
55db890a PO |
1258 | /* |
1259 | * No limit on the number of blocks transferred. | |
1260 | */ | |
1261 | mmc->max_blk_count = mmc->max_req_size; | |
1262 | ||
1da177e4 LT |
1263 | spin_lock_init(&host->lock); |
1264 | ||
1265 | writel(0, host->base + MMCIMASK0); | |
1266 | writel(0, host->base + MMCIMASK1); | |
1267 | writel(0xfff, host->base + MMCICLEAR); | |
1268 | ||
89001446 RK |
1269 | if (gpio_is_valid(plat->gpio_cd)) { |
1270 | ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); | |
1271 | if (ret == 0) | |
1272 | ret = gpio_direction_input(plat->gpio_cd); | |
1273 | if (ret == 0) | |
1274 | host->gpio_cd = plat->gpio_cd; | |
1275 | else if (ret != -ENOSYS) | |
1276 | goto err_gpio_cd; | |
148b8b39 | 1277 | |
17ee083b LW |
1278 | /* |
1279 | * A gpio pin that will detect cards when inserted and removed | |
1280 | * will most likely want to trigger on the edges if it is | |
1281 | * 0 when ejected and 1 when inserted (or mutatis mutandis | |
1282 | * for the inverted case) so we request triggers on both | |
1283 | * edges. | |
1284 | */ | |
148b8b39 | 1285 | ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), |
17ee083b LW |
1286 | mmci_cd_irq, |
1287 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, | |
1288 | DRIVER_NAME " (cd)", host); | |
148b8b39 RV |
1289 | if (ret >= 0) |
1290 | host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); | |
89001446 RK |
1291 | } |
1292 | if (gpio_is_valid(plat->gpio_wp)) { | |
1293 | ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); | |
1294 | if (ret == 0) | |
1295 | ret = gpio_direction_input(plat->gpio_wp); | |
1296 | if (ret == 0) | |
1297 | host->gpio_wp = plat->gpio_wp; | |
1298 | else if (ret != -ENOSYS) | |
1299 | goto err_gpio_wp; | |
1300 | } | |
1301 | ||
4b8caec0 RV |
1302 | if ((host->plat->status || host->gpio_cd != -ENOSYS) |
1303 | && host->gpio_cd_irq < 0) | |
148b8b39 RV |
1304 | mmc->caps |= MMC_CAP_NEEDS_POLL; |
1305 | ||
dace1453 | 1306 | ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); |
1da177e4 LT |
1307 | if (ret) |
1308 | goto unmap; | |
1309 | ||
2686b4b4 LW |
1310 | if (dev->irq[1] == NO_IRQ) |
1311 | host->singleirq = true; | |
1312 | else { | |
1313 | ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, | |
1314 | DRIVER_NAME " (pio)", host); | |
1315 | if (ret) | |
1316 | goto irq0_free; | |
1317 | } | |
1da177e4 | 1318 | |
8cb28155 | 1319 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); |
1da177e4 LT |
1320 | |
1321 | amba_set_drvdata(dev, mmc); | |
1322 | ||
c8ebae37 RK |
1323 | dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", |
1324 | mmc_hostname(mmc), amba_part(dev), amba_manf(dev), | |
1325 | amba_rev(dev), (unsigned long long)dev->res.start, | |
1326 | dev->irq[0], dev->irq[1]); | |
1327 | ||
1328 | mmci_dma_setup(host); | |
1da177e4 | 1329 | |
8c11a94d RK |
1330 | mmc_add_host(mmc); |
1331 | ||
1da177e4 LT |
1332 | return 0; |
1333 | ||
1334 | irq0_free: | |
1335 | free_irq(dev->irq[0], host); | |
1336 | unmap: | |
89001446 RK |
1337 | if (host->gpio_wp != -ENOSYS) |
1338 | gpio_free(host->gpio_wp); | |
1339 | err_gpio_wp: | |
148b8b39 RV |
1340 | if (host->gpio_cd_irq >= 0) |
1341 | free_irq(host->gpio_cd_irq, host); | |
89001446 RK |
1342 | if (host->gpio_cd != -ENOSYS) |
1343 | gpio_free(host->gpio_cd); | |
1344 | err_gpio_cd: | |
1da177e4 LT |
1345 | iounmap(host->base); |
1346 | clk_disable: | |
1347 | clk_disable(host->clk); | |
1da177e4 LT |
1348 | clk_free: |
1349 | clk_put(host->clk); | |
1350 | host_free: | |
1351 | mmc_free_host(mmc); | |
1352 | rel_regions: | |
1353 | amba_release_regions(dev); | |
1354 | out: | |
1355 | return ret; | |
1356 | } | |
1357 | ||
6dc4a47a | 1358 | static int __devexit mmci_remove(struct amba_device *dev) |
1da177e4 LT |
1359 | { |
1360 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
1361 | ||
1362 | amba_set_drvdata(dev, NULL); | |
1363 | ||
1364 | if (mmc) { | |
1365 | struct mmci_host *host = mmc_priv(mmc); | |
1366 | ||
1da177e4 LT |
1367 | mmc_remove_host(mmc); |
1368 | ||
1369 | writel(0, host->base + MMCIMASK0); | |
1370 | writel(0, host->base + MMCIMASK1); | |
1371 | ||
1372 | writel(0, host->base + MMCICOMMAND); | |
1373 | writel(0, host->base + MMCIDATACTRL); | |
1374 | ||
c8ebae37 | 1375 | mmci_dma_release(host); |
1da177e4 | 1376 | free_irq(dev->irq[0], host); |
2686b4b4 LW |
1377 | if (!host->singleirq) |
1378 | free_irq(dev->irq[1], host); | |
1da177e4 | 1379 | |
89001446 RK |
1380 | if (host->gpio_wp != -ENOSYS) |
1381 | gpio_free(host->gpio_wp); | |
148b8b39 RV |
1382 | if (host->gpio_cd_irq >= 0) |
1383 | free_irq(host->gpio_cd_irq, host); | |
89001446 RK |
1384 | if (host->gpio_cd != -ENOSYS) |
1385 | gpio_free(host->gpio_cd); | |
1386 | ||
1da177e4 LT |
1387 | iounmap(host->base); |
1388 | clk_disable(host->clk); | |
1da177e4 LT |
1389 | clk_put(host->clk); |
1390 | ||
99fc5131 LW |
1391 | if (host->vcc) |
1392 | mmc_regulator_set_ocr(mmc, host->vcc, 0); | |
34e84f39 LW |
1393 | regulator_put(host->vcc); |
1394 | ||
1da177e4 LT |
1395 | mmc_free_host(mmc); |
1396 | ||
1397 | amba_release_regions(dev); | |
1398 | } | |
1399 | ||
1400 | return 0; | |
1401 | } | |
1402 | ||
1403 | #ifdef CONFIG_PM | |
e5378ca8 | 1404 | static int mmci_suspend(struct amba_device *dev, pm_message_t state) |
1da177e4 LT |
1405 | { |
1406 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
1407 | int ret = 0; | |
1408 | ||
1409 | if (mmc) { | |
1410 | struct mmci_host *host = mmc_priv(mmc); | |
1411 | ||
1a13f8fa | 1412 | ret = mmc_suspend_host(mmc); |
1da177e4 LT |
1413 | if (ret == 0) |
1414 | writel(0, host->base + MMCIMASK0); | |
1415 | } | |
1416 | ||
1417 | return ret; | |
1418 | } | |
1419 | ||
1420 | static int mmci_resume(struct amba_device *dev) | |
1421 | { | |
1422 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
1423 | int ret = 0; | |
1424 | ||
1425 | if (mmc) { | |
1426 | struct mmci_host *host = mmc_priv(mmc); | |
1427 | ||
1428 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); | |
1429 | ||
1430 | ret = mmc_resume_host(mmc); | |
1431 | } | |
1432 | ||
1433 | return ret; | |
1434 | } | |
1435 | #else | |
1436 | #define mmci_suspend NULL | |
1437 | #define mmci_resume NULL | |
1438 | #endif | |
1439 | ||
1440 | static struct amba_id mmci_ids[] = { | |
1441 | { | |
1442 | .id = 0x00041180, | |
768fbc18 | 1443 | .mask = 0xff0fffff, |
4956e109 | 1444 | .data = &variant_arm, |
1da177e4 | 1445 | }, |
768fbc18 PM |
1446 | { |
1447 | .id = 0x01041180, | |
1448 | .mask = 0xff0fffff, | |
1449 | .data = &variant_arm_extended_fifo, | |
1450 | }, | |
1da177e4 LT |
1451 | { |
1452 | .id = 0x00041181, | |
1453 | .mask = 0x000fffff, | |
4956e109 | 1454 | .data = &variant_arm, |
1da177e4 | 1455 | }, |
cc30d60e LW |
1456 | /* ST Micro variants */ |
1457 | { | |
1458 | .id = 0x00180180, | |
1459 | .mask = 0x00ffffff, | |
4956e109 | 1460 | .data = &variant_u300, |
cc30d60e LW |
1461 | }, |
1462 | { | |
1463 | .id = 0x00280180, | |
1464 | .mask = 0x00ffffff, | |
4956e109 RV |
1465 | .data = &variant_u300, |
1466 | }, | |
1467 | { | |
1468 | .id = 0x00480180, | |
1784b157 | 1469 | .mask = 0xf0ffffff, |
4956e109 | 1470 | .data = &variant_ux500, |
cc30d60e | 1471 | }, |
1784b157 PL |
1472 | { |
1473 | .id = 0x10480180, | |
1474 | .mask = 0xf0ffffff, | |
1475 | .data = &variant_ux500v2, | |
1476 | }, | |
1da177e4 LT |
1477 | { 0, 0 }, |
1478 | }; | |
1479 | ||
1480 | static struct amba_driver mmci_driver = { | |
1481 | .drv = { | |
1482 | .name = DRIVER_NAME, | |
1483 | }, | |
1484 | .probe = mmci_probe, | |
6dc4a47a | 1485 | .remove = __devexit_p(mmci_remove), |
1da177e4 LT |
1486 | .suspend = mmci_suspend, |
1487 | .resume = mmci_resume, | |
1488 | .id_table = mmci_ids, | |
1489 | }; | |
1490 | ||
1491 | static int __init mmci_init(void) | |
1492 | { | |
1493 | return amba_driver_register(&mmci_driver); | |
1494 | } | |
1495 | ||
1496 | static void __exit mmci_exit(void) | |
1497 | { | |
1498 | amba_driver_unregister(&mmci_driver); | |
1499 | } | |
1500 | ||
1501 | module_init(mmci_init); | |
1502 | module_exit(mmci_exit); | |
1503 | module_param(fmax, uint, 0444); | |
1504 | ||
1505 | MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); | |
1506 | MODULE_LICENSE("GPL"); |