Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. | |
64de0289 | 5 | * Copyright (C) 2010 ST-Ericsson AB. |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/highmem.h> | |
019a5f56 | 20 | #include <linux/log2.h> |
1da177e4 | 21 | #include <linux/mmc/host.h> |
a62c80e5 | 22 | #include <linux/amba/bus.h> |
f8ce2547 | 23 | #include <linux/clk.h> |
bd6dee6f | 24 | #include <linux/scatterlist.h> |
89001446 | 25 | #include <linux/gpio.h> |
6ef297f8 | 26 | #include <linux/amba/mmci.h> |
34e84f39 | 27 | #include <linux/regulator/consumer.h> |
1da177e4 | 28 | |
e9c091b4 | 29 | #include <asm/cacheflush.h> |
7b09cdac | 30 | #include <asm/div64.h> |
1da177e4 | 31 | #include <asm/io.h> |
c6b8fdad | 32 | #include <asm/sizes.h> |
1da177e4 LT |
33 | |
34 | #include "mmci.h" | |
35 | ||
36 | #define DRIVER_NAME "mmci-pl18x" | |
37 | ||
1da177e4 LT |
38 | static unsigned int fmax = 515633; |
39 | ||
a6a6464a LW |
40 | /* |
41 | * This must be called with host->lock held | |
42 | */ | |
43 | static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) | |
44 | { | |
45 | u32 clk = 0; | |
46 | ||
47 | if (desired) { | |
48 | if (desired >= host->mclk) { | |
49 | clk = MCI_CLK_BYPASS; | |
50 | host->cclk = host->mclk; | |
51 | } else { | |
52 | clk = host->mclk / (2 * desired) - 1; | |
53 | if (clk >= 256) | |
54 | clk = 255; | |
55 | host->cclk = host->mclk / (2 * (clk + 1)); | |
56 | } | |
b43149c1 | 57 | if (host->hw_designer == AMBA_VENDOR_ST) |
a6a6464a LW |
58 | clk |= MCI_FCEN; /* Bug fix in ST IP block */ |
59 | clk |= MCI_CLK_ENABLE; | |
60 | /* This hasn't proven to be worthwhile */ | |
61 | /* clk |= MCI_CLK_PWRSAVE; */ | |
62 | } | |
63 | ||
9e6c82cd LW |
64 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) |
65 | clk |= MCI_WIDE_BUS; | |
66 | ||
a6a6464a LW |
67 | writel(clk, host->base + MMCICLOCK); |
68 | } | |
69 | ||
1da177e4 LT |
70 | static void |
71 | mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) | |
72 | { | |
73 | writel(0, host->base + MMCICOMMAND); | |
74 | ||
e47c222b RK |
75 | BUG_ON(host->data); |
76 | ||
1da177e4 LT |
77 | host->mrq = NULL; |
78 | host->cmd = NULL; | |
79 | ||
80 | if (mrq->data) | |
81 | mrq->data->bytes_xfered = host->data_xfered; | |
82 | ||
83 | /* | |
84 | * Need to drop the host lock here; mmc_request_done may call | |
85 | * back into the driver... | |
86 | */ | |
87 | spin_unlock(&host->lock); | |
88 | mmc_request_done(host->mmc, mrq); | |
89 | spin_lock(&host->lock); | |
90 | } | |
91 | ||
92 | static void mmci_stop_data(struct mmci_host *host) | |
93 | { | |
94 | writel(0, host->base + MMCIDATACTRL); | |
95 | writel(0, host->base + MMCIMASK1); | |
96 | host->data = NULL; | |
97 | } | |
98 | ||
99 | static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) | |
100 | { | |
101 | unsigned int datactrl, timeout, irqmask; | |
7b09cdac | 102 | unsigned long long clks; |
1da177e4 | 103 | void __iomem *base; |
3bc87f24 | 104 | int blksz_bits; |
1da177e4 | 105 | |
64de0289 LW |
106 | dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", |
107 | data->blksz, data->blocks, data->flags); | |
1da177e4 LT |
108 | |
109 | host->data = data; | |
3bc87f24 | 110 | host->size = data->blksz; |
1da177e4 LT |
111 | host->data_xfered = 0; |
112 | ||
113 | mmci_init_sg(host, data); | |
114 | ||
7b09cdac RK |
115 | clks = (unsigned long long)data->timeout_ns * host->cclk; |
116 | do_div(clks, 1000000000UL); | |
117 | ||
118 | timeout = data->timeout_clks + (unsigned int)clks; | |
1da177e4 LT |
119 | |
120 | base = host->base; | |
121 | writel(timeout, base + MMCIDATATIMER); | |
122 | writel(host->size, base + MMCIDATALENGTH); | |
123 | ||
3bc87f24 RK |
124 | blksz_bits = ffs(data->blksz) - 1; |
125 | BUG_ON(1 << blksz_bits != data->blksz); | |
126 | ||
127 | datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; | |
1da177e4 LT |
128 | if (data->flags & MMC_DATA_READ) { |
129 | datactrl |= MCI_DPSM_DIRECTION; | |
130 | irqmask = MCI_RXFIFOHALFFULLMASK; | |
0425a142 RK |
131 | |
132 | /* | |
133 | * If we have less than a FIFOSIZE of bytes to transfer, | |
134 | * trigger a PIO interrupt as soon as any data is available. | |
135 | */ | |
136 | if (host->size < MCI_FIFOSIZE) | |
137 | irqmask |= MCI_RXDATAAVLBLMASK; | |
1da177e4 LT |
138 | } else { |
139 | /* | |
140 | * We don't actually need to include "FIFO empty" here | |
141 | * since its implicit in "FIFO half empty". | |
142 | */ | |
143 | irqmask = MCI_TXFIFOHALFEMPTYMASK; | |
144 | } | |
145 | ||
146 | writel(datactrl, base + MMCIDATACTRL); | |
147 | writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); | |
148 | writel(irqmask, base + MMCIMASK1); | |
149 | } | |
150 | ||
151 | static void | |
152 | mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) | |
153 | { | |
154 | void __iomem *base = host->base; | |
155 | ||
64de0289 | 156 | dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", |
1da177e4 LT |
157 | cmd->opcode, cmd->arg, cmd->flags); |
158 | ||
159 | if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { | |
160 | writel(0, base + MMCICOMMAND); | |
161 | udelay(1); | |
162 | } | |
163 | ||
164 | c |= cmd->opcode | MCI_CPSM_ENABLE; | |
e9225176 RK |
165 | if (cmd->flags & MMC_RSP_PRESENT) { |
166 | if (cmd->flags & MMC_RSP_136) | |
167 | c |= MCI_CPSM_LONGRSP; | |
1da177e4 | 168 | c |= MCI_CPSM_RESPONSE; |
1da177e4 LT |
169 | } |
170 | if (/*interrupt*/0) | |
171 | c |= MCI_CPSM_INTERRUPT; | |
172 | ||
173 | host->cmd = cmd; | |
174 | ||
175 | writel(cmd->arg, base + MMCIARGUMENT); | |
176 | writel(c, base + MMCICOMMAND); | |
177 | } | |
178 | ||
179 | static void | |
180 | mmci_data_irq(struct mmci_host *host, struct mmc_data *data, | |
181 | unsigned int status) | |
182 | { | |
183 | if (status & MCI_DATABLOCKEND) { | |
3bc87f24 | 184 | host->data_xfered += data->blksz; |
f28e8a4d LW |
185 | #ifdef CONFIG_ARCH_U300 |
186 | /* | |
187 | * On the U300 some signal or other is | |
188 | * badly routed so that a data write does | |
189 | * not properly terminate with a MCI_DATAEND | |
190 | * status flag. This quirk will make writes | |
191 | * work again. | |
192 | */ | |
193 | if (data->flags & MMC_DATA_WRITE) | |
194 | status |= MCI_DATAEND; | |
195 | #endif | |
1da177e4 LT |
196 | } |
197 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) { | |
64de0289 | 198 | dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ (status %08x)\n", status); |
1da177e4 | 199 | if (status & MCI_DATACRCFAIL) |
17b0429d | 200 | data->error = -EILSEQ; |
1da177e4 | 201 | else if (status & MCI_DATATIMEOUT) |
17b0429d | 202 | data->error = -ETIMEDOUT; |
1da177e4 | 203 | else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN)) |
17b0429d | 204 | data->error = -EIO; |
1da177e4 | 205 | status |= MCI_DATAEND; |
e9c091b4 RK |
206 | |
207 | /* | |
208 | * We hit an error condition. Ensure that any data | |
209 | * partially written to a page is properly coherent. | |
210 | */ | |
211 | if (host->sg_len && data->flags & MMC_DATA_READ) | |
bd6dee6f | 212 | flush_dcache_page(sg_page(host->sg_ptr)); |
1da177e4 LT |
213 | } |
214 | if (status & MCI_DATAEND) { | |
215 | mmci_stop_data(host); | |
216 | ||
217 | if (!data->stop) { | |
218 | mmci_request_end(host, data->mrq); | |
219 | } else { | |
220 | mmci_start_command(host, data->stop, 0); | |
221 | } | |
222 | } | |
223 | } | |
224 | ||
225 | static void | |
226 | mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, | |
227 | unsigned int status) | |
228 | { | |
229 | void __iomem *base = host->base; | |
230 | ||
231 | host->cmd = NULL; | |
232 | ||
233 | cmd->resp[0] = readl(base + MMCIRESPONSE0); | |
234 | cmd->resp[1] = readl(base + MMCIRESPONSE1); | |
235 | cmd->resp[2] = readl(base + MMCIRESPONSE2); | |
236 | cmd->resp[3] = readl(base + MMCIRESPONSE3); | |
237 | ||
238 | if (status & MCI_CMDTIMEOUT) { | |
17b0429d | 239 | cmd->error = -ETIMEDOUT; |
1da177e4 | 240 | } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { |
17b0429d | 241 | cmd->error = -EILSEQ; |
1da177e4 LT |
242 | } |
243 | ||
17b0429d | 244 | if (!cmd->data || cmd->error) { |
e47c222b RK |
245 | if (host->data) |
246 | mmci_stop_data(host); | |
1da177e4 LT |
247 | mmci_request_end(host, cmd->mrq); |
248 | } else if (!(cmd->data->flags & MMC_DATA_READ)) { | |
249 | mmci_start_data(host, cmd->data); | |
250 | } | |
251 | } | |
252 | ||
253 | static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) | |
254 | { | |
255 | void __iomem *base = host->base; | |
256 | char *ptr = buffer; | |
257 | u32 status; | |
26eed9a5 | 258 | int host_remain = host->size; |
1da177e4 LT |
259 | |
260 | do { | |
26eed9a5 | 261 | int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); |
1da177e4 LT |
262 | |
263 | if (count > remain) | |
264 | count = remain; | |
265 | ||
266 | if (count <= 0) | |
267 | break; | |
268 | ||
269 | readsl(base + MMCIFIFO, ptr, count >> 2); | |
270 | ||
271 | ptr += count; | |
272 | remain -= count; | |
26eed9a5 | 273 | host_remain -= count; |
1da177e4 LT |
274 | |
275 | if (remain == 0) | |
276 | break; | |
277 | ||
278 | status = readl(base + MMCISTATUS); | |
279 | } while (status & MCI_RXDATAAVLBL); | |
280 | ||
281 | return ptr - buffer; | |
282 | } | |
283 | ||
284 | static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) | |
285 | { | |
286 | void __iomem *base = host->base; | |
287 | char *ptr = buffer; | |
288 | ||
289 | do { | |
290 | unsigned int count, maxcnt; | |
291 | ||
292 | maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE; | |
293 | count = min(remain, maxcnt); | |
294 | ||
295 | writesl(base + MMCIFIFO, ptr, count >> 2); | |
296 | ||
297 | ptr += count; | |
298 | remain -= count; | |
299 | ||
300 | if (remain == 0) | |
301 | break; | |
302 | ||
303 | status = readl(base + MMCISTATUS); | |
304 | } while (status & MCI_TXFIFOHALFEMPTY); | |
305 | ||
306 | return ptr - buffer; | |
307 | } | |
308 | ||
309 | /* | |
310 | * PIO data transfer IRQ handler. | |
311 | */ | |
7d12e780 | 312 | static irqreturn_t mmci_pio_irq(int irq, void *dev_id) |
1da177e4 LT |
313 | { |
314 | struct mmci_host *host = dev_id; | |
315 | void __iomem *base = host->base; | |
316 | u32 status; | |
317 | ||
318 | status = readl(base + MMCISTATUS); | |
319 | ||
64de0289 | 320 | dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); |
1da177e4 LT |
321 | |
322 | do { | |
323 | unsigned long flags; | |
324 | unsigned int remain, len; | |
325 | char *buffer; | |
326 | ||
327 | /* | |
328 | * For write, we only need to test the half-empty flag | |
329 | * here - if the FIFO is completely empty, then by | |
330 | * definition it is more than half empty. | |
331 | * | |
332 | * For read, check for data available. | |
333 | */ | |
334 | if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) | |
335 | break; | |
336 | ||
337 | /* | |
338 | * Map the current scatter buffer. | |
339 | */ | |
340 | buffer = mmci_kmap_atomic(host, &flags) + host->sg_off; | |
341 | remain = host->sg_ptr->length - host->sg_off; | |
342 | ||
343 | len = 0; | |
344 | if (status & MCI_RXACTIVE) | |
345 | len = mmci_pio_read(host, buffer, remain); | |
346 | if (status & MCI_TXACTIVE) | |
347 | len = mmci_pio_write(host, buffer, remain, status); | |
348 | ||
349 | /* | |
350 | * Unmap the buffer. | |
351 | */ | |
f3e2628b | 352 | mmci_kunmap_atomic(host, buffer, &flags); |
1da177e4 LT |
353 | |
354 | host->sg_off += len; | |
355 | host->size -= len; | |
356 | remain -= len; | |
357 | ||
358 | if (remain) | |
359 | break; | |
360 | ||
e9c091b4 RK |
361 | /* |
362 | * If we were reading, and we have completed this | |
363 | * page, ensure that the data cache is coherent. | |
364 | */ | |
365 | if (status & MCI_RXACTIVE) | |
bd6dee6f | 366 | flush_dcache_page(sg_page(host->sg_ptr)); |
e9c091b4 | 367 | |
1da177e4 LT |
368 | if (!mmci_next_sg(host)) |
369 | break; | |
370 | ||
371 | status = readl(base + MMCISTATUS); | |
372 | } while (1); | |
373 | ||
374 | /* | |
375 | * If we're nearing the end of the read, switch to | |
376 | * "any data available" mode. | |
377 | */ | |
378 | if (status & MCI_RXACTIVE && host->size < MCI_FIFOSIZE) | |
379 | writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1); | |
380 | ||
381 | /* | |
382 | * If we run out of data, disable the data IRQs; this | |
383 | * prevents a race where the FIFO becomes empty before | |
384 | * the chip itself has disabled the data path, and | |
385 | * stops us racing with our data end IRQ. | |
386 | */ | |
387 | if (host->size == 0) { | |
388 | writel(0, base + MMCIMASK1); | |
389 | writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); | |
390 | } | |
391 | ||
392 | return IRQ_HANDLED; | |
393 | } | |
394 | ||
395 | /* | |
396 | * Handle completion of command and data transfers. | |
397 | */ | |
7d12e780 | 398 | static irqreturn_t mmci_irq(int irq, void *dev_id) |
1da177e4 LT |
399 | { |
400 | struct mmci_host *host = dev_id; | |
401 | u32 status; | |
402 | int ret = 0; | |
403 | ||
404 | spin_lock(&host->lock); | |
405 | ||
406 | do { | |
407 | struct mmc_command *cmd; | |
408 | struct mmc_data *data; | |
409 | ||
410 | status = readl(host->base + MMCISTATUS); | |
411 | status &= readl(host->base + MMCIMASK0); | |
412 | writel(status, host->base + MMCICLEAR); | |
413 | ||
64de0289 | 414 | dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); |
1da177e4 LT |
415 | |
416 | data = host->data; | |
417 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN| | |
418 | MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data) | |
419 | mmci_data_irq(host, data, status); | |
420 | ||
421 | cmd = host->cmd; | |
422 | if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) | |
423 | mmci_cmd_irq(host, cmd, status); | |
424 | ||
425 | ret = 1; | |
426 | } while (status); | |
427 | ||
428 | spin_unlock(&host->lock); | |
429 | ||
430 | return IRQ_RETVAL(ret); | |
431 | } | |
432 | ||
433 | static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
434 | { | |
435 | struct mmci_host *host = mmc_priv(mmc); | |
9e943021 | 436 | unsigned long flags; |
1da177e4 LT |
437 | |
438 | WARN_ON(host->mrq != NULL); | |
439 | ||
019a5f56 | 440 | if (mrq->data && !is_power_of_2(mrq->data->blksz)) { |
64de0289 LW |
441 | dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", |
442 | mrq->data->blksz); | |
255d01af PO |
443 | mrq->cmd->error = -EINVAL; |
444 | mmc_request_done(mmc, mrq); | |
445 | return; | |
446 | } | |
447 | ||
9e943021 | 448 | spin_lock_irqsave(&host->lock, flags); |
1da177e4 LT |
449 | |
450 | host->mrq = mrq; | |
451 | ||
452 | if (mrq->data && mrq->data->flags & MMC_DATA_READ) | |
453 | mmci_start_data(host, mrq->data); | |
454 | ||
455 | mmci_start_command(host, mrq->cmd, 0); | |
456 | ||
9e943021 | 457 | spin_unlock_irqrestore(&host->lock, flags); |
1da177e4 LT |
458 | } |
459 | ||
460 | static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
461 | { | |
462 | struct mmci_host *host = mmc_priv(mmc); | |
a6a6464a LW |
463 | u32 pwr = 0; |
464 | unsigned long flags; | |
1da177e4 | 465 | |
1da177e4 LT |
466 | switch (ios->power_mode) { |
467 | case MMC_POWER_OFF: | |
34e84f39 LW |
468 | if(host->vcc && |
469 | regulator_is_enabled(host->vcc)) | |
470 | regulator_disable(host->vcc); | |
1da177e4 LT |
471 | break; |
472 | case MMC_POWER_UP: | |
34e84f39 LW |
473 | #ifdef CONFIG_REGULATOR |
474 | if (host->vcc) | |
475 | /* This implicitly enables the regulator */ | |
476 | mmc_regulator_set_ocr(host->vcc, ios->vdd); | |
477 | #endif | |
478 | /* | |
479 | * The translate_vdd function is not used if you have | |
480 | * an external regulator, or your design is really weird. | |
481 | * Using it would mean sending in power control BOTH using | |
482 | * a regulator AND the 4 MMCIPWR bits. If we don't have | |
483 | * a regulator, we might have some other platform specific | |
484 | * power control behind this translate function. | |
485 | */ | |
486 | if (!host->vcc && host->plat->translate_vdd) | |
487 | pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd); | |
cc30d60e | 488 | /* The ST version does not have this, fall through to POWER_ON */ |
f17a1f06 | 489 | if (host->hw_designer != AMBA_VENDOR_ST) { |
cc30d60e LW |
490 | pwr |= MCI_PWR_UP; |
491 | break; | |
492 | } | |
1da177e4 LT |
493 | case MMC_POWER_ON: |
494 | pwr |= MCI_PWR_ON; | |
495 | break; | |
496 | } | |
497 | ||
cc30d60e | 498 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { |
f17a1f06 | 499 | if (host->hw_designer != AMBA_VENDOR_ST) |
cc30d60e LW |
500 | pwr |= MCI_ROD; |
501 | else { | |
502 | /* | |
503 | * The ST Micro variant use the ROD bit for something | |
504 | * else and only has OD (Open Drain). | |
505 | */ | |
506 | pwr |= MCI_OD; | |
507 | } | |
508 | } | |
1da177e4 | 509 | |
a6a6464a LW |
510 | spin_lock_irqsave(&host->lock, flags); |
511 | ||
512 | mmci_set_clkreg(host, ios->clock); | |
1da177e4 LT |
513 | |
514 | if (host->pwr != pwr) { | |
515 | host->pwr = pwr; | |
516 | writel(pwr, host->base + MMCIPOWER); | |
517 | } | |
a6a6464a LW |
518 | |
519 | spin_unlock_irqrestore(&host->lock, flags); | |
1da177e4 LT |
520 | } |
521 | ||
89001446 RK |
522 | static int mmci_get_ro(struct mmc_host *mmc) |
523 | { | |
524 | struct mmci_host *host = mmc_priv(mmc); | |
525 | ||
526 | if (host->gpio_wp == -ENOSYS) | |
527 | return -ENOSYS; | |
528 | ||
529 | return gpio_get_value(host->gpio_wp); | |
530 | } | |
531 | ||
532 | static int mmci_get_cd(struct mmc_host *mmc) | |
533 | { | |
534 | struct mmci_host *host = mmc_priv(mmc); | |
535 | unsigned int status; | |
536 | ||
537 | if (host->gpio_cd == -ENOSYS) | |
538 | status = host->plat->status(mmc_dev(host->mmc)); | |
539 | else | |
540 | status = gpio_get_value(host->gpio_cd); | |
541 | ||
542 | return !status; | |
543 | } | |
544 | ||
ab7aefd0 | 545 | static const struct mmc_host_ops mmci_ops = { |
1da177e4 LT |
546 | .request = mmci_request, |
547 | .set_ios = mmci_set_ios, | |
89001446 RK |
548 | .get_ro = mmci_get_ro, |
549 | .get_cd = mmci_get_cd, | |
1da177e4 LT |
550 | }; |
551 | ||
552 | static void mmci_check_status(unsigned long data) | |
553 | { | |
554 | struct mmci_host *host = (struct mmci_host *)data; | |
89001446 | 555 | unsigned int status = mmci_get_cd(host->mmc); |
1da177e4 | 556 | |
1da177e4 | 557 | if (status ^ host->oldstat) |
8dc00335 | 558 | mmc_detect_change(host->mmc, 0); |
1da177e4 LT |
559 | |
560 | host->oldstat = status; | |
561 | mod_timer(&host->timer, jiffies + HZ); | |
562 | } | |
563 | ||
03fbdb15 | 564 | static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) |
1da177e4 | 565 | { |
6ef297f8 | 566 | struct mmci_platform_data *plat = dev->dev.platform_data; |
1da177e4 LT |
567 | struct mmci_host *host; |
568 | struct mmc_host *mmc; | |
569 | int ret; | |
570 | ||
571 | /* must have platform data */ | |
572 | if (!plat) { | |
573 | ret = -EINVAL; | |
574 | goto out; | |
575 | } | |
576 | ||
577 | ret = amba_request_regions(dev, DRIVER_NAME); | |
578 | if (ret) | |
579 | goto out; | |
580 | ||
581 | mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); | |
582 | if (!mmc) { | |
583 | ret = -ENOMEM; | |
584 | goto rel_regions; | |
585 | } | |
586 | ||
587 | host = mmc_priv(mmc); | |
4ea580f1 | 588 | host->mmc = mmc; |
012b7d33 | 589 | |
89001446 RK |
590 | host->gpio_wp = -ENOSYS; |
591 | host->gpio_cd = -ENOSYS; | |
592 | ||
012b7d33 RK |
593 | host->hw_designer = amba_manf(dev); |
594 | host->hw_revision = amba_rev(dev); | |
64de0289 LW |
595 | dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); |
596 | dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); | |
012b7d33 | 597 | |
ee569c43 | 598 | host->clk = clk_get(&dev->dev, NULL); |
1da177e4 LT |
599 | if (IS_ERR(host->clk)) { |
600 | ret = PTR_ERR(host->clk); | |
601 | host->clk = NULL; | |
602 | goto host_free; | |
603 | } | |
604 | ||
1da177e4 LT |
605 | ret = clk_enable(host->clk); |
606 | if (ret) | |
a8d3584a | 607 | goto clk_free; |
1da177e4 LT |
608 | |
609 | host->plat = plat; | |
610 | host->mclk = clk_get_rate(host->clk); | |
c8df9a53 LW |
611 | /* |
612 | * According to the spec, mclk is max 100 MHz, | |
613 | * so we try to adjust the clock down to this, | |
614 | * (if possible). | |
615 | */ | |
616 | if (host->mclk > 100000000) { | |
617 | ret = clk_set_rate(host->clk, 100000000); | |
618 | if (ret < 0) | |
619 | goto clk_disable; | |
620 | host->mclk = clk_get_rate(host->clk); | |
64de0289 LW |
621 | dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", |
622 | host->mclk); | |
c8df9a53 | 623 | } |
dc890c2d | 624 | host->base = ioremap(dev->res.start, resource_size(&dev->res)); |
1da177e4 LT |
625 | if (!host->base) { |
626 | ret = -ENOMEM; | |
627 | goto clk_disable; | |
628 | } | |
629 | ||
630 | mmc->ops = &mmci_ops; | |
631 | mmc->f_min = (host->mclk + 511) / 512; | |
632 | mmc->f_max = min(host->mclk, fmax); | |
64de0289 LW |
633 | dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); |
634 | ||
34e84f39 LW |
635 | #ifdef CONFIG_REGULATOR |
636 | /* If we're using the regulator framework, try to fetch a regulator */ | |
637 | host->vcc = regulator_get(&dev->dev, "vmmc"); | |
638 | if (IS_ERR(host->vcc)) | |
639 | host->vcc = NULL; | |
640 | else { | |
641 | int mask = mmc_regulator_get_ocrmask(host->vcc); | |
642 | ||
643 | if (mask < 0) | |
644 | dev_err(&dev->dev, "error getting OCR mask (%d)\n", | |
645 | mask); | |
646 | else { | |
647 | host->mmc->ocr_avail = (u32) mask; | |
648 | if (plat->ocr_mask) | |
649 | dev_warn(&dev->dev, | |
650 | "Provided ocr_mask/setpower will not be used " | |
651 | "(using regulator instead)\n"); | |
652 | } | |
653 | } | |
654 | #endif | |
655 | /* Fall back to platform data if no regulator is found */ | |
656 | if (host->vcc == NULL) | |
657 | mmc->ocr_avail = plat->ocr_mask; | |
9e6c82cd | 658 | mmc->caps = plat->capabilities; |
1da177e4 LT |
659 | |
660 | /* | |
661 | * We can do SGIO | |
662 | */ | |
663 | mmc->max_hw_segs = 16; | |
664 | mmc->max_phys_segs = NR_SG; | |
665 | ||
666 | /* | |
667 | * Since we only have a 16-bit data length register, we must | |
668 | * ensure that we don't exceed 2^16-1 bytes in a single request. | |
1da177e4 | 669 | */ |
55db890a | 670 | mmc->max_req_size = 65535; |
1da177e4 LT |
671 | |
672 | /* | |
673 | * Set the maximum segment size. Since we aren't doing DMA | |
674 | * (yet) we are only limited by the data length register. | |
675 | */ | |
55db890a | 676 | mmc->max_seg_size = mmc->max_req_size; |
1da177e4 | 677 | |
fe4a3c7a PO |
678 | /* |
679 | * Block size can be up to 2048 bytes, but must be a power of two. | |
680 | */ | |
681 | mmc->max_blk_size = 2048; | |
682 | ||
55db890a PO |
683 | /* |
684 | * No limit on the number of blocks transferred. | |
685 | */ | |
686 | mmc->max_blk_count = mmc->max_req_size; | |
687 | ||
1da177e4 LT |
688 | spin_lock_init(&host->lock); |
689 | ||
690 | writel(0, host->base + MMCIMASK0); | |
691 | writel(0, host->base + MMCIMASK1); | |
692 | writel(0xfff, host->base + MMCICLEAR); | |
693 | ||
89001446 RK |
694 | if (gpio_is_valid(plat->gpio_cd)) { |
695 | ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); | |
696 | if (ret == 0) | |
697 | ret = gpio_direction_input(plat->gpio_cd); | |
698 | if (ret == 0) | |
699 | host->gpio_cd = plat->gpio_cd; | |
700 | else if (ret != -ENOSYS) | |
701 | goto err_gpio_cd; | |
702 | } | |
703 | if (gpio_is_valid(plat->gpio_wp)) { | |
704 | ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); | |
705 | if (ret == 0) | |
706 | ret = gpio_direction_input(plat->gpio_wp); | |
707 | if (ret == 0) | |
708 | host->gpio_wp = plat->gpio_wp; | |
709 | else if (ret != -ENOSYS) | |
710 | goto err_gpio_wp; | |
711 | } | |
712 | ||
dace1453 | 713 | ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); |
1da177e4 LT |
714 | if (ret) |
715 | goto unmap; | |
716 | ||
dace1453 | 717 | ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, DRIVER_NAME " (pio)", host); |
1da177e4 LT |
718 | if (ret) |
719 | goto irq0_free; | |
720 | ||
721 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); | |
722 | ||
723 | amba_set_drvdata(dev, mmc); | |
89001446 | 724 | host->oldstat = mmci_get_cd(host->mmc); |
1da177e4 LT |
725 | |
726 | mmc_add_host(mmc); | |
727 | ||
64de0289 | 728 | dev_info(&dev->dev, "%s: MMCI rev %x cfg %02x at 0x%016llx irq %d,%d\n", |
d366b643 | 729 | mmc_hostname(mmc), amba_rev(dev), amba_config(dev), |
e29419ff | 730 | (unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]); |
1da177e4 LT |
731 | |
732 | init_timer(&host->timer); | |
733 | host->timer.data = (unsigned long)host; | |
734 | host->timer.function = mmci_check_status; | |
735 | host->timer.expires = jiffies + HZ; | |
736 | add_timer(&host->timer); | |
737 | ||
738 | return 0; | |
739 | ||
740 | irq0_free: | |
741 | free_irq(dev->irq[0], host); | |
742 | unmap: | |
89001446 RK |
743 | if (host->gpio_wp != -ENOSYS) |
744 | gpio_free(host->gpio_wp); | |
745 | err_gpio_wp: | |
746 | if (host->gpio_cd != -ENOSYS) | |
747 | gpio_free(host->gpio_cd); | |
748 | err_gpio_cd: | |
1da177e4 LT |
749 | iounmap(host->base); |
750 | clk_disable: | |
751 | clk_disable(host->clk); | |
1da177e4 LT |
752 | clk_free: |
753 | clk_put(host->clk); | |
754 | host_free: | |
755 | mmc_free_host(mmc); | |
756 | rel_regions: | |
757 | amba_release_regions(dev); | |
758 | out: | |
759 | return ret; | |
760 | } | |
761 | ||
6dc4a47a | 762 | static int __devexit mmci_remove(struct amba_device *dev) |
1da177e4 LT |
763 | { |
764 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
765 | ||
766 | amba_set_drvdata(dev, NULL); | |
767 | ||
768 | if (mmc) { | |
769 | struct mmci_host *host = mmc_priv(mmc); | |
770 | ||
771 | del_timer_sync(&host->timer); | |
772 | ||
773 | mmc_remove_host(mmc); | |
774 | ||
775 | writel(0, host->base + MMCIMASK0); | |
776 | writel(0, host->base + MMCIMASK1); | |
777 | ||
778 | writel(0, host->base + MMCICOMMAND); | |
779 | writel(0, host->base + MMCIDATACTRL); | |
780 | ||
781 | free_irq(dev->irq[0], host); | |
782 | free_irq(dev->irq[1], host); | |
783 | ||
89001446 RK |
784 | if (host->gpio_wp != -ENOSYS) |
785 | gpio_free(host->gpio_wp); | |
786 | if (host->gpio_cd != -ENOSYS) | |
787 | gpio_free(host->gpio_cd); | |
788 | ||
1da177e4 LT |
789 | iounmap(host->base); |
790 | clk_disable(host->clk); | |
1da177e4 LT |
791 | clk_put(host->clk); |
792 | ||
34e84f39 LW |
793 | if (regulator_is_enabled(host->vcc)) |
794 | regulator_disable(host->vcc); | |
795 | regulator_put(host->vcc); | |
796 | ||
1da177e4 LT |
797 | mmc_free_host(mmc); |
798 | ||
799 | amba_release_regions(dev); | |
800 | } | |
801 | ||
802 | return 0; | |
803 | } | |
804 | ||
805 | #ifdef CONFIG_PM | |
e5378ca8 | 806 | static int mmci_suspend(struct amba_device *dev, pm_message_t state) |
1da177e4 LT |
807 | { |
808 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
809 | int ret = 0; | |
810 | ||
811 | if (mmc) { | |
812 | struct mmci_host *host = mmc_priv(mmc); | |
813 | ||
814 | ret = mmc_suspend_host(mmc, state); | |
815 | if (ret == 0) | |
816 | writel(0, host->base + MMCIMASK0); | |
817 | } | |
818 | ||
819 | return ret; | |
820 | } | |
821 | ||
822 | static int mmci_resume(struct amba_device *dev) | |
823 | { | |
824 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
825 | int ret = 0; | |
826 | ||
827 | if (mmc) { | |
828 | struct mmci_host *host = mmc_priv(mmc); | |
829 | ||
830 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); | |
831 | ||
832 | ret = mmc_resume_host(mmc); | |
833 | } | |
834 | ||
835 | return ret; | |
836 | } | |
837 | #else | |
838 | #define mmci_suspend NULL | |
839 | #define mmci_resume NULL | |
840 | #endif | |
841 | ||
842 | static struct amba_id mmci_ids[] = { | |
843 | { | |
844 | .id = 0x00041180, | |
845 | .mask = 0x000fffff, | |
846 | }, | |
847 | { | |
848 | .id = 0x00041181, | |
849 | .mask = 0x000fffff, | |
850 | }, | |
cc30d60e LW |
851 | /* ST Micro variants */ |
852 | { | |
853 | .id = 0x00180180, | |
854 | .mask = 0x00ffffff, | |
855 | }, | |
856 | { | |
857 | .id = 0x00280180, | |
858 | .mask = 0x00ffffff, | |
859 | }, | |
1da177e4 LT |
860 | { 0, 0 }, |
861 | }; | |
862 | ||
863 | static struct amba_driver mmci_driver = { | |
864 | .drv = { | |
865 | .name = DRIVER_NAME, | |
866 | }, | |
867 | .probe = mmci_probe, | |
6dc4a47a | 868 | .remove = __devexit_p(mmci_remove), |
1da177e4 LT |
869 | .suspend = mmci_suspend, |
870 | .resume = mmci_resume, | |
871 | .id_table = mmci_ids, | |
872 | }; | |
873 | ||
874 | static int __init mmci_init(void) | |
875 | { | |
876 | return amba_driver_register(&mmci_driver); | |
877 | } | |
878 | ||
879 | static void __exit mmci_exit(void) | |
880 | { | |
881 | amba_driver_unregister(&mmci_driver); | |
882 | } | |
883 | ||
884 | module_init(mmci_init); | |
885 | module_exit(mmci_exit); | |
886 | module_param(fmax, uint, 0444); | |
887 | ||
888 | MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); | |
889 | MODULE_LICENSE("GPL"); |