Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. | |
c8ebae37 | 5 | * Copyright (C) 2010 ST-Ericsson SA |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/interrupt.h> | |
613b152c | 17 | #include <linux/kernel.h> |
1da177e4 LT |
18 | #include <linux/delay.h> |
19 | #include <linux/err.h> | |
20 | #include <linux/highmem.h> | |
019a5f56 | 21 | #include <linux/log2.h> |
1da177e4 | 22 | #include <linux/mmc/host.h> |
34177802 | 23 | #include <linux/mmc/card.h> |
a62c80e5 | 24 | #include <linux/amba/bus.h> |
f8ce2547 | 25 | #include <linux/clk.h> |
bd6dee6f | 26 | #include <linux/scatterlist.h> |
89001446 | 27 | #include <linux/gpio.h> |
34e84f39 | 28 | #include <linux/regulator/consumer.h> |
c8ebae37 RK |
29 | #include <linux/dmaengine.h> |
30 | #include <linux/dma-mapping.h> | |
31 | #include <linux/amba/mmci.h> | |
1da177e4 | 32 | |
7b09cdac | 33 | #include <asm/div64.h> |
1da177e4 | 34 | #include <asm/io.h> |
c6b8fdad | 35 | #include <asm/sizes.h> |
1da177e4 LT |
36 | |
37 | #include "mmci.h" | |
38 | ||
39 | #define DRIVER_NAME "mmci-pl18x" | |
40 | ||
1da177e4 LT |
41 | static unsigned int fmax = 515633; |
42 | ||
4956e109 RV |
43 | /** |
44 | * struct variant_data - MMCI variant-specific quirks | |
45 | * @clkreg: default value for MCICLOCK register | |
4380c14f | 46 | * @clkreg_enable: enable value for MMCICLOCK register |
08458ef6 | 47 | * @datalength_bits: number of bits in the MMCIDATALENGTH register |
8301bb68 RV |
48 | * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY |
49 | * is asserted (likewise for RX) | |
50 | * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY | |
51 | * is asserted (likewise for RX) | |
34177802 | 52 | * @sdio: variant supports SDIO |
b70a67f9 | 53 | * @st_clkdiv: true if using a ST-specific clock divider algorithm |
4956e109 RV |
54 | */ |
55 | struct variant_data { | |
56 | unsigned int clkreg; | |
4380c14f | 57 | unsigned int clkreg_enable; |
08458ef6 | 58 | unsigned int datalength_bits; |
8301bb68 RV |
59 | unsigned int fifosize; |
60 | unsigned int fifohalfsize; | |
34177802 | 61 | bool sdio; |
b70a67f9 | 62 | bool st_clkdiv; |
4956e109 RV |
63 | }; |
64 | ||
65 | static struct variant_data variant_arm = { | |
8301bb68 RV |
66 | .fifosize = 16 * 4, |
67 | .fifohalfsize = 8 * 4, | |
08458ef6 | 68 | .datalength_bits = 16, |
4956e109 RV |
69 | }; |
70 | ||
71 | static struct variant_data variant_u300 = { | |
8301bb68 RV |
72 | .fifosize = 16 * 4, |
73 | .fifohalfsize = 8 * 4, | |
4380c14f | 74 | .clkreg_enable = 1 << 13, /* HWFCEN */ |
08458ef6 | 75 | .datalength_bits = 16, |
34177802 | 76 | .sdio = true, |
4956e109 RV |
77 | }; |
78 | ||
79 | static struct variant_data variant_ux500 = { | |
8301bb68 RV |
80 | .fifosize = 30 * 4, |
81 | .fifohalfsize = 8 * 4, | |
4956e109 | 82 | .clkreg = MCI_CLK_ENABLE, |
4380c14f | 83 | .clkreg_enable = 1 << 14, /* HWFCEN */ |
08458ef6 | 84 | .datalength_bits = 24, |
34177802 | 85 | .sdio = true, |
b70a67f9 | 86 | .st_clkdiv = true, |
4956e109 | 87 | }; |
b70a67f9 | 88 | |
a6a6464a LW |
89 | /* |
90 | * This must be called with host->lock held | |
91 | */ | |
92 | static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) | |
93 | { | |
4956e109 RV |
94 | struct variant_data *variant = host->variant; |
95 | u32 clk = variant->clkreg; | |
a6a6464a LW |
96 | |
97 | if (desired) { | |
98 | if (desired >= host->mclk) { | |
991a86e1 | 99 | clk = MCI_CLK_BYPASS; |
a6a6464a | 100 | host->cclk = host->mclk; |
b70a67f9 LW |
101 | } else if (variant->st_clkdiv) { |
102 | /* | |
103 | * DB8500 TRM says f = mclk / (clkdiv + 2) | |
104 | * => clkdiv = (mclk / f) - 2 | |
105 | * Round the divider up so we don't exceed the max | |
106 | * frequency | |
107 | */ | |
108 | clk = DIV_ROUND_UP(host->mclk, desired) - 2; | |
109 | if (clk >= 256) | |
110 | clk = 255; | |
111 | host->cclk = host->mclk / (clk + 2); | |
a6a6464a | 112 | } else { |
b70a67f9 LW |
113 | /* |
114 | * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) | |
115 | * => clkdiv = mclk / (2 * f) - 1 | |
116 | */ | |
a6a6464a LW |
117 | clk = host->mclk / (2 * desired) - 1; |
118 | if (clk >= 256) | |
119 | clk = 255; | |
120 | host->cclk = host->mclk / (2 * (clk + 1)); | |
121 | } | |
4380c14f RV |
122 | |
123 | clk |= variant->clkreg_enable; | |
a6a6464a LW |
124 | clk |= MCI_CLK_ENABLE; |
125 | /* This hasn't proven to be worthwhile */ | |
126 | /* clk |= MCI_CLK_PWRSAVE; */ | |
127 | } | |
128 | ||
9e6c82cd | 129 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) |
771dc157 LW |
130 | clk |= MCI_4BIT_BUS; |
131 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) | |
132 | clk |= MCI_ST_8BIT_BUS; | |
9e6c82cd | 133 | |
a6a6464a LW |
134 | writel(clk, host->base + MMCICLOCK); |
135 | } | |
136 | ||
1da177e4 LT |
137 | static void |
138 | mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) | |
139 | { | |
140 | writel(0, host->base + MMCICOMMAND); | |
141 | ||
e47c222b RK |
142 | BUG_ON(host->data); |
143 | ||
1da177e4 LT |
144 | host->mrq = NULL; |
145 | host->cmd = NULL; | |
146 | ||
1da177e4 LT |
147 | /* |
148 | * Need to drop the host lock here; mmc_request_done may call | |
149 | * back into the driver... | |
150 | */ | |
151 | spin_unlock(&host->lock); | |
152 | mmc_request_done(host->mmc, mrq); | |
153 | spin_lock(&host->lock); | |
154 | } | |
155 | ||
2686b4b4 LW |
156 | static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) |
157 | { | |
158 | void __iomem *base = host->base; | |
159 | ||
160 | if (host->singleirq) { | |
161 | unsigned int mask0 = readl(base + MMCIMASK0); | |
162 | ||
163 | mask0 &= ~MCI_IRQ1MASK; | |
164 | mask0 |= mask; | |
165 | ||
166 | writel(mask0, base + MMCIMASK0); | |
167 | } | |
168 | ||
169 | writel(mask, base + MMCIMASK1); | |
170 | } | |
171 | ||
1da177e4 LT |
172 | static void mmci_stop_data(struct mmci_host *host) |
173 | { | |
174 | writel(0, host->base + MMCIDATACTRL); | |
2686b4b4 | 175 | mmci_set_mask1(host, 0); |
1da177e4 LT |
176 | host->data = NULL; |
177 | } | |
178 | ||
4ce1d6cb RV |
179 | static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) |
180 | { | |
181 | unsigned int flags = SG_MITER_ATOMIC; | |
182 | ||
183 | if (data->flags & MMC_DATA_READ) | |
184 | flags |= SG_MITER_TO_SG; | |
185 | else | |
186 | flags |= SG_MITER_FROM_SG; | |
187 | ||
188 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); | |
189 | } | |
190 | ||
c8ebae37 RK |
191 | /* |
192 | * All the DMA operation mode stuff goes inside this ifdef. | |
193 | * This assumes that you have a generic DMA device interface, | |
194 | * no custom DMA interfaces are supported. | |
195 | */ | |
196 | #ifdef CONFIG_DMA_ENGINE | |
197 | static void __devinit mmci_dma_setup(struct mmci_host *host) | |
198 | { | |
199 | struct mmci_platform_data *plat = host->plat; | |
200 | const char *rxname, *txname; | |
201 | dma_cap_mask_t mask; | |
202 | ||
203 | if (!plat || !plat->dma_filter) { | |
204 | dev_info(mmc_dev(host->mmc), "no DMA platform data\n"); | |
205 | return; | |
206 | } | |
207 | ||
208 | /* Try to acquire a generic DMA engine slave channel */ | |
209 | dma_cap_zero(mask); | |
210 | dma_cap_set(DMA_SLAVE, mask); | |
211 | ||
212 | /* | |
213 | * If only an RX channel is specified, the driver will | |
214 | * attempt to use it bidirectionally, however if it is | |
215 | * is specified but cannot be located, DMA will be disabled. | |
216 | */ | |
217 | if (plat->dma_rx_param) { | |
218 | host->dma_rx_channel = dma_request_channel(mask, | |
219 | plat->dma_filter, | |
220 | plat->dma_rx_param); | |
221 | /* E.g if no DMA hardware is present */ | |
222 | if (!host->dma_rx_channel) | |
223 | dev_err(mmc_dev(host->mmc), "no RX DMA channel\n"); | |
224 | } | |
225 | ||
226 | if (plat->dma_tx_param) { | |
227 | host->dma_tx_channel = dma_request_channel(mask, | |
228 | plat->dma_filter, | |
229 | plat->dma_tx_param); | |
230 | if (!host->dma_tx_channel) | |
231 | dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n"); | |
232 | } else { | |
233 | host->dma_tx_channel = host->dma_rx_channel; | |
234 | } | |
235 | ||
236 | if (host->dma_rx_channel) | |
237 | rxname = dma_chan_name(host->dma_rx_channel); | |
238 | else | |
239 | rxname = "none"; | |
240 | ||
241 | if (host->dma_tx_channel) | |
242 | txname = dma_chan_name(host->dma_tx_channel); | |
243 | else | |
244 | txname = "none"; | |
245 | ||
246 | dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", | |
247 | rxname, txname); | |
248 | ||
249 | /* | |
250 | * Limit the maximum segment size in any SG entry according to | |
251 | * the parameters of the DMA engine device. | |
252 | */ | |
253 | if (host->dma_tx_channel) { | |
254 | struct device *dev = host->dma_tx_channel->device->dev; | |
255 | unsigned int max_seg_size = dma_get_max_seg_size(dev); | |
256 | ||
257 | if (max_seg_size < host->mmc->max_seg_size) | |
258 | host->mmc->max_seg_size = max_seg_size; | |
259 | } | |
260 | if (host->dma_rx_channel) { | |
261 | struct device *dev = host->dma_rx_channel->device->dev; | |
262 | unsigned int max_seg_size = dma_get_max_seg_size(dev); | |
263 | ||
264 | if (max_seg_size < host->mmc->max_seg_size) | |
265 | host->mmc->max_seg_size = max_seg_size; | |
266 | } | |
267 | } | |
268 | ||
269 | /* | |
270 | * This is used in __devinit or __devexit so inline it | |
271 | * so it can be discarded. | |
272 | */ | |
273 | static inline void mmci_dma_release(struct mmci_host *host) | |
274 | { | |
275 | struct mmci_platform_data *plat = host->plat; | |
276 | ||
277 | if (host->dma_rx_channel) | |
278 | dma_release_channel(host->dma_rx_channel); | |
279 | if (host->dma_tx_channel && plat->dma_tx_param) | |
280 | dma_release_channel(host->dma_tx_channel); | |
281 | host->dma_rx_channel = host->dma_tx_channel = NULL; | |
282 | } | |
283 | ||
284 | static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) | |
285 | { | |
286 | struct dma_chan *chan = host->dma_current; | |
287 | enum dma_data_direction dir; | |
288 | u32 status; | |
289 | int i; | |
290 | ||
291 | /* Wait up to 1ms for the DMA to complete */ | |
292 | for (i = 0; ; i++) { | |
293 | status = readl(host->base + MMCISTATUS); | |
294 | if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) | |
295 | break; | |
296 | udelay(10); | |
297 | } | |
298 | ||
299 | /* | |
300 | * Check to see whether we still have some data left in the FIFO - | |
301 | * this catches DMA controllers which are unable to monitor the | |
302 | * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- | |
303 | * contiguous buffers. On TX, we'll get a FIFO underrun error. | |
304 | */ | |
305 | if (status & MCI_RXDATAAVLBLMASK) { | |
306 | dmaengine_terminate_all(chan); | |
307 | if (!data->error) | |
308 | data->error = -EIO; | |
309 | } | |
310 | ||
311 | if (data->flags & MMC_DATA_WRITE) { | |
312 | dir = DMA_TO_DEVICE; | |
313 | } else { | |
314 | dir = DMA_FROM_DEVICE; | |
315 | } | |
316 | ||
317 | dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); | |
318 | ||
319 | /* | |
320 | * Use of DMA with scatter-gather is impossible. | |
321 | * Give up with DMA and switch back to PIO mode. | |
322 | */ | |
323 | if (status & MCI_RXDATAAVLBLMASK) { | |
324 | dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); | |
325 | mmci_dma_release(host); | |
326 | } | |
327 | } | |
328 | ||
329 | static void mmci_dma_data_error(struct mmci_host *host) | |
330 | { | |
331 | dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); | |
332 | dmaengine_terminate_all(host->dma_current); | |
333 | } | |
334 | ||
335 | static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) | |
336 | { | |
337 | struct variant_data *variant = host->variant; | |
338 | struct dma_slave_config conf = { | |
339 | .src_addr = host->phybase + MMCIFIFO, | |
340 | .dst_addr = host->phybase + MMCIFIFO, | |
341 | .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
342 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
343 | .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ | |
344 | .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ | |
345 | }; | |
346 | struct mmc_data *data = host->data; | |
347 | struct dma_chan *chan; | |
348 | struct dma_device *device; | |
349 | struct dma_async_tx_descriptor *desc; | |
350 | int nr_sg; | |
351 | ||
352 | host->dma_current = NULL; | |
353 | ||
354 | if (data->flags & MMC_DATA_READ) { | |
355 | conf.direction = DMA_FROM_DEVICE; | |
356 | chan = host->dma_rx_channel; | |
357 | } else { | |
358 | conf.direction = DMA_TO_DEVICE; | |
359 | chan = host->dma_tx_channel; | |
360 | } | |
361 | ||
362 | /* If there's no DMA channel, fall back to PIO */ | |
363 | if (!chan) | |
364 | return -EINVAL; | |
365 | ||
366 | /* If less than or equal to the fifo size, don't bother with DMA */ | |
367 | if (host->size <= variant->fifosize) | |
368 | return -EINVAL; | |
369 | ||
370 | device = chan->device; | |
371 | nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, conf.direction); | |
372 | if (nr_sg == 0) | |
373 | return -EINVAL; | |
374 | ||
375 | dmaengine_slave_config(chan, &conf); | |
376 | desc = device->device_prep_slave_sg(chan, data->sg, nr_sg, | |
377 | conf.direction, DMA_CTRL_ACK); | |
378 | if (!desc) | |
379 | goto unmap_exit; | |
380 | ||
381 | /* Okay, go for it. */ | |
382 | host->dma_current = chan; | |
383 | ||
384 | dev_vdbg(mmc_dev(host->mmc), | |
385 | "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", | |
386 | data->sg_len, data->blksz, data->blocks, data->flags); | |
387 | dmaengine_submit(desc); | |
388 | dma_async_issue_pending(chan); | |
389 | ||
390 | datactrl |= MCI_DPSM_DMAENABLE; | |
391 | ||
392 | /* Trigger the DMA transfer */ | |
393 | writel(datactrl, host->base + MMCIDATACTRL); | |
394 | ||
395 | /* | |
396 | * Let the MMCI say when the data is ended and it's time | |
397 | * to fire next DMA request. When that happens, MMCI will | |
398 | * call mmci_data_end() | |
399 | */ | |
400 | writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, | |
401 | host->base + MMCIMASK0); | |
402 | return 0; | |
403 | ||
404 | unmap_exit: | |
405 | dmaengine_terminate_all(chan); | |
406 | dma_unmap_sg(device->dev, data->sg, data->sg_len, conf.direction); | |
407 | return -ENOMEM; | |
408 | } | |
409 | #else | |
410 | /* Blank functions if the DMA engine is not available */ | |
411 | static inline void mmci_dma_setup(struct mmci_host *host) | |
412 | { | |
413 | } | |
414 | ||
415 | static inline void mmci_dma_release(struct mmci_host *host) | |
416 | { | |
417 | } | |
418 | ||
419 | static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) | |
420 | { | |
421 | } | |
422 | ||
423 | static inline void mmci_dma_data_error(struct mmci_host *host) | |
424 | { | |
425 | } | |
426 | ||
427 | static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) | |
428 | { | |
429 | return -ENOSYS; | |
430 | } | |
431 | #endif | |
432 | ||
1da177e4 LT |
433 | static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) |
434 | { | |
8301bb68 | 435 | struct variant_data *variant = host->variant; |
1da177e4 | 436 | unsigned int datactrl, timeout, irqmask; |
7b09cdac | 437 | unsigned long long clks; |
1da177e4 | 438 | void __iomem *base; |
3bc87f24 | 439 | int blksz_bits; |
1da177e4 | 440 | |
64de0289 LW |
441 | dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", |
442 | data->blksz, data->blocks, data->flags); | |
1da177e4 LT |
443 | |
444 | host->data = data; | |
528320db | 445 | host->size = data->blksz * data->blocks; |
51d4375d | 446 | data->bytes_xfered = 0; |
1da177e4 | 447 | |
7b09cdac RK |
448 | clks = (unsigned long long)data->timeout_ns * host->cclk; |
449 | do_div(clks, 1000000000UL); | |
450 | ||
451 | timeout = data->timeout_clks + (unsigned int)clks; | |
1da177e4 LT |
452 | |
453 | base = host->base; | |
454 | writel(timeout, base + MMCIDATATIMER); | |
455 | writel(host->size, base + MMCIDATALENGTH); | |
456 | ||
3bc87f24 RK |
457 | blksz_bits = ffs(data->blksz) - 1; |
458 | BUG_ON(1 << blksz_bits != data->blksz); | |
459 | ||
460 | datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; | |
c8ebae37 RK |
461 | |
462 | if (data->flags & MMC_DATA_READ) | |
1da177e4 | 463 | datactrl |= MCI_DPSM_DIRECTION; |
c8ebae37 RK |
464 | |
465 | /* | |
466 | * Attempt to use DMA operation mode, if this | |
467 | * should fail, fall back to PIO mode | |
468 | */ | |
469 | if (!mmci_dma_start_data(host, datactrl)) | |
470 | return; | |
471 | ||
472 | /* IRQ mode, map the SG list for CPU reading/writing */ | |
473 | mmci_init_sg(host, data); | |
474 | ||
475 | if (data->flags & MMC_DATA_READ) { | |
1da177e4 | 476 | irqmask = MCI_RXFIFOHALFFULLMASK; |
0425a142 RK |
477 | |
478 | /* | |
c4d877c1 RK |
479 | * If we have less than the fifo 'half-full' threshold to |
480 | * transfer, trigger a PIO interrupt as soon as any data | |
481 | * is available. | |
0425a142 | 482 | */ |
c4d877c1 | 483 | if (host->size < variant->fifohalfsize) |
0425a142 | 484 | irqmask |= MCI_RXDATAAVLBLMASK; |
1da177e4 LT |
485 | } else { |
486 | /* | |
487 | * We don't actually need to include "FIFO empty" here | |
488 | * since its implicit in "FIFO half empty". | |
489 | */ | |
490 | irqmask = MCI_TXFIFOHALFEMPTYMASK; | |
491 | } | |
492 | ||
34177802 LW |
493 | /* The ST Micro variants has a special bit to enable SDIO */ |
494 | if (variant->sdio && host->mmc->card) | |
495 | if (mmc_card_sdio(host->mmc->card)) | |
496 | datactrl |= MCI_ST_DPSM_SDIOEN; | |
497 | ||
1da177e4 LT |
498 | writel(datactrl, base + MMCIDATACTRL); |
499 | writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); | |
2686b4b4 | 500 | mmci_set_mask1(host, irqmask); |
1da177e4 LT |
501 | } |
502 | ||
503 | static void | |
504 | mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) | |
505 | { | |
506 | void __iomem *base = host->base; | |
507 | ||
64de0289 | 508 | dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", |
1da177e4 LT |
509 | cmd->opcode, cmd->arg, cmd->flags); |
510 | ||
511 | if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { | |
512 | writel(0, base + MMCICOMMAND); | |
513 | udelay(1); | |
514 | } | |
515 | ||
516 | c |= cmd->opcode | MCI_CPSM_ENABLE; | |
e9225176 RK |
517 | if (cmd->flags & MMC_RSP_PRESENT) { |
518 | if (cmd->flags & MMC_RSP_136) | |
519 | c |= MCI_CPSM_LONGRSP; | |
1da177e4 | 520 | c |= MCI_CPSM_RESPONSE; |
1da177e4 LT |
521 | } |
522 | if (/*interrupt*/0) | |
523 | c |= MCI_CPSM_INTERRUPT; | |
524 | ||
525 | host->cmd = cmd; | |
526 | ||
527 | writel(cmd->arg, base + MMCIARGUMENT); | |
528 | writel(c, base + MMCICOMMAND); | |
529 | } | |
530 | ||
531 | static void | |
532 | mmci_data_irq(struct mmci_host *host, struct mmc_data *data, | |
533 | unsigned int status) | |
534 | { | |
f20f8f21 | 535 | /* First check for errors */ |
1da177e4 | 536 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) { |
8cb28155 | 537 | u32 remain, success; |
f20f8f21 | 538 | |
c8ebae37 RK |
539 | /* Terminate the DMA transfer */ |
540 | if (dma_inprogress(host)) | |
541 | mmci_dma_data_error(host); | |
e9c091b4 RK |
542 | |
543 | /* | |
c8afc9d5 RK |
544 | * Calculate how far we are into the transfer. Note that |
545 | * the data counter gives the number of bytes transferred | |
546 | * on the MMC bus, not on the host side. On reads, this | |
547 | * can be as much as a FIFO-worth of data ahead. This | |
548 | * matters for FIFO overruns only. | |
e9c091b4 | 549 | */ |
f5a106d9 | 550 | remain = readl(host->base + MMCIDATACNT); |
8cb28155 LW |
551 | success = data->blksz * data->blocks - remain; |
552 | ||
c8afc9d5 RK |
553 | dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", |
554 | status, success); | |
8cb28155 LW |
555 | if (status & MCI_DATACRCFAIL) { |
556 | /* Last block was not successful */ | |
c8afc9d5 | 557 | success -= 1; |
17b0429d | 558 | data->error = -EILSEQ; |
8cb28155 | 559 | } else if (status & MCI_DATATIMEOUT) { |
17b0429d | 560 | data->error = -ETIMEDOUT; |
c8afc9d5 RK |
561 | } else if (status & MCI_TXUNDERRUN) { |
562 | data->error = -EIO; | |
563 | } else if (status & MCI_RXOVERRUN) { | |
564 | if (success > host->variant->fifosize) | |
565 | success -= host->variant->fifosize; | |
566 | else | |
567 | success = 0; | |
17b0429d | 568 | data->error = -EIO; |
4ce1d6cb | 569 | } |
51d4375d | 570 | data->bytes_xfered = round_down(success, data->blksz); |
1da177e4 | 571 | } |
f20f8f21 | 572 | |
8cb28155 LW |
573 | if (status & MCI_DATABLOCKEND) |
574 | dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); | |
f20f8f21 | 575 | |
ccff9b51 | 576 | if (status & MCI_DATAEND || data->error) { |
c8ebae37 RK |
577 | if (dma_inprogress(host)) |
578 | mmci_dma_unmap(host, data); | |
1da177e4 LT |
579 | mmci_stop_data(host); |
580 | ||
8cb28155 LW |
581 | if (!data->error) |
582 | /* The error clause is handled above, success! */ | |
51d4375d | 583 | data->bytes_xfered = data->blksz * data->blocks; |
f20f8f21 | 584 | |
1da177e4 LT |
585 | if (!data->stop) { |
586 | mmci_request_end(host, data->mrq); | |
587 | } else { | |
588 | mmci_start_command(host, data->stop, 0); | |
589 | } | |
590 | } | |
591 | } | |
592 | ||
593 | static void | |
594 | mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, | |
595 | unsigned int status) | |
596 | { | |
597 | void __iomem *base = host->base; | |
598 | ||
599 | host->cmd = NULL; | |
600 | ||
1da177e4 | 601 | if (status & MCI_CMDTIMEOUT) { |
17b0429d | 602 | cmd->error = -ETIMEDOUT; |
1da177e4 | 603 | } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { |
17b0429d | 604 | cmd->error = -EILSEQ; |
9047b435 RKAL |
605 | } else { |
606 | cmd->resp[0] = readl(base + MMCIRESPONSE0); | |
607 | cmd->resp[1] = readl(base + MMCIRESPONSE1); | |
608 | cmd->resp[2] = readl(base + MMCIRESPONSE2); | |
609 | cmd->resp[3] = readl(base + MMCIRESPONSE3); | |
1da177e4 LT |
610 | } |
611 | ||
17b0429d | 612 | if (!cmd->data || cmd->error) { |
e47c222b RK |
613 | if (host->data) |
614 | mmci_stop_data(host); | |
1da177e4 LT |
615 | mmci_request_end(host, cmd->mrq); |
616 | } else if (!(cmd->data->flags & MMC_DATA_READ)) { | |
617 | mmci_start_data(host, cmd->data); | |
618 | } | |
619 | } | |
620 | ||
621 | static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) | |
622 | { | |
623 | void __iomem *base = host->base; | |
624 | char *ptr = buffer; | |
625 | u32 status; | |
26eed9a5 | 626 | int host_remain = host->size; |
1da177e4 LT |
627 | |
628 | do { | |
26eed9a5 | 629 | int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); |
1da177e4 LT |
630 | |
631 | if (count > remain) | |
632 | count = remain; | |
633 | ||
634 | if (count <= 0) | |
635 | break; | |
636 | ||
637 | readsl(base + MMCIFIFO, ptr, count >> 2); | |
638 | ||
639 | ptr += count; | |
640 | remain -= count; | |
26eed9a5 | 641 | host_remain -= count; |
1da177e4 LT |
642 | |
643 | if (remain == 0) | |
644 | break; | |
645 | ||
646 | status = readl(base + MMCISTATUS); | |
647 | } while (status & MCI_RXDATAAVLBL); | |
648 | ||
649 | return ptr - buffer; | |
650 | } | |
651 | ||
652 | static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) | |
653 | { | |
8301bb68 | 654 | struct variant_data *variant = host->variant; |
1da177e4 LT |
655 | void __iomem *base = host->base; |
656 | char *ptr = buffer; | |
657 | ||
658 | do { | |
659 | unsigned int count, maxcnt; | |
660 | ||
8301bb68 RV |
661 | maxcnt = status & MCI_TXFIFOEMPTY ? |
662 | variant->fifosize : variant->fifohalfsize; | |
1da177e4 LT |
663 | count = min(remain, maxcnt); |
664 | ||
34177802 LW |
665 | /* |
666 | * The ST Micro variant for SDIO transfer sizes | |
667 | * less then 8 bytes should have clock H/W flow | |
668 | * control disabled. | |
669 | */ | |
670 | if (variant->sdio && | |
671 | mmc_card_sdio(host->mmc->card)) { | |
672 | if (count < 8) | |
673 | writel(readl(host->base + MMCICLOCK) & | |
674 | ~variant->clkreg_enable, | |
675 | host->base + MMCICLOCK); | |
676 | else | |
677 | writel(readl(host->base + MMCICLOCK) | | |
678 | variant->clkreg_enable, | |
679 | host->base + MMCICLOCK); | |
680 | } | |
681 | ||
682 | /* | |
683 | * SDIO especially may want to send something that is | |
684 | * not divisible by 4 (as opposed to card sectors | |
685 | * etc), and the FIFO only accept full 32-bit writes. | |
686 | * So compensate by adding +3 on the count, a single | |
687 | * byte become a 32bit write, 7 bytes will be two | |
688 | * 32bit writes etc. | |
689 | */ | |
690 | writesl(base + MMCIFIFO, ptr, (count + 3) >> 2); | |
1da177e4 LT |
691 | |
692 | ptr += count; | |
693 | remain -= count; | |
694 | ||
695 | if (remain == 0) | |
696 | break; | |
697 | ||
698 | status = readl(base + MMCISTATUS); | |
699 | } while (status & MCI_TXFIFOHALFEMPTY); | |
700 | ||
701 | return ptr - buffer; | |
702 | } | |
703 | ||
704 | /* | |
705 | * PIO data transfer IRQ handler. | |
706 | */ | |
7d12e780 | 707 | static irqreturn_t mmci_pio_irq(int irq, void *dev_id) |
1da177e4 LT |
708 | { |
709 | struct mmci_host *host = dev_id; | |
4ce1d6cb | 710 | struct sg_mapping_iter *sg_miter = &host->sg_miter; |
8301bb68 | 711 | struct variant_data *variant = host->variant; |
1da177e4 | 712 | void __iomem *base = host->base; |
4ce1d6cb | 713 | unsigned long flags; |
1da177e4 LT |
714 | u32 status; |
715 | ||
716 | status = readl(base + MMCISTATUS); | |
717 | ||
64de0289 | 718 | dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); |
1da177e4 | 719 | |
4ce1d6cb RV |
720 | local_irq_save(flags); |
721 | ||
1da177e4 | 722 | do { |
1da177e4 LT |
723 | unsigned int remain, len; |
724 | char *buffer; | |
725 | ||
726 | /* | |
727 | * For write, we only need to test the half-empty flag | |
728 | * here - if the FIFO is completely empty, then by | |
729 | * definition it is more than half empty. | |
730 | * | |
731 | * For read, check for data available. | |
732 | */ | |
733 | if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) | |
734 | break; | |
735 | ||
4ce1d6cb RV |
736 | if (!sg_miter_next(sg_miter)) |
737 | break; | |
738 | ||
739 | buffer = sg_miter->addr; | |
740 | remain = sg_miter->length; | |
1da177e4 LT |
741 | |
742 | len = 0; | |
743 | if (status & MCI_RXACTIVE) | |
744 | len = mmci_pio_read(host, buffer, remain); | |
745 | if (status & MCI_TXACTIVE) | |
746 | len = mmci_pio_write(host, buffer, remain, status); | |
747 | ||
4ce1d6cb | 748 | sg_miter->consumed = len; |
1da177e4 | 749 | |
1da177e4 LT |
750 | host->size -= len; |
751 | remain -= len; | |
752 | ||
753 | if (remain) | |
754 | break; | |
755 | ||
1da177e4 LT |
756 | status = readl(base + MMCISTATUS); |
757 | } while (1); | |
758 | ||
4ce1d6cb RV |
759 | sg_miter_stop(sg_miter); |
760 | ||
761 | local_irq_restore(flags); | |
762 | ||
1da177e4 | 763 | /* |
c4d877c1 RK |
764 | * If we have less than the fifo 'half-full' threshold to transfer, |
765 | * trigger a PIO interrupt as soon as any data is available. | |
1da177e4 | 766 | */ |
c4d877c1 | 767 | if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) |
2686b4b4 | 768 | mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); |
1da177e4 LT |
769 | |
770 | /* | |
771 | * If we run out of data, disable the data IRQs; this | |
772 | * prevents a race where the FIFO becomes empty before | |
773 | * the chip itself has disabled the data path, and | |
774 | * stops us racing with our data end IRQ. | |
775 | */ | |
776 | if (host->size == 0) { | |
2686b4b4 | 777 | mmci_set_mask1(host, 0); |
1da177e4 LT |
778 | writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); |
779 | } | |
780 | ||
781 | return IRQ_HANDLED; | |
782 | } | |
783 | ||
784 | /* | |
785 | * Handle completion of command and data transfers. | |
786 | */ | |
7d12e780 | 787 | static irqreturn_t mmci_irq(int irq, void *dev_id) |
1da177e4 LT |
788 | { |
789 | struct mmci_host *host = dev_id; | |
790 | u32 status; | |
791 | int ret = 0; | |
792 | ||
793 | spin_lock(&host->lock); | |
794 | ||
795 | do { | |
796 | struct mmc_command *cmd; | |
797 | struct mmc_data *data; | |
798 | ||
799 | status = readl(host->base + MMCISTATUS); | |
2686b4b4 LW |
800 | |
801 | if (host->singleirq) { | |
802 | if (status & readl(host->base + MMCIMASK1)) | |
803 | mmci_pio_irq(irq, dev_id); | |
804 | ||
805 | status &= ~MCI_IRQ1MASK; | |
806 | } | |
807 | ||
1da177e4 LT |
808 | status &= readl(host->base + MMCIMASK0); |
809 | writel(status, host->base + MMCICLEAR); | |
810 | ||
64de0289 | 811 | dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); |
1da177e4 LT |
812 | |
813 | data = host->data; | |
814 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN| | |
815 | MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data) | |
816 | mmci_data_irq(host, data, status); | |
817 | ||
818 | cmd = host->cmd; | |
819 | if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) | |
820 | mmci_cmd_irq(host, cmd, status); | |
821 | ||
822 | ret = 1; | |
823 | } while (status); | |
824 | ||
825 | spin_unlock(&host->lock); | |
826 | ||
827 | return IRQ_RETVAL(ret); | |
828 | } | |
829 | ||
830 | static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
831 | { | |
832 | struct mmci_host *host = mmc_priv(mmc); | |
9e943021 | 833 | unsigned long flags; |
1da177e4 LT |
834 | |
835 | WARN_ON(host->mrq != NULL); | |
836 | ||
019a5f56 | 837 | if (mrq->data && !is_power_of_2(mrq->data->blksz)) { |
64de0289 LW |
838 | dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", |
839 | mrq->data->blksz); | |
255d01af PO |
840 | mrq->cmd->error = -EINVAL; |
841 | mmc_request_done(mmc, mrq); | |
842 | return; | |
843 | } | |
844 | ||
9e943021 | 845 | spin_lock_irqsave(&host->lock, flags); |
1da177e4 LT |
846 | |
847 | host->mrq = mrq; | |
848 | ||
849 | if (mrq->data && mrq->data->flags & MMC_DATA_READ) | |
850 | mmci_start_data(host, mrq->data); | |
851 | ||
852 | mmci_start_command(host, mrq->cmd, 0); | |
853 | ||
9e943021 | 854 | spin_unlock_irqrestore(&host->lock, flags); |
1da177e4 LT |
855 | } |
856 | ||
857 | static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
858 | { | |
859 | struct mmci_host *host = mmc_priv(mmc); | |
a6a6464a LW |
860 | u32 pwr = 0; |
861 | unsigned long flags; | |
99fc5131 | 862 | int ret; |
1da177e4 | 863 | |
1da177e4 LT |
864 | switch (ios->power_mode) { |
865 | case MMC_POWER_OFF: | |
99fc5131 LW |
866 | if (host->vcc) |
867 | ret = mmc_regulator_set_ocr(mmc, host->vcc, 0); | |
1da177e4 LT |
868 | break; |
869 | case MMC_POWER_UP: | |
99fc5131 LW |
870 | if (host->vcc) { |
871 | ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd); | |
872 | if (ret) { | |
873 | dev_err(mmc_dev(mmc), "unable to set OCR\n"); | |
874 | /* | |
875 | * The .set_ios() function in the mmc_host_ops | |
876 | * struct return void, and failing to set the | |
877 | * power should be rare so we print an error | |
878 | * and return here. | |
879 | */ | |
880 | return; | |
881 | } | |
882 | } | |
bb8f563c RV |
883 | if (host->plat->vdd_handler) |
884 | pwr |= host->plat->vdd_handler(mmc_dev(mmc), ios->vdd, | |
885 | ios->power_mode); | |
cc30d60e | 886 | /* The ST version does not have this, fall through to POWER_ON */ |
f17a1f06 | 887 | if (host->hw_designer != AMBA_VENDOR_ST) { |
cc30d60e LW |
888 | pwr |= MCI_PWR_UP; |
889 | break; | |
890 | } | |
1da177e4 LT |
891 | case MMC_POWER_ON: |
892 | pwr |= MCI_PWR_ON; | |
893 | break; | |
894 | } | |
895 | ||
cc30d60e | 896 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { |
f17a1f06 | 897 | if (host->hw_designer != AMBA_VENDOR_ST) |
cc30d60e LW |
898 | pwr |= MCI_ROD; |
899 | else { | |
900 | /* | |
901 | * The ST Micro variant use the ROD bit for something | |
902 | * else and only has OD (Open Drain). | |
903 | */ | |
904 | pwr |= MCI_OD; | |
905 | } | |
906 | } | |
1da177e4 | 907 | |
a6a6464a LW |
908 | spin_lock_irqsave(&host->lock, flags); |
909 | ||
910 | mmci_set_clkreg(host, ios->clock); | |
1da177e4 LT |
911 | |
912 | if (host->pwr != pwr) { | |
913 | host->pwr = pwr; | |
914 | writel(pwr, host->base + MMCIPOWER); | |
915 | } | |
a6a6464a LW |
916 | |
917 | spin_unlock_irqrestore(&host->lock, flags); | |
1da177e4 LT |
918 | } |
919 | ||
89001446 RK |
920 | static int mmci_get_ro(struct mmc_host *mmc) |
921 | { | |
922 | struct mmci_host *host = mmc_priv(mmc); | |
923 | ||
924 | if (host->gpio_wp == -ENOSYS) | |
925 | return -ENOSYS; | |
926 | ||
18a06301 | 927 | return gpio_get_value_cansleep(host->gpio_wp); |
89001446 RK |
928 | } |
929 | ||
930 | static int mmci_get_cd(struct mmc_host *mmc) | |
931 | { | |
932 | struct mmci_host *host = mmc_priv(mmc); | |
29719445 | 933 | struct mmci_platform_data *plat = host->plat; |
89001446 RK |
934 | unsigned int status; |
935 | ||
4b8caec0 RV |
936 | if (host->gpio_cd == -ENOSYS) { |
937 | if (!plat->status) | |
938 | return 1; /* Assume always present */ | |
939 | ||
29719445 | 940 | status = plat->status(mmc_dev(host->mmc)); |
4b8caec0 | 941 | } else |
18a06301 LW |
942 | status = !!gpio_get_value_cansleep(host->gpio_cd) |
943 | ^ plat->cd_invert; | |
89001446 | 944 | |
74bc8093 RK |
945 | /* |
946 | * Use positive logic throughout - status is zero for no card, | |
947 | * non-zero for card inserted. | |
948 | */ | |
949 | return status; | |
89001446 RK |
950 | } |
951 | ||
148b8b39 RV |
952 | static irqreturn_t mmci_cd_irq(int irq, void *dev_id) |
953 | { | |
954 | struct mmci_host *host = dev_id; | |
955 | ||
956 | mmc_detect_change(host->mmc, msecs_to_jiffies(500)); | |
957 | ||
958 | return IRQ_HANDLED; | |
959 | } | |
960 | ||
ab7aefd0 | 961 | static const struct mmc_host_ops mmci_ops = { |
1da177e4 LT |
962 | .request = mmci_request, |
963 | .set_ios = mmci_set_ios, | |
89001446 RK |
964 | .get_ro = mmci_get_ro, |
965 | .get_cd = mmci_get_cd, | |
1da177e4 LT |
966 | }; |
967 | ||
aa25afad RK |
968 | static int __devinit mmci_probe(struct amba_device *dev, |
969 | const struct amba_id *id) | |
1da177e4 | 970 | { |
6ef297f8 | 971 | struct mmci_platform_data *plat = dev->dev.platform_data; |
4956e109 | 972 | struct variant_data *variant = id->data; |
1da177e4 LT |
973 | struct mmci_host *host; |
974 | struct mmc_host *mmc; | |
975 | int ret; | |
976 | ||
977 | /* must have platform data */ | |
978 | if (!plat) { | |
979 | ret = -EINVAL; | |
980 | goto out; | |
981 | } | |
982 | ||
983 | ret = amba_request_regions(dev, DRIVER_NAME); | |
984 | if (ret) | |
985 | goto out; | |
986 | ||
987 | mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); | |
988 | if (!mmc) { | |
989 | ret = -ENOMEM; | |
990 | goto rel_regions; | |
991 | } | |
992 | ||
993 | host = mmc_priv(mmc); | |
4ea580f1 | 994 | host->mmc = mmc; |
012b7d33 | 995 | |
89001446 RK |
996 | host->gpio_wp = -ENOSYS; |
997 | host->gpio_cd = -ENOSYS; | |
148b8b39 | 998 | host->gpio_cd_irq = -1; |
89001446 | 999 | |
012b7d33 RK |
1000 | host->hw_designer = amba_manf(dev); |
1001 | host->hw_revision = amba_rev(dev); | |
64de0289 LW |
1002 | dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); |
1003 | dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); | |
012b7d33 | 1004 | |
ee569c43 | 1005 | host->clk = clk_get(&dev->dev, NULL); |
1da177e4 LT |
1006 | if (IS_ERR(host->clk)) { |
1007 | ret = PTR_ERR(host->clk); | |
1008 | host->clk = NULL; | |
1009 | goto host_free; | |
1010 | } | |
1011 | ||
1da177e4 LT |
1012 | ret = clk_enable(host->clk); |
1013 | if (ret) | |
a8d3584a | 1014 | goto clk_free; |
1da177e4 LT |
1015 | |
1016 | host->plat = plat; | |
4956e109 | 1017 | host->variant = variant; |
1da177e4 | 1018 | host->mclk = clk_get_rate(host->clk); |
c8df9a53 LW |
1019 | /* |
1020 | * According to the spec, mclk is max 100 MHz, | |
1021 | * so we try to adjust the clock down to this, | |
1022 | * (if possible). | |
1023 | */ | |
1024 | if (host->mclk > 100000000) { | |
1025 | ret = clk_set_rate(host->clk, 100000000); | |
1026 | if (ret < 0) | |
1027 | goto clk_disable; | |
1028 | host->mclk = clk_get_rate(host->clk); | |
64de0289 LW |
1029 | dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", |
1030 | host->mclk); | |
c8df9a53 | 1031 | } |
c8ebae37 | 1032 | host->phybase = dev->res.start; |
dc890c2d | 1033 | host->base = ioremap(dev->res.start, resource_size(&dev->res)); |
1da177e4 LT |
1034 | if (!host->base) { |
1035 | ret = -ENOMEM; | |
1036 | goto clk_disable; | |
1037 | } | |
1038 | ||
1039 | mmc->ops = &mmci_ops; | |
1040 | mmc->f_min = (host->mclk + 511) / 512; | |
808d97cc LW |
1041 | /* |
1042 | * If the platform data supplies a maximum operating | |
1043 | * frequency, this takes precedence. Else, we fall back | |
1044 | * to using the module parameter, which has a (low) | |
1045 | * default value in case it is not specified. Either | |
1046 | * value must not exceed the clock rate into the block, | |
1047 | * of course. | |
1048 | */ | |
1049 | if (plat->f_max) | |
1050 | mmc->f_max = min(host->mclk, plat->f_max); | |
1051 | else | |
1052 | mmc->f_max = min(host->mclk, fmax); | |
64de0289 LW |
1053 | dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); |
1054 | ||
34e84f39 LW |
1055 | #ifdef CONFIG_REGULATOR |
1056 | /* If we're using the regulator framework, try to fetch a regulator */ | |
1057 | host->vcc = regulator_get(&dev->dev, "vmmc"); | |
1058 | if (IS_ERR(host->vcc)) | |
1059 | host->vcc = NULL; | |
1060 | else { | |
1061 | int mask = mmc_regulator_get_ocrmask(host->vcc); | |
1062 | ||
1063 | if (mask < 0) | |
1064 | dev_err(&dev->dev, "error getting OCR mask (%d)\n", | |
1065 | mask); | |
1066 | else { | |
1067 | host->mmc->ocr_avail = (u32) mask; | |
1068 | if (plat->ocr_mask) | |
1069 | dev_warn(&dev->dev, | |
1070 | "Provided ocr_mask/setpower will not be used " | |
1071 | "(using regulator instead)\n"); | |
1072 | } | |
1073 | } | |
1074 | #endif | |
1075 | /* Fall back to platform data if no regulator is found */ | |
1076 | if (host->vcc == NULL) | |
1077 | mmc->ocr_avail = plat->ocr_mask; | |
9e6c82cd | 1078 | mmc->caps = plat->capabilities; |
1da177e4 LT |
1079 | |
1080 | /* | |
1081 | * We can do SGIO | |
1082 | */ | |
a36274e0 | 1083 | mmc->max_segs = NR_SG; |
1da177e4 LT |
1084 | |
1085 | /* | |
08458ef6 RV |
1086 | * Since only a certain number of bits are valid in the data length |
1087 | * register, we must ensure that we don't exceed 2^num-1 bytes in a | |
1088 | * single request. | |
1da177e4 | 1089 | */ |
08458ef6 | 1090 | mmc->max_req_size = (1 << variant->datalength_bits) - 1; |
1da177e4 LT |
1091 | |
1092 | /* | |
1093 | * Set the maximum segment size. Since we aren't doing DMA | |
1094 | * (yet) we are only limited by the data length register. | |
1095 | */ | |
55db890a | 1096 | mmc->max_seg_size = mmc->max_req_size; |
1da177e4 | 1097 | |
fe4a3c7a PO |
1098 | /* |
1099 | * Block size can be up to 2048 bytes, but must be a power of two. | |
1100 | */ | |
1101 | mmc->max_blk_size = 2048; | |
1102 | ||
55db890a PO |
1103 | /* |
1104 | * No limit on the number of blocks transferred. | |
1105 | */ | |
1106 | mmc->max_blk_count = mmc->max_req_size; | |
1107 | ||
1da177e4 LT |
1108 | spin_lock_init(&host->lock); |
1109 | ||
1110 | writel(0, host->base + MMCIMASK0); | |
1111 | writel(0, host->base + MMCIMASK1); | |
1112 | writel(0xfff, host->base + MMCICLEAR); | |
1113 | ||
89001446 RK |
1114 | if (gpio_is_valid(plat->gpio_cd)) { |
1115 | ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); | |
1116 | if (ret == 0) | |
1117 | ret = gpio_direction_input(plat->gpio_cd); | |
1118 | if (ret == 0) | |
1119 | host->gpio_cd = plat->gpio_cd; | |
1120 | else if (ret != -ENOSYS) | |
1121 | goto err_gpio_cd; | |
148b8b39 RV |
1122 | |
1123 | ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), | |
1124 | mmci_cd_irq, 0, | |
1125 | DRIVER_NAME " (cd)", host); | |
1126 | if (ret >= 0) | |
1127 | host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); | |
89001446 RK |
1128 | } |
1129 | if (gpio_is_valid(plat->gpio_wp)) { | |
1130 | ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); | |
1131 | if (ret == 0) | |
1132 | ret = gpio_direction_input(plat->gpio_wp); | |
1133 | if (ret == 0) | |
1134 | host->gpio_wp = plat->gpio_wp; | |
1135 | else if (ret != -ENOSYS) | |
1136 | goto err_gpio_wp; | |
1137 | } | |
1138 | ||
4b8caec0 RV |
1139 | if ((host->plat->status || host->gpio_cd != -ENOSYS) |
1140 | && host->gpio_cd_irq < 0) | |
148b8b39 RV |
1141 | mmc->caps |= MMC_CAP_NEEDS_POLL; |
1142 | ||
dace1453 | 1143 | ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); |
1da177e4 LT |
1144 | if (ret) |
1145 | goto unmap; | |
1146 | ||
2686b4b4 LW |
1147 | if (dev->irq[1] == NO_IRQ) |
1148 | host->singleirq = true; | |
1149 | else { | |
1150 | ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, | |
1151 | DRIVER_NAME " (pio)", host); | |
1152 | if (ret) | |
1153 | goto irq0_free; | |
1154 | } | |
1da177e4 | 1155 | |
8cb28155 | 1156 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); |
1da177e4 LT |
1157 | |
1158 | amba_set_drvdata(dev, mmc); | |
1159 | ||
c8ebae37 RK |
1160 | dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", |
1161 | mmc_hostname(mmc), amba_part(dev), amba_manf(dev), | |
1162 | amba_rev(dev), (unsigned long long)dev->res.start, | |
1163 | dev->irq[0], dev->irq[1]); | |
1164 | ||
1165 | mmci_dma_setup(host); | |
1da177e4 | 1166 | |
8c11a94d RK |
1167 | mmc_add_host(mmc); |
1168 | ||
1da177e4 LT |
1169 | return 0; |
1170 | ||
1171 | irq0_free: | |
1172 | free_irq(dev->irq[0], host); | |
1173 | unmap: | |
89001446 RK |
1174 | if (host->gpio_wp != -ENOSYS) |
1175 | gpio_free(host->gpio_wp); | |
1176 | err_gpio_wp: | |
148b8b39 RV |
1177 | if (host->gpio_cd_irq >= 0) |
1178 | free_irq(host->gpio_cd_irq, host); | |
89001446 RK |
1179 | if (host->gpio_cd != -ENOSYS) |
1180 | gpio_free(host->gpio_cd); | |
1181 | err_gpio_cd: | |
1da177e4 LT |
1182 | iounmap(host->base); |
1183 | clk_disable: | |
1184 | clk_disable(host->clk); | |
1da177e4 LT |
1185 | clk_free: |
1186 | clk_put(host->clk); | |
1187 | host_free: | |
1188 | mmc_free_host(mmc); | |
1189 | rel_regions: | |
1190 | amba_release_regions(dev); | |
1191 | out: | |
1192 | return ret; | |
1193 | } | |
1194 | ||
6dc4a47a | 1195 | static int __devexit mmci_remove(struct amba_device *dev) |
1da177e4 LT |
1196 | { |
1197 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
1198 | ||
1199 | amba_set_drvdata(dev, NULL); | |
1200 | ||
1201 | if (mmc) { | |
1202 | struct mmci_host *host = mmc_priv(mmc); | |
1203 | ||
1da177e4 LT |
1204 | mmc_remove_host(mmc); |
1205 | ||
1206 | writel(0, host->base + MMCIMASK0); | |
1207 | writel(0, host->base + MMCIMASK1); | |
1208 | ||
1209 | writel(0, host->base + MMCICOMMAND); | |
1210 | writel(0, host->base + MMCIDATACTRL); | |
1211 | ||
c8ebae37 | 1212 | mmci_dma_release(host); |
1da177e4 | 1213 | free_irq(dev->irq[0], host); |
2686b4b4 LW |
1214 | if (!host->singleirq) |
1215 | free_irq(dev->irq[1], host); | |
1da177e4 | 1216 | |
89001446 RK |
1217 | if (host->gpio_wp != -ENOSYS) |
1218 | gpio_free(host->gpio_wp); | |
148b8b39 RV |
1219 | if (host->gpio_cd_irq >= 0) |
1220 | free_irq(host->gpio_cd_irq, host); | |
89001446 RK |
1221 | if (host->gpio_cd != -ENOSYS) |
1222 | gpio_free(host->gpio_cd); | |
1223 | ||
1da177e4 LT |
1224 | iounmap(host->base); |
1225 | clk_disable(host->clk); | |
1da177e4 LT |
1226 | clk_put(host->clk); |
1227 | ||
99fc5131 LW |
1228 | if (host->vcc) |
1229 | mmc_regulator_set_ocr(mmc, host->vcc, 0); | |
34e84f39 LW |
1230 | regulator_put(host->vcc); |
1231 | ||
1da177e4 LT |
1232 | mmc_free_host(mmc); |
1233 | ||
1234 | amba_release_regions(dev); | |
1235 | } | |
1236 | ||
1237 | return 0; | |
1238 | } | |
1239 | ||
1240 | #ifdef CONFIG_PM | |
e5378ca8 | 1241 | static int mmci_suspend(struct amba_device *dev, pm_message_t state) |
1da177e4 LT |
1242 | { |
1243 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
1244 | int ret = 0; | |
1245 | ||
1246 | if (mmc) { | |
1247 | struct mmci_host *host = mmc_priv(mmc); | |
1248 | ||
1a13f8fa | 1249 | ret = mmc_suspend_host(mmc); |
1da177e4 LT |
1250 | if (ret == 0) |
1251 | writel(0, host->base + MMCIMASK0); | |
1252 | } | |
1253 | ||
1254 | return ret; | |
1255 | } | |
1256 | ||
1257 | static int mmci_resume(struct amba_device *dev) | |
1258 | { | |
1259 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
1260 | int ret = 0; | |
1261 | ||
1262 | if (mmc) { | |
1263 | struct mmci_host *host = mmc_priv(mmc); | |
1264 | ||
1265 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); | |
1266 | ||
1267 | ret = mmc_resume_host(mmc); | |
1268 | } | |
1269 | ||
1270 | return ret; | |
1271 | } | |
1272 | #else | |
1273 | #define mmci_suspend NULL | |
1274 | #define mmci_resume NULL | |
1275 | #endif | |
1276 | ||
1277 | static struct amba_id mmci_ids[] = { | |
1278 | { | |
1279 | .id = 0x00041180, | |
1280 | .mask = 0x000fffff, | |
4956e109 | 1281 | .data = &variant_arm, |
1da177e4 LT |
1282 | }, |
1283 | { | |
1284 | .id = 0x00041181, | |
1285 | .mask = 0x000fffff, | |
4956e109 | 1286 | .data = &variant_arm, |
1da177e4 | 1287 | }, |
cc30d60e LW |
1288 | /* ST Micro variants */ |
1289 | { | |
1290 | .id = 0x00180180, | |
1291 | .mask = 0x00ffffff, | |
4956e109 | 1292 | .data = &variant_u300, |
cc30d60e LW |
1293 | }, |
1294 | { | |
1295 | .id = 0x00280180, | |
1296 | .mask = 0x00ffffff, | |
4956e109 RV |
1297 | .data = &variant_u300, |
1298 | }, | |
1299 | { | |
1300 | .id = 0x00480180, | |
1301 | .mask = 0x00ffffff, | |
1302 | .data = &variant_ux500, | |
cc30d60e | 1303 | }, |
1da177e4 LT |
1304 | { 0, 0 }, |
1305 | }; | |
1306 | ||
1307 | static struct amba_driver mmci_driver = { | |
1308 | .drv = { | |
1309 | .name = DRIVER_NAME, | |
1310 | }, | |
1311 | .probe = mmci_probe, | |
6dc4a47a | 1312 | .remove = __devexit_p(mmci_remove), |
1da177e4 LT |
1313 | .suspend = mmci_suspend, |
1314 | .resume = mmci_resume, | |
1315 | .id_table = mmci_ids, | |
1316 | }; | |
1317 | ||
1318 | static int __init mmci_init(void) | |
1319 | { | |
1320 | return amba_driver_register(&mmci_driver); | |
1321 | } | |
1322 | ||
1323 | static void __exit mmci_exit(void) | |
1324 | { | |
1325 | amba_driver_unregister(&mmci_driver); | |
1326 | } | |
1327 | ||
1328 | module_init(mmci_init); | |
1329 | module_exit(mmci_exit); | |
1330 | module_param(fmax, uint, 0444); | |
1331 | ||
1332 | MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); | |
1333 | MODULE_LICENSE("GPL"); |