Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. | |
c8ebae37 | 5 | * Copyright (C) 2010 ST-Ericsson SA |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/interrupt.h> | |
613b152c | 17 | #include <linux/kernel.h> |
000bc9d5 | 18 | #include <linux/slab.h> |
1da177e4 LT |
19 | #include <linux/delay.h> |
20 | #include <linux/err.h> | |
21 | #include <linux/highmem.h> | |
019a5f56 | 22 | #include <linux/log2.h> |
1da177e4 | 23 | #include <linux/mmc/host.h> |
34177802 | 24 | #include <linux/mmc/card.h> |
a62c80e5 | 25 | #include <linux/amba/bus.h> |
f8ce2547 | 26 | #include <linux/clk.h> |
bd6dee6f | 27 | #include <linux/scatterlist.h> |
89001446 | 28 | #include <linux/gpio.h> |
9a597016 | 29 | #include <linux/of_gpio.h> |
34e84f39 | 30 | #include <linux/regulator/consumer.h> |
c8ebae37 RK |
31 | #include <linux/dmaengine.h> |
32 | #include <linux/dma-mapping.h> | |
33 | #include <linux/amba/mmci.h> | |
1c3be369 | 34 | #include <linux/pm_runtime.h> |
258aea76 | 35 | #include <linux/types.h> |
a9a83785 | 36 | #include <linux/pinctrl/consumer.h> |
1da177e4 | 37 | |
7b09cdac | 38 | #include <asm/div64.h> |
1da177e4 | 39 | #include <asm/io.h> |
c6b8fdad | 40 | #include <asm/sizes.h> |
1da177e4 LT |
41 | |
42 | #include "mmci.h" | |
43 | ||
44 | #define DRIVER_NAME "mmci-pl18x" | |
45 | ||
1da177e4 LT |
46 | static unsigned int fmax = 515633; |
47 | ||
4956e109 RV |
48 | /** |
49 | * struct variant_data - MMCI variant-specific quirks | |
50 | * @clkreg: default value for MCICLOCK register | |
4380c14f | 51 | * @clkreg_enable: enable value for MMCICLOCK register |
08458ef6 | 52 | * @datalength_bits: number of bits in the MMCIDATALENGTH register |
8301bb68 RV |
53 | * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY |
54 | * is asserted (likewise for RX) | |
55 | * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY | |
56 | * is asserted (likewise for RX) | |
34177802 | 57 | * @sdio: variant supports SDIO |
b70a67f9 | 58 | * @st_clkdiv: true if using a ST-specific clock divider algorithm |
1784b157 | 59 | * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register |
7d72a1d4 | 60 | * @pwrreg_powerup: power up value for MMCIPOWER register |
4d1a3a0d | 61 | * @signal_direction: input/out direction of bus signals can be indicated |
4956e109 RV |
62 | */ |
63 | struct variant_data { | |
64 | unsigned int clkreg; | |
4380c14f | 65 | unsigned int clkreg_enable; |
08458ef6 | 66 | unsigned int datalength_bits; |
8301bb68 RV |
67 | unsigned int fifosize; |
68 | unsigned int fifohalfsize; | |
34177802 | 69 | bool sdio; |
b70a67f9 | 70 | bool st_clkdiv; |
1784b157 | 71 | bool blksz_datactrl16; |
7d72a1d4 | 72 | u32 pwrreg_powerup; |
4d1a3a0d | 73 | bool signal_direction; |
4956e109 RV |
74 | }; |
75 | ||
76 | static struct variant_data variant_arm = { | |
8301bb68 RV |
77 | .fifosize = 16 * 4, |
78 | .fifohalfsize = 8 * 4, | |
08458ef6 | 79 | .datalength_bits = 16, |
7d72a1d4 | 80 | .pwrreg_powerup = MCI_PWR_UP, |
4956e109 RV |
81 | }; |
82 | ||
768fbc18 PM |
83 | static struct variant_data variant_arm_extended_fifo = { |
84 | .fifosize = 128 * 4, | |
85 | .fifohalfsize = 64 * 4, | |
86 | .datalength_bits = 16, | |
7d72a1d4 | 87 | .pwrreg_powerup = MCI_PWR_UP, |
768fbc18 PM |
88 | }; |
89 | ||
4956e109 | 90 | static struct variant_data variant_u300 = { |
8301bb68 RV |
91 | .fifosize = 16 * 4, |
92 | .fifohalfsize = 8 * 4, | |
49ac215e | 93 | .clkreg_enable = MCI_ST_U300_HWFCEN, |
08458ef6 | 94 | .datalength_bits = 16, |
34177802 | 95 | .sdio = true, |
7d72a1d4 | 96 | .pwrreg_powerup = MCI_PWR_ON, |
4d1a3a0d | 97 | .signal_direction = true, |
4956e109 RV |
98 | }; |
99 | ||
34fd4213 LW |
100 | static struct variant_data variant_nomadik = { |
101 | .fifosize = 16 * 4, | |
102 | .fifohalfsize = 8 * 4, | |
103 | .clkreg = MCI_CLK_ENABLE, | |
104 | .datalength_bits = 24, | |
105 | .sdio = true, | |
106 | .st_clkdiv = true, | |
107 | .pwrreg_powerup = MCI_PWR_ON, | |
108 | .signal_direction = true, | |
109 | }; | |
110 | ||
4956e109 | 111 | static struct variant_data variant_ux500 = { |
8301bb68 RV |
112 | .fifosize = 30 * 4, |
113 | .fifohalfsize = 8 * 4, | |
4956e109 | 114 | .clkreg = MCI_CLK_ENABLE, |
49ac215e | 115 | .clkreg_enable = MCI_ST_UX500_HWFCEN, |
08458ef6 | 116 | .datalength_bits = 24, |
34177802 | 117 | .sdio = true, |
b70a67f9 | 118 | .st_clkdiv = true, |
7d72a1d4 | 119 | .pwrreg_powerup = MCI_PWR_ON, |
4d1a3a0d | 120 | .signal_direction = true, |
4956e109 | 121 | }; |
b70a67f9 | 122 | |
1784b157 PL |
123 | static struct variant_data variant_ux500v2 = { |
124 | .fifosize = 30 * 4, | |
125 | .fifohalfsize = 8 * 4, | |
126 | .clkreg = MCI_CLK_ENABLE, | |
127 | .clkreg_enable = MCI_ST_UX500_HWFCEN, | |
128 | .datalength_bits = 24, | |
129 | .sdio = true, | |
130 | .st_clkdiv = true, | |
131 | .blksz_datactrl16 = true, | |
7d72a1d4 | 132 | .pwrreg_powerup = MCI_PWR_ON, |
4d1a3a0d | 133 | .signal_direction = true, |
1784b157 PL |
134 | }; |
135 | ||
7437cfa5 UH |
136 | /* |
137 | * This must be called with host->lock held | |
138 | */ | |
139 | static void mmci_write_clkreg(struct mmci_host *host, u32 clk) | |
140 | { | |
141 | if (host->clk_reg != clk) { | |
142 | host->clk_reg = clk; | |
143 | writel(clk, host->base + MMCICLOCK); | |
144 | } | |
145 | } | |
146 | ||
147 | /* | |
148 | * This must be called with host->lock held | |
149 | */ | |
150 | static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) | |
151 | { | |
152 | if (host->pwr_reg != pwr) { | |
153 | host->pwr_reg = pwr; | |
154 | writel(pwr, host->base + MMCIPOWER); | |
155 | } | |
156 | } | |
157 | ||
a6a6464a LW |
158 | /* |
159 | * This must be called with host->lock held | |
160 | */ | |
161 | static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) | |
162 | { | |
4956e109 RV |
163 | struct variant_data *variant = host->variant; |
164 | u32 clk = variant->clkreg; | |
a6a6464a LW |
165 | |
166 | if (desired) { | |
167 | if (desired >= host->mclk) { | |
991a86e1 | 168 | clk = MCI_CLK_BYPASS; |
399bc486 LW |
169 | if (variant->st_clkdiv) |
170 | clk |= MCI_ST_UX500_NEG_EDGE; | |
a6a6464a | 171 | host->cclk = host->mclk; |
b70a67f9 LW |
172 | } else if (variant->st_clkdiv) { |
173 | /* | |
174 | * DB8500 TRM says f = mclk / (clkdiv + 2) | |
175 | * => clkdiv = (mclk / f) - 2 | |
176 | * Round the divider up so we don't exceed the max | |
177 | * frequency | |
178 | */ | |
179 | clk = DIV_ROUND_UP(host->mclk, desired) - 2; | |
180 | if (clk >= 256) | |
181 | clk = 255; | |
182 | host->cclk = host->mclk / (clk + 2); | |
a6a6464a | 183 | } else { |
b70a67f9 LW |
184 | /* |
185 | * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) | |
186 | * => clkdiv = mclk / (2 * f) - 1 | |
187 | */ | |
a6a6464a LW |
188 | clk = host->mclk / (2 * desired) - 1; |
189 | if (clk >= 256) | |
190 | clk = 255; | |
191 | host->cclk = host->mclk / (2 * (clk + 1)); | |
192 | } | |
4380c14f RV |
193 | |
194 | clk |= variant->clkreg_enable; | |
a6a6464a LW |
195 | clk |= MCI_CLK_ENABLE; |
196 | /* This hasn't proven to be worthwhile */ | |
197 | /* clk |= MCI_CLK_PWRSAVE; */ | |
198 | } | |
199 | ||
9e6c82cd | 200 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) |
771dc157 LW |
201 | clk |= MCI_4BIT_BUS; |
202 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) | |
203 | clk |= MCI_ST_8BIT_BUS; | |
9e6c82cd | 204 | |
7437cfa5 | 205 | mmci_write_clkreg(host, clk); |
a6a6464a LW |
206 | } |
207 | ||
1da177e4 LT |
208 | static void |
209 | mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) | |
210 | { | |
211 | writel(0, host->base + MMCICOMMAND); | |
212 | ||
e47c222b RK |
213 | BUG_ON(host->data); |
214 | ||
1da177e4 LT |
215 | host->mrq = NULL; |
216 | host->cmd = NULL; | |
217 | ||
1da177e4 | 218 | mmc_request_done(host->mmc, mrq); |
2cd976c4 UH |
219 | |
220 | pm_runtime_mark_last_busy(mmc_dev(host->mmc)); | |
221 | pm_runtime_put_autosuspend(mmc_dev(host->mmc)); | |
1da177e4 LT |
222 | } |
223 | ||
2686b4b4 LW |
224 | static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) |
225 | { | |
226 | void __iomem *base = host->base; | |
227 | ||
228 | if (host->singleirq) { | |
229 | unsigned int mask0 = readl(base + MMCIMASK0); | |
230 | ||
231 | mask0 &= ~MCI_IRQ1MASK; | |
232 | mask0 |= mask; | |
233 | ||
234 | writel(mask0, base + MMCIMASK0); | |
235 | } | |
236 | ||
237 | writel(mask, base + MMCIMASK1); | |
238 | } | |
239 | ||
1da177e4 LT |
240 | static void mmci_stop_data(struct mmci_host *host) |
241 | { | |
242 | writel(0, host->base + MMCIDATACTRL); | |
2686b4b4 | 243 | mmci_set_mask1(host, 0); |
1da177e4 LT |
244 | host->data = NULL; |
245 | } | |
246 | ||
4ce1d6cb RV |
247 | static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) |
248 | { | |
249 | unsigned int flags = SG_MITER_ATOMIC; | |
250 | ||
251 | if (data->flags & MMC_DATA_READ) | |
252 | flags |= SG_MITER_TO_SG; | |
253 | else | |
254 | flags |= SG_MITER_FROM_SG; | |
255 | ||
256 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); | |
257 | } | |
258 | ||
c8ebae37 RK |
259 | /* |
260 | * All the DMA operation mode stuff goes inside this ifdef. | |
261 | * This assumes that you have a generic DMA device interface, | |
262 | * no custom DMA interfaces are supported. | |
263 | */ | |
264 | #ifdef CONFIG_DMA_ENGINE | |
265 | static void __devinit mmci_dma_setup(struct mmci_host *host) | |
266 | { | |
267 | struct mmci_platform_data *plat = host->plat; | |
268 | const char *rxname, *txname; | |
269 | dma_cap_mask_t mask; | |
270 | ||
271 | if (!plat || !plat->dma_filter) { | |
272 | dev_info(mmc_dev(host->mmc), "no DMA platform data\n"); | |
273 | return; | |
274 | } | |
275 | ||
58c7ccbf PF |
276 | /* initialize pre request cookie */ |
277 | host->next_data.cookie = 1; | |
278 | ||
c8ebae37 RK |
279 | /* Try to acquire a generic DMA engine slave channel */ |
280 | dma_cap_zero(mask); | |
281 | dma_cap_set(DMA_SLAVE, mask); | |
282 | ||
283 | /* | |
284 | * If only an RX channel is specified, the driver will | |
285 | * attempt to use it bidirectionally, however if it is | |
286 | * is specified but cannot be located, DMA will be disabled. | |
287 | */ | |
288 | if (plat->dma_rx_param) { | |
289 | host->dma_rx_channel = dma_request_channel(mask, | |
290 | plat->dma_filter, | |
291 | plat->dma_rx_param); | |
292 | /* E.g if no DMA hardware is present */ | |
293 | if (!host->dma_rx_channel) | |
294 | dev_err(mmc_dev(host->mmc), "no RX DMA channel\n"); | |
295 | } | |
296 | ||
297 | if (plat->dma_tx_param) { | |
298 | host->dma_tx_channel = dma_request_channel(mask, | |
299 | plat->dma_filter, | |
300 | plat->dma_tx_param); | |
301 | if (!host->dma_tx_channel) | |
302 | dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n"); | |
303 | } else { | |
304 | host->dma_tx_channel = host->dma_rx_channel; | |
305 | } | |
306 | ||
307 | if (host->dma_rx_channel) | |
308 | rxname = dma_chan_name(host->dma_rx_channel); | |
309 | else | |
310 | rxname = "none"; | |
311 | ||
312 | if (host->dma_tx_channel) | |
313 | txname = dma_chan_name(host->dma_tx_channel); | |
314 | else | |
315 | txname = "none"; | |
316 | ||
317 | dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", | |
318 | rxname, txname); | |
319 | ||
320 | /* | |
321 | * Limit the maximum segment size in any SG entry according to | |
322 | * the parameters of the DMA engine device. | |
323 | */ | |
324 | if (host->dma_tx_channel) { | |
325 | struct device *dev = host->dma_tx_channel->device->dev; | |
326 | unsigned int max_seg_size = dma_get_max_seg_size(dev); | |
327 | ||
328 | if (max_seg_size < host->mmc->max_seg_size) | |
329 | host->mmc->max_seg_size = max_seg_size; | |
330 | } | |
331 | if (host->dma_rx_channel) { | |
332 | struct device *dev = host->dma_rx_channel->device->dev; | |
333 | unsigned int max_seg_size = dma_get_max_seg_size(dev); | |
334 | ||
335 | if (max_seg_size < host->mmc->max_seg_size) | |
336 | host->mmc->max_seg_size = max_seg_size; | |
337 | } | |
338 | } | |
339 | ||
340 | /* | |
341 | * This is used in __devinit or __devexit so inline it | |
342 | * so it can be discarded. | |
343 | */ | |
344 | static inline void mmci_dma_release(struct mmci_host *host) | |
345 | { | |
346 | struct mmci_platform_data *plat = host->plat; | |
347 | ||
348 | if (host->dma_rx_channel) | |
349 | dma_release_channel(host->dma_rx_channel); | |
350 | if (host->dma_tx_channel && plat->dma_tx_param) | |
351 | dma_release_channel(host->dma_tx_channel); | |
352 | host->dma_rx_channel = host->dma_tx_channel = NULL; | |
353 | } | |
354 | ||
355 | static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) | |
356 | { | |
357 | struct dma_chan *chan = host->dma_current; | |
358 | enum dma_data_direction dir; | |
359 | u32 status; | |
360 | int i; | |
361 | ||
362 | /* Wait up to 1ms for the DMA to complete */ | |
363 | for (i = 0; ; i++) { | |
364 | status = readl(host->base + MMCISTATUS); | |
365 | if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) | |
366 | break; | |
367 | udelay(10); | |
368 | } | |
369 | ||
370 | /* | |
371 | * Check to see whether we still have some data left in the FIFO - | |
372 | * this catches DMA controllers which are unable to monitor the | |
373 | * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- | |
374 | * contiguous buffers. On TX, we'll get a FIFO underrun error. | |
375 | */ | |
376 | if (status & MCI_RXDATAAVLBLMASK) { | |
377 | dmaengine_terminate_all(chan); | |
378 | if (!data->error) | |
379 | data->error = -EIO; | |
380 | } | |
381 | ||
382 | if (data->flags & MMC_DATA_WRITE) { | |
383 | dir = DMA_TO_DEVICE; | |
384 | } else { | |
385 | dir = DMA_FROM_DEVICE; | |
386 | } | |
387 | ||
58c7ccbf PF |
388 | if (!data->host_cookie) |
389 | dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); | |
c8ebae37 RK |
390 | |
391 | /* | |
392 | * Use of DMA with scatter-gather is impossible. | |
393 | * Give up with DMA and switch back to PIO mode. | |
394 | */ | |
395 | if (status & MCI_RXDATAAVLBLMASK) { | |
396 | dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); | |
397 | mmci_dma_release(host); | |
398 | } | |
399 | } | |
400 | ||
401 | static void mmci_dma_data_error(struct mmci_host *host) | |
402 | { | |
403 | dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); | |
404 | dmaengine_terminate_all(host->dma_current); | |
405 | } | |
406 | ||
58c7ccbf PF |
407 | static int mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, |
408 | struct mmci_host_next *next) | |
c8ebae37 RK |
409 | { |
410 | struct variant_data *variant = host->variant; | |
411 | struct dma_slave_config conf = { | |
412 | .src_addr = host->phybase + MMCIFIFO, | |
413 | .dst_addr = host->phybase + MMCIFIFO, | |
414 | .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
415 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
416 | .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ | |
417 | .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ | |
258aea76 | 418 | .device_fc = false, |
c8ebae37 | 419 | }; |
c8ebae37 RK |
420 | struct dma_chan *chan; |
421 | struct dma_device *device; | |
422 | struct dma_async_tx_descriptor *desc; | |
05f5799c | 423 | enum dma_data_direction buffer_dirn; |
c8ebae37 RK |
424 | int nr_sg; |
425 | ||
58c7ccbf PF |
426 | /* Check if next job is already prepared */ |
427 | if (data->host_cookie && !next && | |
428 | host->dma_current && host->dma_desc_current) | |
429 | return 0; | |
430 | ||
431 | if (!next) { | |
432 | host->dma_current = NULL; | |
433 | host->dma_desc_current = NULL; | |
434 | } | |
c8ebae37 RK |
435 | |
436 | if (data->flags & MMC_DATA_READ) { | |
05f5799c VK |
437 | conf.direction = DMA_DEV_TO_MEM; |
438 | buffer_dirn = DMA_FROM_DEVICE; | |
c8ebae37 RK |
439 | chan = host->dma_rx_channel; |
440 | } else { | |
05f5799c VK |
441 | conf.direction = DMA_MEM_TO_DEV; |
442 | buffer_dirn = DMA_TO_DEVICE; | |
c8ebae37 RK |
443 | chan = host->dma_tx_channel; |
444 | } | |
445 | ||
446 | /* If there's no DMA channel, fall back to PIO */ | |
447 | if (!chan) | |
448 | return -EINVAL; | |
449 | ||
450 | /* If less than or equal to the fifo size, don't bother with DMA */ | |
58c7ccbf | 451 | if (data->blksz * data->blocks <= variant->fifosize) |
c8ebae37 RK |
452 | return -EINVAL; |
453 | ||
454 | device = chan->device; | |
05f5799c | 455 | nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); |
c8ebae37 RK |
456 | if (nr_sg == 0) |
457 | return -EINVAL; | |
458 | ||
459 | dmaengine_slave_config(chan, &conf); | |
16052827 | 460 | desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, |
c8ebae37 RK |
461 | conf.direction, DMA_CTRL_ACK); |
462 | if (!desc) | |
463 | goto unmap_exit; | |
464 | ||
58c7ccbf PF |
465 | if (next) { |
466 | next->dma_chan = chan; | |
467 | next->dma_desc = desc; | |
468 | } else { | |
469 | host->dma_current = chan; | |
470 | host->dma_desc_current = desc; | |
471 | } | |
472 | ||
473 | return 0; | |
c8ebae37 | 474 | |
58c7ccbf PF |
475 | unmap_exit: |
476 | if (!next) | |
477 | dmaengine_terminate_all(chan); | |
05f5799c | 478 | dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); |
58c7ccbf PF |
479 | return -ENOMEM; |
480 | } | |
481 | ||
482 | static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) | |
483 | { | |
484 | int ret; | |
485 | struct mmc_data *data = host->data; | |
486 | ||
487 | ret = mmci_dma_prep_data(host, host->data, NULL); | |
488 | if (ret) | |
489 | return ret; | |
490 | ||
491 | /* Okay, go for it. */ | |
c8ebae37 RK |
492 | dev_vdbg(mmc_dev(host->mmc), |
493 | "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", | |
494 | data->sg_len, data->blksz, data->blocks, data->flags); | |
58c7ccbf PF |
495 | dmaengine_submit(host->dma_desc_current); |
496 | dma_async_issue_pending(host->dma_current); | |
c8ebae37 RK |
497 | |
498 | datactrl |= MCI_DPSM_DMAENABLE; | |
499 | ||
500 | /* Trigger the DMA transfer */ | |
501 | writel(datactrl, host->base + MMCIDATACTRL); | |
502 | ||
503 | /* | |
504 | * Let the MMCI say when the data is ended and it's time | |
505 | * to fire next DMA request. When that happens, MMCI will | |
506 | * call mmci_data_end() | |
507 | */ | |
508 | writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, | |
509 | host->base + MMCIMASK0); | |
510 | return 0; | |
58c7ccbf | 511 | } |
c8ebae37 | 512 | |
58c7ccbf PF |
513 | static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) |
514 | { | |
515 | struct mmci_host_next *next = &host->next_data; | |
516 | ||
517 | if (data->host_cookie && data->host_cookie != next->cookie) { | |
a3c76eb9 | 518 | pr_warning("[%s] invalid cookie: data->host_cookie %d" |
58c7ccbf PF |
519 | " host->next_data.cookie %d\n", |
520 | __func__, data->host_cookie, host->next_data.cookie); | |
521 | data->host_cookie = 0; | |
522 | } | |
523 | ||
524 | if (!data->host_cookie) | |
525 | return; | |
526 | ||
527 | host->dma_desc_current = next->dma_desc; | |
528 | host->dma_current = next->dma_chan; | |
529 | ||
530 | next->dma_desc = NULL; | |
531 | next->dma_chan = NULL; | |
c8ebae37 | 532 | } |
58c7ccbf PF |
533 | |
534 | static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, | |
535 | bool is_first_req) | |
536 | { | |
537 | struct mmci_host *host = mmc_priv(mmc); | |
538 | struct mmc_data *data = mrq->data; | |
539 | struct mmci_host_next *nd = &host->next_data; | |
540 | ||
541 | if (!data) | |
542 | return; | |
543 | ||
544 | if (data->host_cookie) { | |
545 | data->host_cookie = 0; | |
546 | return; | |
547 | } | |
548 | ||
549 | /* if config for dma */ | |
550 | if (((data->flags & MMC_DATA_WRITE) && host->dma_tx_channel) || | |
551 | ((data->flags & MMC_DATA_READ) && host->dma_rx_channel)) { | |
552 | if (mmci_dma_prep_data(host, data, nd)) | |
553 | data->host_cookie = 0; | |
554 | else | |
555 | data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; | |
556 | } | |
557 | } | |
558 | ||
559 | static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, | |
560 | int err) | |
561 | { | |
562 | struct mmci_host *host = mmc_priv(mmc); | |
563 | struct mmc_data *data = mrq->data; | |
564 | struct dma_chan *chan; | |
565 | enum dma_data_direction dir; | |
566 | ||
567 | if (!data) | |
568 | return; | |
569 | ||
570 | if (data->flags & MMC_DATA_READ) { | |
571 | dir = DMA_FROM_DEVICE; | |
572 | chan = host->dma_rx_channel; | |
573 | } else { | |
574 | dir = DMA_TO_DEVICE; | |
575 | chan = host->dma_tx_channel; | |
576 | } | |
577 | ||
578 | ||
579 | /* if config for dma */ | |
580 | if (chan) { | |
581 | if (err) | |
582 | dmaengine_terminate_all(chan); | |
8e3336b1 | 583 | if (data->host_cookie) |
58c7ccbf PF |
584 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, |
585 | data->sg_len, dir); | |
586 | mrq->data->host_cookie = 0; | |
587 | } | |
588 | } | |
589 | ||
c8ebae37 RK |
590 | #else |
591 | /* Blank functions if the DMA engine is not available */ | |
58c7ccbf PF |
592 | static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) |
593 | { | |
594 | } | |
c8ebae37 RK |
595 | static inline void mmci_dma_setup(struct mmci_host *host) |
596 | { | |
597 | } | |
598 | ||
599 | static inline void mmci_dma_release(struct mmci_host *host) | |
600 | { | |
601 | } | |
602 | ||
603 | static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) | |
604 | { | |
605 | } | |
606 | ||
607 | static inline void mmci_dma_data_error(struct mmci_host *host) | |
608 | { | |
609 | } | |
610 | ||
611 | static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) | |
612 | { | |
613 | return -ENOSYS; | |
614 | } | |
58c7ccbf PF |
615 | |
616 | #define mmci_pre_request NULL | |
617 | #define mmci_post_request NULL | |
618 | ||
c8ebae37 RK |
619 | #endif |
620 | ||
1da177e4 LT |
621 | static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) |
622 | { | |
8301bb68 | 623 | struct variant_data *variant = host->variant; |
1da177e4 | 624 | unsigned int datactrl, timeout, irqmask; |
7b09cdac | 625 | unsigned long long clks; |
1da177e4 | 626 | void __iomem *base; |
3bc87f24 | 627 | int blksz_bits; |
1da177e4 | 628 | |
64de0289 LW |
629 | dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", |
630 | data->blksz, data->blocks, data->flags); | |
1da177e4 LT |
631 | |
632 | host->data = data; | |
528320db | 633 | host->size = data->blksz * data->blocks; |
51d4375d | 634 | data->bytes_xfered = 0; |
1da177e4 | 635 | |
7b09cdac RK |
636 | clks = (unsigned long long)data->timeout_ns * host->cclk; |
637 | do_div(clks, 1000000000UL); | |
638 | ||
639 | timeout = data->timeout_clks + (unsigned int)clks; | |
1da177e4 LT |
640 | |
641 | base = host->base; | |
642 | writel(timeout, base + MMCIDATATIMER); | |
643 | writel(host->size, base + MMCIDATALENGTH); | |
644 | ||
3bc87f24 RK |
645 | blksz_bits = ffs(data->blksz) - 1; |
646 | BUG_ON(1 << blksz_bits != data->blksz); | |
647 | ||
1784b157 PL |
648 | if (variant->blksz_datactrl16) |
649 | datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); | |
650 | else | |
651 | datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; | |
c8ebae37 RK |
652 | |
653 | if (data->flags & MMC_DATA_READ) | |
1da177e4 | 654 | datactrl |= MCI_DPSM_DIRECTION; |
c8ebae37 | 655 | |
7258db7e UH |
656 | /* The ST Micro variants has a special bit to enable SDIO */ |
657 | if (variant->sdio && host->mmc->card) | |
06c1a121 UH |
658 | if (mmc_card_sdio(host->mmc->card)) { |
659 | /* | |
660 | * The ST Micro variants has a special bit | |
661 | * to enable SDIO. | |
662 | */ | |
663 | u32 clk; | |
664 | ||
7258db7e UH |
665 | datactrl |= MCI_ST_DPSM_SDIOEN; |
666 | ||
06c1a121 | 667 | /* |
70ac0935 UH |
668 | * The ST Micro variant for SDIO small write transfers |
669 | * needs to have clock H/W flow control disabled, | |
670 | * otherwise the transfer will not start. The threshold | |
671 | * depends on the rate of MCLK. | |
06c1a121 | 672 | */ |
70ac0935 UH |
673 | if (data->flags & MMC_DATA_WRITE && |
674 | (host->size < 8 || | |
675 | (host->size <= 8 && host->mclk > 50000000))) | |
06c1a121 UH |
676 | clk = host->clk_reg & ~variant->clkreg_enable; |
677 | else | |
678 | clk = host->clk_reg | variant->clkreg_enable; | |
679 | ||
680 | mmci_write_clkreg(host, clk); | |
681 | } | |
682 | ||
c8ebae37 RK |
683 | /* |
684 | * Attempt to use DMA operation mode, if this | |
685 | * should fail, fall back to PIO mode | |
686 | */ | |
687 | if (!mmci_dma_start_data(host, datactrl)) | |
688 | return; | |
689 | ||
690 | /* IRQ mode, map the SG list for CPU reading/writing */ | |
691 | mmci_init_sg(host, data); | |
692 | ||
693 | if (data->flags & MMC_DATA_READ) { | |
1da177e4 | 694 | irqmask = MCI_RXFIFOHALFFULLMASK; |
0425a142 RK |
695 | |
696 | /* | |
c4d877c1 RK |
697 | * If we have less than the fifo 'half-full' threshold to |
698 | * transfer, trigger a PIO interrupt as soon as any data | |
699 | * is available. | |
0425a142 | 700 | */ |
c4d877c1 | 701 | if (host->size < variant->fifohalfsize) |
0425a142 | 702 | irqmask |= MCI_RXDATAAVLBLMASK; |
1da177e4 LT |
703 | } else { |
704 | /* | |
705 | * We don't actually need to include "FIFO empty" here | |
706 | * since its implicit in "FIFO half empty". | |
707 | */ | |
708 | irqmask = MCI_TXFIFOHALFEMPTYMASK; | |
709 | } | |
710 | ||
711 | writel(datactrl, base + MMCIDATACTRL); | |
712 | writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); | |
2686b4b4 | 713 | mmci_set_mask1(host, irqmask); |
1da177e4 LT |
714 | } |
715 | ||
716 | static void | |
717 | mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) | |
718 | { | |
719 | void __iomem *base = host->base; | |
720 | ||
64de0289 | 721 | dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", |
1da177e4 LT |
722 | cmd->opcode, cmd->arg, cmd->flags); |
723 | ||
724 | if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { | |
725 | writel(0, base + MMCICOMMAND); | |
726 | udelay(1); | |
727 | } | |
728 | ||
729 | c |= cmd->opcode | MCI_CPSM_ENABLE; | |
e9225176 RK |
730 | if (cmd->flags & MMC_RSP_PRESENT) { |
731 | if (cmd->flags & MMC_RSP_136) | |
732 | c |= MCI_CPSM_LONGRSP; | |
1da177e4 | 733 | c |= MCI_CPSM_RESPONSE; |
1da177e4 LT |
734 | } |
735 | if (/*interrupt*/0) | |
736 | c |= MCI_CPSM_INTERRUPT; | |
737 | ||
738 | host->cmd = cmd; | |
739 | ||
740 | writel(cmd->arg, base + MMCIARGUMENT); | |
741 | writel(c, base + MMCICOMMAND); | |
742 | } | |
743 | ||
744 | static void | |
745 | mmci_data_irq(struct mmci_host *host, struct mmc_data *data, | |
746 | unsigned int status) | |
747 | { | |
f20f8f21 | 748 | /* First check for errors */ |
b63038d6 UH |
749 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| |
750 | MCI_TXUNDERRUN|MCI_RXOVERRUN)) { | |
8cb28155 | 751 | u32 remain, success; |
f20f8f21 | 752 | |
c8ebae37 RK |
753 | /* Terminate the DMA transfer */ |
754 | if (dma_inprogress(host)) | |
755 | mmci_dma_data_error(host); | |
e9c091b4 RK |
756 | |
757 | /* | |
c8afc9d5 RK |
758 | * Calculate how far we are into the transfer. Note that |
759 | * the data counter gives the number of bytes transferred | |
760 | * on the MMC bus, not on the host side. On reads, this | |
761 | * can be as much as a FIFO-worth of data ahead. This | |
762 | * matters for FIFO overruns only. | |
e9c091b4 | 763 | */ |
f5a106d9 | 764 | remain = readl(host->base + MMCIDATACNT); |
8cb28155 LW |
765 | success = data->blksz * data->blocks - remain; |
766 | ||
c8afc9d5 RK |
767 | dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", |
768 | status, success); | |
8cb28155 LW |
769 | if (status & MCI_DATACRCFAIL) { |
770 | /* Last block was not successful */ | |
c8afc9d5 | 771 | success -= 1; |
17b0429d | 772 | data->error = -EILSEQ; |
8cb28155 | 773 | } else if (status & MCI_DATATIMEOUT) { |
17b0429d | 774 | data->error = -ETIMEDOUT; |
757df746 LW |
775 | } else if (status & MCI_STARTBITERR) { |
776 | data->error = -ECOMM; | |
c8afc9d5 RK |
777 | } else if (status & MCI_TXUNDERRUN) { |
778 | data->error = -EIO; | |
779 | } else if (status & MCI_RXOVERRUN) { | |
780 | if (success > host->variant->fifosize) | |
781 | success -= host->variant->fifosize; | |
782 | else | |
783 | success = 0; | |
17b0429d | 784 | data->error = -EIO; |
4ce1d6cb | 785 | } |
51d4375d | 786 | data->bytes_xfered = round_down(success, data->blksz); |
1da177e4 | 787 | } |
f20f8f21 | 788 | |
8cb28155 LW |
789 | if (status & MCI_DATABLOCKEND) |
790 | dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); | |
f20f8f21 | 791 | |
ccff9b51 | 792 | if (status & MCI_DATAEND || data->error) { |
c8ebae37 RK |
793 | if (dma_inprogress(host)) |
794 | mmci_dma_unmap(host, data); | |
1da177e4 LT |
795 | mmci_stop_data(host); |
796 | ||
8cb28155 LW |
797 | if (!data->error) |
798 | /* The error clause is handled above, success! */ | |
51d4375d | 799 | data->bytes_xfered = data->blksz * data->blocks; |
f20f8f21 | 800 | |
1da177e4 LT |
801 | if (!data->stop) { |
802 | mmci_request_end(host, data->mrq); | |
803 | } else { | |
804 | mmci_start_command(host, data->stop, 0); | |
805 | } | |
806 | } | |
807 | } | |
808 | ||
809 | static void | |
810 | mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, | |
811 | unsigned int status) | |
812 | { | |
813 | void __iomem *base = host->base; | |
814 | ||
815 | host->cmd = NULL; | |
816 | ||
1da177e4 | 817 | if (status & MCI_CMDTIMEOUT) { |
17b0429d | 818 | cmd->error = -ETIMEDOUT; |
1da177e4 | 819 | } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { |
17b0429d | 820 | cmd->error = -EILSEQ; |
9047b435 RKAL |
821 | } else { |
822 | cmd->resp[0] = readl(base + MMCIRESPONSE0); | |
823 | cmd->resp[1] = readl(base + MMCIRESPONSE1); | |
824 | cmd->resp[2] = readl(base + MMCIRESPONSE2); | |
825 | cmd->resp[3] = readl(base + MMCIRESPONSE3); | |
1da177e4 LT |
826 | } |
827 | ||
17b0429d | 828 | if (!cmd->data || cmd->error) { |
3b6e3c73 UH |
829 | if (host->data) { |
830 | /* Terminate the DMA transfer */ | |
831 | if (dma_inprogress(host)) | |
832 | mmci_dma_data_error(host); | |
e47c222b | 833 | mmci_stop_data(host); |
3b6e3c73 | 834 | } |
1da177e4 LT |
835 | mmci_request_end(host, cmd->mrq); |
836 | } else if (!(cmd->data->flags & MMC_DATA_READ)) { | |
837 | mmci_start_data(host, cmd->data); | |
838 | } | |
839 | } | |
840 | ||
841 | static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) | |
842 | { | |
843 | void __iomem *base = host->base; | |
844 | char *ptr = buffer; | |
845 | u32 status; | |
26eed9a5 | 846 | int host_remain = host->size; |
1da177e4 LT |
847 | |
848 | do { | |
26eed9a5 | 849 | int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); |
1da177e4 LT |
850 | |
851 | if (count > remain) | |
852 | count = remain; | |
853 | ||
854 | if (count <= 0) | |
855 | break; | |
856 | ||
393e5e24 UH |
857 | /* |
858 | * SDIO especially may want to send something that is | |
859 | * not divisible by 4 (as opposed to card sectors | |
860 | * etc). Therefore make sure to always read the last bytes | |
861 | * while only doing full 32-bit reads towards the FIFO. | |
862 | */ | |
863 | if (unlikely(count & 0x3)) { | |
864 | if (count < 4) { | |
865 | unsigned char buf[4]; | |
866 | readsl(base + MMCIFIFO, buf, 1); | |
867 | memcpy(ptr, buf, count); | |
868 | } else { | |
869 | readsl(base + MMCIFIFO, ptr, count >> 2); | |
870 | count &= ~0x3; | |
871 | } | |
872 | } else { | |
873 | readsl(base + MMCIFIFO, ptr, count >> 2); | |
874 | } | |
1da177e4 LT |
875 | |
876 | ptr += count; | |
877 | remain -= count; | |
26eed9a5 | 878 | host_remain -= count; |
1da177e4 LT |
879 | |
880 | if (remain == 0) | |
881 | break; | |
882 | ||
883 | status = readl(base + MMCISTATUS); | |
884 | } while (status & MCI_RXDATAAVLBL); | |
885 | ||
886 | return ptr - buffer; | |
887 | } | |
888 | ||
889 | static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) | |
890 | { | |
8301bb68 | 891 | struct variant_data *variant = host->variant; |
1da177e4 LT |
892 | void __iomem *base = host->base; |
893 | char *ptr = buffer; | |
894 | ||
895 | do { | |
896 | unsigned int count, maxcnt; | |
897 | ||
8301bb68 RV |
898 | maxcnt = status & MCI_TXFIFOEMPTY ? |
899 | variant->fifosize : variant->fifohalfsize; | |
1da177e4 LT |
900 | count = min(remain, maxcnt); |
901 | ||
34177802 LW |
902 | /* |
903 | * SDIO especially may want to send something that is | |
904 | * not divisible by 4 (as opposed to card sectors | |
905 | * etc), and the FIFO only accept full 32-bit writes. | |
906 | * So compensate by adding +3 on the count, a single | |
907 | * byte become a 32bit write, 7 bytes will be two | |
908 | * 32bit writes etc. | |
909 | */ | |
910 | writesl(base + MMCIFIFO, ptr, (count + 3) >> 2); | |
1da177e4 LT |
911 | |
912 | ptr += count; | |
913 | remain -= count; | |
914 | ||
915 | if (remain == 0) | |
916 | break; | |
917 | ||
918 | status = readl(base + MMCISTATUS); | |
919 | } while (status & MCI_TXFIFOHALFEMPTY); | |
920 | ||
921 | return ptr - buffer; | |
922 | } | |
923 | ||
924 | /* | |
925 | * PIO data transfer IRQ handler. | |
926 | */ | |
7d12e780 | 927 | static irqreturn_t mmci_pio_irq(int irq, void *dev_id) |
1da177e4 LT |
928 | { |
929 | struct mmci_host *host = dev_id; | |
4ce1d6cb | 930 | struct sg_mapping_iter *sg_miter = &host->sg_miter; |
8301bb68 | 931 | struct variant_data *variant = host->variant; |
1da177e4 | 932 | void __iomem *base = host->base; |
4ce1d6cb | 933 | unsigned long flags; |
1da177e4 LT |
934 | u32 status; |
935 | ||
936 | status = readl(base + MMCISTATUS); | |
937 | ||
64de0289 | 938 | dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); |
1da177e4 | 939 | |
4ce1d6cb RV |
940 | local_irq_save(flags); |
941 | ||
1da177e4 | 942 | do { |
1da177e4 LT |
943 | unsigned int remain, len; |
944 | char *buffer; | |
945 | ||
946 | /* | |
947 | * For write, we only need to test the half-empty flag | |
948 | * here - if the FIFO is completely empty, then by | |
949 | * definition it is more than half empty. | |
950 | * | |
951 | * For read, check for data available. | |
952 | */ | |
953 | if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) | |
954 | break; | |
955 | ||
4ce1d6cb RV |
956 | if (!sg_miter_next(sg_miter)) |
957 | break; | |
958 | ||
959 | buffer = sg_miter->addr; | |
960 | remain = sg_miter->length; | |
1da177e4 LT |
961 | |
962 | len = 0; | |
963 | if (status & MCI_RXACTIVE) | |
964 | len = mmci_pio_read(host, buffer, remain); | |
965 | if (status & MCI_TXACTIVE) | |
966 | len = mmci_pio_write(host, buffer, remain, status); | |
967 | ||
4ce1d6cb | 968 | sg_miter->consumed = len; |
1da177e4 | 969 | |
1da177e4 LT |
970 | host->size -= len; |
971 | remain -= len; | |
972 | ||
973 | if (remain) | |
974 | break; | |
975 | ||
1da177e4 LT |
976 | status = readl(base + MMCISTATUS); |
977 | } while (1); | |
978 | ||
4ce1d6cb RV |
979 | sg_miter_stop(sg_miter); |
980 | ||
981 | local_irq_restore(flags); | |
982 | ||
1da177e4 | 983 | /* |
c4d877c1 RK |
984 | * If we have less than the fifo 'half-full' threshold to transfer, |
985 | * trigger a PIO interrupt as soon as any data is available. | |
1da177e4 | 986 | */ |
c4d877c1 | 987 | if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) |
2686b4b4 | 988 | mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); |
1da177e4 LT |
989 | |
990 | /* | |
991 | * If we run out of data, disable the data IRQs; this | |
992 | * prevents a race where the FIFO becomes empty before | |
993 | * the chip itself has disabled the data path, and | |
994 | * stops us racing with our data end IRQ. | |
995 | */ | |
996 | if (host->size == 0) { | |
2686b4b4 | 997 | mmci_set_mask1(host, 0); |
1da177e4 LT |
998 | writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); |
999 | } | |
1000 | ||
1001 | return IRQ_HANDLED; | |
1002 | } | |
1003 | ||
1004 | /* | |
1005 | * Handle completion of command and data transfers. | |
1006 | */ | |
7d12e780 | 1007 | static irqreturn_t mmci_irq(int irq, void *dev_id) |
1da177e4 LT |
1008 | { |
1009 | struct mmci_host *host = dev_id; | |
1010 | u32 status; | |
1011 | int ret = 0; | |
1012 | ||
1013 | spin_lock(&host->lock); | |
1014 | ||
1015 | do { | |
1016 | struct mmc_command *cmd; | |
1017 | struct mmc_data *data; | |
1018 | ||
1019 | status = readl(host->base + MMCISTATUS); | |
2686b4b4 LW |
1020 | |
1021 | if (host->singleirq) { | |
1022 | if (status & readl(host->base + MMCIMASK1)) | |
1023 | mmci_pio_irq(irq, dev_id); | |
1024 | ||
1025 | status &= ~MCI_IRQ1MASK; | |
1026 | } | |
1027 | ||
1da177e4 LT |
1028 | status &= readl(host->base + MMCIMASK0); |
1029 | writel(status, host->base + MMCICLEAR); | |
1030 | ||
64de0289 | 1031 | dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); |
1da177e4 LT |
1032 | |
1033 | data = host->data; | |
b63038d6 UH |
1034 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| |
1035 | MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND| | |
1036 | MCI_DATABLOCKEND) && data) | |
1da177e4 LT |
1037 | mmci_data_irq(host, data, status); |
1038 | ||
1039 | cmd = host->cmd; | |
1040 | if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) | |
1041 | mmci_cmd_irq(host, cmd, status); | |
1042 | ||
1043 | ret = 1; | |
1044 | } while (status); | |
1045 | ||
1046 | spin_unlock(&host->lock); | |
1047 | ||
1048 | return IRQ_RETVAL(ret); | |
1049 | } | |
1050 | ||
1051 | static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
1052 | { | |
1053 | struct mmci_host *host = mmc_priv(mmc); | |
9e943021 | 1054 | unsigned long flags; |
1da177e4 LT |
1055 | |
1056 | WARN_ON(host->mrq != NULL); | |
1057 | ||
019a5f56 | 1058 | if (mrq->data && !is_power_of_2(mrq->data->blksz)) { |
64de0289 LW |
1059 | dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", |
1060 | mrq->data->blksz); | |
255d01af PO |
1061 | mrq->cmd->error = -EINVAL; |
1062 | mmc_request_done(mmc, mrq); | |
1063 | return; | |
1064 | } | |
1065 | ||
1c3be369 RK |
1066 | pm_runtime_get_sync(mmc_dev(mmc)); |
1067 | ||
9e943021 | 1068 | spin_lock_irqsave(&host->lock, flags); |
1da177e4 LT |
1069 | |
1070 | host->mrq = mrq; | |
1071 | ||
58c7ccbf PF |
1072 | if (mrq->data) |
1073 | mmci_get_next_data(host, mrq->data); | |
1074 | ||
1da177e4 LT |
1075 | if (mrq->data && mrq->data->flags & MMC_DATA_READ) |
1076 | mmci_start_data(host, mrq->data); | |
1077 | ||
1078 | mmci_start_command(host, mrq->cmd, 0); | |
1079 | ||
9e943021 | 1080 | spin_unlock_irqrestore(&host->lock, flags); |
1da177e4 LT |
1081 | } |
1082 | ||
1083 | static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
1084 | { | |
1085 | struct mmci_host *host = mmc_priv(mmc); | |
7d72a1d4 | 1086 | struct variant_data *variant = host->variant; |
a6a6464a LW |
1087 | u32 pwr = 0; |
1088 | unsigned long flags; | |
99fc5131 | 1089 | int ret; |
1da177e4 | 1090 | |
2cd976c4 UH |
1091 | pm_runtime_get_sync(mmc_dev(mmc)); |
1092 | ||
bc521818 UH |
1093 | if (host->plat->ios_handler && |
1094 | host->plat->ios_handler(mmc_dev(mmc), ios)) | |
1095 | dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); | |
1096 | ||
1da177e4 LT |
1097 | switch (ios->power_mode) { |
1098 | case MMC_POWER_OFF: | |
99fc5131 LW |
1099 | if (host->vcc) |
1100 | ret = mmc_regulator_set_ocr(mmc, host->vcc, 0); | |
1da177e4 LT |
1101 | break; |
1102 | case MMC_POWER_UP: | |
99fc5131 LW |
1103 | if (host->vcc) { |
1104 | ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd); | |
1105 | if (ret) { | |
1106 | dev_err(mmc_dev(mmc), "unable to set OCR\n"); | |
1107 | /* | |
1108 | * The .set_ios() function in the mmc_host_ops | |
1109 | * struct return void, and failing to set the | |
1110 | * power should be rare so we print an error | |
1111 | * and return here. | |
1112 | */ | |
2cd976c4 | 1113 | goto out; |
99fc5131 LW |
1114 | } |
1115 | } | |
7d72a1d4 UH |
1116 | /* |
1117 | * The ST Micro variant doesn't have the PL180s MCI_PWR_UP | |
1118 | * and instead uses MCI_PWR_ON so apply whatever value is | |
1119 | * configured in the variant data. | |
1120 | */ | |
1121 | pwr |= variant->pwrreg_powerup; | |
1122 | ||
1123 | break; | |
1da177e4 LT |
1124 | case MMC_POWER_ON: |
1125 | pwr |= MCI_PWR_ON; | |
1126 | break; | |
1127 | } | |
1128 | ||
4d1a3a0d UH |
1129 | if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { |
1130 | /* | |
1131 | * The ST Micro variant has some additional bits | |
1132 | * indicating signal direction for the signals in | |
1133 | * the SD/MMC bus and feedback-clock usage. | |
1134 | */ | |
1135 | pwr |= host->plat->sigdir; | |
1136 | ||
1137 | if (ios->bus_width == MMC_BUS_WIDTH_4) | |
1138 | pwr &= ~MCI_ST_DATA74DIREN; | |
1139 | else if (ios->bus_width == MMC_BUS_WIDTH_1) | |
1140 | pwr &= (~MCI_ST_DATA74DIREN & | |
1141 | ~MCI_ST_DATA31DIREN & | |
1142 | ~MCI_ST_DATA2DIREN); | |
1143 | } | |
1144 | ||
cc30d60e | 1145 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { |
f17a1f06 | 1146 | if (host->hw_designer != AMBA_VENDOR_ST) |
cc30d60e LW |
1147 | pwr |= MCI_ROD; |
1148 | else { | |
1149 | /* | |
1150 | * The ST Micro variant use the ROD bit for something | |
1151 | * else and only has OD (Open Drain). | |
1152 | */ | |
1153 | pwr |= MCI_OD; | |
1154 | } | |
1155 | } | |
1da177e4 | 1156 | |
a6a6464a LW |
1157 | spin_lock_irqsave(&host->lock, flags); |
1158 | ||
1159 | mmci_set_clkreg(host, ios->clock); | |
7437cfa5 | 1160 | mmci_write_pwrreg(host, pwr); |
a6a6464a LW |
1161 | |
1162 | spin_unlock_irqrestore(&host->lock, flags); | |
2cd976c4 UH |
1163 | |
1164 | out: | |
1165 | pm_runtime_mark_last_busy(mmc_dev(mmc)); | |
1166 | pm_runtime_put_autosuspend(mmc_dev(mmc)); | |
1da177e4 LT |
1167 | } |
1168 | ||
89001446 RK |
1169 | static int mmci_get_ro(struct mmc_host *mmc) |
1170 | { | |
1171 | struct mmci_host *host = mmc_priv(mmc); | |
1172 | ||
1173 | if (host->gpio_wp == -ENOSYS) | |
1174 | return -ENOSYS; | |
1175 | ||
18a06301 | 1176 | return gpio_get_value_cansleep(host->gpio_wp); |
89001446 RK |
1177 | } |
1178 | ||
1179 | static int mmci_get_cd(struct mmc_host *mmc) | |
1180 | { | |
1181 | struct mmci_host *host = mmc_priv(mmc); | |
29719445 | 1182 | struct mmci_platform_data *plat = host->plat; |
89001446 RK |
1183 | unsigned int status; |
1184 | ||
4b8caec0 RV |
1185 | if (host->gpio_cd == -ENOSYS) { |
1186 | if (!plat->status) | |
1187 | return 1; /* Assume always present */ | |
1188 | ||
29719445 | 1189 | status = plat->status(mmc_dev(host->mmc)); |
4b8caec0 | 1190 | } else |
18a06301 LW |
1191 | status = !!gpio_get_value_cansleep(host->gpio_cd) |
1192 | ^ plat->cd_invert; | |
89001446 | 1193 | |
74bc8093 RK |
1194 | /* |
1195 | * Use positive logic throughout - status is zero for no card, | |
1196 | * non-zero for card inserted. | |
1197 | */ | |
1198 | return status; | |
89001446 RK |
1199 | } |
1200 | ||
148b8b39 RV |
1201 | static irqreturn_t mmci_cd_irq(int irq, void *dev_id) |
1202 | { | |
1203 | struct mmci_host *host = dev_id; | |
1204 | ||
1205 | mmc_detect_change(host->mmc, msecs_to_jiffies(500)); | |
1206 | ||
1207 | return IRQ_HANDLED; | |
1208 | } | |
1209 | ||
ab7aefd0 | 1210 | static const struct mmc_host_ops mmci_ops = { |
1da177e4 | 1211 | .request = mmci_request, |
58c7ccbf PF |
1212 | .pre_req = mmci_pre_request, |
1213 | .post_req = mmci_post_request, | |
1da177e4 | 1214 | .set_ios = mmci_set_ios, |
89001446 RK |
1215 | .get_ro = mmci_get_ro, |
1216 | .get_cd = mmci_get_cd, | |
1da177e4 LT |
1217 | }; |
1218 | ||
000bc9d5 LJ |
1219 | #ifdef CONFIG_OF |
1220 | static void mmci_dt_populate_generic_pdata(struct device_node *np, | |
1221 | struct mmci_platform_data *pdata) | |
1222 | { | |
1223 | int bus_width = 0; | |
1224 | ||
9a597016 | 1225 | pdata->gpio_wp = of_get_named_gpio(np, "wp-gpios", 0); |
9a597016 | 1226 | pdata->gpio_cd = of_get_named_gpio(np, "cd-gpios", 0); |
000bc9d5 LJ |
1227 | |
1228 | if (of_get_property(np, "cd-inverted", NULL)) | |
1229 | pdata->cd_invert = true; | |
1230 | else | |
1231 | pdata->cd_invert = false; | |
1232 | ||
1233 | of_property_read_u32(np, "max-frequency", &pdata->f_max); | |
1234 | if (!pdata->f_max) | |
1235 | pr_warn("%s has no 'max-frequency' property\n", np->full_name); | |
1236 | ||
1237 | if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) | |
1238 | pdata->capabilities |= MMC_CAP_MMC_HIGHSPEED; | |
1239 | if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) | |
1240 | pdata->capabilities |= MMC_CAP_SD_HIGHSPEED; | |
1241 | ||
1242 | of_property_read_u32(np, "bus-width", &bus_width); | |
1243 | switch (bus_width) { | |
1244 | case 0 : | |
1245 | /* No bus-width supplied. */ | |
1246 | break; | |
1247 | case 4 : | |
1248 | pdata->capabilities |= MMC_CAP_4_BIT_DATA; | |
1249 | break; | |
1250 | case 8 : | |
1251 | pdata->capabilities |= MMC_CAP_8_BIT_DATA; | |
1252 | break; | |
1253 | default : | |
1254 | pr_warn("%s: Unsupported bus width\n", np->full_name); | |
1255 | } | |
1256 | } | |
c0a120a4 LJ |
1257 | #else |
1258 | static void mmci_dt_populate_generic_pdata(struct device_node *np, | |
1259 | struct mmci_platform_data *pdata) | |
1260 | { | |
1261 | return; | |
1262 | } | |
000bc9d5 LJ |
1263 | #endif |
1264 | ||
aa25afad RK |
1265 | static int __devinit mmci_probe(struct amba_device *dev, |
1266 | const struct amba_id *id) | |
1da177e4 | 1267 | { |
6ef297f8 | 1268 | struct mmci_platform_data *plat = dev->dev.platform_data; |
000bc9d5 | 1269 | struct device_node *np = dev->dev.of_node; |
4956e109 | 1270 | struct variant_data *variant = id->data; |
1da177e4 LT |
1271 | struct mmci_host *host; |
1272 | struct mmc_host *mmc; | |
1273 | int ret; | |
1274 | ||
000bc9d5 LJ |
1275 | /* Must have platform data or Device Tree. */ |
1276 | if (!plat && !np) { | |
1277 | dev_err(&dev->dev, "No plat data or DT found\n"); | |
1278 | return -EINVAL; | |
1da177e4 LT |
1279 | } |
1280 | ||
b9b52918 LJ |
1281 | if (!plat) { |
1282 | plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); | |
1283 | if (!plat) | |
1284 | return -ENOMEM; | |
1285 | } | |
1286 | ||
000bc9d5 LJ |
1287 | if (np) |
1288 | mmci_dt_populate_generic_pdata(np, plat); | |
1289 | ||
1da177e4 LT |
1290 | ret = amba_request_regions(dev, DRIVER_NAME); |
1291 | if (ret) | |
1292 | goto out; | |
1293 | ||
1294 | mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); | |
1295 | if (!mmc) { | |
1296 | ret = -ENOMEM; | |
1297 | goto rel_regions; | |
1298 | } | |
1299 | ||
1300 | host = mmc_priv(mmc); | |
4ea580f1 | 1301 | host->mmc = mmc; |
012b7d33 | 1302 | |
89001446 RK |
1303 | host->gpio_wp = -ENOSYS; |
1304 | host->gpio_cd = -ENOSYS; | |
148b8b39 | 1305 | host->gpio_cd_irq = -1; |
89001446 | 1306 | |
012b7d33 RK |
1307 | host->hw_designer = amba_manf(dev); |
1308 | host->hw_revision = amba_rev(dev); | |
64de0289 LW |
1309 | dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); |
1310 | dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); | |
012b7d33 | 1311 | |
ee569c43 | 1312 | host->clk = clk_get(&dev->dev, NULL); |
1da177e4 LT |
1313 | if (IS_ERR(host->clk)) { |
1314 | ret = PTR_ERR(host->clk); | |
1315 | host->clk = NULL; | |
1316 | goto host_free; | |
1317 | } | |
1318 | ||
ac940938 | 1319 | ret = clk_prepare_enable(host->clk); |
1da177e4 | 1320 | if (ret) |
a8d3584a | 1321 | goto clk_free; |
1da177e4 LT |
1322 | |
1323 | host->plat = plat; | |
4956e109 | 1324 | host->variant = variant; |
1da177e4 | 1325 | host->mclk = clk_get_rate(host->clk); |
c8df9a53 LW |
1326 | /* |
1327 | * According to the spec, mclk is max 100 MHz, | |
1328 | * so we try to adjust the clock down to this, | |
1329 | * (if possible). | |
1330 | */ | |
1331 | if (host->mclk > 100000000) { | |
1332 | ret = clk_set_rate(host->clk, 100000000); | |
1333 | if (ret < 0) | |
1334 | goto clk_disable; | |
1335 | host->mclk = clk_get_rate(host->clk); | |
64de0289 LW |
1336 | dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", |
1337 | host->mclk); | |
c8df9a53 | 1338 | } |
c8ebae37 | 1339 | host->phybase = dev->res.start; |
dc890c2d | 1340 | host->base = ioremap(dev->res.start, resource_size(&dev->res)); |
1da177e4 LT |
1341 | if (!host->base) { |
1342 | ret = -ENOMEM; | |
1343 | goto clk_disable; | |
1344 | } | |
1345 | ||
1346 | mmc->ops = &mmci_ops; | |
7f294e49 LW |
1347 | /* |
1348 | * The ARM and ST versions of the block have slightly different | |
1349 | * clock divider equations which means that the minimum divider | |
1350 | * differs too. | |
1351 | */ | |
1352 | if (variant->st_clkdiv) | |
1353 | mmc->f_min = DIV_ROUND_UP(host->mclk, 257); | |
1354 | else | |
1355 | mmc->f_min = DIV_ROUND_UP(host->mclk, 512); | |
808d97cc LW |
1356 | /* |
1357 | * If the platform data supplies a maximum operating | |
1358 | * frequency, this takes precedence. Else, we fall back | |
1359 | * to using the module parameter, which has a (low) | |
1360 | * default value in case it is not specified. Either | |
1361 | * value must not exceed the clock rate into the block, | |
1362 | * of course. | |
1363 | */ | |
1364 | if (plat->f_max) | |
1365 | mmc->f_max = min(host->mclk, plat->f_max); | |
1366 | else | |
1367 | mmc->f_max = min(host->mclk, fmax); | |
64de0289 LW |
1368 | dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); |
1369 | ||
a9a83785 LW |
1370 | host->pinctrl = devm_pinctrl_get(&dev->dev); |
1371 | if (IS_ERR(host->pinctrl)) { | |
1372 | ret = PTR_ERR(host->pinctrl); | |
1373 | goto clk_disable; | |
1374 | } | |
1375 | ||
1376 | host->pins_default = pinctrl_lookup_state(host->pinctrl, | |
1377 | PINCTRL_STATE_DEFAULT); | |
1378 | ||
1379 | /* enable pins to be muxed in and configured */ | |
1380 | if (!IS_ERR(host->pins_default)) { | |
1381 | ret = pinctrl_select_state(host->pinctrl, host->pins_default); | |
1382 | if (ret) | |
1383 | dev_warn(&dev->dev, "could not set default pins\n"); | |
1384 | } else | |
1385 | dev_warn(&dev->dev, "could not get default pinstate\n"); | |
1386 | ||
34e84f39 LW |
1387 | #ifdef CONFIG_REGULATOR |
1388 | /* If we're using the regulator framework, try to fetch a regulator */ | |
1389 | host->vcc = regulator_get(&dev->dev, "vmmc"); | |
1390 | if (IS_ERR(host->vcc)) | |
1391 | host->vcc = NULL; | |
1392 | else { | |
1393 | int mask = mmc_regulator_get_ocrmask(host->vcc); | |
1394 | ||
1395 | if (mask < 0) | |
1396 | dev_err(&dev->dev, "error getting OCR mask (%d)\n", | |
1397 | mask); | |
1398 | else { | |
1399 | host->mmc->ocr_avail = (u32) mask; | |
1400 | if (plat->ocr_mask) | |
1401 | dev_warn(&dev->dev, | |
1402 | "Provided ocr_mask/setpower will not be used " | |
1403 | "(using regulator instead)\n"); | |
1404 | } | |
1405 | } | |
1406 | #endif | |
1407 | /* Fall back to platform data if no regulator is found */ | |
1408 | if (host->vcc == NULL) | |
1409 | mmc->ocr_avail = plat->ocr_mask; | |
9e6c82cd | 1410 | mmc->caps = plat->capabilities; |
5a092627 | 1411 | mmc->caps2 = plat->capabilities2; |
1da177e4 LT |
1412 | |
1413 | /* | |
1414 | * We can do SGIO | |
1415 | */ | |
a36274e0 | 1416 | mmc->max_segs = NR_SG; |
1da177e4 LT |
1417 | |
1418 | /* | |
08458ef6 RV |
1419 | * Since only a certain number of bits are valid in the data length |
1420 | * register, we must ensure that we don't exceed 2^num-1 bytes in a | |
1421 | * single request. | |
1da177e4 | 1422 | */ |
08458ef6 | 1423 | mmc->max_req_size = (1 << variant->datalength_bits) - 1; |
1da177e4 LT |
1424 | |
1425 | /* | |
1426 | * Set the maximum segment size. Since we aren't doing DMA | |
1427 | * (yet) we are only limited by the data length register. | |
1428 | */ | |
55db890a | 1429 | mmc->max_seg_size = mmc->max_req_size; |
1da177e4 | 1430 | |
fe4a3c7a PO |
1431 | /* |
1432 | * Block size can be up to 2048 bytes, but must be a power of two. | |
1433 | */ | |
8f7f6b7e | 1434 | mmc->max_blk_size = 1 << 11; |
fe4a3c7a | 1435 | |
55db890a | 1436 | /* |
8f7f6b7e WD |
1437 | * Limit the number of blocks transferred so that we don't overflow |
1438 | * the maximum request size. | |
55db890a | 1439 | */ |
8f7f6b7e | 1440 | mmc->max_blk_count = mmc->max_req_size >> 11; |
55db890a | 1441 | |
1da177e4 LT |
1442 | spin_lock_init(&host->lock); |
1443 | ||
1444 | writel(0, host->base + MMCIMASK0); | |
1445 | writel(0, host->base + MMCIMASK1); | |
1446 | writel(0xfff, host->base + MMCICLEAR); | |
1447 | ||
2805b9ab RS |
1448 | if (plat->gpio_cd == -EPROBE_DEFER) { |
1449 | ret = -EPROBE_DEFER; | |
1450 | goto err_gpio_cd; | |
1451 | } | |
89001446 RK |
1452 | if (gpio_is_valid(plat->gpio_cd)) { |
1453 | ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); | |
1454 | if (ret == 0) | |
1455 | ret = gpio_direction_input(plat->gpio_cd); | |
1456 | if (ret == 0) | |
1457 | host->gpio_cd = plat->gpio_cd; | |
1458 | else if (ret != -ENOSYS) | |
1459 | goto err_gpio_cd; | |
148b8b39 | 1460 | |
17ee083b LW |
1461 | /* |
1462 | * A gpio pin that will detect cards when inserted and removed | |
1463 | * will most likely want to trigger on the edges if it is | |
1464 | * 0 when ejected and 1 when inserted (or mutatis mutandis | |
1465 | * for the inverted case) so we request triggers on both | |
1466 | * edges. | |
1467 | */ | |
148b8b39 | 1468 | ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), |
17ee083b LW |
1469 | mmci_cd_irq, |
1470 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, | |
1471 | DRIVER_NAME " (cd)", host); | |
148b8b39 RV |
1472 | if (ret >= 0) |
1473 | host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); | |
89001446 | 1474 | } |
2805b9ab RS |
1475 | if (plat->gpio_wp == -EPROBE_DEFER) { |
1476 | ret = -EPROBE_DEFER; | |
1477 | goto err_gpio_wp; | |
1478 | } | |
89001446 RK |
1479 | if (gpio_is_valid(plat->gpio_wp)) { |
1480 | ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); | |
1481 | if (ret == 0) | |
1482 | ret = gpio_direction_input(plat->gpio_wp); | |
1483 | if (ret == 0) | |
1484 | host->gpio_wp = plat->gpio_wp; | |
1485 | else if (ret != -ENOSYS) | |
1486 | goto err_gpio_wp; | |
1487 | } | |
1488 | ||
4b8caec0 RV |
1489 | if ((host->plat->status || host->gpio_cd != -ENOSYS) |
1490 | && host->gpio_cd_irq < 0) | |
148b8b39 RV |
1491 | mmc->caps |= MMC_CAP_NEEDS_POLL; |
1492 | ||
dace1453 | 1493 | ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); |
1da177e4 LT |
1494 | if (ret) |
1495 | goto unmap; | |
1496 | ||
dfb85185 | 1497 | if (!dev->irq[1]) |
2686b4b4 LW |
1498 | host->singleirq = true; |
1499 | else { | |
1500 | ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, | |
1501 | DRIVER_NAME " (pio)", host); | |
1502 | if (ret) | |
1503 | goto irq0_free; | |
1504 | } | |
1da177e4 | 1505 | |
8cb28155 | 1506 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); |
1da177e4 LT |
1507 | |
1508 | amba_set_drvdata(dev, mmc); | |
1509 | ||
c8ebae37 RK |
1510 | dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", |
1511 | mmc_hostname(mmc), amba_part(dev), amba_manf(dev), | |
1512 | amba_rev(dev), (unsigned long long)dev->res.start, | |
1513 | dev->irq[0], dev->irq[1]); | |
1514 | ||
1515 | mmci_dma_setup(host); | |
1da177e4 | 1516 | |
2cd976c4 UH |
1517 | pm_runtime_set_autosuspend_delay(&dev->dev, 50); |
1518 | pm_runtime_use_autosuspend(&dev->dev); | |
1c3be369 RK |
1519 | pm_runtime_put(&dev->dev); |
1520 | ||
8c11a94d RK |
1521 | mmc_add_host(mmc); |
1522 | ||
1da177e4 LT |
1523 | return 0; |
1524 | ||
1525 | irq0_free: | |
1526 | free_irq(dev->irq[0], host); | |
1527 | unmap: | |
89001446 RK |
1528 | if (host->gpio_wp != -ENOSYS) |
1529 | gpio_free(host->gpio_wp); | |
1530 | err_gpio_wp: | |
148b8b39 RV |
1531 | if (host->gpio_cd_irq >= 0) |
1532 | free_irq(host->gpio_cd_irq, host); | |
89001446 RK |
1533 | if (host->gpio_cd != -ENOSYS) |
1534 | gpio_free(host->gpio_cd); | |
1535 | err_gpio_cd: | |
1da177e4 LT |
1536 | iounmap(host->base); |
1537 | clk_disable: | |
ac940938 | 1538 | clk_disable_unprepare(host->clk); |
1da177e4 LT |
1539 | clk_free: |
1540 | clk_put(host->clk); | |
1541 | host_free: | |
1542 | mmc_free_host(mmc); | |
1543 | rel_regions: | |
1544 | amba_release_regions(dev); | |
1545 | out: | |
1546 | return ret; | |
1547 | } | |
1548 | ||
6dc4a47a | 1549 | static int __devexit mmci_remove(struct amba_device *dev) |
1da177e4 LT |
1550 | { |
1551 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
1552 | ||
1553 | amba_set_drvdata(dev, NULL); | |
1554 | ||
1555 | if (mmc) { | |
1556 | struct mmci_host *host = mmc_priv(mmc); | |
1557 | ||
1c3be369 RK |
1558 | /* |
1559 | * Undo pm_runtime_put() in probe. We use the _sync | |
1560 | * version here so that we can access the primecell. | |
1561 | */ | |
1562 | pm_runtime_get_sync(&dev->dev); | |
1563 | ||
1da177e4 LT |
1564 | mmc_remove_host(mmc); |
1565 | ||
1566 | writel(0, host->base + MMCIMASK0); | |
1567 | writel(0, host->base + MMCIMASK1); | |
1568 | ||
1569 | writel(0, host->base + MMCICOMMAND); | |
1570 | writel(0, host->base + MMCIDATACTRL); | |
1571 | ||
c8ebae37 | 1572 | mmci_dma_release(host); |
1da177e4 | 1573 | free_irq(dev->irq[0], host); |
2686b4b4 LW |
1574 | if (!host->singleirq) |
1575 | free_irq(dev->irq[1], host); | |
1da177e4 | 1576 | |
89001446 RK |
1577 | if (host->gpio_wp != -ENOSYS) |
1578 | gpio_free(host->gpio_wp); | |
148b8b39 RV |
1579 | if (host->gpio_cd_irq >= 0) |
1580 | free_irq(host->gpio_cd_irq, host); | |
89001446 RK |
1581 | if (host->gpio_cd != -ENOSYS) |
1582 | gpio_free(host->gpio_cd); | |
1583 | ||
1da177e4 | 1584 | iounmap(host->base); |
ac940938 | 1585 | clk_disable_unprepare(host->clk); |
1da177e4 LT |
1586 | clk_put(host->clk); |
1587 | ||
99fc5131 LW |
1588 | if (host->vcc) |
1589 | mmc_regulator_set_ocr(mmc, host->vcc, 0); | |
34e84f39 LW |
1590 | regulator_put(host->vcc); |
1591 | ||
1da177e4 LT |
1592 | mmc_free_host(mmc); |
1593 | ||
1594 | amba_release_regions(dev); | |
1595 | } | |
1596 | ||
1597 | return 0; | |
1598 | } | |
1599 | ||
48fa7003 UH |
1600 | #ifdef CONFIG_SUSPEND |
1601 | static int mmci_suspend(struct device *dev) | |
1da177e4 | 1602 | { |
48fa7003 UH |
1603 | struct amba_device *adev = to_amba_device(dev); |
1604 | struct mmc_host *mmc = amba_get_drvdata(adev); | |
1da177e4 LT |
1605 | int ret = 0; |
1606 | ||
1607 | if (mmc) { | |
1608 | struct mmci_host *host = mmc_priv(mmc); | |
1609 | ||
1a13f8fa | 1610 | ret = mmc_suspend_host(mmc); |
2cd976c4 UH |
1611 | if (ret == 0) { |
1612 | pm_runtime_get_sync(dev); | |
1da177e4 | 1613 | writel(0, host->base + MMCIMASK0); |
2cd976c4 | 1614 | } |
1da177e4 LT |
1615 | } |
1616 | ||
1617 | return ret; | |
1618 | } | |
1619 | ||
48fa7003 | 1620 | static int mmci_resume(struct device *dev) |
1da177e4 | 1621 | { |
48fa7003 UH |
1622 | struct amba_device *adev = to_amba_device(dev); |
1623 | struct mmc_host *mmc = amba_get_drvdata(adev); | |
1da177e4 LT |
1624 | int ret = 0; |
1625 | ||
1626 | if (mmc) { | |
1627 | struct mmci_host *host = mmc_priv(mmc); | |
1628 | ||
1629 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); | |
2cd976c4 | 1630 | pm_runtime_put(dev); |
1da177e4 LT |
1631 | |
1632 | ret = mmc_resume_host(mmc); | |
1633 | } | |
1634 | ||
1635 | return ret; | |
1636 | } | |
1da177e4 LT |
1637 | #endif |
1638 | ||
48fa7003 UH |
1639 | static const struct dev_pm_ops mmci_dev_pm_ops = { |
1640 | SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume) | |
1641 | }; | |
1642 | ||
1da177e4 LT |
1643 | static struct amba_id mmci_ids[] = { |
1644 | { | |
1645 | .id = 0x00041180, | |
768fbc18 | 1646 | .mask = 0xff0fffff, |
4956e109 | 1647 | .data = &variant_arm, |
1da177e4 | 1648 | }, |
768fbc18 PM |
1649 | { |
1650 | .id = 0x01041180, | |
1651 | .mask = 0xff0fffff, | |
1652 | .data = &variant_arm_extended_fifo, | |
1653 | }, | |
1da177e4 LT |
1654 | { |
1655 | .id = 0x00041181, | |
1656 | .mask = 0x000fffff, | |
4956e109 | 1657 | .data = &variant_arm, |
1da177e4 | 1658 | }, |
cc30d60e LW |
1659 | /* ST Micro variants */ |
1660 | { | |
1661 | .id = 0x00180180, | |
1662 | .mask = 0x00ffffff, | |
4956e109 | 1663 | .data = &variant_u300, |
cc30d60e | 1664 | }, |
34fd4213 LW |
1665 | { |
1666 | .id = 0x10180180, | |
1667 | .mask = 0xf0ffffff, | |
1668 | .data = &variant_nomadik, | |
1669 | }, | |
cc30d60e LW |
1670 | { |
1671 | .id = 0x00280180, | |
1672 | .mask = 0x00ffffff, | |
4956e109 RV |
1673 | .data = &variant_u300, |
1674 | }, | |
1675 | { | |
1676 | .id = 0x00480180, | |
1784b157 | 1677 | .mask = 0xf0ffffff, |
4956e109 | 1678 | .data = &variant_ux500, |
cc30d60e | 1679 | }, |
1784b157 PL |
1680 | { |
1681 | .id = 0x10480180, | |
1682 | .mask = 0xf0ffffff, | |
1683 | .data = &variant_ux500v2, | |
1684 | }, | |
1da177e4 LT |
1685 | { 0, 0 }, |
1686 | }; | |
1687 | ||
9f99835f DM |
1688 | MODULE_DEVICE_TABLE(amba, mmci_ids); |
1689 | ||
1da177e4 LT |
1690 | static struct amba_driver mmci_driver = { |
1691 | .drv = { | |
1692 | .name = DRIVER_NAME, | |
48fa7003 | 1693 | .pm = &mmci_dev_pm_ops, |
1da177e4 LT |
1694 | }, |
1695 | .probe = mmci_probe, | |
6dc4a47a | 1696 | .remove = __devexit_p(mmci_remove), |
1da177e4 LT |
1697 | .id_table = mmci_ids, |
1698 | }; | |
1699 | ||
9e5ed094 | 1700 | module_amba_driver(mmci_driver); |
1da177e4 | 1701 | |
1da177e4 LT |
1702 | module_param(fmax, uint, 0444); |
1703 | ||
1704 | MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); | |
1705 | MODULE_LICENSE("GPL"); |