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mmc: mmci: Move all CMD irq handling to mmci_cmd_irq()
[deliverable/linux.git] / drivers / mmc / host / mmci.c
CommitLineData
1da177e4 1/*
70f10482 2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
1da177e4
LT		 3 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
c8ebae37 5 * Copyright (C) 2010 ST-Ericsson SA
1da177e4
LT		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
1da177e4
LT		 11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/device.h>
ef289982 16#include <linux/io.h>
1da177e4 17#include <linux/interrupt.h>
613b152c 18#include <linux/kernel.h>
000bc9d5 19#include <linux/slab.h>
1da177e4
LT		 20#include <linux/delay.h>
21#include <linux/err.h>
22#include <linux/highmem.h>
019a5f56 23#include <linux/log2.h>
70be208f 24#include <linux/mmc/pm.h>
1da177e4 25#include <linux/mmc/host.h>
34177802 26#include <linux/mmc/card.h>
d2762090 27#include <linux/mmc/slot-gpio.h>
a62c80e5 28#include <linux/amba/bus.h>
f8ce2547 29#include <linux/clk.h>
bd6dee6f 30#include <linux/scatterlist.h>
89001446 31#include <linux/gpio.h>
9a597016 32#include <linux/of_gpio.h>
34e84f39 33#include <linux/regulator/consumer.h>
c8ebae37
RK		 34#include <linux/dmaengine.h>
35#include <linux/dma-mapping.h>
36#include <linux/amba/mmci.h>
1c3be369 37#include <linux/pm_runtime.h>
258aea76 38#include <linux/types.h>
a9a83785 39#include <linux/pinctrl/consumer.h>
1da177e4 40
7b09cdac 41#include <asm/div64.h>
1da177e4 42#include <asm/io.h>
c6b8fdad 43#include <asm/sizes.h>
1da177e4
LT		 44
45#include "mmci.h"
46
47#define DRIVER_NAME "mmci-pl18x"
48
1da177e4
LT		 49static unsigned int fmax = 515633;
50
4956e109
RV		 51/**
52 * struct variant_data - MMCI variant-specific quirks
53 * @clkreg: default value for MCICLOCK register
4380c14f 54 * @clkreg_enable: enable value for MMCICLOCK register
e1412d85 55 * @clkreg_8bit_bus_enable: enable value for 8 bit bus
e8740644 56 * @clkreg_neg_edge_enable: enable value for inverted data/cmd output
08458ef6 57 * @datalength_bits: number of bits in the MMCIDATALENGTH register
8301bb68
RV		 58 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
59 * is asserted (likewise for RX)
60 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
61 * is asserted (likewise for RX)
ae7b0061 62 * @data_cmd_enable: enable value for data commands.
34177802 63 * @sdio: variant supports SDIO
b70a67f9 64 * @st_clkdiv: true if using a ST-specific clock divider algorithm
e17dca2b 65 * @datactrl_mask_ddrmode: ddr mode mask in datactrl register.
1784b157 66 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
ff783233
SK		 67 * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl
68 * register
7d72a1d4 69 * @pwrreg_powerup: power up value for MMCIPOWER register
dc6500bf 70 * @f_max: maximum clk frequency supported by the controller.
4d1a3a0d 71 * @signal_direction: input/out direction of bus signals can be indicated
f4670dae 72 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
01259620 73 * @busy_detect: true if busy detection on dat0 is supported
1ff44433 74 * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
3f4e6f7b 75 * @explicit_mclk_control: enable explicit mclk control in driver.
9c34b73d 76 * @qcom_fifo: enables qcom specific fifo pio read logic.
4956e109
RV		 77 */
78struct variant_data {
79 unsigned int clkreg;
4380c14f 80 unsigned int clkreg_enable;
e1412d85 81 unsigned int clkreg_8bit_bus_enable;
e8740644 82 unsigned int clkreg_neg_edge_enable;
08458ef6 83 unsigned int datalength_bits;
8301bb68
RV		 84 unsigned int fifosize;
85 unsigned int fifohalfsize;
ae7b0061 86 unsigned int data_cmd_enable;
e17dca2b 87 unsigned int datactrl_mask_ddrmode;
34177802 88 bool sdio;
b70a67f9 89 bool st_clkdiv;
1784b157 90 bool blksz_datactrl16;
ff783233 91 bool blksz_datactrl4;
7d72a1d4 92 u32 pwrreg_powerup;
dc6500bf 93 u32 f_max;
4d1a3a0d 94 bool signal_direction;
f4670dae 95 bool pwrreg_clkgate;
01259620 96 bool busy_detect;
1ff44433 97 bool pwrreg_nopower;
3f4e6f7b 98 bool explicit_mclk_control;
9c34b73d 99 bool qcom_fifo;
4956e109
RV		 100};
101
102static struct variant_data variant_arm = {
8301bb68
RV		 103 .fifosize = 16 * 4,
104 .fifohalfsize = 8 * 4,
08458ef6 105 .datalength_bits = 16,
7d72a1d4 106 .pwrreg_powerup = MCI_PWR_UP,
dc6500bf 107 .f_max = 100000000,
4956e109
RV		 108};
109
768fbc18
PM		 110static struct variant_data variant_arm_extended_fifo = {
111 .fifosize = 128 * 4,
112 .fifohalfsize = 64 * 4,
113 .datalength_bits = 16,
7d72a1d4 114 .pwrreg_powerup = MCI_PWR_UP,
dc6500bf 115 .f_max = 100000000,
768fbc18
PM		 116};
117
3a37298a
PM		 118static struct variant_data variant_arm_extended_fifo_hwfc = {
119 .fifosize = 128 * 4,
120 .fifohalfsize = 64 * 4,
121 .clkreg_enable = MCI_ARM_HWFCEN,
122 .datalength_bits = 16,
123 .pwrreg_powerup = MCI_PWR_UP,
dc6500bf 124 .f_max = 100000000,
3a37298a
PM		 125};
126
4956e109 127static struct variant_data variant_u300 = {
8301bb68
RV		 128 .fifosize = 16 * 4,
129 .fifohalfsize = 8 * 4,
49ac215e 130 .clkreg_enable = MCI_ST_U300_HWFCEN,
e1412d85 131 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
08458ef6 132 .datalength_bits = 16,
34177802 133 .sdio = true,
7d72a1d4 134 .pwrreg_powerup = MCI_PWR_ON,
dc6500bf 135 .f_max = 100000000,
4d1a3a0d 136 .signal_direction = true,
f4670dae 137 .pwrreg_clkgate = true,
1ff44433 138 .pwrreg_nopower = true,
4956e109
RV		 139};
140
34fd4213
LW		 141static struct variant_data variant_nomadik = {
142 .fifosize = 16 * 4,
143 .fifohalfsize = 8 * 4,
144 .clkreg = MCI_CLK_ENABLE,
145 .datalength_bits = 24,
146 .sdio = true,
147 .st_clkdiv = true,
148 .pwrreg_powerup = MCI_PWR_ON,
dc6500bf 149 .f_max = 100000000,
34fd4213 150 .signal_direction = true,
f4670dae 151 .pwrreg_clkgate = true,
1ff44433 152 .pwrreg_nopower = true,
34fd4213
LW		 153};
154
4956e109 155static struct variant_data variant_ux500 = {
8301bb68
RV		 156 .fifosize = 30 * 4,
157 .fifohalfsize = 8 * 4,
4956e109 158 .clkreg = MCI_CLK_ENABLE,
49ac215e 159 .clkreg_enable = MCI_ST_UX500_HWFCEN,
e1412d85 160 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
e8740644 161 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
08458ef6 162 .datalength_bits = 24,
34177802 163 .sdio = true,
b70a67f9 164 .st_clkdiv = true,
7d72a1d4 165 .pwrreg_powerup = MCI_PWR_ON,
dc6500bf 166 .f_max = 100000000,
4d1a3a0d 167 .signal_direction = true,
f4670dae 168 .pwrreg_clkgate = true,
01259620 169 .busy_detect = true,
1ff44433 170 .pwrreg_nopower = true,
4956e109 171};
b70a67f9 172
1784b157
PL		 173static struct variant_data variant_ux500v2 = {
174 .fifosize = 30 * 4,
175 .fifohalfsize = 8 * 4,
176 .clkreg = MCI_CLK_ENABLE,
177 .clkreg_enable = MCI_ST_UX500_HWFCEN,
e1412d85 178 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
e8740644 179 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
e17dca2b 180 .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE,
1784b157
PL		 181 .datalength_bits = 24,
182 .sdio = true,
183 .st_clkdiv = true,
184 .blksz_datactrl16 = true,
7d72a1d4 185 .pwrreg_powerup = MCI_PWR_ON,
dc6500bf 186 .f_max = 100000000,
4d1a3a0d 187 .signal_direction = true,
f4670dae 188 .pwrreg_clkgate = true,
01259620 189 .busy_detect = true,
1ff44433 190 .pwrreg_nopower = true,
1784b157
PL		 191};
192
55b604ae
SK		 193static struct variant_data variant_qcom = {
194 .fifosize = 16 * 4,
195 .fifohalfsize = 8 * 4,
196 .clkreg = MCI_CLK_ENABLE,
197 .clkreg_enable = MCI_QCOM_CLK_FLOWENA |
198 MCI_QCOM_CLK_SELECT_IN_FBCLK,
199 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8,
200 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE,
201 .data_cmd_enable = MCI_QCOM_CSPM_DATCMD,
202 .blksz_datactrl4 = true,
203 .datalength_bits = 24,
204 .pwrreg_powerup = MCI_PWR_UP,
205 .f_max = 208000000,
206 .explicit_mclk_control = true,
207 .qcom_fifo = true,
208};
209
01259620
UH		 210static int mmci_card_busy(struct mmc_host *mmc)
211{
212 struct mmci_host *host = mmc_priv(mmc);
213 unsigned long flags;
214 int busy = 0;
215
216 pm_runtime_get_sync(mmc_dev(mmc));
217
218 spin_lock_irqsave(&host->lock, flags);
219 if (readl(host->base + MMCISTATUS) & MCI_ST_CARDBUSY)
220 busy = 1;
221 spin_unlock_irqrestore(&host->lock, flags);
222
223 pm_runtime_mark_last_busy(mmc_dev(mmc));
224 pm_runtime_put_autosuspend(mmc_dev(mmc));
225
226 return busy;
227}
228
653a761e
UH		 229/*
230 * Validate mmc prerequisites
231 */
232static int mmci_validate_data(struct mmci_host *host,
233 struct mmc_data *data)
234{
235 if (!data)
236 return 0;
237
238 if (!is_power_of_2(data->blksz)) {
239 dev_err(mmc_dev(host->mmc),
240 "unsupported block size (%d bytes)\n", data->blksz);
241 return -EINVAL;
242 }
243
244 return 0;
245}
246
f829c042
UH		 247static void mmci_reg_delay(struct mmci_host *host)
248{
249 /*
250 * According to the spec, at least three feedback clock cycles
251 * of max 52 MHz must pass between two writes to the MMCICLOCK reg.
252 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes.
253 * Worst delay time during card init is at 100 kHz => 30 us.
254 * Worst delay time when up and running is at 25 MHz => 120 ns.
255 */
256 if (host->cclk < 25000000)
257 udelay(30);
258 else
259 ndelay(120);
260}
261
7437cfa5
UH		 262/*
263 * This must be called with host->lock held
264 */
265static void mmci_write_clkreg(struct mmci_host *host, u32 clk)
266{
267 if (host->clk_reg != clk) {
268 host->clk_reg = clk;
269 writel(clk, host->base + MMCICLOCK);
270 }
271}
272
273/*
274 * This must be called with host->lock held
275 */
276static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
277{
278 if (host->pwr_reg != pwr) {
279 host->pwr_reg = pwr;
280 writel(pwr, host->base + MMCIPOWER);
281 }
282}
283
9cc639a2
UH		 284/*
285 * This must be called with host->lock held
286 */
287static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
288{
01259620
UH		 289 /* Keep ST Micro busy mode if enabled */
290 datactrl |= host->datactrl_reg & MCI_ST_DPSM_BUSYMODE;
291
9cc639a2
UH		 292 if (host->datactrl_reg != datactrl) {
293 host->datactrl_reg = datactrl;
294 writel(datactrl, host->base + MMCIDATACTRL);
295 }
296}
297
a6a6464a
LW		 298/*
299 * This must be called with host->lock held
300 */
301static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
302{
4956e109
RV		 303 struct variant_data *variant = host->variant;
304 u32 clk = variant->clkreg;
a6a6464a 305
c58a8509
UH		 306 /* Make sure cclk reflects the current calculated clock */
307 host->cclk = 0;
308
a6a6464a 309 if (desired) {
3f4e6f7b
SK		 310 if (variant->explicit_mclk_control) {
311 host->cclk = host->mclk;
312 } else if (desired >= host->mclk) {
991a86e1 313 clk = MCI_CLK_BYPASS;
399bc486
LW		 314 if (variant->st_clkdiv)
315 clk |= MCI_ST_UX500_NEG_EDGE;
a6a6464a 316 host->cclk = host->mclk;
b70a67f9
LW		 317 } else if (variant->st_clkdiv) {
318 /*
319 * DB8500 TRM says f = mclk / (clkdiv + 2)
320 * => clkdiv = (mclk / f) - 2
321 * Round the divider up so we don't exceed the max
322 * frequency
323 */
324 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
325 if (clk >= 256)
326 clk = 255;
327 host->cclk = host->mclk / (clk + 2);
a6a6464a 328 } else {
b70a67f9
LW		 329 /*
330 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
331 * => clkdiv = mclk / (2 * f) - 1
332 */
a6a6464a
LW		 333 clk = host->mclk / (2 * desired) - 1;
334 if (clk >= 256)
335 clk = 255;
336 host->cclk = host->mclk / (2 * (clk + 1));
337 }
4380c14f
RV		 338
339 clk |= variant->clkreg_enable;
a6a6464a
LW		 340 clk |= MCI_CLK_ENABLE;
341 /* This hasn't proven to be worthwhile */
342 /* clk |= MCI_CLK_PWRSAVE; */
343 }
344
c58a8509
UH		 345 /* Set actual clock for debug */
346 host->mmc->actual_clock = host->cclk;
347
9e6c82cd 348 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
771dc157
LW		 349 clk |= MCI_4BIT_BUS;
350 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
e1412d85 351 clk |= variant->clkreg_8bit_bus_enable;
9e6c82cd 352
6dad6c95
SJ		 353 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
354 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
e8740644 355 clk |= variant->clkreg_neg_edge_enable;
6dbb6ee0 356
7437cfa5 357 mmci_write_clkreg(host, clk);
a6a6464a
LW		 358}
359
1da177e4
LT		 360static void
361mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
362{
363 writel(0, host->base + MMCICOMMAND);
364
e47c222b
RK		 365 BUG_ON(host->data);
366
1da177e4
LT		 367 host->mrq = NULL;
368 host->cmd = NULL;
369
1da177e4 370 mmc_request_done(host->mmc, mrq);
2cd976c4
UH		 371
372 pm_runtime_mark_last_busy(mmc_dev(host->mmc));
373 pm_runtime_put_autosuspend(mmc_dev(host->mmc));
1da177e4
LT		 374}
375
2686b4b4
LW		 376static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
377{
378 void __iomem *base = host->base;
379
380 if (host->singleirq) {
381 unsigned int mask0 = readl(base + MMCIMASK0);
382
383 mask0 &= ~MCI_IRQ1MASK;
384 mask0 |= mask;
385
386 writel(mask0, base + MMCIMASK0);
387 }
388
389 writel(mask, base + MMCIMASK1);
390}
391
1da177e4
LT		 392static void mmci_stop_data(struct mmci_host *host)
393{
9cc639a2 394 mmci_write_datactrlreg(host, 0);
2686b4b4 395 mmci_set_mask1(host, 0);
1da177e4
LT		 396 host->data = NULL;
397}
398
4ce1d6cb
RV		 399static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
400{
401 unsigned int flags = SG_MITER_ATOMIC;
402
403 if (data->flags & MMC_DATA_READ)
404 flags |= SG_MITER_TO_SG;
405 else
406 flags |= SG_MITER_FROM_SG;
407
408 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
409}
410
c8ebae37
RK		 411/*
412 * All the DMA operation mode stuff goes inside this ifdef.
413 * This assumes that you have a generic DMA device interface,
414 * no custom DMA interfaces are supported.
415 */
416#ifdef CONFIG_DMA_ENGINE
c3be1efd 417static void mmci_dma_setup(struct mmci_host *host)
c8ebae37 418{
c8ebae37
RK		 419 const char *rxname, *txname;
420 dma_cap_mask_t mask;
421
1fd83f0e
LJ		 422 host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx");
423 host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx");
c8ebae37 424
58c7ccbf
PF		 425 /* initialize pre request cookie */
426 host->next_data.cookie = 1;
427
c8ebae37
RK		 428 /* Try to acquire a generic DMA engine slave channel */
429 dma_cap_zero(mask);
430 dma_cap_set(DMA_SLAVE, mask);
431
1fd83f0e
LJ		 432 /*
433 * If only an RX channel is specified, the driver will
434 * attempt to use it bidirectionally, however if it is
435 * is specified but cannot be located, DMA will be disabled.
436 */
437 if (host->dma_rx_channel && !host->dma_tx_channel)
438 host->dma_tx_channel = host->dma_rx_channel;
439
c8ebae37
RK		 440 if (host->dma_rx_channel)
441 rxname = dma_chan_name(host->dma_rx_channel);
442 else
443 rxname = "none";
444
445 if (host->dma_tx_channel)
446 txname = dma_chan_name(host->dma_tx_channel);
447 else
448 txname = "none";
449
450 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
451 rxname, txname);
452
453 /*
454 * Limit the maximum segment size in any SG entry according to
455 * the parameters of the DMA engine device.
456 */
457 if (host->dma_tx_channel) {
458 struct device *dev = host->dma_tx_channel->device->dev;
459 unsigned int max_seg_size = dma_get_max_seg_size(dev);
460
461 if (max_seg_size < host->mmc->max_seg_size)
462 host->mmc->max_seg_size = max_seg_size;
463 }
464 if (host->dma_rx_channel) {
465 struct device *dev = host->dma_rx_channel->device->dev;
466 unsigned int max_seg_size = dma_get_max_seg_size(dev);
467
468 if (max_seg_size < host->mmc->max_seg_size)
469 host->mmc->max_seg_size = max_seg_size;
470 }
471}
472
473/*
6e0ee714 474 * This is used in or so inline it
c8ebae37
RK		 475 * so it can be discarded.
476 */
477static inline void mmci_dma_release(struct mmci_host *host)
478{
c8ebae37
RK		 479 if (host->dma_rx_channel)
480 dma_release_channel(host->dma_rx_channel);
8c3a05b4 481 if (host->dma_tx_channel)
c8ebae37
RK		 482 dma_release_channel(host->dma_tx_channel);
483 host->dma_rx_channel = host->dma_tx_channel = NULL;
484}
485
653a761e
UH		 486static void mmci_dma_data_error(struct mmci_host *host)
487{
488 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
489 dmaengine_terminate_all(host->dma_current);
490 host->dma_current = NULL;
491 host->dma_desc_current = NULL;
492 host->data->host_cookie = 0;
493}
494
c8ebae37
RK		 495static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
496{
653a761e 497 struct dma_chan *chan;
c8ebae37 498 enum dma_data_direction dir;
653a761e
UH		 499
500 if (data->flags & MMC_DATA_READ) {
501 dir = DMA_FROM_DEVICE;
502 chan = host->dma_rx_channel;
503 } else {
504 dir = DMA_TO_DEVICE;
505 chan = host->dma_tx_channel;
506 }
507
508 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
509}
510
511static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data)
512{
c8ebae37
RK		 513 u32 status;
514 int i;
515
516 /* Wait up to 1ms for the DMA to complete */
517 for (i = 0; ; i++) {
518 status = readl(host->base + MMCISTATUS);
519 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
520 break;
521 udelay(10);
522 }
523
524 /*
525 * Check to see whether we still have some data left in the FIFO -
526 * this catches DMA controllers which are unable to monitor the
527 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
528 * contiguous buffers. On TX, we'll get a FIFO underrun error.
529 */
530 if (status & MCI_RXDATAAVLBLMASK) {
653a761e 531 mmci_dma_data_error(host);
c8ebae37
RK		 532 if (!data->error)
533 data->error = -EIO;
534 }
535
58c7ccbf 536 if (!data->host_cookie)
653a761e 537 mmci_dma_unmap(host, data);
c8ebae37
RK		 538
539 /*
540 * Use of DMA with scatter-gather is impossible.
541 * Give up with DMA and switch back to PIO mode.
542 */
543 if (status & MCI_RXDATAAVLBLMASK) {
544 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
545 mmci_dma_release(host);
546 }
c8ebae37 547
653a761e
UH		 548 host->dma_current = NULL;
549 host->dma_desc_current = NULL;
c8ebae37
RK		 550}
551
653a761e
UH		 552/* prepares DMA channel and DMA descriptor, returns non-zero on failure */
553static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data,
554 struct dma_chan **dma_chan,
555 struct dma_async_tx_descriptor **dma_desc)
c8ebae37
RK		 556{
557 struct variant_data *variant = host->variant;
558 struct dma_slave_config conf = {
559 .src_addr = host->phybase + MMCIFIFO,
560 .dst_addr = host->phybase + MMCIFIFO,
561 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
562 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
563 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
564 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
258aea76 565 .device_fc = false,
c8ebae37 566 };
c8ebae37
RK		 567 struct dma_chan *chan;
568 struct dma_device *device;
569 struct dma_async_tx_descriptor *desc;
05f5799c 570 enum dma_data_direction buffer_dirn;
c8ebae37
RK		 571 int nr_sg;
572
c8ebae37 573 if (data->flags & MMC_DATA_READ) {
05f5799c
VK		 574 conf.direction = DMA_DEV_TO_MEM;
575 buffer_dirn = DMA_FROM_DEVICE;
c8ebae37
RK		 576 chan = host->dma_rx_channel;
577 } else {
05f5799c
VK		 578 conf.direction = DMA_MEM_TO_DEV;
579 buffer_dirn = DMA_TO_DEVICE;
c8ebae37
RK		 580 chan = host->dma_tx_channel;
581 }
582
583 /* If there's no DMA channel, fall back to PIO */
584 if (!chan)
585 return -EINVAL;
586
587 /* If less than or equal to the fifo size, don't bother with DMA */
58c7ccbf 588 if (data->blksz * data->blocks <= variant->fifosize)
c8ebae37
RK		 589 return -EINVAL;
590
591 device = chan->device;
05f5799c 592 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
c8ebae37
RK		 593 if (nr_sg == 0)
594 return -EINVAL;
595
596 dmaengine_slave_config(chan, &conf);
16052827 597 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg,
c8ebae37
RK		 598 conf.direction, DMA_CTRL_ACK);
599 if (!desc)
600 goto unmap_exit;
601
653a761e
UH		 602 *dma_chan = chan;
603 *dma_desc = desc;
58c7ccbf
PF		 604
605 return 0;
c8ebae37 606
58c7ccbf 607 unmap_exit:
05f5799c 608 dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
58c7ccbf
PF		 609 return -ENOMEM;
610}
611
653a761e
UH		 612static inline int mmci_dma_prep_data(struct mmci_host *host,
613 struct mmc_data *data)
614{
615 /* Check if next job is already prepared. */
616 if (host->dma_current && host->dma_desc_current)
617 return 0;
618
619 /* No job were prepared thus do it now. */
620 return __mmci_dma_prep_data(host, data, &host->dma_current,
621 &host->dma_desc_current);
622}
623
624static inline int mmci_dma_prep_next(struct mmci_host *host,
625 struct mmc_data *data)
626{
627 struct mmci_host_next *nd = &host->next_data;
628 return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc);
629}
630
58c7ccbf
PF		 631static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
632{
633 int ret;
634 struct mmc_data *data = host->data;
635
653a761e 636 ret = mmci_dma_prep_data(host, host->data);
58c7ccbf
PF		 637 if (ret)
638 return ret;
639
640 /* Okay, go for it. */
c8ebae37
RK		 641 dev_vdbg(mmc_dev(host->mmc),
642 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
643 data->sg_len, data->blksz, data->blocks, data->flags);
58c7ccbf
PF		 644 dmaengine_submit(host->dma_desc_current);
645 dma_async_issue_pending(host->dma_current);
c8ebae37
RK		 646
647 datactrl |= MCI_DPSM_DMAENABLE;
648
649 /* Trigger the DMA transfer */
9cc639a2 650 mmci_write_datactrlreg(host, datactrl);
c8ebae37
RK		 651
652 /*
653 * Let the MMCI say when the data is ended and it's time
654 * to fire next DMA request. When that happens, MMCI will
655 * call mmci_data_end()
656 */
657 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
658 host->base + MMCIMASK0);
659 return 0;
58c7ccbf 660}
c8ebae37 661
58c7ccbf
PF		 662static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
663{
664 struct mmci_host_next *next = &host->next_data;
665
653a761e
UH		 666 WARN_ON(data->host_cookie && data->host_cookie != next->cookie);
667 WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan));
58c7ccbf
PF		 668
669 host->dma_desc_current = next->dma_desc;
670 host->dma_current = next->dma_chan;
58c7ccbf
PF		 671 next->dma_desc = NULL;
672 next->dma_chan = NULL;
c8ebae37 673}
58c7ccbf
PF		 674
675static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq,
676 bool is_first_req)
677{
678 struct mmci_host *host = mmc_priv(mmc);
679 struct mmc_data *data = mrq->data;
680 struct mmci_host_next *nd = &host->next_data;
681
682 if (!data)
683 return;
684
653a761e
UH		 685 BUG_ON(data->host_cookie);
686
687 if (mmci_validate_data(host, data))
58c7ccbf 688 return;
58c7ccbf 689
653a761e
UH		 690 if (!mmci_dma_prep_next(host, data))
691 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie;
58c7ccbf
PF		 692}
693
694static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
695 int err)
696{
697 struct mmci_host *host = mmc_priv(mmc);
698 struct mmc_data *data = mrq->data;
58c7ccbf 699
653a761e 700 if (!data || !data->host_cookie)
58c7ccbf
PF		 701 return;
702
653a761e 703 mmci_dma_unmap(host, data);
58c7ccbf 704
653a761e
UH		 705 if (err) {
706 struct mmci_host_next *next = &host->next_data;
707 struct dma_chan *chan;
708 if (data->flags & MMC_DATA_READ)
709 chan = host->dma_rx_channel;
710 else
711 chan = host->dma_tx_channel;
712 dmaengine_terminate_all(chan);
58c7ccbf 713
653a761e
UH		 714 next->dma_desc = NULL;
715 next->dma_chan = NULL;
58c7ccbf
PF		 716 }
717}
718
c8ebae37
RK		 719#else
720/* Blank functions if the DMA engine is not available */
58c7ccbf
PF		 721static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
722{
723}
c8ebae37
RK		 724static inline void mmci_dma_setup(struct mmci_host *host)
725{
726}
727
728static inline void mmci_dma_release(struct mmci_host *host)
729{
730}
731
732static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
733{
734}
735
653a761e
UH		 736static inline void mmci_dma_finalize(struct mmci_host *host,
737 struct mmc_data *data)
738{
739}
740
c8ebae37
RK		 741static inline void mmci_dma_data_error(struct mmci_host *host)
742{
743}
744
745static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
746{
747 return -ENOSYS;
748}
58c7ccbf
PF		 749
750#define mmci_pre_request NULL
751#define mmci_post_request NULL
752
c8ebae37
RK		 753#endif
754
1da177e4
LT		 755static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
756{
8301bb68 757 struct variant_data *variant = host->variant;
1da177e4 758 unsigned int datactrl, timeout, irqmask;
7b09cdac 759 unsigned long long clks;
1da177e4 760 void __iomem *base;
3bc87f24 761 int blksz_bits;
1da177e4 762
64de0289
LW		 763 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
764 data->blksz, data->blocks, data->flags);
1da177e4
LT		 765
766 host->data = data;
528320db 767 host->size = data->blksz * data->blocks;
51d4375d 768 data->bytes_xfered = 0;
1da177e4 769
7b09cdac 770 clks = (unsigned long long)data->timeout_ns * host->cclk;
c4a35769 771 do_div(clks, NSEC_PER_SEC);
7b09cdac
RK		 772
773 timeout = data->timeout_clks + (unsigned int)clks;
1da177e4
LT		 774
775 base = host->base;
776 writel(timeout, base + MMCIDATATIMER);
777 writel(host->size, base + MMCIDATALENGTH);
778
3bc87f24
RK		 779 blksz_bits = ffs(data->blksz) - 1;
780 BUG_ON(1 << blksz_bits != data->blksz);
781
1784b157
PL		 782 if (variant->blksz_datactrl16)
783 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16);
ff783233
SK		 784 else if (variant->blksz_datactrl4)
785 datactrl = MCI_DPSM_ENABLE | (data->blksz << 4);
1784b157
PL		 786 else
787 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
c8ebae37
RK		 788
789 if (data->flags & MMC_DATA_READ)
1da177e4 790 datactrl |= MCI_DPSM_DIRECTION;
c8ebae37 791
7258db7e
UH		 792 /* The ST Micro variants has a special bit to enable SDIO */
793 if (variant->sdio && host->mmc->card)
06c1a121
UH		 794 if (mmc_card_sdio(host->mmc->card)) {
795 /*
796 * The ST Micro variants has a special bit
797 * to enable SDIO.
798 */
799 u32 clk;
800
7258db7e
UH		 801 datactrl |= MCI_ST_DPSM_SDIOEN;
802
06c1a121 803 /*
70ac0935
UH		 804 * The ST Micro variant for SDIO small write transfers
805 * needs to have clock H/W flow control disabled,
806 * otherwise the transfer will not start. The threshold
807 * depends on the rate of MCLK.
06c1a121 808 */
70ac0935
UH		 809 if (data->flags & MMC_DATA_WRITE &&
810 (host->size < 8 ||
811 (host->size <= 8 && host->mclk > 50000000)))
06c1a121
UH		 812 clk = host->clk_reg & ~variant->clkreg_enable;
813 else
814 clk = host->clk_reg | variant->clkreg_enable;
815
816 mmci_write_clkreg(host, clk);
817 }
818
6dad6c95
SJ		 819 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
820 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
e17dca2b 821 datactrl |= variant->datactrl_mask_ddrmode;
6dbb6ee0 822
c8ebae37
RK		 823 /*
824 * Attempt to use DMA operation mode, if this
825 * should fail, fall back to PIO mode
826 */
827 if (!mmci_dma_start_data(host, datactrl))
828 return;
829
830 /* IRQ mode, map the SG list for CPU reading/writing */
831 mmci_init_sg(host, data);
832
833 if (data->flags & MMC_DATA_READ) {
1da177e4 834 irqmask = MCI_RXFIFOHALFFULLMASK;
0425a142
RK		 835
836 /*
c4d877c1
RK		 837 * If we have less than the fifo 'half-full' threshold to
838 * transfer, trigger a PIO interrupt as soon as any data
839 * is available.
0425a142 840 */
c4d877c1 841 if (host->size < variant->fifohalfsize)
0425a142 842 irqmask |= MCI_RXDATAAVLBLMASK;
1da177e4
LT		 843 } else {
844 /*
845 * We don't actually need to include "FIFO empty" here
846 * since its implicit in "FIFO half empty".
847 */
848 irqmask = MCI_TXFIFOHALFEMPTYMASK;
849 }
850
9cc639a2 851 mmci_write_datactrlreg(host, datactrl);
1da177e4 852 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
2686b4b4 853 mmci_set_mask1(host, irqmask);
1da177e4
LT		 854}
855
856static void
857mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
858{
859 void __iomem *base = host->base;
860
64de0289 861 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
1da177e4
LT		 862 cmd->opcode, cmd->arg, cmd->flags);
863
864 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
865 writel(0, base + MMCICOMMAND);
6adb2a80 866 mmci_reg_delay(host);
1da177e4
LT		 867 }
868
869 c |= cmd->opcode | MCI_CPSM_ENABLE;
e9225176
RK		 870 if (cmd->flags & MMC_RSP_PRESENT) {
871 if (cmd->flags & MMC_RSP_136)
872 c |= MCI_CPSM_LONGRSP;
1da177e4 873 c |= MCI_CPSM_RESPONSE;
1da177e4
LT		 874 }
875 if (/*interrupt*/0)
876 c |= MCI_CPSM_INTERRUPT;
877
ae7b0061
SK		 878 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC)
879 c |= host->variant->data_cmd_enable;
880
1da177e4
LT		 881 host->cmd = cmd;
882
883 writel(cmd->arg, base + MMCIARGUMENT);
884 writel(c, base + MMCICOMMAND);
885}
886
887static void
888mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
889 unsigned int status)
890{
1cb9da50
UH		 891 /* Make sure we have data to handle */
892 if (!data)
893 return;
894
f20f8f21 895 /* First check for errors */
b63038d6
UH		 896 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
897 MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
8cb28155 898 u32 remain, success;
f20f8f21 899
c8ebae37 900 /* Terminate the DMA transfer */
653a761e 901 if (dma_inprogress(host)) {
c8ebae37 902 mmci_dma_data_error(host);
653a761e
UH		 903 mmci_dma_unmap(host, data);
904 }
e9c091b4
RK		 905
906 /*
c8afc9d5
RK		 907 * Calculate how far we are into the transfer. Note that
908 * the data counter gives the number of bytes transferred
909 * on the MMC bus, not on the host side. On reads, this
910 * can be as much as a FIFO-worth of data ahead. This
911 * matters for FIFO overruns only.
e9c091b4 912 */
f5a106d9 913 remain = readl(host->base + MMCIDATACNT);
8cb28155
LW		 914 success = data->blksz * data->blocks - remain;
915
c8afc9d5
RK		 916 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
917 status, success);
8cb28155
LW		 918 if (status & MCI_DATACRCFAIL) {
919 /* Last block was not successful */
c8afc9d5 920 success -= 1;
17b0429d 921 data->error = -EILSEQ;
8cb28155 922 } else if (status & MCI_DATATIMEOUT) {
17b0429d 923 data->error = -ETIMEDOUT;
757df746
LW		 924 } else if (status & MCI_STARTBITERR) {
925 data->error = -ECOMM;
c8afc9d5
RK		 926 } else if (status & MCI_TXUNDERRUN) {
927 data->error = -EIO;
928 } else if (status & MCI_RXOVERRUN) {
929 if (success > host->variant->fifosize)
930 success -= host->variant->fifosize;
931 else
932 success = 0;
17b0429d 933 data->error = -EIO;
4ce1d6cb 934 }
51d4375d 935 data->bytes_xfered = round_down(success, data->blksz);
1da177e4 936 }
f20f8f21 937
8cb28155
LW		 938 if (status & MCI_DATABLOCKEND)
939 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
f20f8f21 940
ccff9b51 941 if (status & MCI_DATAEND || data->error) {
c8ebae37 942 if (dma_inprogress(host))
653a761e 943 mmci_dma_finalize(host, data);
1da177e4
LT		 944 mmci_stop_data(host);
945
8cb28155
LW		 946 if (!data->error)
947 /* The error clause is handled above, success! */
51d4375d 948 data->bytes_xfered = data->blksz * data->blocks;
f20f8f21 949
024629c6 950 if (!data->stop || host->mrq->sbc) {
1da177e4
LT		 951 mmci_request_end(host, data->mrq);
952 } else {
953 mmci_start_command(host, data->stop, 0);
954 }
955 }
956}
957
958static void
959mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
960 unsigned int status)
961{
962 void __iomem *base = host->base;
ad82bfea
UH		 963 bool sbc, busy_resp;
964
965 if (!cmd)
966 return;
967
968 sbc = (cmd == host->mrq->sbc);
969 busy_resp = host->variant->busy_detect && (cmd->flags & MMC_RSP_BUSY);
970
971 if (!((status|host->busy_status) & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|
972 MCI_CMDSENT|MCI_CMDRESPEND)))
973 return;
8d94b54d
UH		 974
975 /* Check if we need to wait for busy completion. */
976 if (host->busy_status && (status & MCI_ST_CARDBUSY))
977 return;
978
979 /* Enable busy completion if needed and supported. */
980 if (!host->busy_status && busy_resp &&
981 !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) &&
982 (readl(base + MMCISTATUS) & MCI_ST_CARDBUSY)) {
983 writel(readl(base + MMCIMASK0) | MCI_ST_BUSYEND,
984 base + MMCIMASK0);
985 host->busy_status = status & (MCI_CMDSENT|MCI_CMDRESPEND);
986 return;
987 }
988
989 /* At busy completion, mask the IRQ and complete the request. */
990 if (host->busy_status) {
991 writel(readl(base + MMCIMASK0) & ~MCI_ST_BUSYEND,
992 base + MMCIMASK0);
993 host->busy_status = 0;
994 }
1da177e4
LT		 995
996 host->cmd = NULL;
997
1da177e4 998 if (status & MCI_CMDTIMEOUT) {
17b0429d 999 cmd->error = -ETIMEDOUT;
1da177e4 1000 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
17b0429d 1001 cmd->error = -EILSEQ;
9047b435
RKAL		 1002 } else {
1003 cmd->resp[0] = readl(base + MMCIRESPONSE0);
1004 cmd->resp[1] = readl(base + MMCIRESPONSE1);
1005 cmd->resp[2] = readl(base + MMCIRESPONSE2);
1006 cmd->resp[3] = readl(base + MMCIRESPONSE3);
1da177e4
LT		 1007 }
1008
024629c6 1009 if ((!sbc && !cmd->data) || cmd->error) {
3b6e3c73
UH		 1010 if (host->data) {
1011 /* Terminate the DMA transfer */
653a761e 1012 if (dma_inprogress(host)) {
3b6e3c73 1013 mmci_dma_data_error(host);
653a761e
UH		 1014 mmci_dma_unmap(host, host->data);
1015 }
e47c222b 1016 mmci_stop_data(host);
3b6e3c73 1017 }
024629c6
UH		 1018 mmci_request_end(host, host->mrq);
1019 } else if (sbc) {
1020 mmci_start_command(host, host->mrq->cmd, 0);
1da177e4
LT		 1021 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
1022 mmci_start_data(host, cmd->data);
1023 }
1024}
1025
9c34b73d
SK		 1026static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain)
1027{
1028 return remain - (readl(host->base + MMCIFIFOCNT) << 2);
1029}
1030
1031static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r)
1032{
1033 /*
1034 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses
1035 * from the fifo range should be used
1036 */
1037 if (status & MCI_RXFIFOHALFFULL)
1038 return host->variant->fifohalfsize;
1039 else if (status & MCI_RXDATAAVLBL)
1040 return 4;
1041
1042 return 0;
1043}
1044
1da177e4
LT		 1045static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
1046{
1047 void __iomem *base = host->base;
1048 char *ptr = buffer;
9c34b73d 1049 u32 status = readl(host->base + MMCISTATUS);
26eed9a5 1050 int host_remain = host->size;
1da177e4
LT		 1051
1052 do {
9c34b73d 1053 int count = host->get_rx_fifocnt(host, status, host_remain);
1da177e4
LT		 1054
1055 if (count > remain)
1056 count = remain;
1057
1058 if (count <= 0)
1059 break;
1060
393e5e24
UH		 1061 /*
1062 * SDIO especially may want to send something that is
1063 * not divisible by 4 (as opposed to card sectors
1064 * etc). Therefore make sure to always read the last bytes
1065 * while only doing full 32-bit reads towards the FIFO.
1066 */
1067 if (unlikely(count & 0x3)) {
1068 if (count < 4) {
1069 unsigned char buf[4];
4b85da08 1070 ioread32_rep(base + MMCIFIFO, buf, 1);
393e5e24
UH		 1071 memcpy(ptr, buf, count);
1072 } else {
4b85da08 1073 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
393e5e24
UH		 1074 count &= ~0x3;
1075 }
1076 } else {
4b85da08 1077 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
393e5e24 1078 }
1da177e4
LT		 1079
1080 ptr += count;
1081 remain -= count;
26eed9a5 1082 host_remain -= count;
1da177e4
LT		 1083
1084 if (remain == 0)
1085 break;
1086
1087 status = readl(base + MMCISTATUS);
1088 } while (status & MCI_RXDATAAVLBL);
1089
1090 return ptr - buffer;
1091}
1092
1093static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
1094{
8301bb68 1095 struct variant_data *variant = host->variant;
1da177e4
LT		 1096 void __iomem *base = host->base;
1097 char *ptr = buffer;
1098
1099 do {
1100 unsigned int count, maxcnt;
1101
8301bb68
RV		 1102 maxcnt = status & MCI_TXFIFOEMPTY ?
1103 variant->fifosize : variant->fifohalfsize;
1da177e4
LT		 1104 count = min(remain, maxcnt);
1105
34177802
LW		 1106 /*
1107 * SDIO especially may want to send something that is
1108 * not divisible by 4 (as opposed to card sectors
1109 * etc), and the FIFO only accept full 32-bit writes.
1110 * So compensate by adding +3 on the count, a single
1111 * byte become a 32bit write, 7 bytes will be two
1112 * 32bit writes etc.
1113 */
4b85da08 1114 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2);
1da177e4
LT		 1115
1116 ptr += count;
1117 remain -= count;
1118
1119 if (remain == 0)
1120 break;
1121
1122 status = readl(base + MMCISTATUS);
1123 } while (status & MCI_TXFIFOHALFEMPTY);
1124
1125 return ptr - buffer;
1126}
1127
1128/*
1129 * PIO data transfer IRQ handler.
1130 */
7d12e780 1131static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
1da177e4
LT		 1132{
1133 struct mmci_host *host = dev_id;
4ce1d6cb 1134 struct sg_mapping_iter *sg_miter = &host->sg_miter;
8301bb68 1135 struct variant_data *variant = host->variant;
1da177e4 1136 void __iomem *base = host->base;
4ce1d6cb 1137 unsigned long flags;
1da177e4
LT		 1138 u32 status;
1139
1140 status = readl(base + MMCISTATUS);
1141
64de0289 1142 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
1da177e4 1143
4ce1d6cb
RV		 1144 local_irq_save(flags);
1145
1da177e4 1146 do {
1da177e4
LT		 1147 unsigned int remain, len;
1148 char *buffer;
1149
1150 /*
1151 * For write, we only need to test the half-empty flag
1152 * here - if the FIFO is completely empty, then by
1153 * definition it is more than half empty.
1154 *
1155 * For read, check for data available.
1156 */
1157 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
1158 break;
1159
4ce1d6cb
RV		 1160 if (!sg_miter_next(sg_miter))
1161 break;
1162
1163 buffer = sg_miter->addr;
1164 remain = sg_miter->length;
1da177e4
LT		 1165
1166 len = 0;
1167 if (status & MCI_RXACTIVE)
1168 len = mmci_pio_read(host, buffer, remain);
1169 if (status & MCI_TXACTIVE)
1170 len = mmci_pio_write(host, buffer, remain, status);
1171
4ce1d6cb 1172 sg_miter->consumed = len;
1da177e4 1173
1da177e4
LT		 1174 host->size -= len;
1175 remain -= len;
1176
1177 if (remain)
1178 break;
1179
1da177e4
LT		 1180 status = readl(base + MMCISTATUS);
1181 } while (1);
1182
4ce1d6cb
RV		 1183 sg_miter_stop(sg_miter);
1184
1185 local_irq_restore(flags);
1186
1da177e4 1187 /*
c4d877c1
RK		 1188 * If we have less than the fifo 'half-full' threshold to transfer,
1189 * trigger a PIO interrupt as soon as any data is available.
1da177e4 1190 */
c4d877c1 1191 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
2686b4b4 1192 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
1da177e4
LT		 1193
1194 /*
1195 * If we run out of data, disable the data IRQs; this
1196 * prevents a race where the FIFO becomes empty before
1197 * the chip itself has disabled the data path, and
1198 * stops us racing with our data end IRQ.
1199 */
1200 if (host->size == 0) {
2686b4b4 1201 mmci_set_mask1(host, 0);
1da177e4
LT		 1202 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
1203 }
1204
1205 return IRQ_HANDLED;
1206}
1207
1208/*
1209 * Handle completion of command and data transfers.
1210 */
7d12e780 1211static irqreturn_t mmci_irq(int irq, void *dev_id)
1da177e4
LT		 1212{
1213 struct mmci_host *host = dev_id;
1214 u32 status;
1215 int ret = 0;
1216
1217 spin_lock(&host->lock);
1218
1219 do {
1da177e4 1220 status = readl(host->base + MMCISTATUS);
2686b4b4
LW		 1221
1222 if (host->singleirq) {
1223 if (status & readl(host->base + MMCIMASK1))
1224 mmci_pio_irq(irq, dev_id);
1225
1226 status &= ~MCI_IRQ1MASK;
1227 }
1228
8d94b54d
UH		 1229 /*
1230 * We intentionally clear the MCI_ST_CARDBUSY IRQ here (if it's
1231 * enabled) since the HW seems to be triggering the IRQ on both
1232 * edges while monitoring DAT0 for busy completion.
1233 */
1da177e4
LT		 1234 status &= readl(host->base + MMCIMASK0);
1235 writel(status, host->base + MMCICLEAR);
1236
64de0289 1237 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
1da177e4 1238
ad82bfea 1239 mmci_cmd_irq(host, host->cmd, status);
1cb9da50 1240 mmci_data_irq(host, host->data, status);
1da177e4 1241
8d94b54d
UH		 1242 /* Don't poll for busy completion in irq context. */
1243 if (host->busy_status)
1244 status &= ~MCI_ST_CARDBUSY;
1245
1da177e4
LT		 1246 ret = 1;
1247 } while (status);
1248
1249 spin_unlock(&host->lock);
1250
1251 return IRQ_RETVAL(ret);
1252}
1253
1254static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1255{
1256 struct mmci_host *host = mmc_priv(mmc);
9e943021 1257 unsigned long flags;
1da177e4
LT		 1258
1259 WARN_ON(host->mrq != NULL);
1260
653a761e
UH		 1261 mrq->cmd->error = mmci_validate_data(host, mrq->data);
1262 if (mrq->cmd->error) {
255d01af
PO		 1263 mmc_request_done(mmc, mrq);
1264 return;
1265 }
1266
1c3be369
RK		 1267 pm_runtime_get_sync(mmc_dev(mmc));
1268
9e943021 1269 spin_lock_irqsave(&host->lock, flags);
1da177e4
LT		 1270
1271 host->mrq = mrq;
1272
58c7ccbf
PF		 1273 if (mrq->data)
1274 mmci_get_next_data(host, mrq->data);
1275
1da177e4
LT		 1276 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
1277 mmci_start_data(host, mrq->data);
1278
024629c6
UH		 1279 if (mrq->sbc)
1280 mmci_start_command(host, mrq->sbc, 0);
1281 else
1282 mmci_start_command(host, mrq->cmd, 0);
1da177e4 1283
9e943021 1284 spin_unlock_irqrestore(&host->lock, flags);
1da177e4
LT		 1285}
1286
1287static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1288{
1289 struct mmci_host *host = mmc_priv(mmc);
7d72a1d4 1290 struct variant_data *variant = host->variant;
a6a6464a
LW		 1291 u32 pwr = 0;
1292 unsigned long flags;
db90f91f 1293 int ret;
1da177e4 1294
2cd976c4
UH		 1295 pm_runtime_get_sync(mmc_dev(mmc));
1296
bc521818
UH		 1297 if (host->plat->ios_handler &&
1298 host->plat->ios_handler(mmc_dev(mmc), ios))
1299 dev_err(mmc_dev(mmc), "platform ios_handler failed\n");
1300
1da177e4
LT		 1301 switch (ios->power_mode) {
1302 case MMC_POWER_OFF:
599c1d5c
UH		 1303 if (!IS_ERR(mmc->supply.vmmc))
1304 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
237fb5e6 1305
7c0136ef 1306 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
237fb5e6 1307 regulator_disable(mmc->supply.vqmmc);
7c0136ef
UH		 1308 host->vqmmc_enabled = false;
1309 }
237fb5e6 1310
1da177e4
LT		 1311 break;
1312 case MMC_POWER_UP:
599c1d5c
UH		 1313 if (!IS_ERR(mmc->supply.vmmc))
1314 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1315
7d72a1d4
UH		 1316 /*
1317 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
1318 * and instead uses MCI_PWR_ON so apply whatever value is
1319 * configured in the variant data.
1320 */
1321 pwr |= variant->pwrreg_powerup;
1322
1323 break;
1da177e4 1324 case MMC_POWER_ON:
7c0136ef 1325 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
db90f91f
LJ		 1326 ret = regulator_enable(mmc->supply.vqmmc);
1327 if (ret < 0)
1328 dev_err(mmc_dev(mmc),
1329 "failed to enable vqmmc regulator\n");
7c0136ef
UH		 1330 else
1331 host->vqmmc_enabled = true;
db90f91f 1332 }
237fb5e6 1333
1da177e4
LT		 1334 pwr |= MCI_PWR_ON;
1335 break;
1336 }
1337
4d1a3a0d
UH		 1338 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
1339 /*
1340 * The ST Micro variant has some additional bits
1341 * indicating signal direction for the signals in
1342 * the SD/MMC bus and feedback-clock usage.
1343 */
4593df29 1344 pwr |= host->pwr_reg_add;
4d1a3a0d
UH		 1345
1346 if (ios->bus_width == MMC_BUS_WIDTH_4)
1347 pwr &= ~MCI_ST_DATA74DIREN;
1348 else if (ios->bus_width == MMC_BUS_WIDTH_1)
1349 pwr &= (~MCI_ST_DATA74DIREN &
1350 ~MCI_ST_DATA31DIREN &
1351 ~MCI_ST_DATA2DIREN);
1352 }
1353
cc30d60e 1354 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
f17a1f06 1355 if (host->hw_designer != AMBA_VENDOR_ST)
cc30d60e
LW		 1356 pwr |= MCI_ROD;
1357 else {
1358 /*
1359 * The ST Micro variant use the ROD bit for something
1360 * else and only has OD (Open Drain).
1361 */
1362 pwr |= MCI_OD;
1363 }
1364 }
1da177e4 1365
f4670dae
UH		 1366 /*
1367 * If clock = 0 and the variant requires the MMCIPOWER to be used for
1368 * gating the clock, the MCI_PWR_ON bit is cleared.
1369 */
1370 if (!ios->clock && variant->pwrreg_clkgate)
1371 pwr &= ~MCI_PWR_ON;
1372
3f4e6f7b
SK		 1373 if (host->variant->explicit_mclk_control &&
1374 ios->clock != host->clock_cache) {
1375 ret = clk_set_rate(host->clk, ios->clock);
1376 if (ret < 0)
1377 dev_err(mmc_dev(host->mmc),
1378 "Error setting clock rate (%d)\n", ret);
1379 else
1380 host->mclk = clk_get_rate(host->clk);
1381 }
1382 host->clock_cache = ios->clock;
1383
a6a6464a
LW		 1384 spin_lock_irqsave(&host->lock, flags);
1385
1386 mmci_set_clkreg(host, ios->clock);
7437cfa5 1387 mmci_write_pwrreg(host, pwr);
f829c042 1388 mmci_reg_delay(host);
a6a6464a
LW		 1389
1390 spin_unlock_irqrestore(&host->lock, flags);
2cd976c4 1391
2cd976c4
UH		 1392 pm_runtime_mark_last_busy(mmc_dev(mmc));
1393 pm_runtime_put_autosuspend(mmc_dev(mmc));
1da177e4
LT		 1394}
1395
89001446
RK		 1396static int mmci_get_cd(struct mmc_host *mmc)
1397{
1398 struct mmci_host *host = mmc_priv(mmc);
29719445 1399 struct mmci_platform_data *plat = host->plat;
d2762090 1400 unsigned int status = mmc_gpio_get_cd(mmc);
89001446 1401
d2762090 1402 if (status == -ENOSYS) {
4b8caec0
RV		 1403 if (!plat->status)
1404 return 1; /* Assume always present */
1405
29719445 1406 status = plat->status(mmc_dev(host->mmc));
d2762090 1407 }
74bc8093 1408 return status;
89001446
RK		 1409}
1410
0f3ed7f7
UH		 1411static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1412{
1413 int ret = 0;
1414
1415 if (!IS_ERR(mmc->supply.vqmmc)) {
1416
1417 pm_runtime_get_sync(mmc_dev(mmc));
1418
1419 switch (ios->signal_voltage) {
1420 case MMC_SIGNAL_VOLTAGE_330:
1421 ret = regulator_set_voltage(mmc->supply.vqmmc,
1422 2700000, 3600000);
1423 break;
1424 case MMC_SIGNAL_VOLTAGE_180:
1425 ret = regulator_set_voltage(mmc->supply.vqmmc,
1426 1700000, 1950000);
1427 break;
1428 case MMC_SIGNAL_VOLTAGE_120:
1429 ret = regulator_set_voltage(mmc->supply.vqmmc,
1430 1100000, 1300000);
1431 break;
1432 }
1433
1434 if (ret)
1435 dev_warn(mmc_dev(mmc), "Voltage switch failed\n");
1436
1437 pm_runtime_mark_last_busy(mmc_dev(mmc));
1438 pm_runtime_put_autosuspend(mmc_dev(mmc));
1439 }
1440
1441 return ret;
1442}
1443
01259620 1444static struct mmc_host_ops mmci_ops = {
1da177e4 1445 .request = mmci_request,
58c7ccbf
PF		 1446 .pre_req = mmci_pre_request,
1447 .post_req = mmci_post_request,
1da177e4 1448 .set_ios = mmci_set_ios,
d2762090 1449 .get_ro = mmc_gpio_get_ro,
89001446 1450 .get_cd = mmci_get_cd,
0f3ed7f7 1451 .start_signal_voltage_switch = mmci_sig_volt_switch,
1da177e4
LT		 1452};
1453
4593df29 1454static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc)
000bc9d5 1455{
4593df29
UH		 1456 struct mmci_host *host = mmc_priv(mmc);
1457 int ret = mmc_of_parse(mmc);
1458
1459 if (ret)
1460 return ret;
1461
ae94cafe 1462 if (of_get_property(np, "st,sig-dir-dat0", NULL))
4593df29 1463 host->pwr_reg_add |= MCI_ST_DATA0DIREN;
ae94cafe 1464 if (of_get_property(np, "st,sig-dir-dat2", NULL))
4593df29 1465 host->pwr_reg_add |= MCI_ST_DATA2DIREN;
ae94cafe 1466 if (of_get_property(np, "st,sig-dir-dat31", NULL))
4593df29 1467 host->pwr_reg_add |= MCI_ST_DATA31DIREN;
ae94cafe 1468 if (of_get_property(np, "st,sig-dir-dat74", NULL))
4593df29 1469 host->pwr_reg_add |= MCI_ST_DATA74DIREN;
ae94cafe 1470 if (of_get_property(np, "st,sig-dir-cmd", NULL))
4593df29 1471 host->pwr_reg_add |= MCI_ST_CMDDIREN;
1a7e99c1 1472 if (of_get_property(np, "st,sig-pin-fbclk", NULL))
4593df29 1473 host->pwr_reg_add |= MCI_ST_FBCLKEN;
000bc9d5
LJ		 1474
1475 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
78f87df2 1476 mmc->caps |= MMC_CAP_MMC_HIGHSPEED;
000bc9d5 1477 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
78f87df2 1478 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
000bc9d5 1479
78f87df2 1480 return 0;
c0a120a4 1481}
000bc9d5 1482
c3be1efd 1483static int mmci_probe(struct amba_device *dev,
aa25afad 1484 const struct amba_id *id)
1da177e4 1485{
6ef297f8 1486 struct mmci_platform_data *plat = dev->dev.platform_data;
000bc9d5 1487 struct device_node *np = dev->dev.of_node;
4956e109 1488 struct variant_data *variant = id->data;
1da177e4
LT		 1489 struct mmci_host *host;
1490 struct mmc_host *mmc;
1491 int ret;
1492
000bc9d5
LJ		 1493 /* Must have platform data or Device Tree. */
1494 if (!plat && !np) {
1495 dev_err(&dev->dev, "No plat data or DT found\n");
1496 return -EINVAL;
1da177e4
LT		 1497 }
1498
b9b52918
LJ		 1499 if (!plat) {
1500 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL);
1501 if (!plat)
1502 return -ENOMEM;
1503 }
1504
1da177e4 1505 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
ef289982
UH		 1506 if (!mmc)
1507 return -ENOMEM;
1da177e4 1508
78f87df2
UH		 1509 ret = mmci_of_parse(np, mmc);
1510 if (ret)
1511 goto host_free;
1512
1da177e4 1513 host = mmc_priv(mmc);
4ea580f1 1514 host->mmc = mmc;
012b7d33
RK		 1515
1516 host->hw_designer = amba_manf(dev);
1517 host->hw_revision = amba_rev(dev);
64de0289
LW		 1518 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1519 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
012b7d33 1520
665ba56f 1521 host->clk = devm_clk_get(&dev->dev, NULL);
1da177e4
LT		 1522 if (IS_ERR(host->clk)) {
1523 ret = PTR_ERR(host->clk);
1da177e4
LT		 1524 goto host_free;
1525 }
1526
ac940938 1527 ret = clk_prepare_enable(host->clk);
1da177e4 1528 if (ret)
665ba56f 1529 goto host_free;
1da177e4 1530
9c34b73d
SK		 1531 if (variant->qcom_fifo)
1532 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt;
1533 else
1534 host->get_rx_fifocnt = mmci_get_rx_fifocnt;
1535
1da177e4 1536 host->plat = plat;
4956e109 1537 host->variant = variant;
1da177e4 1538 host->mclk = clk_get_rate(host->clk);
c8df9a53
LW		 1539 /*
1540 * According to the spec, mclk is max 100 MHz,
1541 * so we try to adjust the clock down to this,
1542 * (if possible).
1543 */
dc6500bf
SK		 1544 if (host->mclk > variant->f_max) {
1545 ret = clk_set_rate(host->clk, variant->f_max);
c8df9a53
LW		 1546 if (ret < 0)
1547 goto clk_disable;
1548 host->mclk = clk_get_rate(host->clk);
64de0289
LW		 1549 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1550 host->mclk);
c8df9a53 1551 }
ef289982 1552
c8ebae37 1553 host->phybase = dev->res.start;
ef289982
UH		 1554 host->base = devm_ioremap_resource(&dev->dev, &dev->res);
1555 if (IS_ERR(host->base)) {
1556 ret = PTR_ERR(host->base);
1da177e4
LT		 1557 goto clk_disable;
1558 }
1559
7f294e49
LW		 1560 /*
1561 * The ARM and ST versions of the block have slightly different
1562 * clock divider equations which means that the minimum divider
1563 * differs too.
3f4e6f7b 1564 * on Qualcomm like controllers get the nearest minimum clock to 100Khz
7f294e49
LW		 1565 */
1566 if (variant->st_clkdiv)
1567 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
3f4e6f7b
SK		 1568 else if (variant->explicit_mclk_control)
1569 mmc->f_min = clk_round_rate(host->clk, 100000);
7f294e49
LW		 1570 else
1571 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
808d97cc 1572 /*
78f87df2
UH		 1573 * If no maximum operating frequency is supplied, fall back to use
1574 * the module parameter, which has a (low) default value in case it
1575 * is not specified. Either value must not exceed the clock rate into
5080a08d 1576 * the block, of course.
808d97cc 1577 */
78f87df2 1578 if (mmc->f_max)
3f4e6f7b
SK		 1579 mmc->f_max = variant->explicit_mclk_control ?
1580 min(variant->f_max, mmc->f_max) :
1581 min(host->mclk, mmc->f_max);
808d97cc 1582 else
3f4e6f7b
SK		 1583 mmc->f_max = variant->explicit_mclk_control ?
1584 fmax : min(host->mclk, fmax);
1585
1586
64de0289
LW		 1587 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1588
599c1d5c
UH		 1589 /* Get regulators and the supported OCR mask */
1590 mmc_regulator_get_supply(mmc);
1591 if (!mmc->ocr_avail)
34e84f39 1592 mmc->ocr_avail = plat->ocr_mask;
599c1d5c
UH		 1593 else if (plat->ocr_mask)
1594 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1595
78f87df2 1596 /* DT takes precedence over platform data. */
78f87df2
UH		 1597 if (!np) {
1598 if (!plat->cd_invert)
1599 mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
1600 mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1601 }
1da177e4 1602
9dd8a8b8
UH		 1603 /* We support these capabilities. */
1604 mmc->caps |= MMC_CAP_CMD23;
1605
8d94b54d
UH		 1606 if (variant->busy_detect) {
1607 mmci_ops.card_busy = mmci_card_busy;
1608 mmci_write_datactrlreg(host, MCI_ST_DPSM_BUSYMODE);
1609 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1610 mmc->max_busy_timeout = 0;
1611 }
1612
1613 mmc->ops = &mmci_ops;
1614
70be208f 1615 /* We support these PM capabilities. */
78f87df2 1616 mmc->pm_caps |= MMC_PM_KEEP_POWER;
70be208f 1617
1da177e4
LT		 1618 /*
1619 * We can do SGIO
1620 */
a36274e0 1621 mmc->max_segs = NR_SG;
1da177e4
LT		 1622
1623 /*
08458ef6
RV		 1624 * Since only a certain number of bits are valid in the data length
1625 * register, we must ensure that we don't exceed 2^num-1 bytes in a
1626 * single request.
1da177e4 1627 */
08458ef6 1628 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
1da177e4
LT		 1629
1630 /*
1631 * Set the maximum segment size. Since we aren't doing DMA
1632 * (yet) we are only limited by the data length register.
1633 */
55db890a 1634 mmc->max_seg_size = mmc->max_req_size;
1da177e4 1635
fe4a3c7a
PO		 1636 /*
1637 * Block size can be up to 2048 bytes, but must be a power of two.
1638 */
8f7f6b7e 1639 mmc->max_blk_size = 1 << 11;
fe4a3c7a 1640
55db890a 1641 /*
8f7f6b7e
WD		 1642 * Limit the number of blocks transferred so that we don't overflow
1643 * the maximum request size.
55db890a 1644 */
8f7f6b7e 1645 mmc->max_blk_count = mmc->max_req_size >> 11;
55db890a 1646
1da177e4
LT		 1647 spin_lock_init(&host->lock);
1648
1649 writel(0, host->base + MMCIMASK0);
1650 writel(0, host->base + MMCIMASK1);
1651 writel(0xfff, host->base + MMCICLEAR);
1652
78f87df2
UH		 1653 /* If DT, cd/wp gpios must be supplied through it. */
1654 if (!np && gpio_is_valid(plat->gpio_cd)) {
d2762090
UH		 1655 ret = mmc_gpio_request_cd(mmc, plat->gpio_cd, 0);
1656 if (ret)
ef289982 1657 goto clk_disable;
89001446 1658 }
78f87df2 1659 if (!np && gpio_is_valid(plat->gpio_wp)) {
d2762090
UH		 1660 ret = mmc_gpio_request_ro(mmc, plat->gpio_wp);
1661 if (ret)
ef289982 1662 goto clk_disable;
89001446
RK		 1663 }
1664
ef289982
UH		 1665 ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED,
1666 DRIVER_NAME " (cmd)", host);
1da177e4 1667 if (ret)
ef289982 1668 goto clk_disable;
1da177e4 1669
dfb85185 1670 if (!dev->irq[1])
2686b4b4
LW		 1671 host->singleirq = true;
1672 else {
ef289982
UH		 1673 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq,
1674 IRQF_SHARED, DRIVER_NAME " (pio)", host);
2686b4b4 1675 if (ret)
ef289982 1676 goto clk_disable;
2686b4b4 1677 }
1da177e4 1678
8cb28155 1679 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1da177e4
LT		 1680
1681 amba_set_drvdata(dev, mmc);
1682
c8ebae37
RK		 1683 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
1684 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
1685 amba_rev(dev), (unsigned long long)dev->res.start,
1686 dev->irq[0], dev->irq[1]);
1687
1688 mmci_dma_setup(host);
1da177e4 1689
2cd976c4
UH		 1690 pm_runtime_set_autosuspend_delay(&dev->dev, 50);
1691 pm_runtime_use_autosuspend(&dev->dev);
1c3be369
RK		 1692 pm_runtime_put(&dev->dev);
1693
8c11a94d
RK		 1694 mmc_add_host(mmc);
1695
1da177e4
LT		 1696 return 0;
1697
1da177e4 1698 clk_disable:
ac940938 1699 clk_disable_unprepare(host->clk);
1da177e4
LT		 1700 host_free:
1701 mmc_free_host(mmc);
1da177e4
LT		 1702 return ret;
1703}
1704
6e0ee714 1705static int mmci_remove(struct amba_device *dev)
1da177e4
LT		 1706{
1707 struct mmc_host *mmc = amba_get_drvdata(dev);
1708
1da177e4
LT		 1709 if (mmc) {
1710 struct mmci_host *host = mmc_priv(mmc);
1711
1c3be369
RK		 1712 /*
1713 * Undo pm_runtime_put() in probe. We use the _sync
1714 * version here so that we can access the primecell.
1715 */
1716 pm_runtime_get_sync(&dev->dev);
1717
1da177e4
LT		 1718 mmc_remove_host(mmc);
1719
1720 writel(0, host->base + MMCIMASK0);
1721 writel(0, host->base + MMCIMASK1);
1722
1723 writel(0, host->base + MMCICOMMAND);
1724 writel(0, host->base + MMCIDATACTRL);
1725
c8ebae37 1726 mmci_dma_release(host);
ac940938 1727 clk_disable_unprepare(host->clk);
1da177e4 1728 mmc_free_host(mmc);
1da177e4
LT		 1729 }
1730
1731 return 0;
1732}
1733
571dce4f 1734#ifdef CONFIG_PM
1ff44433
UH		 1735static void mmci_save(struct mmci_host *host)
1736{
1737 unsigned long flags;
1738
42dcc89a 1739 spin_lock_irqsave(&host->lock, flags);
1ff44433 1740
42dcc89a
UH		 1741 writel(0, host->base + MMCIMASK0);
1742 if (host->variant->pwrreg_nopower) {
1ff44433
UH		 1743 writel(0, host->base + MMCIDATACTRL);
1744 writel(0, host->base + MMCIPOWER);
1745 writel(0, host->base + MMCICLOCK);
1ff44433 1746 }
42dcc89a 1747 mmci_reg_delay(host);
1ff44433 1748
42dcc89a 1749 spin_unlock_irqrestore(&host->lock, flags);
1ff44433
UH		 1750}
1751
1752static void mmci_restore(struct mmci_host *host)
1753{
1754 unsigned long flags;
1755
42dcc89a 1756 spin_lock_irqsave(&host->lock, flags);
1ff44433 1757
42dcc89a 1758 if (host->variant->pwrreg_nopower) {
1ff44433
UH		 1759 writel(host->clk_reg, host->base + MMCICLOCK);
1760 writel(host->datactrl_reg, host->base + MMCIDATACTRL);
1761 writel(host->pwr_reg, host->base + MMCIPOWER);
1ff44433 1762 }
42dcc89a
UH		 1763 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1764 mmci_reg_delay(host);
1765
1766 spin_unlock_irqrestore(&host->lock, flags);
1ff44433
UH		 1767}
1768
8259293a
UH		 1769static int mmci_runtime_suspend(struct device *dev)
1770{
1771 struct amba_device *adev = to_amba_device(dev);
1772 struct mmc_host *mmc = amba_get_drvdata(adev);
1773
1774 if (mmc) {
1775 struct mmci_host *host = mmc_priv(mmc);
e36bd9c6 1776 pinctrl_pm_select_sleep_state(dev);
1ff44433 1777 mmci_save(host);
8259293a
UH		 1778 clk_disable_unprepare(host->clk);
1779 }
1780
1781 return 0;
1782}
1783
1784static int mmci_runtime_resume(struct device *dev)
1785{
1786 struct amba_device *adev = to_amba_device(dev);
1787 struct mmc_host *mmc = amba_get_drvdata(adev);
1788
1789 if (mmc) {
1790 struct mmci_host *host = mmc_priv(mmc);
1791 clk_prepare_enable(host->clk);
1ff44433 1792 mmci_restore(host);
e36bd9c6 1793 pinctrl_pm_select_default_state(dev);
8259293a
UH		 1794 }
1795
1796 return 0;
1797}
1798#endif
1799
48fa7003 1800static const struct dev_pm_ops mmci_dev_pm_ops = {
f3737fa3
UH		 1801 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1802 pm_runtime_force_resume)
571dce4f 1803 SET_PM_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL)
48fa7003
UH		 1804};
1805
1da177e4
LT		 1806static struct amba_id mmci_ids[] = {
1807 {
1808 .id = 0x00041180,
768fbc18 1809 .mask = 0xff0fffff,
4956e109 1810 .data = &variant_arm,
1da177e4 1811 },
768fbc18
PM		 1812 {
1813 .id = 0x01041180,
1814 .mask = 0xff0fffff,
1815 .data = &variant_arm_extended_fifo,
1816 },
3a37298a
PM		 1817 {
1818 .id = 0x02041180,
1819 .mask = 0xff0fffff,
1820 .data = &variant_arm_extended_fifo_hwfc,
1821 },
1da177e4
LT		 1822 {
1823 .id = 0x00041181,
1824 .mask = 0x000fffff,
4956e109 1825 .data = &variant_arm,
1da177e4 1826 },
cc30d60e
LW		 1827 /* ST Micro variants */
1828 {
1829 .id = 0x00180180,
1830 .mask = 0x00ffffff,
4956e109 1831 .data = &variant_u300,
cc30d60e 1832 },
34fd4213
LW		 1833 {
1834 .id = 0x10180180,
1835 .mask = 0xf0ffffff,
1836 .data = &variant_nomadik,
1837 },
cc30d60e
LW		 1838 {
1839 .id = 0x00280180,
1840 .mask = 0x00ffffff,
4956e109
RV		 1841 .data = &variant_u300,
1842 },
1843 {
1844 .id = 0x00480180,
1784b157 1845 .mask = 0xf0ffffff,
4956e109 1846 .data = &variant_ux500,
cc30d60e 1847 },
1784b157
PL		 1848 {
1849 .id = 0x10480180,
1850 .mask = 0xf0ffffff,
1851 .data = &variant_ux500v2,
1852 },
55b604ae
SK		 1853 /* Qualcomm variants */
1854 {
1855 .id = 0x00051180,
1856 .mask = 0x000fffff,
1857 .data = &variant_qcom,
1858 },
1da177e4
LT		 1859 { 0, 0 },
1860};
1861
9f99835f
DM		 1862MODULE_DEVICE_TABLE(amba, mmci_ids);
1863
1da177e4
LT		 1864static struct amba_driver mmci_driver = {
1865 .drv = {
1866 .name = DRIVER_NAME,
48fa7003 1867 .pm = &mmci_dev_pm_ops,
1da177e4
LT		 1868 },
1869 .probe = mmci_probe,
0433c143 1870 .remove = mmci_remove,
1da177e4
LT		 1871 .id_table = mmci_ids,
1872};
1873
9e5ed094 1874module_amba_driver(mmci_driver);
1da177e4 1875
1da177e4
LT		 1876module_param(fmax, uint, 0444);
1877
1878MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
1879MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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