Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. | |
c8ebae37 | 5 | * Copyright (C) 2010 ST-Ericsson SA |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/interrupt.h> | |
613b152c | 17 | #include <linux/kernel.h> |
1da177e4 LT |
18 | #include <linux/delay.h> |
19 | #include <linux/err.h> | |
20 | #include <linux/highmem.h> | |
019a5f56 | 21 | #include <linux/log2.h> |
1da177e4 | 22 | #include <linux/mmc/host.h> |
34177802 | 23 | #include <linux/mmc/card.h> |
a62c80e5 | 24 | #include <linux/amba/bus.h> |
f8ce2547 | 25 | #include <linux/clk.h> |
bd6dee6f | 26 | #include <linux/scatterlist.h> |
89001446 | 27 | #include <linux/gpio.h> |
34e84f39 | 28 | #include <linux/regulator/consumer.h> |
c8ebae37 RK |
29 | #include <linux/dmaengine.h> |
30 | #include <linux/dma-mapping.h> | |
31 | #include <linux/amba/mmci.h> | |
1c3be369 | 32 | #include <linux/pm_runtime.h> |
1da177e4 | 33 | |
7b09cdac | 34 | #include <asm/div64.h> |
1da177e4 | 35 | #include <asm/io.h> |
c6b8fdad | 36 | #include <asm/sizes.h> |
1da177e4 LT |
37 | |
38 | #include "mmci.h" | |
39 | ||
40 | #define DRIVER_NAME "mmci-pl18x" | |
41 | ||
1da177e4 LT |
42 | static unsigned int fmax = 515633; |
43 | ||
4956e109 RV |
44 | /** |
45 | * struct variant_data - MMCI variant-specific quirks | |
46 | * @clkreg: default value for MCICLOCK register | |
4380c14f | 47 | * @clkreg_enable: enable value for MMCICLOCK register |
08458ef6 | 48 | * @datalength_bits: number of bits in the MMCIDATALENGTH register |
8301bb68 RV |
49 | * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY |
50 | * is asserted (likewise for RX) | |
51 | * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY | |
52 | * is asserted (likewise for RX) | |
34177802 | 53 | * @sdio: variant supports SDIO |
b70a67f9 | 54 | * @st_clkdiv: true if using a ST-specific clock divider algorithm |
1784b157 | 55 | * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register |
4956e109 RV |
56 | */ |
57 | struct variant_data { | |
58 | unsigned int clkreg; | |
4380c14f | 59 | unsigned int clkreg_enable; |
08458ef6 | 60 | unsigned int datalength_bits; |
8301bb68 RV |
61 | unsigned int fifosize; |
62 | unsigned int fifohalfsize; | |
34177802 | 63 | bool sdio; |
b70a67f9 | 64 | bool st_clkdiv; |
1784b157 | 65 | bool blksz_datactrl16; |
4956e109 RV |
66 | }; |
67 | ||
68 | static struct variant_data variant_arm = { | |
8301bb68 RV |
69 | .fifosize = 16 * 4, |
70 | .fifohalfsize = 8 * 4, | |
08458ef6 | 71 | .datalength_bits = 16, |
4956e109 RV |
72 | }; |
73 | ||
768fbc18 PM |
74 | static struct variant_data variant_arm_extended_fifo = { |
75 | .fifosize = 128 * 4, | |
76 | .fifohalfsize = 64 * 4, | |
77 | .datalength_bits = 16, | |
78 | }; | |
79 | ||
4956e109 | 80 | static struct variant_data variant_u300 = { |
8301bb68 RV |
81 | .fifosize = 16 * 4, |
82 | .fifohalfsize = 8 * 4, | |
49ac215e | 83 | .clkreg_enable = MCI_ST_U300_HWFCEN, |
08458ef6 | 84 | .datalength_bits = 16, |
34177802 | 85 | .sdio = true, |
4956e109 RV |
86 | }; |
87 | ||
88 | static struct variant_data variant_ux500 = { | |
8301bb68 RV |
89 | .fifosize = 30 * 4, |
90 | .fifohalfsize = 8 * 4, | |
4956e109 | 91 | .clkreg = MCI_CLK_ENABLE, |
49ac215e | 92 | .clkreg_enable = MCI_ST_UX500_HWFCEN, |
08458ef6 | 93 | .datalength_bits = 24, |
34177802 | 94 | .sdio = true, |
b70a67f9 | 95 | .st_clkdiv = true, |
4956e109 | 96 | }; |
b70a67f9 | 97 | |
1784b157 PL |
98 | static struct variant_data variant_ux500v2 = { |
99 | .fifosize = 30 * 4, | |
100 | .fifohalfsize = 8 * 4, | |
101 | .clkreg = MCI_CLK_ENABLE, | |
102 | .clkreg_enable = MCI_ST_UX500_HWFCEN, | |
103 | .datalength_bits = 24, | |
104 | .sdio = true, | |
105 | .st_clkdiv = true, | |
106 | .blksz_datactrl16 = true, | |
107 | }; | |
108 | ||
a6a6464a LW |
109 | /* |
110 | * This must be called with host->lock held | |
111 | */ | |
112 | static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) | |
113 | { | |
4956e109 RV |
114 | struct variant_data *variant = host->variant; |
115 | u32 clk = variant->clkreg; | |
a6a6464a LW |
116 | |
117 | if (desired) { | |
118 | if (desired >= host->mclk) { | |
991a86e1 | 119 | clk = MCI_CLK_BYPASS; |
399bc486 LW |
120 | if (variant->st_clkdiv) |
121 | clk |= MCI_ST_UX500_NEG_EDGE; | |
a6a6464a | 122 | host->cclk = host->mclk; |
b70a67f9 LW |
123 | } else if (variant->st_clkdiv) { |
124 | /* | |
125 | * DB8500 TRM says f = mclk / (clkdiv + 2) | |
126 | * => clkdiv = (mclk / f) - 2 | |
127 | * Round the divider up so we don't exceed the max | |
128 | * frequency | |
129 | */ | |
130 | clk = DIV_ROUND_UP(host->mclk, desired) - 2; | |
131 | if (clk >= 256) | |
132 | clk = 255; | |
133 | host->cclk = host->mclk / (clk + 2); | |
a6a6464a | 134 | } else { |
b70a67f9 LW |
135 | /* |
136 | * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) | |
137 | * => clkdiv = mclk / (2 * f) - 1 | |
138 | */ | |
a6a6464a LW |
139 | clk = host->mclk / (2 * desired) - 1; |
140 | if (clk >= 256) | |
141 | clk = 255; | |
142 | host->cclk = host->mclk / (2 * (clk + 1)); | |
143 | } | |
4380c14f RV |
144 | |
145 | clk |= variant->clkreg_enable; | |
a6a6464a LW |
146 | clk |= MCI_CLK_ENABLE; |
147 | /* This hasn't proven to be worthwhile */ | |
148 | /* clk |= MCI_CLK_PWRSAVE; */ | |
149 | } | |
150 | ||
9e6c82cd | 151 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) |
771dc157 LW |
152 | clk |= MCI_4BIT_BUS; |
153 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) | |
154 | clk |= MCI_ST_8BIT_BUS; | |
9e6c82cd | 155 | |
a6a6464a LW |
156 | writel(clk, host->base + MMCICLOCK); |
157 | } | |
158 | ||
1da177e4 LT |
159 | static void |
160 | mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) | |
161 | { | |
162 | writel(0, host->base + MMCICOMMAND); | |
163 | ||
e47c222b RK |
164 | BUG_ON(host->data); |
165 | ||
1da177e4 LT |
166 | host->mrq = NULL; |
167 | host->cmd = NULL; | |
168 | ||
1da177e4 LT |
169 | /* |
170 | * Need to drop the host lock here; mmc_request_done may call | |
171 | * back into the driver... | |
172 | */ | |
173 | spin_unlock(&host->lock); | |
1c3be369 | 174 | pm_runtime_put(mmc_dev(host->mmc)); |
1da177e4 LT |
175 | mmc_request_done(host->mmc, mrq); |
176 | spin_lock(&host->lock); | |
177 | } | |
178 | ||
2686b4b4 LW |
179 | static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) |
180 | { | |
181 | void __iomem *base = host->base; | |
182 | ||
183 | if (host->singleirq) { | |
184 | unsigned int mask0 = readl(base + MMCIMASK0); | |
185 | ||
186 | mask0 &= ~MCI_IRQ1MASK; | |
187 | mask0 |= mask; | |
188 | ||
189 | writel(mask0, base + MMCIMASK0); | |
190 | } | |
191 | ||
192 | writel(mask, base + MMCIMASK1); | |
193 | } | |
194 | ||
1da177e4 LT |
195 | static void mmci_stop_data(struct mmci_host *host) |
196 | { | |
197 | writel(0, host->base + MMCIDATACTRL); | |
2686b4b4 | 198 | mmci_set_mask1(host, 0); |
1da177e4 LT |
199 | host->data = NULL; |
200 | } | |
201 | ||
4ce1d6cb RV |
202 | static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) |
203 | { | |
204 | unsigned int flags = SG_MITER_ATOMIC; | |
205 | ||
206 | if (data->flags & MMC_DATA_READ) | |
207 | flags |= SG_MITER_TO_SG; | |
208 | else | |
209 | flags |= SG_MITER_FROM_SG; | |
210 | ||
211 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); | |
212 | } | |
213 | ||
c8ebae37 RK |
214 | /* |
215 | * All the DMA operation mode stuff goes inside this ifdef. | |
216 | * This assumes that you have a generic DMA device interface, | |
217 | * no custom DMA interfaces are supported. | |
218 | */ | |
219 | #ifdef CONFIG_DMA_ENGINE | |
220 | static void __devinit mmci_dma_setup(struct mmci_host *host) | |
221 | { | |
222 | struct mmci_platform_data *plat = host->plat; | |
223 | const char *rxname, *txname; | |
224 | dma_cap_mask_t mask; | |
225 | ||
226 | if (!plat || !plat->dma_filter) { | |
227 | dev_info(mmc_dev(host->mmc), "no DMA platform data\n"); | |
228 | return; | |
229 | } | |
230 | ||
58c7ccbf PF |
231 | /* initialize pre request cookie */ |
232 | host->next_data.cookie = 1; | |
233 | ||
c8ebae37 RK |
234 | /* Try to acquire a generic DMA engine slave channel */ |
235 | dma_cap_zero(mask); | |
236 | dma_cap_set(DMA_SLAVE, mask); | |
237 | ||
238 | /* | |
239 | * If only an RX channel is specified, the driver will | |
240 | * attempt to use it bidirectionally, however if it is | |
241 | * is specified but cannot be located, DMA will be disabled. | |
242 | */ | |
243 | if (plat->dma_rx_param) { | |
244 | host->dma_rx_channel = dma_request_channel(mask, | |
245 | plat->dma_filter, | |
246 | plat->dma_rx_param); | |
247 | /* E.g if no DMA hardware is present */ | |
248 | if (!host->dma_rx_channel) | |
249 | dev_err(mmc_dev(host->mmc), "no RX DMA channel\n"); | |
250 | } | |
251 | ||
252 | if (plat->dma_tx_param) { | |
253 | host->dma_tx_channel = dma_request_channel(mask, | |
254 | plat->dma_filter, | |
255 | plat->dma_tx_param); | |
256 | if (!host->dma_tx_channel) | |
257 | dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n"); | |
258 | } else { | |
259 | host->dma_tx_channel = host->dma_rx_channel; | |
260 | } | |
261 | ||
262 | if (host->dma_rx_channel) | |
263 | rxname = dma_chan_name(host->dma_rx_channel); | |
264 | else | |
265 | rxname = "none"; | |
266 | ||
267 | if (host->dma_tx_channel) | |
268 | txname = dma_chan_name(host->dma_tx_channel); | |
269 | else | |
270 | txname = "none"; | |
271 | ||
272 | dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", | |
273 | rxname, txname); | |
274 | ||
275 | /* | |
276 | * Limit the maximum segment size in any SG entry according to | |
277 | * the parameters of the DMA engine device. | |
278 | */ | |
279 | if (host->dma_tx_channel) { | |
280 | struct device *dev = host->dma_tx_channel->device->dev; | |
281 | unsigned int max_seg_size = dma_get_max_seg_size(dev); | |
282 | ||
283 | if (max_seg_size < host->mmc->max_seg_size) | |
284 | host->mmc->max_seg_size = max_seg_size; | |
285 | } | |
286 | if (host->dma_rx_channel) { | |
287 | struct device *dev = host->dma_rx_channel->device->dev; | |
288 | unsigned int max_seg_size = dma_get_max_seg_size(dev); | |
289 | ||
290 | if (max_seg_size < host->mmc->max_seg_size) | |
291 | host->mmc->max_seg_size = max_seg_size; | |
292 | } | |
293 | } | |
294 | ||
295 | /* | |
296 | * This is used in __devinit or __devexit so inline it | |
297 | * so it can be discarded. | |
298 | */ | |
299 | static inline void mmci_dma_release(struct mmci_host *host) | |
300 | { | |
301 | struct mmci_platform_data *plat = host->plat; | |
302 | ||
303 | if (host->dma_rx_channel) | |
304 | dma_release_channel(host->dma_rx_channel); | |
305 | if (host->dma_tx_channel && plat->dma_tx_param) | |
306 | dma_release_channel(host->dma_tx_channel); | |
307 | host->dma_rx_channel = host->dma_tx_channel = NULL; | |
308 | } | |
309 | ||
310 | static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) | |
311 | { | |
312 | struct dma_chan *chan = host->dma_current; | |
313 | enum dma_data_direction dir; | |
314 | u32 status; | |
315 | int i; | |
316 | ||
317 | /* Wait up to 1ms for the DMA to complete */ | |
318 | for (i = 0; ; i++) { | |
319 | status = readl(host->base + MMCISTATUS); | |
320 | if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) | |
321 | break; | |
322 | udelay(10); | |
323 | } | |
324 | ||
325 | /* | |
326 | * Check to see whether we still have some data left in the FIFO - | |
327 | * this catches DMA controllers which are unable to monitor the | |
328 | * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- | |
329 | * contiguous buffers. On TX, we'll get a FIFO underrun error. | |
330 | */ | |
331 | if (status & MCI_RXDATAAVLBLMASK) { | |
332 | dmaengine_terminate_all(chan); | |
333 | if (!data->error) | |
334 | data->error = -EIO; | |
335 | } | |
336 | ||
337 | if (data->flags & MMC_DATA_WRITE) { | |
338 | dir = DMA_TO_DEVICE; | |
339 | } else { | |
340 | dir = DMA_FROM_DEVICE; | |
341 | } | |
342 | ||
58c7ccbf PF |
343 | if (!data->host_cookie) |
344 | dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); | |
c8ebae37 RK |
345 | |
346 | /* | |
347 | * Use of DMA with scatter-gather is impossible. | |
348 | * Give up with DMA and switch back to PIO mode. | |
349 | */ | |
350 | if (status & MCI_RXDATAAVLBLMASK) { | |
351 | dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); | |
352 | mmci_dma_release(host); | |
353 | } | |
354 | } | |
355 | ||
356 | static void mmci_dma_data_error(struct mmci_host *host) | |
357 | { | |
358 | dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); | |
359 | dmaengine_terminate_all(host->dma_current); | |
360 | } | |
361 | ||
58c7ccbf PF |
362 | static int mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, |
363 | struct mmci_host_next *next) | |
c8ebae37 RK |
364 | { |
365 | struct variant_data *variant = host->variant; | |
366 | struct dma_slave_config conf = { | |
367 | .src_addr = host->phybase + MMCIFIFO, | |
368 | .dst_addr = host->phybase + MMCIFIFO, | |
369 | .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
370 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
371 | .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ | |
372 | .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ | |
373 | }; | |
c8ebae37 RK |
374 | struct dma_chan *chan; |
375 | struct dma_device *device; | |
376 | struct dma_async_tx_descriptor *desc; | |
377 | int nr_sg; | |
378 | ||
58c7ccbf PF |
379 | /* Check if next job is already prepared */ |
380 | if (data->host_cookie && !next && | |
381 | host->dma_current && host->dma_desc_current) | |
382 | return 0; | |
383 | ||
384 | if (!next) { | |
385 | host->dma_current = NULL; | |
386 | host->dma_desc_current = NULL; | |
387 | } | |
c8ebae37 RK |
388 | |
389 | if (data->flags & MMC_DATA_READ) { | |
390 | conf.direction = DMA_FROM_DEVICE; | |
391 | chan = host->dma_rx_channel; | |
392 | } else { | |
393 | conf.direction = DMA_TO_DEVICE; | |
394 | chan = host->dma_tx_channel; | |
395 | } | |
396 | ||
397 | /* If there's no DMA channel, fall back to PIO */ | |
398 | if (!chan) | |
399 | return -EINVAL; | |
400 | ||
401 | /* If less than or equal to the fifo size, don't bother with DMA */ | |
58c7ccbf | 402 | if (data->blksz * data->blocks <= variant->fifosize) |
c8ebae37 RK |
403 | return -EINVAL; |
404 | ||
405 | device = chan->device; | |
406 | nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, conf.direction); | |
407 | if (nr_sg == 0) | |
408 | return -EINVAL; | |
409 | ||
410 | dmaengine_slave_config(chan, &conf); | |
411 | desc = device->device_prep_slave_sg(chan, data->sg, nr_sg, | |
412 | conf.direction, DMA_CTRL_ACK); | |
413 | if (!desc) | |
414 | goto unmap_exit; | |
415 | ||
58c7ccbf PF |
416 | if (next) { |
417 | next->dma_chan = chan; | |
418 | next->dma_desc = desc; | |
419 | } else { | |
420 | host->dma_current = chan; | |
421 | host->dma_desc_current = desc; | |
422 | } | |
423 | ||
424 | return 0; | |
c8ebae37 | 425 | |
58c7ccbf PF |
426 | unmap_exit: |
427 | if (!next) | |
428 | dmaengine_terminate_all(chan); | |
429 | dma_unmap_sg(device->dev, data->sg, data->sg_len, conf.direction); | |
430 | return -ENOMEM; | |
431 | } | |
432 | ||
433 | static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) | |
434 | { | |
435 | int ret; | |
436 | struct mmc_data *data = host->data; | |
437 | ||
438 | ret = mmci_dma_prep_data(host, host->data, NULL); | |
439 | if (ret) | |
440 | return ret; | |
441 | ||
442 | /* Okay, go for it. */ | |
c8ebae37 RK |
443 | dev_vdbg(mmc_dev(host->mmc), |
444 | "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", | |
445 | data->sg_len, data->blksz, data->blocks, data->flags); | |
58c7ccbf PF |
446 | dmaengine_submit(host->dma_desc_current); |
447 | dma_async_issue_pending(host->dma_current); | |
c8ebae37 RK |
448 | |
449 | datactrl |= MCI_DPSM_DMAENABLE; | |
450 | ||
451 | /* Trigger the DMA transfer */ | |
452 | writel(datactrl, host->base + MMCIDATACTRL); | |
453 | ||
454 | /* | |
455 | * Let the MMCI say when the data is ended and it's time | |
456 | * to fire next DMA request. When that happens, MMCI will | |
457 | * call mmci_data_end() | |
458 | */ | |
459 | writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, | |
460 | host->base + MMCIMASK0); | |
461 | return 0; | |
58c7ccbf | 462 | } |
c8ebae37 | 463 | |
58c7ccbf PF |
464 | static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) |
465 | { | |
466 | struct mmci_host_next *next = &host->next_data; | |
467 | ||
468 | if (data->host_cookie && data->host_cookie != next->cookie) { | |
a3c76eb9 | 469 | pr_warning("[%s] invalid cookie: data->host_cookie %d" |
58c7ccbf PF |
470 | " host->next_data.cookie %d\n", |
471 | __func__, data->host_cookie, host->next_data.cookie); | |
472 | data->host_cookie = 0; | |
473 | } | |
474 | ||
475 | if (!data->host_cookie) | |
476 | return; | |
477 | ||
478 | host->dma_desc_current = next->dma_desc; | |
479 | host->dma_current = next->dma_chan; | |
480 | ||
481 | next->dma_desc = NULL; | |
482 | next->dma_chan = NULL; | |
c8ebae37 | 483 | } |
58c7ccbf PF |
484 | |
485 | static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, | |
486 | bool is_first_req) | |
487 | { | |
488 | struct mmci_host *host = mmc_priv(mmc); | |
489 | struct mmc_data *data = mrq->data; | |
490 | struct mmci_host_next *nd = &host->next_data; | |
491 | ||
492 | if (!data) | |
493 | return; | |
494 | ||
495 | if (data->host_cookie) { | |
496 | data->host_cookie = 0; | |
497 | return; | |
498 | } | |
499 | ||
500 | /* if config for dma */ | |
501 | if (((data->flags & MMC_DATA_WRITE) && host->dma_tx_channel) || | |
502 | ((data->flags & MMC_DATA_READ) && host->dma_rx_channel)) { | |
503 | if (mmci_dma_prep_data(host, data, nd)) | |
504 | data->host_cookie = 0; | |
505 | else | |
506 | data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; | |
507 | } | |
508 | } | |
509 | ||
510 | static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, | |
511 | int err) | |
512 | { | |
513 | struct mmci_host *host = mmc_priv(mmc); | |
514 | struct mmc_data *data = mrq->data; | |
515 | struct dma_chan *chan; | |
516 | enum dma_data_direction dir; | |
517 | ||
518 | if (!data) | |
519 | return; | |
520 | ||
521 | if (data->flags & MMC_DATA_READ) { | |
522 | dir = DMA_FROM_DEVICE; | |
523 | chan = host->dma_rx_channel; | |
524 | } else { | |
525 | dir = DMA_TO_DEVICE; | |
526 | chan = host->dma_tx_channel; | |
527 | } | |
528 | ||
529 | ||
530 | /* if config for dma */ | |
531 | if (chan) { | |
532 | if (err) | |
533 | dmaengine_terminate_all(chan); | |
8e3336b1 | 534 | if (data->host_cookie) |
58c7ccbf PF |
535 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, |
536 | data->sg_len, dir); | |
537 | mrq->data->host_cookie = 0; | |
538 | } | |
539 | } | |
540 | ||
c8ebae37 RK |
541 | #else |
542 | /* Blank functions if the DMA engine is not available */ | |
58c7ccbf PF |
543 | static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) |
544 | { | |
545 | } | |
c8ebae37 RK |
546 | static inline void mmci_dma_setup(struct mmci_host *host) |
547 | { | |
548 | } | |
549 | ||
550 | static inline void mmci_dma_release(struct mmci_host *host) | |
551 | { | |
552 | } | |
553 | ||
554 | static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) | |
555 | { | |
556 | } | |
557 | ||
558 | static inline void mmci_dma_data_error(struct mmci_host *host) | |
559 | { | |
560 | } | |
561 | ||
562 | static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) | |
563 | { | |
564 | return -ENOSYS; | |
565 | } | |
58c7ccbf PF |
566 | |
567 | #define mmci_pre_request NULL | |
568 | #define mmci_post_request NULL | |
569 | ||
c8ebae37 RK |
570 | #endif |
571 | ||
1da177e4 LT |
572 | static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) |
573 | { | |
8301bb68 | 574 | struct variant_data *variant = host->variant; |
1da177e4 | 575 | unsigned int datactrl, timeout, irqmask; |
7b09cdac | 576 | unsigned long long clks; |
1da177e4 | 577 | void __iomem *base; |
3bc87f24 | 578 | int blksz_bits; |
1da177e4 | 579 | |
64de0289 LW |
580 | dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", |
581 | data->blksz, data->blocks, data->flags); | |
1da177e4 LT |
582 | |
583 | host->data = data; | |
528320db | 584 | host->size = data->blksz * data->blocks; |
51d4375d | 585 | data->bytes_xfered = 0; |
1da177e4 | 586 | |
7b09cdac RK |
587 | clks = (unsigned long long)data->timeout_ns * host->cclk; |
588 | do_div(clks, 1000000000UL); | |
589 | ||
590 | timeout = data->timeout_clks + (unsigned int)clks; | |
1da177e4 LT |
591 | |
592 | base = host->base; | |
593 | writel(timeout, base + MMCIDATATIMER); | |
594 | writel(host->size, base + MMCIDATALENGTH); | |
595 | ||
3bc87f24 RK |
596 | blksz_bits = ffs(data->blksz) - 1; |
597 | BUG_ON(1 << blksz_bits != data->blksz); | |
598 | ||
1784b157 PL |
599 | if (variant->blksz_datactrl16) |
600 | datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); | |
601 | else | |
602 | datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; | |
c8ebae37 RK |
603 | |
604 | if (data->flags & MMC_DATA_READ) | |
1da177e4 | 605 | datactrl |= MCI_DPSM_DIRECTION; |
c8ebae37 RK |
606 | |
607 | /* | |
608 | * Attempt to use DMA operation mode, if this | |
609 | * should fail, fall back to PIO mode | |
610 | */ | |
611 | if (!mmci_dma_start_data(host, datactrl)) | |
612 | return; | |
613 | ||
614 | /* IRQ mode, map the SG list for CPU reading/writing */ | |
615 | mmci_init_sg(host, data); | |
616 | ||
617 | if (data->flags & MMC_DATA_READ) { | |
1da177e4 | 618 | irqmask = MCI_RXFIFOHALFFULLMASK; |
0425a142 RK |
619 | |
620 | /* | |
c4d877c1 RK |
621 | * If we have less than the fifo 'half-full' threshold to |
622 | * transfer, trigger a PIO interrupt as soon as any data | |
623 | * is available. | |
0425a142 | 624 | */ |
c4d877c1 | 625 | if (host->size < variant->fifohalfsize) |
0425a142 | 626 | irqmask |= MCI_RXDATAAVLBLMASK; |
1da177e4 LT |
627 | } else { |
628 | /* | |
629 | * We don't actually need to include "FIFO empty" here | |
630 | * since its implicit in "FIFO half empty". | |
631 | */ | |
632 | irqmask = MCI_TXFIFOHALFEMPTYMASK; | |
633 | } | |
634 | ||
34177802 LW |
635 | /* The ST Micro variants has a special bit to enable SDIO */ |
636 | if (variant->sdio && host->mmc->card) | |
637 | if (mmc_card_sdio(host->mmc->card)) | |
638 | datactrl |= MCI_ST_DPSM_SDIOEN; | |
639 | ||
1da177e4 LT |
640 | writel(datactrl, base + MMCIDATACTRL); |
641 | writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); | |
2686b4b4 | 642 | mmci_set_mask1(host, irqmask); |
1da177e4 LT |
643 | } |
644 | ||
645 | static void | |
646 | mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) | |
647 | { | |
648 | void __iomem *base = host->base; | |
649 | ||
64de0289 | 650 | dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", |
1da177e4 LT |
651 | cmd->opcode, cmd->arg, cmd->flags); |
652 | ||
653 | if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { | |
654 | writel(0, base + MMCICOMMAND); | |
655 | udelay(1); | |
656 | } | |
657 | ||
658 | c |= cmd->opcode | MCI_CPSM_ENABLE; | |
e9225176 RK |
659 | if (cmd->flags & MMC_RSP_PRESENT) { |
660 | if (cmd->flags & MMC_RSP_136) | |
661 | c |= MCI_CPSM_LONGRSP; | |
1da177e4 | 662 | c |= MCI_CPSM_RESPONSE; |
1da177e4 LT |
663 | } |
664 | if (/*interrupt*/0) | |
665 | c |= MCI_CPSM_INTERRUPT; | |
666 | ||
667 | host->cmd = cmd; | |
668 | ||
669 | writel(cmd->arg, base + MMCIARGUMENT); | |
670 | writel(c, base + MMCICOMMAND); | |
671 | } | |
672 | ||
673 | static void | |
674 | mmci_data_irq(struct mmci_host *host, struct mmc_data *data, | |
675 | unsigned int status) | |
676 | { | |
f20f8f21 | 677 | /* First check for errors */ |
b63038d6 UH |
678 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| |
679 | MCI_TXUNDERRUN|MCI_RXOVERRUN)) { | |
8cb28155 | 680 | u32 remain, success; |
f20f8f21 | 681 | |
c8ebae37 RK |
682 | /* Terminate the DMA transfer */ |
683 | if (dma_inprogress(host)) | |
684 | mmci_dma_data_error(host); | |
e9c091b4 RK |
685 | |
686 | /* | |
c8afc9d5 RK |
687 | * Calculate how far we are into the transfer. Note that |
688 | * the data counter gives the number of bytes transferred | |
689 | * on the MMC bus, not on the host side. On reads, this | |
690 | * can be as much as a FIFO-worth of data ahead. This | |
691 | * matters for FIFO overruns only. | |
e9c091b4 | 692 | */ |
f5a106d9 | 693 | remain = readl(host->base + MMCIDATACNT); |
8cb28155 LW |
694 | success = data->blksz * data->blocks - remain; |
695 | ||
c8afc9d5 RK |
696 | dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", |
697 | status, success); | |
8cb28155 LW |
698 | if (status & MCI_DATACRCFAIL) { |
699 | /* Last block was not successful */ | |
c8afc9d5 | 700 | success -= 1; |
17b0429d | 701 | data->error = -EILSEQ; |
8cb28155 | 702 | } else if (status & MCI_DATATIMEOUT) { |
17b0429d | 703 | data->error = -ETIMEDOUT; |
757df746 LW |
704 | } else if (status & MCI_STARTBITERR) { |
705 | data->error = -ECOMM; | |
c8afc9d5 RK |
706 | } else if (status & MCI_TXUNDERRUN) { |
707 | data->error = -EIO; | |
708 | } else if (status & MCI_RXOVERRUN) { | |
709 | if (success > host->variant->fifosize) | |
710 | success -= host->variant->fifosize; | |
711 | else | |
712 | success = 0; | |
17b0429d | 713 | data->error = -EIO; |
4ce1d6cb | 714 | } |
51d4375d | 715 | data->bytes_xfered = round_down(success, data->blksz); |
1da177e4 | 716 | } |
f20f8f21 | 717 | |
8cb28155 LW |
718 | if (status & MCI_DATABLOCKEND) |
719 | dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); | |
f20f8f21 | 720 | |
ccff9b51 | 721 | if (status & MCI_DATAEND || data->error) { |
c8ebae37 RK |
722 | if (dma_inprogress(host)) |
723 | mmci_dma_unmap(host, data); | |
1da177e4 LT |
724 | mmci_stop_data(host); |
725 | ||
8cb28155 LW |
726 | if (!data->error) |
727 | /* The error clause is handled above, success! */ | |
51d4375d | 728 | data->bytes_xfered = data->blksz * data->blocks; |
f20f8f21 | 729 | |
1da177e4 LT |
730 | if (!data->stop) { |
731 | mmci_request_end(host, data->mrq); | |
732 | } else { | |
733 | mmci_start_command(host, data->stop, 0); | |
734 | } | |
735 | } | |
736 | } | |
737 | ||
738 | static void | |
739 | mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, | |
740 | unsigned int status) | |
741 | { | |
742 | void __iomem *base = host->base; | |
743 | ||
744 | host->cmd = NULL; | |
745 | ||
1da177e4 | 746 | if (status & MCI_CMDTIMEOUT) { |
17b0429d | 747 | cmd->error = -ETIMEDOUT; |
1da177e4 | 748 | } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { |
17b0429d | 749 | cmd->error = -EILSEQ; |
9047b435 RKAL |
750 | } else { |
751 | cmd->resp[0] = readl(base + MMCIRESPONSE0); | |
752 | cmd->resp[1] = readl(base + MMCIRESPONSE1); | |
753 | cmd->resp[2] = readl(base + MMCIRESPONSE2); | |
754 | cmd->resp[3] = readl(base + MMCIRESPONSE3); | |
1da177e4 LT |
755 | } |
756 | ||
17b0429d | 757 | if (!cmd->data || cmd->error) { |
e47c222b RK |
758 | if (host->data) |
759 | mmci_stop_data(host); | |
1da177e4 LT |
760 | mmci_request_end(host, cmd->mrq); |
761 | } else if (!(cmd->data->flags & MMC_DATA_READ)) { | |
762 | mmci_start_data(host, cmd->data); | |
763 | } | |
764 | } | |
765 | ||
766 | static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) | |
767 | { | |
768 | void __iomem *base = host->base; | |
769 | char *ptr = buffer; | |
770 | u32 status; | |
26eed9a5 | 771 | int host_remain = host->size; |
1da177e4 LT |
772 | |
773 | do { | |
26eed9a5 | 774 | int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); |
1da177e4 LT |
775 | |
776 | if (count > remain) | |
777 | count = remain; | |
778 | ||
779 | if (count <= 0) | |
780 | break; | |
781 | ||
782 | readsl(base + MMCIFIFO, ptr, count >> 2); | |
783 | ||
784 | ptr += count; | |
785 | remain -= count; | |
26eed9a5 | 786 | host_remain -= count; |
1da177e4 LT |
787 | |
788 | if (remain == 0) | |
789 | break; | |
790 | ||
791 | status = readl(base + MMCISTATUS); | |
792 | } while (status & MCI_RXDATAAVLBL); | |
793 | ||
794 | return ptr - buffer; | |
795 | } | |
796 | ||
797 | static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) | |
798 | { | |
8301bb68 | 799 | struct variant_data *variant = host->variant; |
1da177e4 LT |
800 | void __iomem *base = host->base; |
801 | char *ptr = buffer; | |
802 | ||
803 | do { | |
804 | unsigned int count, maxcnt; | |
805 | ||
8301bb68 RV |
806 | maxcnt = status & MCI_TXFIFOEMPTY ? |
807 | variant->fifosize : variant->fifohalfsize; | |
1da177e4 LT |
808 | count = min(remain, maxcnt); |
809 | ||
34177802 LW |
810 | /* |
811 | * The ST Micro variant for SDIO transfer sizes | |
812 | * less then 8 bytes should have clock H/W flow | |
813 | * control disabled. | |
814 | */ | |
815 | if (variant->sdio && | |
816 | mmc_card_sdio(host->mmc->card)) { | |
817 | if (count < 8) | |
818 | writel(readl(host->base + MMCICLOCK) & | |
819 | ~variant->clkreg_enable, | |
820 | host->base + MMCICLOCK); | |
821 | else | |
822 | writel(readl(host->base + MMCICLOCK) | | |
823 | variant->clkreg_enable, | |
824 | host->base + MMCICLOCK); | |
825 | } | |
826 | ||
827 | /* | |
828 | * SDIO especially may want to send something that is | |
829 | * not divisible by 4 (as opposed to card sectors | |
830 | * etc), and the FIFO only accept full 32-bit writes. | |
831 | * So compensate by adding +3 on the count, a single | |
832 | * byte become a 32bit write, 7 bytes will be two | |
833 | * 32bit writes etc. | |
834 | */ | |
835 | writesl(base + MMCIFIFO, ptr, (count + 3) >> 2); | |
1da177e4 LT |
836 | |
837 | ptr += count; | |
838 | remain -= count; | |
839 | ||
840 | if (remain == 0) | |
841 | break; | |
842 | ||
843 | status = readl(base + MMCISTATUS); | |
844 | } while (status & MCI_TXFIFOHALFEMPTY); | |
845 | ||
846 | return ptr - buffer; | |
847 | } | |
848 | ||
849 | /* | |
850 | * PIO data transfer IRQ handler. | |
851 | */ | |
7d12e780 | 852 | static irqreturn_t mmci_pio_irq(int irq, void *dev_id) |
1da177e4 LT |
853 | { |
854 | struct mmci_host *host = dev_id; | |
4ce1d6cb | 855 | struct sg_mapping_iter *sg_miter = &host->sg_miter; |
8301bb68 | 856 | struct variant_data *variant = host->variant; |
1da177e4 | 857 | void __iomem *base = host->base; |
4ce1d6cb | 858 | unsigned long flags; |
1da177e4 LT |
859 | u32 status; |
860 | ||
861 | status = readl(base + MMCISTATUS); | |
862 | ||
64de0289 | 863 | dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); |
1da177e4 | 864 | |
4ce1d6cb RV |
865 | local_irq_save(flags); |
866 | ||
1da177e4 | 867 | do { |
1da177e4 LT |
868 | unsigned int remain, len; |
869 | char *buffer; | |
870 | ||
871 | /* | |
872 | * For write, we only need to test the half-empty flag | |
873 | * here - if the FIFO is completely empty, then by | |
874 | * definition it is more than half empty. | |
875 | * | |
876 | * For read, check for data available. | |
877 | */ | |
878 | if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) | |
879 | break; | |
880 | ||
4ce1d6cb RV |
881 | if (!sg_miter_next(sg_miter)) |
882 | break; | |
883 | ||
884 | buffer = sg_miter->addr; | |
885 | remain = sg_miter->length; | |
1da177e4 LT |
886 | |
887 | len = 0; | |
888 | if (status & MCI_RXACTIVE) | |
889 | len = mmci_pio_read(host, buffer, remain); | |
890 | if (status & MCI_TXACTIVE) | |
891 | len = mmci_pio_write(host, buffer, remain, status); | |
892 | ||
4ce1d6cb | 893 | sg_miter->consumed = len; |
1da177e4 | 894 | |
1da177e4 LT |
895 | host->size -= len; |
896 | remain -= len; | |
897 | ||
898 | if (remain) | |
899 | break; | |
900 | ||
1da177e4 LT |
901 | status = readl(base + MMCISTATUS); |
902 | } while (1); | |
903 | ||
4ce1d6cb RV |
904 | sg_miter_stop(sg_miter); |
905 | ||
906 | local_irq_restore(flags); | |
907 | ||
1da177e4 | 908 | /* |
c4d877c1 RK |
909 | * If we have less than the fifo 'half-full' threshold to transfer, |
910 | * trigger a PIO interrupt as soon as any data is available. | |
1da177e4 | 911 | */ |
c4d877c1 | 912 | if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) |
2686b4b4 | 913 | mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); |
1da177e4 LT |
914 | |
915 | /* | |
916 | * If we run out of data, disable the data IRQs; this | |
917 | * prevents a race where the FIFO becomes empty before | |
918 | * the chip itself has disabled the data path, and | |
919 | * stops us racing with our data end IRQ. | |
920 | */ | |
921 | if (host->size == 0) { | |
2686b4b4 | 922 | mmci_set_mask1(host, 0); |
1da177e4 LT |
923 | writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); |
924 | } | |
925 | ||
926 | return IRQ_HANDLED; | |
927 | } | |
928 | ||
929 | /* | |
930 | * Handle completion of command and data transfers. | |
931 | */ | |
7d12e780 | 932 | static irqreturn_t mmci_irq(int irq, void *dev_id) |
1da177e4 LT |
933 | { |
934 | struct mmci_host *host = dev_id; | |
935 | u32 status; | |
936 | int ret = 0; | |
937 | ||
938 | spin_lock(&host->lock); | |
939 | ||
940 | do { | |
941 | struct mmc_command *cmd; | |
942 | struct mmc_data *data; | |
943 | ||
944 | status = readl(host->base + MMCISTATUS); | |
2686b4b4 LW |
945 | |
946 | if (host->singleirq) { | |
947 | if (status & readl(host->base + MMCIMASK1)) | |
948 | mmci_pio_irq(irq, dev_id); | |
949 | ||
950 | status &= ~MCI_IRQ1MASK; | |
951 | } | |
952 | ||
1da177e4 LT |
953 | status &= readl(host->base + MMCIMASK0); |
954 | writel(status, host->base + MMCICLEAR); | |
955 | ||
64de0289 | 956 | dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); |
1da177e4 LT |
957 | |
958 | data = host->data; | |
b63038d6 UH |
959 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| |
960 | MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND| | |
961 | MCI_DATABLOCKEND) && data) | |
1da177e4 LT |
962 | mmci_data_irq(host, data, status); |
963 | ||
964 | cmd = host->cmd; | |
965 | if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) | |
966 | mmci_cmd_irq(host, cmd, status); | |
967 | ||
968 | ret = 1; | |
969 | } while (status); | |
970 | ||
971 | spin_unlock(&host->lock); | |
972 | ||
973 | return IRQ_RETVAL(ret); | |
974 | } | |
975 | ||
976 | static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
977 | { | |
978 | struct mmci_host *host = mmc_priv(mmc); | |
9e943021 | 979 | unsigned long flags; |
1da177e4 LT |
980 | |
981 | WARN_ON(host->mrq != NULL); | |
982 | ||
019a5f56 | 983 | if (mrq->data && !is_power_of_2(mrq->data->blksz)) { |
64de0289 LW |
984 | dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", |
985 | mrq->data->blksz); | |
255d01af PO |
986 | mrq->cmd->error = -EINVAL; |
987 | mmc_request_done(mmc, mrq); | |
988 | return; | |
989 | } | |
990 | ||
1c3be369 RK |
991 | pm_runtime_get_sync(mmc_dev(mmc)); |
992 | ||
9e943021 | 993 | spin_lock_irqsave(&host->lock, flags); |
1da177e4 LT |
994 | |
995 | host->mrq = mrq; | |
996 | ||
58c7ccbf PF |
997 | if (mrq->data) |
998 | mmci_get_next_data(host, mrq->data); | |
999 | ||
1da177e4 LT |
1000 | if (mrq->data && mrq->data->flags & MMC_DATA_READ) |
1001 | mmci_start_data(host, mrq->data); | |
1002 | ||
1003 | mmci_start_command(host, mrq->cmd, 0); | |
1004 | ||
9e943021 | 1005 | spin_unlock_irqrestore(&host->lock, flags); |
1da177e4 LT |
1006 | } |
1007 | ||
1008 | static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
1009 | { | |
1010 | struct mmci_host *host = mmc_priv(mmc); | |
a6a6464a LW |
1011 | u32 pwr = 0; |
1012 | unsigned long flags; | |
99fc5131 | 1013 | int ret; |
1da177e4 | 1014 | |
1da177e4 LT |
1015 | switch (ios->power_mode) { |
1016 | case MMC_POWER_OFF: | |
99fc5131 LW |
1017 | if (host->vcc) |
1018 | ret = mmc_regulator_set_ocr(mmc, host->vcc, 0); | |
1da177e4 LT |
1019 | break; |
1020 | case MMC_POWER_UP: | |
99fc5131 LW |
1021 | if (host->vcc) { |
1022 | ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd); | |
1023 | if (ret) { | |
1024 | dev_err(mmc_dev(mmc), "unable to set OCR\n"); | |
1025 | /* | |
1026 | * The .set_ios() function in the mmc_host_ops | |
1027 | * struct return void, and failing to set the | |
1028 | * power should be rare so we print an error | |
1029 | * and return here. | |
1030 | */ | |
1031 | return; | |
1032 | } | |
1033 | } | |
bb8f563c RV |
1034 | if (host->plat->vdd_handler) |
1035 | pwr |= host->plat->vdd_handler(mmc_dev(mmc), ios->vdd, | |
1036 | ios->power_mode); | |
cc30d60e | 1037 | /* The ST version does not have this, fall through to POWER_ON */ |
f17a1f06 | 1038 | if (host->hw_designer != AMBA_VENDOR_ST) { |
cc30d60e LW |
1039 | pwr |= MCI_PWR_UP; |
1040 | break; | |
1041 | } | |
1da177e4 LT |
1042 | case MMC_POWER_ON: |
1043 | pwr |= MCI_PWR_ON; | |
1044 | break; | |
1045 | } | |
1046 | ||
cc30d60e | 1047 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { |
f17a1f06 | 1048 | if (host->hw_designer != AMBA_VENDOR_ST) |
cc30d60e LW |
1049 | pwr |= MCI_ROD; |
1050 | else { | |
1051 | /* | |
1052 | * The ST Micro variant use the ROD bit for something | |
1053 | * else and only has OD (Open Drain). | |
1054 | */ | |
1055 | pwr |= MCI_OD; | |
1056 | } | |
1057 | } | |
1da177e4 | 1058 | |
a6a6464a LW |
1059 | spin_lock_irqsave(&host->lock, flags); |
1060 | ||
1061 | mmci_set_clkreg(host, ios->clock); | |
1da177e4 LT |
1062 | |
1063 | if (host->pwr != pwr) { | |
1064 | host->pwr = pwr; | |
1065 | writel(pwr, host->base + MMCIPOWER); | |
1066 | } | |
a6a6464a LW |
1067 | |
1068 | spin_unlock_irqrestore(&host->lock, flags); | |
1da177e4 LT |
1069 | } |
1070 | ||
89001446 RK |
1071 | static int mmci_get_ro(struct mmc_host *mmc) |
1072 | { | |
1073 | struct mmci_host *host = mmc_priv(mmc); | |
1074 | ||
1075 | if (host->gpio_wp == -ENOSYS) | |
1076 | return -ENOSYS; | |
1077 | ||
18a06301 | 1078 | return gpio_get_value_cansleep(host->gpio_wp); |
89001446 RK |
1079 | } |
1080 | ||
1081 | static int mmci_get_cd(struct mmc_host *mmc) | |
1082 | { | |
1083 | struct mmci_host *host = mmc_priv(mmc); | |
29719445 | 1084 | struct mmci_platform_data *plat = host->plat; |
89001446 RK |
1085 | unsigned int status; |
1086 | ||
4b8caec0 RV |
1087 | if (host->gpio_cd == -ENOSYS) { |
1088 | if (!plat->status) | |
1089 | return 1; /* Assume always present */ | |
1090 | ||
29719445 | 1091 | status = plat->status(mmc_dev(host->mmc)); |
4b8caec0 | 1092 | } else |
18a06301 LW |
1093 | status = !!gpio_get_value_cansleep(host->gpio_cd) |
1094 | ^ plat->cd_invert; | |
89001446 | 1095 | |
74bc8093 RK |
1096 | /* |
1097 | * Use positive logic throughout - status is zero for no card, | |
1098 | * non-zero for card inserted. | |
1099 | */ | |
1100 | return status; | |
89001446 RK |
1101 | } |
1102 | ||
148b8b39 RV |
1103 | static irqreturn_t mmci_cd_irq(int irq, void *dev_id) |
1104 | { | |
1105 | struct mmci_host *host = dev_id; | |
1106 | ||
1107 | mmc_detect_change(host->mmc, msecs_to_jiffies(500)); | |
1108 | ||
1109 | return IRQ_HANDLED; | |
1110 | } | |
1111 | ||
ab7aefd0 | 1112 | static const struct mmc_host_ops mmci_ops = { |
1da177e4 | 1113 | .request = mmci_request, |
58c7ccbf PF |
1114 | .pre_req = mmci_pre_request, |
1115 | .post_req = mmci_post_request, | |
1da177e4 | 1116 | .set_ios = mmci_set_ios, |
89001446 RK |
1117 | .get_ro = mmci_get_ro, |
1118 | .get_cd = mmci_get_cd, | |
1da177e4 LT |
1119 | }; |
1120 | ||
aa25afad RK |
1121 | static int __devinit mmci_probe(struct amba_device *dev, |
1122 | const struct amba_id *id) | |
1da177e4 | 1123 | { |
6ef297f8 | 1124 | struct mmci_platform_data *plat = dev->dev.platform_data; |
4956e109 | 1125 | struct variant_data *variant = id->data; |
1da177e4 LT |
1126 | struct mmci_host *host; |
1127 | struct mmc_host *mmc; | |
1128 | int ret; | |
1129 | ||
1130 | /* must have platform data */ | |
1131 | if (!plat) { | |
1132 | ret = -EINVAL; | |
1133 | goto out; | |
1134 | } | |
1135 | ||
1136 | ret = amba_request_regions(dev, DRIVER_NAME); | |
1137 | if (ret) | |
1138 | goto out; | |
1139 | ||
1140 | mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); | |
1141 | if (!mmc) { | |
1142 | ret = -ENOMEM; | |
1143 | goto rel_regions; | |
1144 | } | |
1145 | ||
1146 | host = mmc_priv(mmc); | |
4ea580f1 | 1147 | host->mmc = mmc; |
012b7d33 | 1148 | |
89001446 RK |
1149 | host->gpio_wp = -ENOSYS; |
1150 | host->gpio_cd = -ENOSYS; | |
148b8b39 | 1151 | host->gpio_cd_irq = -1; |
89001446 | 1152 | |
012b7d33 RK |
1153 | host->hw_designer = amba_manf(dev); |
1154 | host->hw_revision = amba_rev(dev); | |
64de0289 LW |
1155 | dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); |
1156 | dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); | |
012b7d33 | 1157 | |
ee569c43 | 1158 | host->clk = clk_get(&dev->dev, NULL); |
1da177e4 LT |
1159 | if (IS_ERR(host->clk)) { |
1160 | ret = PTR_ERR(host->clk); | |
1161 | host->clk = NULL; | |
1162 | goto host_free; | |
1163 | } | |
1164 | ||
52ca0f3a | 1165 | ret = clk_prepare(host->clk); |
1da177e4 | 1166 | if (ret) |
a8d3584a | 1167 | goto clk_free; |
1da177e4 | 1168 | |
52ca0f3a RK |
1169 | ret = clk_enable(host->clk); |
1170 | if (ret) | |
1171 | goto clk_unprep; | |
1172 | ||
1da177e4 | 1173 | host->plat = plat; |
4956e109 | 1174 | host->variant = variant; |
1da177e4 | 1175 | host->mclk = clk_get_rate(host->clk); |
c8df9a53 LW |
1176 | /* |
1177 | * According to the spec, mclk is max 100 MHz, | |
1178 | * so we try to adjust the clock down to this, | |
1179 | * (if possible). | |
1180 | */ | |
1181 | if (host->mclk > 100000000) { | |
1182 | ret = clk_set_rate(host->clk, 100000000); | |
1183 | if (ret < 0) | |
1184 | goto clk_disable; | |
1185 | host->mclk = clk_get_rate(host->clk); | |
64de0289 LW |
1186 | dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", |
1187 | host->mclk); | |
c8df9a53 | 1188 | } |
c8ebae37 | 1189 | host->phybase = dev->res.start; |
dc890c2d | 1190 | host->base = ioremap(dev->res.start, resource_size(&dev->res)); |
1da177e4 LT |
1191 | if (!host->base) { |
1192 | ret = -ENOMEM; | |
1193 | goto clk_disable; | |
1194 | } | |
1195 | ||
1196 | mmc->ops = &mmci_ops; | |
7f294e49 LW |
1197 | /* |
1198 | * The ARM and ST versions of the block have slightly different | |
1199 | * clock divider equations which means that the minimum divider | |
1200 | * differs too. | |
1201 | */ | |
1202 | if (variant->st_clkdiv) | |
1203 | mmc->f_min = DIV_ROUND_UP(host->mclk, 257); | |
1204 | else | |
1205 | mmc->f_min = DIV_ROUND_UP(host->mclk, 512); | |
808d97cc LW |
1206 | /* |
1207 | * If the platform data supplies a maximum operating | |
1208 | * frequency, this takes precedence. Else, we fall back | |
1209 | * to using the module parameter, which has a (low) | |
1210 | * default value in case it is not specified. Either | |
1211 | * value must not exceed the clock rate into the block, | |
1212 | * of course. | |
1213 | */ | |
1214 | if (plat->f_max) | |
1215 | mmc->f_max = min(host->mclk, plat->f_max); | |
1216 | else | |
1217 | mmc->f_max = min(host->mclk, fmax); | |
64de0289 LW |
1218 | dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); |
1219 | ||
34e84f39 LW |
1220 | #ifdef CONFIG_REGULATOR |
1221 | /* If we're using the regulator framework, try to fetch a regulator */ | |
1222 | host->vcc = regulator_get(&dev->dev, "vmmc"); | |
1223 | if (IS_ERR(host->vcc)) | |
1224 | host->vcc = NULL; | |
1225 | else { | |
1226 | int mask = mmc_regulator_get_ocrmask(host->vcc); | |
1227 | ||
1228 | if (mask < 0) | |
1229 | dev_err(&dev->dev, "error getting OCR mask (%d)\n", | |
1230 | mask); | |
1231 | else { | |
1232 | host->mmc->ocr_avail = (u32) mask; | |
1233 | if (plat->ocr_mask) | |
1234 | dev_warn(&dev->dev, | |
1235 | "Provided ocr_mask/setpower will not be used " | |
1236 | "(using regulator instead)\n"); | |
1237 | } | |
1238 | } | |
1239 | #endif | |
1240 | /* Fall back to platform data if no regulator is found */ | |
1241 | if (host->vcc == NULL) | |
1242 | mmc->ocr_avail = plat->ocr_mask; | |
9e6c82cd | 1243 | mmc->caps = plat->capabilities; |
1da177e4 LT |
1244 | |
1245 | /* | |
1246 | * We can do SGIO | |
1247 | */ | |
a36274e0 | 1248 | mmc->max_segs = NR_SG; |
1da177e4 LT |
1249 | |
1250 | /* | |
08458ef6 RV |
1251 | * Since only a certain number of bits are valid in the data length |
1252 | * register, we must ensure that we don't exceed 2^num-1 bytes in a | |
1253 | * single request. | |
1da177e4 | 1254 | */ |
08458ef6 | 1255 | mmc->max_req_size = (1 << variant->datalength_bits) - 1; |
1da177e4 LT |
1256 | |
1257 | /* | |
1258 | * Set the maximum segment size. Since we aren't doing DMA | |
1259 | * (yet) we are only limited by the data length register. | |
1260 | */ | |
55db890a | 1261 | mmc->max_seg_size = mmc->max_req_size; |
1da177e4 | 1262 | |
fe4a3c7a PO |
1263 | /* |
1264 | * Block size can be up to 2048 bytes, but must be a power of two. | |
1265 | */ | |
1266 | mmc->max_blk_size = 2048; | |
1267 | ||
55db890a PO |
1268 | /* |
1269 | * No limit on the number of blocks transferred. | |
1270 | */ | |
1271 | mmc->max_blk_count = mmc->max_req_size; | |
1272 | ||
1da177e4 LT |
1273 | spin_lock_init(&host->lock); |
1274 | ||
1275 | writel(0, host->base + MMCIMASK0); | |
1276 | writel(0, host->base + MMCIMASK1); | |
1277 | writel(0xfff, host->base + MMCICLEAR); | |
1278 | ||
89001446 RK |
1279 | if (gpio_is_valid(plat->gpio_cd)) { |
1280 | ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); | |
1281 | if (ret == 0) | |
1282 | ret = gpio_direction_input(plat->gpio_cd); | |
1283 | if (ret == 0) | |
1284 | host->gpio_cd = plat->gpio_cd; | |
1285 | else if (ret != -ENOSYS) | |
1286 | goto err_gpio_cd; | |
148b8b39 | 1287 | |
17ee083b LW |
1288 | /* |
1289 | * A gpio pin that will detect cards when inserted and removed | |
1290 | * will most likely want to trigger on the edges if it is | |
1291 | * 0 when ejected and 1 when inserted (or mutatis mutandis | |
1292 | * for the inverted case) so we request triggers on both | |
1293 | * edges. | |
1294 | */ | |
148b8b39 | 1295 | ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), |
17ee083b LW |
1296 | mmci_cd_irq, |
1297 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, | |
1298 | DRIVER_NAME " (cd)", host); | |
148b8b39 RV |
1299 | if (ret >= 0) |
1300 | host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); | |
89001446 RK |
1301 | } |
1302 | if (gpio_is_valid(plat->gpio_wp)) { | |
1303 | ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); | |
1304 | if (ret == 0) | |
1305 | ret = gpio_direction_input(plat->gpio_wp); | |
1306 | if (ret == 0) | |
1307 | host->gpio_wp = plat->gpio_wp; | |
1308 | else if (ret != -ENOSYS) | |
1309 | goto err_gpio_wp; | |
1310 | } | |
1311 | ||
4b8caec0 RV |
1312 | if ((host->plat->status || host->gpio_cd != -ENOSYS) |
1313 | && host->gpio_cd_irq < 0) | |
148b8b39 RV |
1314 | mmc->caps |= MMC_CAP_NEEDS_POLL; |
1315 | ||
dace1453 | 1316 | ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); |
1da177e4 LT |
1317 | if (ret) |
1318 | goto unmap; | |
1319 | ||
2686b4b4 LW |
1320 | if (dev->irq[1] == NO_IRQ) |
1321 | host->singleirq = true; | |
1322 | else { | |
1323 | ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, | |
1324 | DRIVER_NAME " (pio)", host); | |
1325 | if (ret) | |
1326 | goto irq0_free; | |
1327 | } | |
1da177e4 | 1328 | |
8cb28155 | 1329 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); |
1da177e4 LT |
1330 | |
1331 | amba_set_drvdata(dev, mmc); | |
1332 | ||
c8ebae37 RK |
1333 | dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", |
1334 | mmc_hostname(mmc), amba_part(dev), amba_manf(dev), | |
1335 | amba_rev(dev), (unsigned long long)dev->res.start, | |
1336 | dev->irq[0], dev->irq[1]); | |
1337 | ||
1338 | mmci_dma_setup(host); | |
1da177e4 | 1339 | |
1c3be369 RK |
1340 | pm_runtime_put(&dev->dev); |
1341 | ||
8c11a94d RK |
1342 | mmc_add_host(mmc); |
1343 | ||
1da177e4 LT |
1344 | return 0; |
1345 | ||
1346 | irq0_free: | |
1347 | free_irq(dev->irq[0], host); | |
1348 | unmap: | |
89001446 RK |
1349 | if (host->gpio_wp != -ENOSYS) |
1350 | gpio_free(host->gpio_wp); | |
1351 | err_gpio_wp: | |
148b8b39 RV |
1352 | if (host->gpio_cd_irq >= 0) |
1353 | free_irq(host->gpio_cd_irq, host); | |
89001446 RK |
1354 | if (host->gpio_cd != -ENOSYS) |
1355 | gpio_free(host->gpio_cd); | |
1356 | err_gpio_cd: | |
1da177e4 LT |
1357 | iounmap(host->base); |
1358 | clk_disable: | |
1359 | clk_disable(host->clk); | |
52ca0f3a RK |
1360 | clk_unprep: |
1361 | clk_unprepare(host->clk); | |
1da177e4 LT |
1362 | clk_free: |
1363 | clk_put(host->clk); | |
1364 | host_free: | |
1365 | mmc_free_host(mmc); | |
1366 | rel_regions: | |
1367 | amba_release_regions(dev); | |
1368 | out: | |
1369 | return ret; | |
1370 | } | |
1371 | ||
6dc4a47a | 1372 | static int __devexit mmci_remove(struct amba_device *dev) |
1da177e4 LT |
1373 | { |
1374 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
1375 | ||
1376 | amba_set_drvdata(dev, NULL); | |
1377 | ||
1378 | if (mmc) { | |
1379 | struct mmci_host *host = mmc_priv(mmc); | |
1380 | ||
1c3be369 RK |
1381 | /* |
1382 | * Undo pm_runtime_put() in probe. We use the _sync | |
1383 | * version here so that we can access the primecell. | |
1384 | */ | |
1385 | pm_runtime_get_sync(&dev->dev); | |
1386 | ||
1da177e4 LT |
1387 | mmc_remove_host(mmc); |
1388 | ||
1389 | writel(0, host->base + MMCIMASK0); | |
1390 | writel(0, host->base + MMCIMASK1); | |
1391 | ||
1392 | writel(0, host->base + MMCICOMMAND); | |
1393 | writel(0, host->base + MMCIDATACTRL); | |
1394 | ||
c8ebae37 | 1395 | mmci_dma_release(host); |
1da177e4 | 1396 | free_irq(dev->irq[0], host); |
2686b4b4 LW |
1397 | if (!host->singleirq) |
1398 | free_irq(dev->irq[1], host); | |
1da177e4 | 1399 | |
89001446 RK |
1400 | if (host->gpio_wp != -ENOSYS) |
1401 | gpio_free(host->gpio_wp); | |
148b8b39 RV |
1402 | if (host->gpio_cd_irq >= 0) |
1403 | free_irq(host->gpio_cd_irq, host); | |
89001446 RK |
1404 | if (host->gpio_cd != -ENOSYS) |
1405 | gpio_free(host->gpio_cd); | |
1406 | ||
1da177e4 LT |
1407 | iounmap(host->base); |
1408 | clk_disable(host->clk); | |
52ca0f3a | 1409 | clk_unprepare(host->clk); |
1da177e4 LT |
1410 | clk_put(host->clk); |
1411 | ||
99fc5131 LW |
1412 | if (host->vcc) |
1413 | mmc_regulator_set_ocr(mmc, host->vcc, 0); | |
34e84f39 LW |
1414 | regulator_put(host->vcc); |
1415 | ||
1da177e4 LT |
1416 | mmc_free_host(mmc); |
1417 | ||
1418 | amba_release_regions(dev); | |
1419 | } | |
1420 | ||
1421 | return 0; | |
1422 | } | |
1423 | ||
1424 | #ifdef CONFIG_PM | |
e5378ca8 | 1425 | static int mmci_suspend(struct amba_device *dev, pm_message_t state) |
1da177e4 LT |
1426 | { |
1427 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
1428 | int ret = 0; | |
1429 | ||
1430 | if (mmc) { | |
1431 | struct mmci_host *host = mmc_priv(mmc); | |
1432 | ||
1a13f8fa | 1433 | ret = mmc_suspend_host(mmc); |
1da177e4 LT |
1434 | if (ret == 0) |
1435 | writel(0, host->base + MMCIMASK0); | |
1436 | } | |
1437 | ||
1438 | return ret; | |
1439 | } | |
1440 | ||
1441 | static int mmci_resume(struct amba_device *dev) | |
1442 | { | |
1443 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
1444 | int ret = 0; | |
1445 | ||
1446 | if (mmc) { | |
1447 | struct mmci_host *host = mmc_priv(mmc); | |
1448 | ||
1449 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); | |
1450 | ||
1451 | ret = mmc_resume_host(mmc); | |
1452 | } | |
1453 | ||
1454 | return ret; | |
1455 | } | |
1456 | #else | |
1457 | #define mmci_suspend NULL | |
1458 | #define mmci_resume NULL | |
1459 | #endif | |
1460 | ||
1461 | static struct amba_id mmci_ids[] = { | |
1462 | { | |
1463 | .id = 0x00041180, | |
768fbc18 | 1464 | .mask = 0xff0fffff, |
4956e109 | 1465 | .data = &variant_arm, |
1da177e4 | 1466 | }, |
768fbc18 PM |
1467 | { |
1468 | .id = 0x01041180, | |
1469 | .mask = 0xff0fffff, | |
1470 | .data = &variant_arm_extended_fifo, | |
1471 | }, | |
1da177e4 LT |
1472 | { |
1473 | .id = 0x00041181, | |
1474 | .mask = 0x000fffff, | |
4956e109 | 1475 | .data = &variant_arm, |
1da177e4 | 1476 | }, |
cc30d60e LW |
1477 | /* ST Micro variants */ |
1478 | { | |
1479 | .id = 0x00180180, | |
1480 | .mask = 0x00ffffff, | |
4956e109 | 1481 | .data = &variant_u300, |
cc30d60e LW |
1482 | }, |
1483 | { | |
1484 | .id = 0x00280180, | |
1485 | .mask = 0x00ffffff, | |
4956e109 RV |
1486 | .data = &variant_u300, |
1487 | }, | |
1488 | { | |
1489 | .id = 0x00480180, | |
1784b157 | 1490 | .mask = 0xf0ffffff, |
4956e109 | 1491 | .data = &variant_ux500, |
cc30d60e | 1492 | }, |
1784b157 PL |
1493 | { |
1494 | .id = 0x10480180, | |
1495 | .mask = 0xf0ffffff, | |
1496 | .data = &variant_ux500v2, | |
1497 | }, | |
1da177e4 LT |
1498 | { 0, 0 }, |
1499 | }; | |
1500 | ||
1501 | static struct amba_driver mmci_driver = { | |
1502 | .drv = { | |
1503 | .name = DRIVER_NAME, | |
1504 | }, | |
1505 | .probe = mmci_probe, | |
6dc4a47a | 1506 | .remove = __devexit_p(mmci_remove), |
1da177e4 LT |
1507 | .suspend = mmci_suspend, |
1508 | .resume = mmci_resume, | |
1509 | .id_table = mmci_ids, | |
1510 | }; | |
1511 | ||
1512 | static int __init mmci_init(void) | |
1513 | { | |
1514 | return amba_driver_register(&mmci_driver); | |
1515 | } | |
1516 | ||
1517 | static void __exit mmci_exit(void) | |
1518 | { | |
1519 | amba_driver_unregister(&mmci_driver); | |
1520 | } | |
1521 | ||
1522 | module_init(mmci_init); | |
1523 | module_exit(mmci_exit); | |
1524 | module_param(fmax, uint, 0444); | |
1525 | ||
1526 | MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); | |
1527 | MODULE_LICENSE("GPL"); |