Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. | |
c8ebae37 | 5 | * Copyright (C) 2010 ST-Ericsson SA |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/device.h> | |
ef289982 | 16 | #include <linux/io.h> |
1da177e4 | 17 | #include <linux/interrupt.h> |
613b152c | 18 | #include <linux/kernel.h> |
000bc9d5 | 19 | #include <linux/slab.h> |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/err.h> | |
22 | #include <linux/highmem.h> | |
019a5f56 | 23 | #include <linux/log2.h> |
70be208f | 24 | #include <linux/mmc/pm.h> |
1da177e4 | 25 | #include <linux/mmc/host.h> |
34177802 | 26 | #include <linux/mmc/card.h> |
d2762090 | 27 | #include <linux/mmc/slot-gpio.h> |
a62c80e5 | 28 | #include <linux/amba/bus.h> |
f8ce2547 | 29 | #include <linux/clk.h> |
bd6dee6f | 30 | #include <linux/scatterlist.h> |
89001446 | 31 | #include <linux/gpio.h> |
9a597016 | 32 | #include <linux/of_gpio.h> |
34e84f39 | 33 | #include <linux/regulator/consumer.h> |
c8ebae37 RK |
34 | #include <linux/dmaengine.h> |
35 | #include <linux/dma-mapping.h> | |
36 | #include <linux/amba/mmci.h> | |
1c3be369 | 37 | #include <linux/pm_runtime.h> |
258aea76 | 38 | #include <linux/types.h> |
a9a83785 | 39 | #include <linux/pinctrl/consumer.h> |
1da177e4 | 40 | |
7b09cdac | 41 | #include <asm/div64.h> |
1da177e4 | 42 | #include <asm/io.h> |
c6b8fdad | 43 | #include <asm/sizes.h> |
1da177e4 LT |
44 | |
45 | #include "mmci.h" | |
46 | ||
47 | #define DRIVER_NAME "mmci-pl18x" | |
48 | ||
1da177e4 LT |
49 | static unsigned int fmax = 515633; |
50 | ||
4956e109 RV |
51 | /** |
52 | * struct variant_data - MMCI variant-specific quirks | |
53 | * @clkreg: default value for MCICLOCK register | |
4380c14f | 54 | * @clkreg_enable: enable value for MMCICLOCK register |
e1412d85 | 55 | * @clkreg_8bit_bus_enable: enable value for 8 bit bus |
e8740644 | 56 | * @clkreg_neg_edge_enable: enable value for inverted data/cmd output |
08458ef6 | 57 | * @datalength_bits: number of bits in the MMCIDATALENGTH register |
8301bb68 RV |
58 | * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY |
59 | * is asserted (likewise for RX) | |
60 | * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY | |
61 | * is asserted (likewise for RX) | |
ae7b0061 | 62 | * @data_cmd_enable: enable value for data commands. |
34177802 | 63 | * @sdio: variant supports SDIO |
b70a67f9 | 64 | * @st_clkdiv: true if using a ST-specific clock divider algorithm |
e17dca2b | 65 | * @datactrl_mask_ddrmode: ddr mode mask in datactrl register. |
1784b157 | 66 | * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register |
ff783233 SK |
67 | * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl |
68 | * register | |
7d72a1d4 | 69 | * @pwrreg_powerup: power up value for MMCIPOWER register |
dc6500bf | 70 | * @f_max: maximum clk frequency supported by the controller. |
4d1a3a0d | 71 | * @signal_direction: input/out direction of bus signals can be indicated |
f4670dae | 72 | * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock |
01259620 | 73 | * @busy_detect: true if busy detection on dat0 is supported |
1ff44433 | 74 | * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply |
4956e109 RV |
75 | */ |
76 | struct variant_data { | |
77 | unsigned int clkreg; | |
4380c14f | 78 | unsigned int clkreg_enable; |
e1412d85 | 79 | unsigned int clkreg_8bit_bus_enable; |
e8740644 | 80 | unsigned int clkreg_neg_edge_enable; |
08458ef6 | 81 | unsigned int datalength_bits; |
8301bb68 RV |
82 | unsigned int fifosize; |
83 | unsigned int fifohalfsize; | |
ae7b0061 | 84 | unsigned int data_cmd_enable; |
e17dca2b | 85 | unsigned int datactrl_mask_ddrmode; |
34177802 | 86 | bool sdio; |
b70a67f9 | 87 | bool st_clkdiv; |
1784b157 | 88 | bool blksz_datactrl16; |
ff783233 | 89 | bool blksz_datactrl4; |
7d72a1d4 | 90 | u32 pwrreg_powerup; |
dc6500bf | 91 | u32 f_max; |
4d1a3a0d | 92 | bool signal_direction; |
f4670dae | 93 | bool pwrreg_clkgate; |
01259620 | 94 | bool busy_detect; |
1ff44433 | 95 | bool pwrreg_nopower; |
4956e109 RV |
96 | }; |
97 | ||
98 | static struct variant_data variant_arm = { | |
8301bb68 RV |
99 | .fifosize = 16 * 4, |
100 | .fifohalfsize = 8 * 4, | |
08458ef6 | 101 | .datalength_bits = 16, |
7d72a1d4 | 102 | .pwrreg_powerup = MCI_PWR_UP, |
dc6500bf | 103 | .f_max = 100000000, |
4956e109 RV |
104 | }; |
105 | ||
768fbc18 PM |
106 | static struct variant_data variant_arm_extended_fifo = { |
107 | .fifosize = 128 * 4, | |
108 | .fifohalfsize = 64 * 4, | |
109 | .datalength_bits = 16, | |
7d72a1d4 | 110 | .pwrreg_powerup = MCI_PWR_UP, |
dc6500bf | 111 | .f_max = 100000000, |
768fbc18 PM |
112 | }; |
113 | ||
3a37298a PM |
114 | static struct variant_data variant_arm_extended_fifo_hwfc = { |
115 | .fifosize = 128 * 4, | |
116 | .fifohalfsize = 64 * 4, | |
117 | .clkreg_enable = MCI_ARM_HWFCEN, | |
118 | .datalength_bits = 16, | |
119 | .pwrreg_powerup = MCI_PWR_UP, | |
dc6500bf | 120 | .f_max = 100000000, |
3a37298a PM |
121 | }; |
122 | ||
4956e109 | 123 | static struct variant_data variant_u300 = { |
8301bb68 RV |
124 | .fifosize = 16 * 4, |
125 | .fifohalfsize = 8 * 4, | |
49ac215e | 126 | .clkreg_enable = MCI_ST_U300_HWFCEN, |
e1412d85 | 127 | .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, |
08458ef6 | 128 | .datalength_bits = 16, |
34177802 | 129 | .sdio = true, |
7d72a1d4 | 130 | .pwrreg_powerup = MCI_PWR_ON, |
dc6500bf | 131 | .f_max = 100000000, |
4d1a3a0d | 132 | .signal_direction = true, |
f4670dae | 133 | .pwrreg_clkgate = true, |
1ff44433 | 134 | .pwrreg_nopower = true, |
4956e109 RV |
135 | }; |
136 | ||
34fd4213 LW |
137 | static struct variant_data variant_nomadik = { |
138 | .fifosize = 16 * 4, | |
139 | .fifohalfsize = 8 * 4, | |
140 | .clkreg = MCI_CLK_ENABLE, | |
141 | .datalength_bits = 24, | |
142 | .sdio = true, | |
143 | .st_clkdiv = true, | |
144 | .pwrreg_powerup = MCI_PWR_ON, | |
dc6500bf | 145 | .f_max = 100000000, |
34fd4213 | 146 | .signal_direction = true, |
f4670dae | 147 | .pwrreg_clkgate = true, |
1ff44433 | 148 | .pwrreg_nopower = true, |
34fd4213 LW |
149 | }; |
150 | ||
4956e109 | 151 | static struct variant_data variant_ux500 = { |
8301bb68 RV |
152 | .fifosize = 30 * 4, |
153 | .fifohalfsize = 8 * 4, | |
4956e109 | 154 | .clkreg = MCI_CLK_ENABLE, |
49ac215e | 155 | .clkreg_enable = MCI_ST_UX500_HWFCEN, |
e1412d85 | 156 | .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, |
e8740644 | 157 | .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, |
08458ef6 | 158 | .datalength_bits = 24, |
34177802 | 159 | .sdio = true, |
b70a67f9 | 160 | .st_clkdiv = true, |
7d72a1d4 | 161 | .pwrreg_powerup = MCI_PWR_ON, |
dc6500bf | 162 | .f_max = 100000000, |
4d1a3a0d | 163 | .signal_direction = true, |
f4670dae | 164 | .pwrreg_clkgate = true, |
01259620 | 165 | .busy_detect = true, |
1ff44433 | 166 | .pwrreg_nopower = true, |
4956e109 | 167 | }; |
b70a67f9 | 168 | |
1784b157 PL |
169 | static struct variant_data variant_ux500v2 = { |
170 | .fifosize = 30 * 4, | |
171 | .fifohalfsize = 8 * 4, | |
172 | .clkreg = MCI_CLK_ENABLE, | |
173 | .clkreg_enable = MCI_ST_UX500_HWFCEN, | |
e1412d85 | 174 | .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, |
e8740644 | 175 | .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, |
e17dca2b | 176 | .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE, |
1784b157 PL |
177 | .datalength_bits = 24, |
178 | .sdio = true, | |
179 | .st_clkdiv = true, | |
180 | .blksz_datactrl16 = true, | |
7d72a1d4 | 181 | .pwrreg_powerup = MCI_PWR_ON, |
dc6500bf | 182 | .f_max = 100000000, |
4d1a3a0d | 183 | .signal_direction = true, |
f4670dae | 184 | .pwrreg_clkgate = true, |
01259620 | 185 | .busy_detect = true, |
1ff44433 | 186 | .pwrreg_nopower = true, |
1784b157 PL |
187 | }; |
188 | ||
01259620 UH |
189 | static int mmci_card_busy(struct mmc_host *mmc) |
190 | { | |
191 | struct mmci_host *host = mmc_priv(mmc); | |
192 | unsigned long flags; | |
193 | int busy = 0; | |
194 | ||
195 | pm_runtime_get_sync(mmc_dev(mmc)); | |
196 | ||
197 | spin_lock_irqsave(&host->lock, flags); | |
198 | if (readl(host->base + MMCISTATUS) & MCI_ST_CARDBUSY) | |
199 | busy = 1; | |
200 | spin_unlock_irqrestore(&host->lock, flags); | |
201 | ||
202 | pm_runtime_mark_last_busy(mmc_dev(mmc)); | |
203 | pm_runtime_put_autosuspend(mmc_dev(mmc)); | |
204 | ||
205 | return busy; | |
206 | } | |
207 | ||
653a761e UH |
208 | /* |
209 | * Validate mmc prerequisites | |
210 | */ | |
211 | static int mmci_validate_data(struct mmci_host *host, | |
212 | struct mmc_data *data) | |
213 | { | |
214 | if (!data) | |
215 | return 0; | |
216 | ||
217 | if (!is_power_of_2(data->blksz)) { | |
218 | dev_err(mmc_dev(host->mmc), | |
219 | "unsupported block size (%d bytes)\n", data->blksz); | |
220 | return -EINVAL; | |
221 | } | |
222 | ||
223 | return 0; | |
224 | } | |
225 | ||
f829c042 UH |
226 | static void mmci_reg_delay(struct mmci_host *host) |
227 | { | |
228 | /* | |
229 | * According to the spec, at least three feedback clock cycles | |
230 | * of max 52 MHz must pass between two writes to the MMCICLOCK reg. | |
231 | * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. | |
232 | * Worst delay time during card init is at 100 kHz => 30 us. | |
233 | * Worst delay time when up and running is at 25 MHz => 120 ns. | |
234 | */ | |
235 | if (host->cclk < 25000000) | |
236 | udelay(30); | |
237 | else | |
238 | ndelay(120); | |
239 | } | |
240 | ||
7437cfa5 UH |
241 | /* |
242 | * This must be called with host->lock held | |
243 | */ | |
244 | static void mmci_write_clkreg(struct mmci_host *host, u32 clk) | |
245 | { | |
246 | if (host->clk_reg != clk) { | |
247 | host->clk_reg = clk; | |
248 | writel(clk, host->base + MMCICLOCK); | |
249 | } | |
250 | } | |
251 | ||
252 | /* | |
253 | * This must be called with host->lock held | |
254 | */ | |
255 | static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) | |
256 | { | |
257 | if (host->pwr_reg != pwr) { | |
258 | host->pwr_reg = pwr; | |
259 | writel(pwr, host->base + MMCIPOWER); | |
260 | } | |
261 | } | |
262 | ||
9cc639a2 UH |
263 | /* |
264 | * This must be called with host->lock held | |
265 | */ | |
266 | static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) | |
267 | { | |
01259620 UH |
268 | /* Keep ST Micro busy mode if enabled */ |
269 | datactrl |= host->datactrl_reg & MCI_ST_DPSM_BUSYMODE; | |
270 | ||
9cc639a2 UH |
271 | if (host->datactrl_reg != datactrl) { |
272 | host->datactrl_reg = datactrl; | |
273 | writel(datactrl, host->base + MMCIDATACTRL); | |
274 | } | |
275 | } | |
276 | ||
a6a6464a LW |
277 | /* |
278 | * This must be called with host->lock held | |
279 | */ | |
280 | static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) | |
281 | { | |
4956e109 RV |
282 | struct variant_data *variant = host->variant; |
283 | u32 clk = variant->clkreg; | |
a6a6464a | 284 | |
c58a8509 UH |
285 | /* Make sure cclk reflects the current calculated clock */ |
286 | host->cclk = 0; | |
287 | ||
a6a6464a LW |
288 | if (desired) { |
289 | if (desired >= host->mclk) { | |
991a86e1 | 290 | clk = MCI_CLK_BYPASS; |
399bc486 LW |
291 | if (variant->st_clkdiv) |
292 | clk |= MCI_ST_UX500_NEG_EDGE; | |
a6a6464a | 293 | host->cclk = host->mclk; |
b70a67f9 LW |
294 | } else if (variant->st_clkdiv) { |
295 | /* | |
296 | * DB8500 TRM says f = mclk / (clkdiv + 2) | |
297 | * => clkdiv = (mclk / f) - 2 | |
298 | * Round the divider up so we don't exceed the max | |
299 | * frequency | |
300 | */ | |
301 | clk = DIV_ROUND_UP(host->mclk, desired) - 2; | |
302 | if (clk >= 256) | |
303 | clk = 255; | |
304 | host->cclk = host->mclk / (clk + 2); | |
a6a6464a | 305 | } else { |
b70a67f9 LW |
306 | /* |
307 | * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) | |
308 | * => clkdiv = mclk / (2 * f) - 1 | |
309 | */ | |
a6a6464a LW |
310 | clk = host->mclk / (2 * desired) - 1; |
311 | if (clk >= 256) | |
312 | clk = 255; | |
313 | host->cclk = host->mclk / (2 * (clk + 1)); | |
314 | } | |
4380c14f RV |
315 | |
316 | clk |= variant->clkreg_enable; | |
a6a6464a LW |
317 | clk |= MCI_CLK_ENABLE; |
318 | /* This hasn't proven to be worthwhile */ | |
319 | /* clk |= MCI_CLK_PWRSAVE; */ | |
320 | } | |
321 | ||
c58a8509 UH |
322 | /* Set actual clock for debug */ |
323 | host->mmc->actual_clock = host->cclk; | |
324 | ||
9e6c82cd | 325 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) |
771dc157 LW |
326 | clk |= MCI_4BIT_BUS; |
327 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) | |
e1412d85 | 328 | clk |= variant->clkreg_8bit_bus_enable; |
9e6c82cd | 329 | |
6dad6c95 SJ |
330 | if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || |
331 | host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) | |
e8740644 | 332 | clk |= variant->clkreg_neg_edge_enable; |
6dbb6ee0 | 333 | |
7437cfa5 | 334 | mmci_write_clkreg(host, clk); |
a6a6464a LW |
335 | } |
336 | ||
1da177e4 LT |
337 | static void |
338 | mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) | |
339 | { | |
340 | writel(0, host->base + MMCICOMMAND); | |
341 | ||
e47c222b RK |
342 | BUG_ON(host->data); |
343 | ||
1da177e4 LT |
344 | host->mrq = NULL; |
345 | host->cmd = NULL; | |
346 | ||
1da177e4 | 347 | mmc_request_done(host->mmc, mrq); |
2cd976c4 UH |
348 | |
349 | pm_runtime_mark_last_busy(mmc_dev(host->mmc)); | |
350 | pm_runtime_put_autosuspend(mmc_dev(host->mmc)); | |
1da177e4 LT |
351 | } |
352 | ||
2686b4b4 LW |
353 | static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) |
354 | { | |
355 | void __iomem *base = host->base; | |
356 | ||
357 | if (host->singleirq) { | |
358 | unsigned int mask0 = readl(base + MMCIMASK0); | |
359 | ||
360 | mask0 &= ~MCI_IRQ1MASK; | |
361 | mask0 |= mask; | |
362 | ||
363 | writel(mask0, base + MMCIMASK0); | |
364 | } | |
365 | ||
366 | writel(mask, base + MMCIMASK1); | |
367 | } | |
368 | ||
1da177e4 LT |
369 | static void mmci_stop_data(struct mmci_host *host) |
370 | { | |
9cc639a2 | 371 | mmci_write_datactrlreg(host, 0); |
2686b4b4 | 372 | mmci_set_mask1(host, 0); |
1da177e4 LT |
373 | host->data = NULL; |
374 | } | |
375 | ||
4ce1d6cb RV |
376 | static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) |
377 | { | |
378 | unsigned int flags = SG_MITER_ATOMIC; | |
379 | ||
380 | if (data->flags & MMC_DATA_READ) | |
381 | flags |= SG_MITER_TO_SG; | |
382 | else | |
383 | flags |= SG_MITER_FROM_SG; | |
384 | ||
385 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); | |
386 | } | |
387 | ||
c8ebae37 RK |
388 | /* |
389 | * All the DMA operation mode stuff goes inside this ifdef. | |
390 | * This assumes that you have a generic DMA device interface, | |
391 | * no custom DMA interfaces are supported. | |
392 | */ | |
393 | #ifdef CONFIG_DMA_ENGINE | |
c3be1efd | 394 | static void mmci_dma_setup(struct mmci_host *host) |
c8ebae37 | 395 | { |
c8ebae37 RK |
396 | const char *rxname, *txname; |
397 | dma_cap_mask_t mask; | |
398 | ||
1fd83f0e LJ |
399 | host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx"); |
400 | host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx"); | |
c8ebae37 | 401 | |
58c7ccbf PF |
402 | /* initialize pre request cookie */ |
403 | host->next_data.cookie = 1; | |
404 | ||
c8ebae37 RK |
405 | /* Try to acquire a generic DMA engine slave channel */ |
406 | dma_cap_zero(mask); | |
407 | dma_cap_set(DMA_SLAVE, mask); | |
408 | ||
1fd83f0e LJ |
409 | /* |
410 | * If only an RX channel is specified, the driver will | |
411 | * attempt to use it bidirectionally, however if it is | |
412 | * is specified but cannot be located, DMA will be disabled. | |
413 | */ | |
414 | if (host->dma_rx_channel && !host->dma_tx_channel) | |
415 | host->dma_tx_channel = host->dma_rx_channel; | |
416 | ||
c8ebae37 RK |
417 | if (host->dma_rx_channel) |
418 | rxname = dma_chan_name(host->dma_rx_channel); | |
419 | else | |
420 | rxname = "none"; | |
421 | ||
422 | if (host->dma_tx_channel) | |
423 | txname = dma_chan_name(host->dma_tx_channel); | |
424 | else | |
425 | txname = "none"; | |
426 | ||
427 | dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", | |
428 | rxname, txname); | |
429 | ||
430 | /* | |
431 | * Limit the maximum segment size in any SG entry according to | |
432 | * the parameters of the DMA engine device. | |
433 | */ | |
434 | if (host->dma_tx_channel) { | |
435 | struct device *dev = host->dma_tx_channel->device->dev; | |
436 | unsigned int max_seg_size = dma_get_max_seg_size(dev); | |
437 | ||
438 | if (max_seg_size < host->mmc->max_seg_size) | |
439 | host->mmc->max_seg_size = max_seg_size; | |
440 | } | |
441 | if (host->dma_rx_channel) { | |
442 | struct device *dev = host->dma_rx_channel->device->dev; | |
443 | unsigned int max_seg_size = dma_get_max_seg_size(dev); | |
444 | ||
445 | if (max_seg_size < host->mmc->max_seg_size) | |
446 | host->mmc->max_seg_size = max_seg_size; | |
447 | } | |
448 | } | |
449 | ||
450 | /* | |
6e0ee714 | 451 | * This is used in or so inline it |
c8ebae37 RK |
452 | * so it can be discarded. |
453 | */ | |
454 | static inline void mmci_dma_release(struct mmci_host *host) | |
455 | { | |
c8ebae37 RK |
456 | if (host->dma_rx_channel) |
457 | dma_release_channel(host->dma_rx_channel); | |
8c3a05b4 | 458 | if (host->dma_tx_channel) |
c8ebae37 RK |
459 | dma_release_channel(host->dma_tx_channel); |
460 | host->dma_rx_channel = host->dma_tx_channel = NULL; | |
461 | } | |
462 | ||
653a761e UH |
463 | static void mmci_dma_data_error(struct mmci_host *host) |
464 | { | |
465 | dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); | |
466 | dmaengine_terminate_all(host->dma_current); | |
467 | host->dma_current = NULL; | |
468 | host->dma_desc_current = NULL; | |
469 | host->data->host_cookie = 0; | |
470 | } | |
471 | ||
c8ebae37 RK |
472 | static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) |
473 | { | |
653a761e | 474 | struct dma_chan *chan; |
c8ebae37 | 475 | enum dma_data_direction dir; |
653a761e UH |
476 | |
477 | if (data->flags & MMC_DATA_READ) { | |
478 | dir = DMA_FROM_DEVICE; | |
479 | chan = host->dma_rx_channel; | |
480 | } else { | |
481 | dir = DMA_TO_DEVICE; | |
482 | chan = host->dma_tx_channel; | |
483 | } | |
484 | ||
485 | dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); | |
486 | } | |
487 | ||
488 | static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) | |
489 | { | |
c8ebae37 RK |
490 | u32 status; |
491 | int i; | |
492 | ||
493 | /* Wait up to 1ms for the DMA to complete */ | |
494 | for (i = 0; ; i++) { | |
495 | status = readl(host->base + MMCISTATUS); | |
496 | if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) | |
497 | break; | |
498 | udelay(10); | |
499 | } | |
500 | ||
501 | /* | |
502 | * Check to see whether we still have some data left in the FIFO - | |
503 | * this catches DMA controllers which are unable to monitor the | |
504 | * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- | |
505 | * contiguous buffers. On TX, we'll get a FIFO underrun error. | |
506 | */ | |
507 | if (status & MCI_RXDATAAVLBLMASK) { | |
653a761e | 508 | mmci_dma_data_error(host); |
c8ebae37 RK |
509 | if (!data->error) |
510 | data->error = -EIO; | |
511 | } | |
512 | ||
58c7ccbf | 513 | if (!data->host_cookie) |
653a761e | 514 | mmci_dma_unmap(host, data); |
c8ebae37 RK |
515 | |
516 | /* | |
517 | * Use of DMA with scatter-gather is impossible. | |
518 | * Give up with DMA and switch back to PIO mode. | |
519 | */ | |
520 | if (status & MCI_RXDATAAVLBLMASK) { | |
521 | dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); | |
522 | mmci_dma_release(host); | |
523 | } | |
c8ebae37 | 524 | |
653a761e UH |
525 | host->dma_current = NULL; |
526 | host->dma_desc_current = NULL; | |
c8ebae37 RK |
527 | } |
528 | ||
653a761e UH |
529 | /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ |
530 | static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, | |
531 | struct dma_chan **dma_chan, | |
532 | struct dma_async_tx_descriptor **dma_desc) | |
c8ebae37 RK |
533 | { |
534 | struct variant_data *variant = host->variant; | |
535 | struct dma_slave_config conf = { | |
536 | .src_addr = host->phybase + MMCIFIFO, | |
537 | .dst_addr = host->phybase + MMCIFIFO, | |
538 | .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
539 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
540 | .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ | |
541 | .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ | |
258aea76 | 542 | .device_fc = false, |
c8ebae37 | 543 | }; |
c8ebae37 RK |
544 | struct dma_chan *chan; |
545 | struct dma_device *device; | |
546 | struct dma_async_tx_descriptor *desc; | |
05f5799c | 547 | enum dma_data_direction buffer_dirn; |
c8ebae37 RK |
548 | int nr_sg; |
549 | ||
c8ebae37 | 550 | if (data->flags & MMC_DATA_READ) { |
05f5799c VK |
551 | conf.direction = DMA_DEV_TO_MEM; |
552 | buffer_dirn = DMA_FROM_DEVICE; | |
c8ebae37 RK |
553 | chan = host->dma_rx_channel; |
554 | } else { | |
05f5799c VK |
555 | conf.direction = DMA_MEM_TO_DEV; |
556 | buffer_dirn = DMA_TO_DEVICE; | |
c8ebae37 RK |
557 | chan = host->dma_tx_channel; |
558 | } | |
559 | ||
560 | /* If there's no DMA channel, fall back to PIO */ | |
561 | if (!chan) | |
562 | return -EINVAL; | |
563 | ||
564 | /* If less than or equal to the fifo size, don't bother with DMA */ | |
58c7ccbf | 565 | if (data->blksz * data->blocks <= variant->fifosize) |
c8ebae37 RK |
566 | return -EINVAL; |
567 | ||
568 | device = chan->device; | |
05f5799c | 569 | nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); |
c8ebae37 RK |
570 | if (nr_sg == 0) |
571 | return -EINVAL; | |
572 | ||
573 | dmaengine_slave_config(chan, &conf); | |
16052827 | 574 | desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, |
c8ebae37 RK |
575 | conf.direction, DMA_CTRL_ACK); |
576 | if (!desc) | |
577 | goto unmap_exit; | |
578 | ||
653a761e UH |
579 | *dma_chan = chan; |
580 | *dma_desc = desc; | |
58c7ccbf PF |
581 | |
582 | return 0; | |
c8ebae37 | 583 | |
58c7ccbf | 584 | unmap_exit: |
05f5799c | 585 | dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); |
58c7ccbf PF |
586 | return -ENOMEM; |
587 | } | |
588 | ||
653a761e UH |
589 | static inline int mmci_dma_prep_data(struct mmci_host *host, |
590 | struct mmc_data *data) | |
591 | { | |
592 | /* Check if next job is already prepared. */ | |
593 | if (host->dma_current && host->dma_desc_current) | |
594 | return 0; | |
595 | ||
596 | /* No job were prepared thus do it now. */ | |
597 | return __mmci_dma_prep_data(host, data, &host->dma_current, | |
598 | &host->dma_desc_current); | |
599 | } | |
600 | ||
601 | static inline int mmci_dma_prep_next(struct mmci_host *host, | |
602 | struct mmc_data *data) | |
603 | { | |
604 | struct mmci_host_next *nd = &host->next_data; | |
605 | return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc); | |
606 | } | |
607 | ||
58c7ccbf PF |
608 | static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) |
609 | { | |
610 | int ret; | |
611 | struct mmc_data *data = host->data; | |
612 | ||
653a761e | 613 | ret = mmci_dma_prep_data(host, host->data); |
58c7ccbf PF |
614 | if (ret) |
615 | return ret; | |
616 | ||
617 | /* Okay, go for it. */ | |
c8ebae37 RK |
618 | dev_vdbg(mmc_dev(host->mmc), |
619 | "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", | |
620 | data->sg_len, data->blksz, data->blocks, data->flags); | |
58c7ccbf PF |
621 | dmaengine_submit(host->dma_desc_current); |
622 | dma_async_issue_pending(host->dma_current); | |
c8ebae37 RK |
623 | |
624 | datactrl |= MCI_DPSM_DMAENABLE; | |
625 | ||
626 | /* Trigger the DMA transfer */ | |
9cc639a2 | 627 | mmci_write_datactrlreg(host, datactrl); |
c8ebae37 RK |
628 | |
629 | /* | |
630 | * Let the MMCI say when the data is ended and it's time | |
631 | * to fire next DMA request. When that happens, MMCI will | |
632 | * call mmci_data_end() | |
633 | */ | |
634 | writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, | |
635 | host->base + MMCIMASK0); | |
636 | return 0; | |
58c7ccbf | 637 | } |
c8ebae37 | 638 | |
58c7ccbf PF |
639 | static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) |
640 | { | |
641 | struct mmci_host_next *next = &host->next_data; | |
642 | ||
653a761e UH |
643 | WARN_ON(data->host_cookie && data->host_cookie != next->cookie); |
644 | WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan)); | |
58c7ccbf PF |
645 | |
646 | host->dma_desc_current = next->dma_desc; | |
647 | host->dma_current = next->dma_chan; | |
58c7ccbf PF |
648 | next->dma_desc = NULL; |
649 | next->dma_chan = NULL; | |
c8ebae37 | 650 | } |
58c7ccbf PF |
651 | |
652 | static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, | |
653 | bool is_first_req) | |
654 | { | |
655 | struct mmci_host *host = mmc_priv(mmc); | |
656 | struct mmc_data *data = mrq->data; | |
657 | struct mmci_host_next *nd = &host->next_data; | |
658 | ||
659 | if (!data) | |
660 | return; | |
661 | ||
653a761e UH |
662 | BUG_ON(data->host_cookie); |
663 | ||
664 | if (mmci_validate_data(host, data)) | |
58c7ccbf | 665 | return; |
58c7ccbf | 666 | |
653a761e UH |
667 | if (!mmci_dma_prep_next(host, data)) |
668 | data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; | |
58c7ccbf PF |
669 | } |
670 | ||
671 | static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, | |
672 | int err) | |
673 | { | |
674 | struct mmci_host *host = mmc_priv(mmc); | |
675 | struct mmc_data *data = mrq->data; | |
58c7ccbf | 676 | |
653a761e | 677 | if (!data || !data->host_cookie) |
58c7ccbf PF |
678 | return; |
679 | ||
653a761e | 680 | mmci_dma_unmap(host, data); |
58c7ccbf | 681 | |
653a761e UH |
682 | if (err) { |
683 | struct mmci_host_next *next = &host->next_data; | |
684 | struct dma_chan *chan; | |
685 | if (data->flags & MMC_DATA_READ) | |
686 | chan = host->dma_rx_channel; | |
687 | else | |
688 | chan = host->dma_tx_channel; | |
689 | dmaengine_terminate_all(chan); | |
58c7ccbf | 690 | |
653a761e UH |
691 | next->dma_desc = NULL; |
692 | next->dma_chan = NULL; | |
58c7ccbf PF |
693 | } |
694 | } | |
695 | ||
c8ebae37 RK |
696 | #else |
697 | /* Blank functions if the DMA engine is not available */ | |
58c7ccbf PF |
698 | static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) |
699 | { | |
700 | } | |
c8ebae37 RK |
701 | static inline void mmci_dma_setup(struct mmci_host *host) |
702 | { | |
703 | } | |
704 | ||
705 | static inline void mmci_dma_release(struct mmci_host *host) | |
706 | { | |
707 | } | |
708 | ||
709 | static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) | |
710 | { | |
711 | } | |
712 | ||
653a761e UH |
713 | static inline void mmci_dma_finalize(struct mmci_host *host, |
714 | struct mmc_data *data) | |
715 | { | |
716 | } | |
717 | ||
c8ebae37 RK |
718 | static inline void mmci_dma_data_error(struct mmci_host *host) |
719 | { | |
720 | } | |
721 | ||
722 | static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) | |
723 | { | |
724 | return -ENOSYS; | |
725 | } | |
58c7ccbf PF |
726 | |
727 | #define mmci_pre_request NULL | |
728 | #define mmci_post_request NULL | |
729 | ||
c8ebae37 RK |
730 | #endif |
731 | ||
1da177e4 LT |
732 | static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) |
733 | { | |
8301bb68 | 734 | struct variant_data *variant = host->variant; |
1da177e4 | 735 | unsigned int datactrl, timeout, irqmask; |
7b09cdac | 736 | unsigned long long clks; |
1da177e4 | 737 | void __iomem *base; |
3bc87f24 | 738 | int blksz_bits; |
1da177e4 | 739 | |
64de0289 LW |
740 | dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", |
741 | data->blksz, data->blocks, data->flags); | |
1da177e4 LT |
742 | |
743 | host->data = data; | |
528320db | 744 | host->size = data->blksz * data->blocks; |
51d4375d | 745 | data->bytes_xfered = 0; |
1da177e4 | 746 | |
7b09cdac | 747 | clks = (unsigned long long)data->timeout_ns * host->cclk; |
c4a35769 | 748 | do_div(clks, NSEC_PER_SEC); |
7b09cdac RK |
749 | |
750 | timeout = data->timeout_clks + (unsigned int)clks; | |
1da177e4 LT |
751 | |
752 | base = host->base; | |
753 | writel(timeout, base + MMCIDATATIMER); | |
754 | writel(host->size, base + MMCIDATALENGTH); | |
755 | ||
3bc87f24 RK |
756 | blksz_bits = ffs(data->blksz) - 1; |
757 | BUG_ON(1 << blksz_bits != data->blksz); | |
758 | ||
1784b157 PL |
759 | if (variant->blksz_datactrl16) |
760 | datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); | |
ff783233 SK |
761 | else if (variant->blksz_datactrl4) |
762 | datactrl = MCI_DPSM_ENABLE | (data->blksz << 4); | |
1784b157 PL |
763 | else |
764 | datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; | |
c8ebae37 RK |
765 | |
766 | if (data->flags & MMC_DATA_READ) | |
1da177e4 | 767 | datactrl |= MCI_DPSM_DIRECTION; |
c8ebae37 | 768 | |
7258db7e UH |
769 | /* The ST Micro variants has a special bit to enable SDIO */ |
770 | if (variant->sdio && host->mmc->card) | |
06c1a121 UH |
771 | if (mmc_card_sdio(host->mmc->card)) { |
772 | /* | |
773 | * The ST Micro variants has a special bit | |
774 | * to enable SDIO. | |
775 | */ | |
776 | u32 clk; | |
777 | ||
7258db7e UH |
778 | datactrl |= MCI_ST_DPSM_SDIOEN; |
779 | ||
06c1a121 | 780 | /* |
70ac0935 UH |
781 | * The ST Micro variant for SDIO small write transfers |
782 | * needs to have clock H/W flow control disabled, | |
783 | * otherwise the transfer will not start. The threshold | |
784 | * depends on the rate of MCLK. | |
06c1a121 | 785 | */ |
70ac0935 UH |
786 | if (data->flags & MMC_DATA_WRITE && |
787 | (host->size < 8 || | |
788 | (host->size <= 8 && host->mclk > 50000000))) | |
06c1a121 UH |
789 | clk = host->clk_reg & ~variant->clkreg_enable; |
790 | else | |
791 | clk = host->clk_reg | variant->clkreg_enable; | |
792 | ||
793 | mmci_write_clkreg(host, clk); | |
794 | } | |
795 | ||
6dad6c95 SJ |
796 | if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || |
797 | host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) | |
e17dca2b | 798 | datactrl |= variant->datactrl_mask_ddrmode; |
6dbb6ee0 | 799 | |
c8ebae37 RK |
800 | /* |
801 | * Attempt to use DMA operation mode, if this | |
802 | * should fail, fall back to PIO mode | |
803 | */ | |
804 | if (!mmci_dma_start_data(host, datactrl)) | |
805 | return; | |
806 | ||
807 | /* IRQ mode, map the SG list for CPU reading/writing */ | |
808 | mmci_init_sg(host, data); | |
809 | ||
810 | if (data->flags & MMC_DATA_READ) { | |
1da177e4 | 811 | irqmask = MCI_RXFIFOHALFFULLMASK; |
0425a142 RK |
812 | |
813 | /* | |
c4d877c1 RK |
814 | * If we have less than the fifo 'half-full' threshold to |
815 | * transfer, trigger a PIO interrupt as soon as any data | |
816 | * is available. | |
0425a142 | 817 | */ |
c4d877c1 | 818 | if (host->size < variant->fifohalfsize) |
0425a142 | 819 | irqmask |= MCI_RXDATAAVLBLMASK; |
1da177e4 LT |
820 | } else { |
821 | /* | |
822 | * We don't actually need to include "FIFO empty" here | |
823 | * since its implicit in "FIFO half empty". | |
824 | */ | |
825 | irqmask = MCI_TXFIFOHALFEMPTYMASK; | |
826 | } | |
827 | ||
9cc639a2 | 828 | mmci_write_datactrlreg(host, datactrl); |
1da177e4 | 829 | writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); |
2686b4b4 | 830 | mmci_set_mask1(host, irqmask); |
1da177e4 LT |
831 | } |
832 | ||
833 | static void | |
834 | mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) | |
835 | { | |
836 | void __iomem *base = host->base; | |
837 | ||
64de0289 | 838 | dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", |
1da177e4 LT |
839 | cmd->opcode, cmd->arg, cmd->flags); |
840 | ||
841 | if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { | |
842 | writel(0, base + MMCICOMMAND); | |
6adb2a80 | 843 | mmci_reg_delay(host); |
1da177e4 LT |
844 | } |
845 | ||
846 | c |= cmd->opcode | MCI_CPSM_ENABLE; | |
e9225176 RK |
847 | if (cmd->flags & MMC_RSP_PRESENT) { |
848 | if (cmd->flags & MMC_RSP_136) | |
849 | c |= MCI_CPSM_LONGRSP; | |
1da177e4 | 850 | c |= MCI_CPSM_RESPONSE; |
1da177e4 LT |
851 | } |
852 | if (/*interrupt*/0) | |
853 | c |= MCI_CPSM_INTERRUPT; | |
854 | ||
ae7b0061 SK |
855 | if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) |
856 | c |= host->variant->data_cmd_enable; | |
857 | ||
1da177e4 LT |
858 | host->cmd = cmd; |
859 | ||
860 | writel(cmd->arg, base + MMCIARGUMENT); | |
861 | writel(c, base + MMCICOMMAND); | |
862 | } | |
863 | ||
864 | static void | |
865 | mmci_data_irq(struct mmci_host *host, struct mmc_data *data, | |
866 | unsigned int status) | |
867 | { | |
f20f8f21 | 868 | /* First check for errors */ |
b63038d6 UH |
869 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| |
870 | MCI_TXUNDERRUN|MCI_RXOVERRUN)) { | |
8cb28155 | 871 | u32 remain, success; |
f20f8f21 | 872 | |
c8ebae37 | 873 | /* Terminate the DMA transfer */ |
653a761e | 874 | if (dma_inprogress(host)) { |
c8ebae37 | 875 | mmci_dma_data_error(host); |
653a761e UH |
876 | mmci_dma_unmap(host, data); |
877 | } | |
e9c091b4 RK |
878 | |
879 | /* | |
c8afc9d5 RK |
880 | * Calculate how far we are into the transfer. Note that |
881 | * the data counter gives the number of bytes transferred | |
882 | * on the MMC bus, not on the host side. On reads, this | |
883 | * can be as much as a FIFO-worth of data ahead. This | |
884 | * matters for FIFO overruns only. | |
e9c091b4 | 885 | */ |
f5a106d9 | 886 | remain = readl(host->base + MMCIDATACNT); |
8cb28155 LW |
887 | success = data->blksz * data->blocks - remain; |
888 | ||
c8afc9d5 RK |
889 | dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", |
890 | status, success); | |
8cb28155 LW |
891 | if (status & MCI_DATACRCFAIL) { |
892 | /* Last block was not successful */ | |
c8afc9d5 | 893 | success -= 1; |
17b0429d | 894 | data->error = -EILSEQ; |
8cb28155 | 895 | } else if (status & MCI_DATATIMEOUT) { |
17b0429d | 896 | data->error = -ETIMEDOUT; |
757df746 LW |
897 | } else if (status & MCI_STARTBITERR) { |
898 | data->error = -ECOMM; | |
c8afc9d5 RK |
899 | } else if (status & MCI_TXUNDERRUN) { |
900 | data->error = -EIO; | |
901 | } else if (status & MCI_RXOVERRUN) { | |
902 | if (success > host->variant->fifosize) | |
903 | success -= host->variant->fifosize; | |
904 | else | |
905 | success = 0; | |
17b0429d | 906 | data->error = -EIO; |
4ce1d6cb | 907 | } |
51d4375d | 908 | data->bytes_xfered = round_down(success, data->blksz); |
1da177e4 | 909 | } |
f20f8f21 | 910 | |
8cb28155 LW |
911 | if (status & MCI_DATABLOCKEND) |
912 | dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); | |
f20f8f21 | 913 | |
ccff9b51 | 914 | if (status & MCI_DATAEND || data->error) { |
c8ebae37 | 915 | if (dma_inprogress(host)) |
653a761e | 916 | mmci_dma_finalize(host, data); |
1da177e4 LT |
917 | mmci_stop_data(host); |
918 | ||
8cb28155 LW |
919 | if (!data->error) |
920 | /* The error clause is handled above, success! */ | |
51d4375d | 921 | data->bytes_xfered = data->blksz * data->blocks; |
f20f8f21 | 922 | |
024629c6 | 923 | if (!data->stop || host->mrq->sbc) { |
1da177e4 LT |
924 | mmci_request_end(host, data->mrq); |
925 | } else { | |
926 | mmci_start_command(host, data->stop, 0); | |
927 | } | |
928 | } | |
929 | } | |
930 | ||
931 | static void | |
932 | mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, | |
933 | unsigned int status) | |
934 | { | |
935 | void __iomem *base = host->base; | |
024629c6 | 936 | bool sbc = (cmd == host->mrq->sbc); |
8d94b54d UH |
937 | bool busy_resp = host->variant->busy_detect && |
938 | (cmd->flags & MMC_RSP_BUSY); | |
939 | ||
940 | /* Check if we need to wait for busy completion. */ | |
941 | if (host->busy_status && (status & MCI_ST_CARDBUSY)) | |
942 | return; | |
943 | ||
944 | /* Enable busy completion if needed and supported. */ | |
945 | if (!host->busy_status && busy_resp && | |
946 | !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) && | |
947 | (readl(base + MMCISTATUS) & MCI_ST_CARDBUSY)) { | |
948 | writel(readl(base + MMCIMASK0) | MCI_ST_BUSYEND, | |
949 | base + MMCIMASK0); | |
950 | host->busy_status = status & (MCI_CMDSENT|MCI_CMDRESPEND); | |
951 | return; | |
952 | } | |
953 | ||
954 | /* At busy completion, mask the IRQ and complete the request. */ | |
955 | if (host->busy_status) { | |
956 | writel(readl(base + MMCIMASK0) & ~MCI_ST_BUSYEND, | |
957 | base + MMCIMASK0); | |
958 | host->busy_status = 0; | |
959 | } | |
1da177e4 LT |
960 | |
961 | host->cmd = NULL; | |
962 | ||
1da177e4 | 963 | if (status & MCI_CMDTIMEOUT) { |
17b0429d | 964 | cmd->error = -ETIMEDOUT; |
1da177e4 | 965 | } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { |
17b0429d | 966 | cmd->error = -EILSEQ; |
9047b435 RKAL |
967 | } else { |
968 | cmd->resp[0] = readl(base + MMCIRESPONSE0); | |
969 | cmd->resp[1] = readl(base + MMCIRESPONSE1); | |
970 | cmd->resp[2] = readl(base + MMCIRESPONSE2); | |
971 | cmd->resp[3] = readl(base + MMCIRESPONSE3); | |
1da177e4 LT |
972 | } |
973 | ||
024629c6 | 974 | if ((!sbc && !cmd->data) || cmd->error) { |
3b6e3c73 UH |
975 | if (host->data) { |
976 | /* Terminate the DMA transfer */ | |
653a761e | 977 | if (dma_inprogress(host)) { |
3b6e3c73 | 978 | mmci_dma_data_error(host); |
653a761e UH |
979 | mmci_dma_unmap(host, host->data); |
980 | } | |
e47c222b | 981 | mmci_stop_data(host); |
3b6e3c73 | 982 | } |
024629c6 UH |
983 | mmci_request_end(host, host->mrq); |
984 | } else if (sbc) { | |
985 | mmci_start_command(host, host->mrq->cmd, 0); | |
1da177e4 LT |
986 | } else if (!(cmd->data->flags & MMC_DATA_READ)) { |
987 | mmci_start_data(host, cmd->data); | |
988 | } | |
989 | } | |
990 | ||
991 | static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) | |
992 | { | |
993 | void __iomem *base = host->base; | |
994 | char *ptr = buffer; | |
995 | u32 status; | |
26eed9a5 | 996 | int host_remain = host->size; |
1da177e4 LT |
997 | |
998 | do { | |
26eed9a5 | 999 | int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); |
1da177e4 LT |
1000 | |
1001 | if (count > remain) | |
1002 | count = remain; | |
1003 | ||
1004 | if (count <= 0) | |
1005 | break; | |
1006 | ||
393e5e24 UH |
1007 | /* |
1008 | * SDIO especially may want to send something that is | |
1009 | * not divisible by 4 (as opposed to card sectors | |
1010 | * etc). Therefore make sure to always read the last bytes | |
1011 | * while only doing full 32-bit reads towards the FIFO. | |
1012 | */ | |
1013 | if (unlikely(count & 0x3)) { | |
1014 | if (count < 4) { | |
1015 | unsigned char buf[4]; | |
4b85da08 | 1016 | ioread32_rep(base + MMCIFIFO, buf, 1); |
393e5e24 UH |
1017 | memcpy(ptr, buf, count); |
1018 | } else { | |
4b85da08 | 1019 | ioread32_rep(base + MMCIFIFO, ptr, count >> 2); |
393e5e24 UH |
1020 | count &= ~0x3; |
1021 | } | |
1022 | } else { | |
4b85da08 | 1023 | ioread32_rep(base + MMCIFIFO, ptr, count >> 2); |
393e5e24 | 1024 | } |
1da177e4 LT |
1025 | |
1026 | ptr += count; | |
1027 | remain -= count; | |
26eed9a5 | 1028 | host_remain -= count; |
1da177e4 LT |
1029 | |
1030 | if (remain == 0) | |
1031 | break; | |
1032 | ||
1033 | status = readl(base + MMCISTATUS); | |
1034 | } while (status & MCI_RXDATAAVLBL); | |
1035 | ||
1036 | return ptr - buffer; | |
1037 | } | |
1038 | ||
1039 | static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) | |
1040 | { | |
8301bb68 | 1041 | struct variant_data *variant = host->variant; |
1da177e4 LT |
1042 | void __iomem *base = host->base; |
1043 | char *ptr = buffer; | |
1044 | ||
1045 | do { | |
1046 | unsigned int count, maxcnt; | |
1047 | ||
8301bb68 RV |
1048 | maxcnt = status & MCI_TXFIFOEMPTY ? |
1049 | variant->fifosize : variant->fifohalfsize; | |
1da177e4 LT |
1050 | count = min(remain, maxcnt); |
1051 | ||
34177802 LW |
1052 | /* |
1053 | * SDIO especially may want to send something that is | |
1054 | * not divisible by 4 (as opposed to card sectors | |
1055 | * etc), and the FIFO only accept full 32-bit writes. | |
1056 | * So compensate by adding +3 on the count, a single | |
1057 | * byte become a 32bit write, 7 bytes will be two | |
1058 | * 32bit writes etc. | |
1059 | */ | |
4b85da08 | 1060 | iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); |
1da177e4 LT |
1061 | |
1062 | ptr += count; | |
1063 | remain -= count; | |
1064 | ||
1065 | if (remain == 0) | |
1066 | break; | |
1067 | ||
1068 | status = readl(base + MMCISTATUS); | |
1069 | } while (status & MCI_TXFIFOHALFEMPTY); | |
1070 | ||
1071 | return ptr - buffer; | |
1072 | } | |
1073 | ||
1074 | /* | |
1075 | * PIO data transfer IRQ handler. | |
1076 | */ | |
7d12e780 | 1077 | static irqreturn_t mmci_pio_irq(int irq, void *dev_id) |
1da177e4 LT |
1078 | { |
1079 | struct mmci_host *host = dev_id; | |
4ce1d6cb | 1080 | struct sg_mapping_iter *sg_miter = &host->sg_miter; |
8301bb68 | 1081 | struct variant_data *variant = host->variant; |
1da177e4 | 1082 | void __iomem *base = host->base; |
4ce1d6cb | 1083 | unsigned long flags; |
1da177e4 LT |
1084 | u32 status; |
1085 | ||
1086 | status = readl(base + MMCISTATUS); | |
1087 | ||
64de0289 | 1088 | dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); |
1da177e4 | 1089 | |
4ce1d6cb RV |
1090 | local_irq_save(flags); |
1091 | ||
1da177e4 | 1092 | do { |
1da177e4 LT |
1093 | unsigned int remain, len; |
1094 | char *buffer; | |
1095 | ||
1096 | /* | |
1097 | * For write, we only need to test the half-empty flag | |
1098 | * here - if the FIFO is completely empty, then by | |
1099 | * definition it is more than half empty. | |
1100 | * | |
1101 | * For read, check for data available. | |
1102 | */ | |
1103 | if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) | |
1104 | break; | |
1105 | ||
4ce1d6cb RV |
1106 | if (!sg_miter_next(sg_miter)) |
1107 | break; | |
1108 | ||
1109 | buffer = sg_miter->addr; | |
1110 | remain = sg_miter->length; | |
1da177e4 LT |
1111 | |
1112 | len = 0; | |
1113 | if (status & MCI_RXACTIVE) | |
1114 | len = mmci_pio_read(host, buffer, remain); | |
1115 | if (status & MCI_TXACTIVE) | |
1116 | len = mmci_pio_write(host, buffer, remain, status); | |
1117 | ||
4ce1d6cb | 1118 | sg_miter->consumed = len; |
1da177e4 | 1119 | |
1da177e4 LT |
1120 | host->size -= len; |
1121 | remain -= len; | |
1122 | ||
1123 | if (remain) | |
1124 | break; | |
1125 | ||
1da177e4 LT |
1126 | status = readl(base + MMCISTATUS); |
1127 | } while (1); | |
1128 | ||
4ce1d6cb RV |
1129 | sg_miter_stop(sg_miter); |
1130 | ||
1131 | local_irq_restore(flags); | |
1132 | ||
1da177e4 | 1133 | /* |
c4d877c1 RK |
1134 | * If we have less than the fifo 'half-full' threshold to transfer, |
1135 | * trigger a PIO interrupt as soon as any data is available. | |
1da177e4 | 1136 | */ |
c4d877c1 | 1137 | if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) |
2686b4b4 | 1138 | mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); |
1da177e4 LT |
1139 | |
1140 | /* | |
1141 | * If we run out of data, disable the data IRQs; this | |
1142 | * prevents a race where the FIFO becomes empty before | |
1143 | * the chip itself has disabled the data path, and | |
1144 | * stops us racing with our data end IRQ. | |
1145 | */ | |
1146 | if (host->size == 0) { | |
2686b4b4 | 1147 | mmci_set_mask1(host, 0); |
1da177e4 LT |
1148 | writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); |
1149 | } | |
1150 | ||
1151 | return IRQ_HANDLED; | |
1152 | } | |
1153 | ||
1154 | /* | |
1155 | * Handle completion of command and data transfers. | |
1156 | */ | |
7d12e780 | 1157 | static irqreturn_t mmci_irq(int irq, void *dev_id) |
1da177e4 LT |
1158 | { |
1159 | struct mmci_host *host = dev_id; | |
1160 | u32 status; | |
1161 | int ret = 0; | |
1162 | ||
1163 | spin_lock(&host->lock); | |
1164 | ||
1165 | do { | |
1166 | struct mmc_command *cmd; | |
1167 | struct mmc_data *data; | |
1168 | ||
1169 | status = readl(host->base + MMCISTATUS); | |
2686b4b4 LW |
1170 | |
1171 | if (host->singleirq) { | |
1172 | if (status & readl(host->base + MMCIMASK1)) | |
1173 | mmci_pio_irq(irq, dev_id); | |
1174 | ||
1175 | status &= ~MCI_IRQ1MASK; | |
1176 | } | |
1177 | ||
8d94b54d UH |
1178 | /* |
1179 | * We intentionally clear the MCI_ST_CARDBUSY IRQ here (if it's | |
1180 | * enabled) since the HW seems to be triggering the IRQ on both | |
1181 | * edges while monitoring DAT0 for busy completion. | |
1182 | */ | |
1da177e4 LT |
1183 | status &= readl(host->base + MMCIMASK0); |
1184 | writel(status, host->base + MMCICLEAR); | |
1185 | ||
64de0289 | 1186 | dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); |
1da177e4 | 1187 | |
e7f3d222 | 1188 | cmd = host->cmd; |
8d94b54d UH |
1189 | if ((status|host->busy_status) & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT| |
1190 | MCI_CMDSENT|MCI_CMDRESPEND) && cmd) | |
e7f3d222 UH |
1191 | mmci_cmd_irq(host, cmd, status); |
1192 | ||
1da177e4 | 1193 | data = host->data; |
b63038d6 UH |
1194 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| |
1195 | MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND| | |
1196 | MCI_DATABLOCKEND) && data) | |
1da177e4 LT |
1197 | mmci_data_irq(host, data, status); |
1198 | ||
8d94b54d UH |
1199 | /* Don't poll for busy completion in irq context. */ |
1200 | if (host->busy_status) | |
1201 | status &= ~MCI_ST_CARDBUSY; | |
1202 | ||
1da177e4 LT |
1203 | ret = 1; |
1204 | } while (status); | |
1205 | ||
1206 | spin_unlock(&host->lock); | |
1207 | ||
1208 | return IRQ_RETVAL(ret); | |
1209 | } | |
1210 | ||
1211 | static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
1212 | { | |
1213 | struct mmci_host *host = mmc_priv(mmc); | |
9e943021 | 1214 | unsigned long flags; |
1da177e4 LT |
1215 | |
1216 | WARN_ON(host->mrq != NULL); | |
1217 | ||
653a761e UH |
1218 | mrq->cmd->error = mmci_validate_data(host, mrq->data); |
1219 | if (mrq->cmd->error) { | |
255d01af PO |
1220 | mmc_request_done(mmc, mrq); |
1221 | return; | |
1222 | } | |
1223 | ||
1c3be369 RK |
1224 | pm_runtime_get_sync(mmc_dev(mmc)); |
1225 | ||
9e943021 | 1226 | spin_lock_irqsave(&host->lock, flags); |
1da177e4 LT |
1227 | |
1228 | host->mrq = mrq; | |
1229 | ||
58c7ccbf PF |
1230 | if (mrq->data) |
1231 | mmci_get_next_data(host, mrq->data); | |
1232 | ||
1da177e4 LT |
1233 | if (mrq->data && mrq->data->flags & MMC_DATA_READ) |
1234 | mmci_start_data(host, mrq->data); | |
1235 | ||
024629c6 UH |
1236 | if (mrq->sbc) |
1237 | mmci_start_command(host, mrq->sbc, 0); | |
1238 | else | |
1239 | mmci_start_command(host, mrq->cmd, 0); | |
1da177e4 | 1240 | |
9e943021 | 1241 | spin_unlock_irqrestore(&host->lock, flags); |
1da177e4 LT |
1242 | } |
1243 | ||
1244 | static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
1245 | { | |
1246 | struct mmci_host *host = mmc_priv(mmc); | |
7d72a1d4 | 1247 | struct variant_data *variant = host->variant; |
a6a6464a LW |
1248 | u32 pwr = 0; |
1249 | unsigned long flags; | |
db90f91f | 1250 | int ret; |
1da177e4 | 1251 | |
2cd976c4 UH |
1252 | pm_runtime_get_sync(mmc_dev(mmc)); |
1253 | ||
bc521818 UH |
1254 | if (host->plat->ios_handler && |
1255 | host->plat->ios_handler(mmc_dev(mmc), ios)) | |
1256 | dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); | |
1257 | ||
1da177e4 LT |
1258 | switch (ios->power_mode) { |
1259 | case MMC_POWER_OFF: | |
599c1d5c UH |
1260 | if (!IS_ERR(mmc->supply.vmmc)) |
1261 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); | |
237fb5e6 | 1262 | |
7c0136ef | 1263 | if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { |
237fb5e6 | 1264 | regulator_disable(mmc->supply.vqmmc); |
7c0136ef UH |
1265 | host->vqmmc_enabled = false; |
1266 | } | |
237fb5e6 | 1267 | |
1da177e4 LT |
1268 | break; |
1269 | case MMC_POWER_UP: | |
599c1d5c UH |
1270 | if (!IS_ERR(mmc->supply.vmmc)) |
1271 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); | |
1272 | ||
7d72a1d4 UH |
1273 | /* |
1274 | * The ST Micro variant doesn't have the PL180s MCI_PWR_UP | |
1275 | * and instead uses MCI_PWR_ON so apply whatever value is | |
1276 | * configured in the variant data. | |
1277 | */ | |
1278 | pwr |= variant->pwrreg_powerup; | |
1279 | ||
1280 | break; | |
1da177e4 | 1281 | case MMC_POWER_ON: |
7c0136ef | 1282 | if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { |
db90f91f LJ |
1283 | ret = regulator_enable(mmc->supply.vqmmc); |
1284 | if (ret < 0) | |
1285 | dev_err(mmc_dev(mmc), | |
1286 | "failed to enable vqmmc regulator\n"); | |
7c0136ef UH |
1287 | else |
1288 | host->vqmmc_enabled = true; | |
db90f91f | 1289 | } |
237fb5e6 | 1290 | |
1da177e4 LT |
1291 | pwr |= MCI_PWR_ON; |
1292 | break; | |
1293 | } | |
1294 | ||
4d1a3a0d UH |
1295 | if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { |
1296 | /* | |
1297 | * The ST Micro variant has some additional bits | |
1298 | * indicating signal direction for the signals in | |
1299 | * the SD/MMC bus and feedback-clock usage. | |
1300 | */ | |
4593df29 | 1301 | pwr |= host->pwr_reg_add; |
4d1a3a0d UH |
1302 | |
1303 | if (ios->bus_width == MMC_BUS_WIDTH_4) | |
1304 | pwr &= ~MCI_ST_DATA74DIREN; | |
1305 | else if (ios->bus_width == MMC_BUS_WIDTH_1) | |
1306 | pwr &= (~MCI_ST_DATA74DIREN & | |
1307 | ~MCI_ST_DATA31DIREN & | |
1308 | ~MCI_ST_DATA2DIREN); | |
1309 | } | |
1310 | ||
cc30d60e | 1311 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { |
f17a1f06 | 1312 | if (host->hw_designer != AMBA_VENDOR_ST) |
cc30d60e LW |
1313 | pwr |= MCI_ROD; |
1314 | else { | |
1315 | /* | |
1316 | * The ST Micro variant use the ROD bit for something | |
1317 | * else and only has OD (Open Drain). | |
1318 | */ | |
1319 | pwr |= MCI_OD; | |
1320 | } | |
1321 | } | |
1da177e4 | 1322 | |
f4670dae UH |
1323 | /* |
1324 | * If clock = 0 and the variant requires the MMCIPOWER to be used for | |
1325 | * gating the clock, the MCI_PWR_ON bit is cleared. | |
1326 | */ | |
1327 | if (!ios->clock && variant->pwrreg_clkgate) | |
1328 | pwr &= ~MCI_PWR_ON; | |
1329 | ||
a6a6464a LW |
1330 | spin_lock_irqsave(&host->lock, flags); |
1331 | ||
1332 | mmci_set_clkreg(host, ios->clock); | |
7437cfa5 | 1333 | mmci_write_pwrreg(host, pwr); |
f829c042 | 1334 | mmci_reg_delay(host); |
a6a6464a LW |
1335 | |
1336 | spin_unlock_irqrestore(&host->lock, flags); | |
2cd976c4 | 1337 | |
2cd976c4 UH |
1338 | pm_runtime_mark_last_busy(mmc_dev(mmc)); |
1339 | pm_runtime_put_autosuspend(mmc_dev(mmc)); | |
1da177e4 LT |
1340 | } |
1341 | ||
89001446 RK |
1342 | static int mmci_get_cd(struct mmc_host *mmc) |
1343 | { | |
1344 | struct mmci_host *host = mmc_priv(mmc); | |
29719445 | 1345 | struct mmci_platform_data *plat = host->plat; |
d2762090 | 1346 | unsigned int status = mmc_gpio_get_cd(mmc); |
89001446 | 1347 | |
d2762090 | 1348 | if (status == -ENOSYS) { |
4b8caec0 RV |
1349 | if (!plat->status) |
1350 | return 1; /* Assume always present */ | |
1351 | ||
29719445 | 1352 | status = plat->status(mmc_dev(host->mmc)); |
d2762090 | 1353 | } |
74bc8093 | 1354 | return status; |
89001446 RK |
1355 | } |
1356 | ||
0f3ed7f7 UH |
1357 | static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) |
1358 | { | |
1359 | int ret = 0; | |
1360 | ||
1361 | if (!IS_ERR(mmc->supply.vqmmc)) { | |
1362 | ||
1363 | pm_runtime_get_sync(mmc_dev(mmc)); | |
1364 | ||
1365 | switch (ios->signal_voltage) { | |
1366 | case MMC_SIGNAL_VOLTAGE_330: | |
1367 | ret = regulator_set_voltage(mmc->supply.vqmmc, | |
1368 | 2700000, 3600000); | |
1369 | break; | |
1370 | case MMC_SIGNAL_VOLTAGE_180: | |
1371 | ret = regulator_set_voltage(mmc->supply.vqmmc, | |
1372 | 1700000, 1950000); | |
1373 | break; | |
1374 | case MMC_SIGNAL_VOLTAGE_120: | |
1375 | ret = regulator_set_voltage(mmc->supply.vqmmc, | |
1376 | 1100000, 1300000); | |
1377 | break; | |
1378 | } | |
1379 | ||
1380 | if (ret) | |
1381 | dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); | |
1382 | ||
1383 | pm_runtime_mark_last_busy(mmc_dev(mmc)); | |
1384 | pm_runtime_put_autosuspend(mmc_dev(mmc)); | |
1385 | } | |
1386 | ||
1387 | return ret; | |
1388 | } | |
1389 | ||
01259620 | 1390 | static struct mmc_host_ops mmci_ops = { |
1da177e4 | 1391 | .request = mmci_request, |
58c7ccbf PF |
1392 | .pre_req = mmci_pre_request, |
1393 | .post_req = mmci_post_request, | |
1da177e4 | 1394 | .set_ios = mmci_set_ios, |
d2762090 | 1395 | .get_ro = mmc_gpio_get_ro, |
89001446 | 1396 | .get_cd = mmci_get_cd, |
0f3ed7f7 | 1397 | .start_signal_voltage_switch = mmci_sig_volt_switch, |
1da177e4 LT |
1398 | }; |
1399 | ||
4593df29 | 1400 | static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) |
000bc9d5 | 1401 | { |
4593df29 UH |
1402 | struct mmci_host *host = mmc_priv(mmc); |
1403 | int ret = mmc_of_parse(mmc); | |
1404 | ||
1405 | if (ret) | |
1406 | return ret; | |
1407 | ||
ae94cafe | 1408 | if (of_get_property(np, "st,sig-dir-dat0", NULL)) |
4593df29 | 1409 | host->pwr_reg_add |= MCI_ST_DATA0DIREN; |
ae94cafe | 1410 | if (of_get_property(np, "st,sig-dir-dat2", NULL)) |
4593df29 | 1411 | host->pwr_reg_add |= MCI_ST_DATA2DIREN; |
ae94cafe | 1412 | if (of_get_property(np, "st,sig-dir-dat31", NULL)) |
4593df29 | 1413 | host->pwr_reg_add |= MCI_ST_DATA31DIREN; |
ae94cafe | 1414 | if (of_get_property(np, "st,sig-dir-dat74", NULL)) |
4593df29 | 1415 | host->pwr_reg_add |= MCI_ST_DATA74DIREN; |
ae94cafe | 1416 | if (of_get_property(np, "st,sig-dir-cmd", NULL)) |
4593df29 | 1417 | host->pwr_reg_add |= MCI_ST_CMDDIREN; |
1a7e99c1 | 1418 | if (of_get_property(np, "st,sig-pin-fbclk", NULL)) |
4593df29 | 1419 | host->pwr_reg_add |= MCI_ST_FBCLKEN; |
000bc9d5 LJ |
1420 | |
1421 | if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) | |
78f87df2 | 1422 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED; |
000bc9d5 | 1423 | if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) |
78f87df2 | 1424 | mmc->caps |= MMC_CAP_SD_HIGHSPEED; |
000bc9d5 | 1425 | |
78f87df2 | 1426 | return 0; |
c0a120a4 | 1427 | } |
000bc9d5 | 1428 | |
c3be1efd | 1429 | static int mmci_probe(struct amba_device *dev, |
aa25afad | 1430 | const struct amba_id *id) |
1da177e4 | 1431 | { |
6ef297f8 | 1432 | struct mmci_platform_data *plat = dev->dev.platform_data; |
000bc9d5 | 1433 | struct device_node *np = dev->dev.of_node; |
4956e109 | 1434 | struct variant_data *variant = id->data; |
1da177e4 LT |
1435 | struct mmci_host *host; |
1436 | struct mmc_host *mmc; | |
1437 | int ret; | |
1438 | ||
000bc9d5 LJ |
1439 | /* Must have platform data or Device Tree. */ |
1440 | if (!plat && !np) { | |
1441 | dev_err(&dev->dev, "No plat data or DT found\n"); | |
1442 | return -EINVAL; | |
1da177e4 LT |
1443 | } |
1444 | ||
b9b52918 LJ |
1445 | if (!plat) { |
1446 | plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); | |
1447 | if (!plat) | |
1448 | return -ENOMEM; | |
1449 | } | |
1450 | ||
1da177e4 | 1451 | mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); |
ef289982 UH |
1452 | if (!mmc) |
1453 | return -ENOMEM; | |
1da177e4 | 1454 | |
78f87df2 UH |
1455 | ret = mmci_of_parse(np, mmc); |
1456 | if (ret) | |
1457 | goto host_free; | |
1458 | ||
1da177e4 | 1459 | host = mmc_priv(mmc); |
4ea580f1 | 1460 | host->mmc = mmc; |
012b7d33 RK |
1461 | |
1462 | host->hw_designer = amba_manf(dev); | |
1463 | host->hw_revision = amba_rev(dev); | |
64de0289 LW |
1464 | dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); |
1465 | dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); | |
012b7d33 | 1466 | |
665ba56f | 1467 | host->clk = devm_clk_get(&dev->dev, NULL); |
1da177e4 LT |
1468 | if (IS_ERR(host->clk)) { |
1469 | ret = PTR_ERR(host->clk); | |
1da177e4 LT |
1470 | goto host_free; |
1471 | } | |
1472 | ||
ac940938 | 1473 | ret = clk_prepare_enable(host->clk); |
1da177e4 | 1474 | if (ret) |
665ba56f | 1475 | goto host_free; |
1da177e4 LT |
1476 | |
1477 | host->plat = plat; | |
4956e109 | 1478 | host->variant = variant; |
1da177e4 | 1479 | host->mclk = clk_get_rate(host->clk); |
c8df9a53 LW |
1480 | /* |
1481 | * According to the spec, mclk is max 100 MHz, | |
1482 | * so we try to adjust the clock down to this, | |
1483 | * (if possible). | |
1484 | */ | |
dc6500bf SK |
1485 | if (host->mclk > variant->f_max) { |
1486 | ret = clk_set_rate(host->clk, variant->f_max); | |
c8df9a53 LW |
1487 | if (ret < 0) |
1488 | goto clk_disable; | |
1489 | host->mclk = clk_get_rate(host->clk); | |
64de0289 LW |
1490 | dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", |
1491 | host->mclk); | |
c8df9a53 | 1492 | } |
ef289982 | 1493 | |
c8ebae37 | 1494 | host->phybase = dev->res.start; |
ef289982 UH |
1495 | host->base = devm_ioremap_resource(&dev->dev, &dev->res); |
1496 | if (IS_ERR(host->base)) { | |
1497 | ret = PTR_ERR(host->base); | |
1da177e4 LT |
1498 | goto clk_disable; |
1499 | } | |
1500 | ||
7f294e49 LW |
1501 | /* |
1502 | * The ARM and ST versions of the block have slightly different | |
1503 | * clock divider equations which means that the minimum divider | |
1504 | * differs too. | |
1505 | */ | |
1506 | if (variant->st_clkdiv) | |
1507 | mmc->f_min = DIV_ROUND_UP(host->mclk, 257); | |
1508 | else | |
1509 | mmc->f_min = DIV_ROUND_UP(host->mclk, 512); | |
808d97cc | 1510 | /* |
78f87df2 UH |
1511 | * If no maximum operating frequency is supplied, fall back to use |
1512 | * the module parameter, which has a (low) default value in case it | |
1513 | * is not specified. Either value must not exceed the clock rate into | |
5080a08d | 1514 | * the block, of course. |
808d97cc | 1515 | */ |
78f87df2 UH |
1516 | if (mmc->f_max) |
1517 | mmc->f_max = min(host->mclk, mmc->f_max); | |
808d97cc LW |
1518 | else |
1519 | mmc->f_max = min(host->mclk, fmax); | |
64de0289 LW |
1520 | dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); |
1521 | ||
599c1d5c UH |
1522 | /* Get regulators and the supported OCR mask */ |
1523 | mmc_regulator_get_supply(mmc); | |
1524 | if (!mmc->ocr_avail) | |
34e84f39 | 1525 | mmc->ocr_avail = plat->ocr_mask; |
599c1d5c UH |
1526 | else if (plat->ocr_mask) |
1527 | dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); | |
1528 | ||
78f87df2 | 1529 | /* DT takes precedence over platform data. */ |
78f87df2 UH |
1530 | if (!np) { |
1531 | if (!plat->cd_invert) | |
1532 | mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH; | |
1533 | mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; | |
1534 | } | |
1da177e4 | 1535 | |
9dd8a8b8 UH |
1536 | /* We support these capabilities. */ |
1537 | mmc->caps |= MMC_CAP_CMD23; | |
1538 | ||
8d94b54d UH |
1539 | if (variant->busy_detect) { |
1540 | mmci_ops.card_busy = mmci_card_busy; | |
1541 | mmci_write_datactrlreg(host, MCI_ST_DPSM_BUSYMODE); | |
1542 | mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; | |
1543 | mmc->max_busy_timeout = 0; | |
1544 | } | |
1545 | ||
1546 | mmc->ops = &mmci_ops; | |
1547 | ||
70be208f | 1548 | /* We support these PM capabilities. */ |
78f87df2 | 1549 | mmc->pm_caps |= MMC_PM_KEEP_POWER; |
70be208f | 1550 | |
1da177e4 LT |
1551 | /* |
1552 | * We can do SGIO | |
1553 | */ | |
a36274e0 | 1554 | mmc->max_segs = NR_SG; |
1da177e4 LT |
1555 | |
1556 | /* | |
08458ef6 RV |
1557 | * Since only a certain number of bits are valid in the data length |
1558 | * register, we must ensure that we don't exceed 2^num-1 bytes in a | |
1559 | * single request. | |
1da177e4 | 1560 | */ |
08458ef6 | 1561 | mmc->max_req_size = (1 << variant->datalength_bits) - 1; |
1da177e4 LT |
1562 | |
1563 | /* | |
1564 | * Set the maximum segment size. Since we aren't doing DMA | |
1565 | * (yet) we are only limited by the data length register. | |
1566 | */ | |
55db890a | 1567 | mmc->max_seg_size = mmc->max_req_size; |
1da177e4 | 1568 | |
fe4a3c7a PO |
1569 | /* |
1570 | * Block size can be up to 2048 bytes, but must be a power of two. | |
1571 | */ | |
8f7f6b7e | 1572 | mmc->max_blk_size = 1 << 11; |
fe4a3c7a | 1573 | |
55db890a | 1574 | /* |
8f7f6b7e WD |
1575 | * Limit the number of blocks transferred so that we don't overflow |
1576 | * the maximum request size. | |
55db890a | 1577 | */ |
8f7f6b7e | 1578 | mmc->max_blk_count = mmc->max_req_size >> 11; |
55db890a | 1579 | |
1da177e4 LT |
1580 | spin_lock_init(&host->lock); |
1581 | ||
1582 | writel(0, host->base + MMCIMASK0); | |
1583 | writel(0, host->base + MMCIMASK1); | |
1584 | writel(0xfff, host->base + MMCICLEAR); | |
1585 | ||
78f87df2 UH |
1586 | /* If DT, cd/wp gpios must be supplied through it. */ |
1587 | if (!np && gpio_is_valid(plat->gpio_cd)) { | |
d2762090 UH |
1588 | ret = mmc_gpio_request_cd(mmc, plat->gpio_cd, 0); |
1589 | if (ret) | |
ef289982 | 1590 | goto clk_disable; |
89001446 | 1591 | } |
78f87df2 | 1592 | if (!np && gpio_is_valid(plat->gpio_wp)) { |
d2762090 UH |
1593 | ret = mmc_gpio_request_ro(mmc, plat->gpio_wp); |
1594 | if (ret) | |
ef289982 | 1595 | goto clk_disable; |
89001446 RK |
1596 | } |
1597 | ||
ef289982 UH |
1598 | ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED, |
1599 | DRIVER_NAME " (cmd)", host); | |
1da177e4 | 1600 | if (ret) |
ef289982 | 1601 | goto clk_disable; |
1da177e4 | 1602 | |
dfb85185 | 1603 | if (!dev->irq[1]) |
2686b4b4 LW |
1604 | host->singleirq = true; |
1605 | else { | |
ef289982 UH |
1606 | ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, |
1607 | IRQF_SHARED, DRIVER_NAME " (pio)", host); | |
2686b4b4 | 1608 | if (ret) |
ef289982 | 1609 | goto clk_disable; |
2686b4b4 | 1610 | } |
1da177e4 | 1611 | |
8cb28155 | 1612 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); |
1da177e4 LT |
1613 | |
1614 | amba_set_drvdata(dev, mmc); | |
1615 | ||
c8ebae37 RK |
1616 | dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", |
1617 | mmc_hostname(mmc), amba_part(dev), amba_manf(dev), | |
1618 | amba_rev(dev), (unsigned long long)dev->res.start, | |
1619 | dev->irq[0], dev->irq[1]); | |
1620 | ||
1621 | mmci_dma_setup(host); | |
1da177e4 | 1622 | |
2cd976c4 UH |
1623 | pm_runtime_set_autosuspend_delay(&dev->dev, 50); |
1624 | pm_runtime_use_autosuspend(&dev->dev); | |
1c3be369 RK |
1625 | pm_runtime_put(&dev->dev); |
1626 | ||
8c11a94d RK |
1627 | mmc_add_host(mmc); |
1628 | ||
1da177e4 LT |
1629 | return 0; |
1630 | ||
1da177e4 | 1631 | clk_disable: |
ac940938 | 1632 | clk_disable_unprepare(host->clk); |
1da177e4 LT |
1633 | host_free: |
1634 | mmc_free_host(mmc); | |
1da177e4 LT |
1635 | return ret; |
1636 | } | |
1637 | ||
6e0ee714 | 1638 | static int mmci_remove(struct amba_device *dev) |
1da177e4 LT |
1639 | { |
1640 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
1641 | ||
1da177e4 LT |
1642 | if (mmc) { |
1643 | struct mmci_host *host = mmc_priv(mmc); | |
1644 | ||
1c3be369 RK |
1645 | /* |
1646 | * Undo pm_runtime_put() in probe. We use the _sync | |
1647 | * version here so that we can access the primecell. | |
1648 | */ | |
1649 | pm_runtime_get_sync(&dev->dev); | |
1650 | ||
1da177e4 LT |
1651 | mmc_remove_host(mmc); |
1652 | ||
1653 | writel(0, host->base + MMCIMASK0); | |
1654 | writel(0, host->base + MMCIMASK1); | |
1655 | ||
1656 | writel(0, host->base + MMCICOMMAND); | |
1657 | writel(0, host->base + MMCIDATACTRL); | |
1658 | ||
c8ebae37 | 1659 | mmci_dma_release(host); |
ac940938 | 1660 | clk_disable_unprepare(host->clk); |
1da177e4 | 1661 | mmc_free_host(mmc); |
1da177e4 LT |
1662 | } |
1663 | ||
1664 | return 0; | |
1665 | } | |
1666 | ||
571dce4f | 1667 | #ifdef CONFIG_PM |
1ff44433 UH |
1668 | static void mmci_save(struct mmci_host *host) |
1669 | { | |
1670 | unsigned long flags; | |
1671 | ||
42dcc89a | 1672 | spin_lock_irqsave(&host->lock, flags); |
1ff44433 | 1673 | |
42dcc89a UH |
1674 | writel(0, host->base + MMCIMASK0); |
1675 | if (host->variant->pwrreg_nopower) { | |
1ff44433 UH |
1676 | writel(0, host->base + MMCIDATACTRL); |
1677 | writel(0, host->base + MMCIPOWER); | |
1678 | writel(0, host->base + MMCICLOCK); | |
1ff44433 | 1679 | } |
42dcc89a | 1680 | mmci_reg_delay(host); |
1ff44433 | 1681 | |
42dcc89a | 1682 | spin_unlock_irqrestore(&host->lock, flags); |
1ff44433 UH |
1683 | } |
1684 | ||
1685 | static void mmci_restore(struct mmci_host *host) | |
1686 | { | |
1687 | unsigned long flags; | |
1688 | ||
42dcc89a | 1689 | spin_lock_irqsave(&host->lock, flags); |
1ff44433 | 1690 | |
42dcc89a | 1691 | if (host->variant->pwrreg_nopower) { |
1ff44433 UH |
1692 | writel(host->clk_reg, host->base + MMCICLOCK); |
1693 | writel(host->datactrl_reg, host->base + MMCIDATACTRL); | |
1694 | writel(host->pwr_reg, host->base + MMCIPOWER); | |
1ff44433 | 1695 | } |
42dcc89a UH |
1696 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); |
1697 | mmci_reg_delay(host); | |
1698 | ||
1699 | spin_unlock_irqrestore(&host->lock, flags); | |
1ff44433 UH |
1700 | } |
1701 | ||
8259293a UH |
1702 | static int mmci_runtime_suspend(struct device *dev) |
1703 | { | |
1704 | struct amba_device *adev = to_amba_device(dev); | |
1705 | struct mmc_host *mmc = amba_get_drvdata(adev); | |
1706 | ||
1707 | if (mmc) { | |
1708 | struct mmci_host *host = mmc_priv(mmc); | |
e36bd9c6 | 1709 | pinctrl_pm_select_sleep_state(dev); |
1ff44433 | 1710 | mmci_save(host); |
8259293a UH |
1711 | clk_disable_unprepare(host->clk); |
1712 | } | |
1713 | ||
1714 | return 0; | |
1715 | } | |
1716 | ||
1717 | static int mmci_runtime_resume(struct device *dev) | |
1718 | { | |
1719 | struct amba_device *adev = to_amba_device(dev); | |
1720 | struct mmc_host *mmc = amba_get_drvdata(adev); | |
1721 | ||
1722 | if (mmc) { | |
1723 | struct mmci_host *host = mmc_priv(mmc); | |
1724 | clk_prepare_enable(host->clk); | |
1ff44433 | 1725 | mmci_restore(host); |
e36bd9c6 | 1726 | pinctrl_pm_select_default_state(dev); |
8259293a UH |
1727 | } |
1728 | ||
1729 | return 0; | |
1730 | } | |
1731 | #endif | |
1732 | ||
48fa7003 | 1733 | static const struct dev_pm_ops mmci_dev_pm_ops = { |
f3737fa3 UH |
1734 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, |
1735 | pm_runtime_force_resume) | |
571dce4f | 1736 | SET_PM_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) |
48fa7003 UH |
1737 | }; |
1738 | ||
1da177e4 LT |
1739 | static struct amba_id mmci_ids[] = { |
1740 | { | |
1741 | .id = 0x00041180, | |
768fbc18 | 1742 | .mask = 0xff0fffff, |
4956e109 | 1743 | .data = &variant_arm, |
1da177e4 | 1744 | }, |
768fbc18 PM |
1745 | { |
1746 | .id = 0x01041180, | |
1747 | .mask = 0xff0fffff, | |
1748 | .data = &variant_arm_extended_fifo, | |
1749 | }, | |
3a37298a PM |
1750 | { |
1751 | .id = 0x02041180, | |
1752 | .mask = 0xff0fffff, | |
1753 | .data = &variant_arm_extended_fifo_hwfc, | |
1754 | }, | |
1da177e4 LT |
1755 | { |
1756 | .id = 0x00041181, | |
1757 | .mask = 0x000fffff, | |
4956e109 | 1758 | .data = &variant_arm, |
1da177e4 | 1759 | }, |
cc30d60e LW |
1760 | /* ST Micro variants */ |
1761 | { | |
1762 | .id = 0x00180180, | |
1763 | .mask = 0x00ffffff, | |
4956e109 | 1764 | .data = &variant_u300, |
cc30d60e | 1765 | }, |
34fd4213 LW |
1766 | { |
1767 | .id = 0x10180180, | |
1768 | .mask = 0xf0ffffff, | |
1769 | .data = &variant_nomadik, | |
1770 | }, | |
cc30d60e LW |
1771 | { |
1772 | .id = 0x00280180, | |
1773 | .mask = 0x00ffffff, | |
4956e109 RV |
1774 | .data = &variant_u300, |
1775 | }, | |
1776 | { | |
1777 | .id = 0x00480180, | |
1784b157 | 1778 | .mask = 0xf0ffffff, |
4956e109 | 1779 | .data = &variant_ux500, |
cc30d60e | 1780 | }, |
1784b157 PL |
1781 | { |
1782 | .id = 0x10480180, | |
1783 | .mask = 0xf0ffffff, | |
1784 | .data = &variant_ux500v2, | |
1785 | }, | |
1da177e4 LT |
1786 | { 0, 0 }, |
1787 | }; | |
1788 | ||
9f99835f DM |
1789 | MODULE_DEVICE_TABLE(amba, mmci_ids); |
1790 | ||
1da177e4 LT |
1791 | static struct amba_driver mmci_driver = { |
1792 | .drv = { | |
1793 | .name = DRIVER_NAME, | |
48fa7003 | 1794 | .pm = &mmci_dev_pm_ops, |
1da177e4 LT |
1795 | }, |
1796 | .probe = mmci_probe, | |
0433c143 | 1797 | .remove = mmci_remove, |
1da177e4 LT |
1798 | .id_table = mmci_ids, |
1799 | }; | |
1800 | ||
9e5ed094 | 1801 | module_amba_driver(mmci_driver); |
1da177e4 | 1802 | |
1da177e4 LT |
1803 | module_param(fmax, uint, 0444); |
1804 | ||
1805 | MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); | |
1806 | MODULE_LICENSE("GPL"); |