Commit | Line | Data |
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1da177e4 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. | |
c8ebae37 | 5 | * Copyright (C) 2010 ST-Ericsson SA |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/device.h> | |
ef289982 | 16 | #include <linux/io.h> |
1da177e4 | 17 | #include <linux/interrupt.h> |
613b152c | 18 | #include <linux/kernel.h> |
000bc9d5 | 19 | #include <linux/slab.h> |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/err.h> | |
22 | #include <linux/highmem.h> | |
019a5f56 | 23 | #include <linux/log2.h> |
70be208f | 24 | #include <linux/mmc/pm.h> |
1da177e4 | 25 | #include <linux/mmc/host.h> |
34177802 | 26 | #include <linux/mmc/card.h> |
d2762090 | 27 | #include <linux/mmc/slot-gpio.h> |
a62c80e5 | 28 | #include <linux/amba/bus.h> |
f8ce2547 | 29 | #include <linux/clk.h> |
bd6dee6f | 30 | #include <linux/scatterlist.h> |
89001446 | 31 | #include <linux/gpio.h> |
9a597016 | 32 | #include <linux/of_gpio.h> |
34e84f39 | 33 | #include <linux/regulator/consumer.h> |
c8ebae37 RK |
34 | #include <linux/dmaengine.h> |
35 | #include <linux/dma-mapping.h> | |
36 | #include <linux/amba/mmci.h> | |
1c3be369 | 37 | #include <linux/pm_runtime.h> |
258aea76 | 38 | #include <linux/types.h> |
a9a83785 | 39 | #include <linux/pinctrl/consumer.h> |
1da177e4 | 40 | |
7b09cdac | 41 | #include <asm/div64.h> |
1da177e4 | 42 | #include <asm/io.h> |
c6b8fdad | 43 | #include <asm/sizes.h> |
1da177e4 LT |
44 | |
45 | #include "mmci.h" | |
46 | ||
47 | #define DRIVER_NAME "mmci-pl18x" | |
48 | ||
1da177e4 LT |
49 | static unsigned int fmax = 515633; |
50 | ||
4956e109 RV |
51 | /** |
52 | * struct variant_data - MMCI variant-specific quirks | |
53 | * @clkreg: default value for MCICLOCK register | |
4380c14f | 54 | * @clkreg_enable: enable value for MMCICLOCK register |
08458ef6 | 55 | * @datalength_bits: number of bits in the MMCIDATALENGTH register |
8301bb68 RV |
56 | * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY |
57 | * is asserted (likewise for RX) | |
58 | * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY | |
59 | * is asserted (likewise for RX) | |
34177802 | 60 | * @sdio: variant supports SDIO |
b70a67f9 | 61 | * @st_clkdiv: true if using a ST-specific clock divider algorithm |
e17dca2b | 62 | * @datactrl_mask_ddrmode: ddr mode mask in datactrl register. |
1784b157 | 63 | * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register |
ff783233 SK |
64 | * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl |
65 | * register | |
7d72a1d4 | 66 | * @pwrreg_powerup: power up value for MMCIPOWER register |
4d1a3a0d | 67 | * @signal_direction: input/out direction of bus signals can be indicated |
f4670dae | 68 | * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock |
01259620 | 69 | * @busy_detect: true if busy detection on dat0 is supported |
1ff44433 | 70 | * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply |
4956e109 RV |
71 | */ |
72 | struct variant_data { | |
73 | unsigned int clkreg; | |
4380c14f | 74 | unsigned int clkreg_enable; |
08458ef6 | 75 | unsigned int datalength_bits; |
8301bb68 RV |
76 | unsigned int fifosize; |
77 | unsigned int fifohalfsize; | |
e17dca2b | 78 | unsigned int datactrl_mask_ddrmode; |
34177802 | 79 | bool sdio; |
b70a67f9 | 80 | bool st_clkdiv; |
1784b157 | 81 | bool blksz_datactrl16; |
ff783233 | 82 | bool blksz_datactrl4; |
7d72a1d4 | 83 | u32 pwrreg_powerup; |
4d1a3a0d | 84 | bool signal_direction; |
f4670dae | 85 | bool pwrreg_clkgate; |
01259620 | 86 | bool busy_detect; |
1ff44433 | 87 | bool pwrreg_nopower; |
4956e109 RV |
88 | }; |
89 | ||
90 | static struct variant_data variant_arm = { | |
8301bb68 RV |
91 | .fifosize = 16 * 4, |
92 | .fifohalfsize = 8 * 4, | |
08458ef6 | 93 | .datalength_bits = 16, |
7d72a1d4 | 94 | .pwrreg_powerup = MCI_PWR_UP, |
4956e109 RV |
95 | }; |
96 | ||
768fbc18 PM |
97 | static struct variant_data variant_arm_extended_fifo = { |
98 | .fifosize = 128 * 4, | |
99 | .fifohalfsize = 64 * 4, | |
100 | .datalength_bits = 16, | |
7d72a1d4 | 101 | .pwrreg_powerup = MCI_PWR_UP, |
768fbc18 PM |
102 | }; |
103 | ||
3a37298a PM |
104 | static struct variant_data variant_arm_extended_fifo_hwfc = { |
105 | .fifosize = 128 * 4, | |
106 | .fifohalfsize = 64 * 4, | |
107 | .clkreg_enable = MCI_ARM_HWFCEN, | |
108 | .datalength_bits = 16, | |
109 | .pwrreg_powerup = MCI_PWR_UP, | |
110 | }; | |
111 | ||
4956e109 | 112 | static struct variant_data variant_u300 = { |
8301bb68 RV |
113 | .fifosize = 16 * 4, |
114 | .fifohalfsize = 8 * 4, | |
49ac215e | 115 | .clkreg_enable = MCI_ST_U300_HWFCEN, |
08458ef6 | 116 | .datalength_bits = 16, |
34177802 | 117 | .sdio = true, |
7d72a1d4 | 118 | .pwrreg_powerup = MCI_PWR_ON, |
4d1a3a0d | 119 | .signal_direction = true, |
f4670dae | 120 | .pwrreg_clkgate = true, |
1ff44433 | 121 | .pwrreg_nopower = true, |
4956e109 RV |
122 | }; |
123 | ||
34fd4213 LW |
124 | static struct variant_data variant_nomadik = { |
125 | .fifosize = 16 * 4, | |
126 | .fifohalfsize = 8 * 4, | |
127 | .clkreg = MCI_CLK_ENABLE, | |
128 | .datalength_bits = 24, | |
129 | .sdio = true, | |
130 | .st_clkdiv = true, | |
131 | .pwrreg_powerup = MCI_PWR_ON, | |
132 | .signal_direction = true, | |
f4670dae | 133 | .pwrreg_clkgate = true, |
1ff44433 | 134 | .pwrreg_nopower = true, |
34fd4213 LW |
135 | }; |
136 | ||
4956e109 | 137 | static struct variant_data variant_ux500 = { |
8301bb68 RV |
138 | .fifosize = 30 * 4, |
139 | .fifohalfsize = 8 * 4, | |
4956e109 | 140 | .clkreg = MCI_CLK_ENABLE, |
49ac215e | 141 | .clkreg_enable = MCI_ST_UX500_HWFCEN, |
08458ef6 | 142 | .datalength_bits = 24, |
34177802 | 143 | .sdio = true, |
b70a67f9 | 144 | .st_clkdiv = true, |
7d72a1d4 | 145 | .pwrreg_powerup = MCI_PWR_ON, |
4d1a3a0d | 146 | .signal_direction = true, |
f4670dae | 147 | .pwrreg_clkgate = true, |
01259620 | 148 | .busy_detect = true, |
1ff44433 | 149 | .pwrreg_nopower = true, |
4956e109 | 150 | }; |
b70a67f9 | 151 | |
1784b157 PL |
152 | static struct variant_data variant_ux500v2 = { |
153 | .fifosize = 30 * 4, | |
154 | .fifohalfsize = 8 * 4, | |
155 | .clkreg = MCI_CLK_ENABLE, | |
156 | .clkreg_enable = MCI_ST_UX500_HWFCEN, | |
e17dca2b | 157 | .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE, |
1784b157 PL |
158 | .datalength_bits = 24, |
159 | .sdio = true, | |
160 | .st_clkdiv = true, | |
161 | .blksz_datactrl16 = true, | |
7d72a1d4 | 162 | .pwrreg_powerup = MCI_PWR_ON, |
4d1a3a0d | 163 | .signal_direction = true, |
f4670dae | 164 | .pwrreg_clkgate = true, |
01259620 | 165 | .busy_detect = true, |
1ff44433 | 166 | .pwrreg_nopower = true, |
1784b157 PL |
167 | }; |
168 | ||
01259620 UH |
169 | static int mmci_card_busy(struct mmc_host *mmc) |
170 | { | |
171 | struct mmci_host *host = mmc_priv(mmc); | |
172 | unsigned long flags; | |
173 | int busy = 0; | |
174 | ||
175 | pm_runtime_get_sync(mmc_dev(mmc)); | |
176 | ||
177 | spin_lock_irqsave(&host->lock, flags); | |
178 | if (readl(host->base + MMCISTATUS) & MCI_ST_CARDBUSY) | |
179 | busy = 1; | |
180 | spin_unlock_irqrestore(&host->lock, flags); | |
181 | ||
182 | pm_runtime_mark_last_busy(mmc_dev(mmc)); | |
183 | pm_runtime_put_autosuspend(mmc_dev(mmc)); | |
184 | ||
185 | return busy; | |
186 | } | |
187 | ||
653a761e UH |
188 | /* |
189 | * Validate mmc prerequisites | |
190 | */ | |
191 | static int mmci_validate_data(struct mmci_host *host, | |
192 | struct mmc_data *data) | |
193 | { | |
194 | if (!data) | |
195 | return 0; | |
196 | ||
197 | if (!is_power_of_2(data->blksz)) { | |
198 | dev_err(mmc_dev(host->mmc), | |
199 | "unsupported block size (%d bytes)\n", data->blksz); | |
200 | return -EINVAL; | |
201 | } | |
202 | ||
203 | return 0; | |
204 | } | |
205 | ||
f829c042 UH |
206 | static void mmci_reg_delay(struct mmci_host *host) |
207 | { | |
208 | /* | |
209 | * According to the spec, at least three feedback clock cycles | |
210 | * of max 52 MHz must pass between two writes to the MMCICLOCK reg. | |
211 | * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. | |
212 | * Worst delay time during card init is at 100 kHz => 30 us. | |
213 | * Worst delay time when up and running is at 25 MHz => 120 ns. | |
214 | */ | |
215 | if (host->cclk < 25000000) | |
216 | udelay(30); | |
217 | else | |
218 | ndelay(120); | |
219 | } | |
220 | ||
7437cfa5 UH |
221 | /* |
222 | * This must be called with host->lock held | |
223 | */ | |
224 | static void mmci_write_clkreg(struct mmci_host *host, u32 clk) | |
225 | { | |
226 | if (host->clk_reg != clk) { | |
227 | host->clk_reg = clk; | |
228 | writel(clk, host->base + MMCICLOCK); | |
229 | } | |
230 | } | |
231 | ||
232 | /* | |
233 | * This must be called with host->lock held | |
234 | */ | |
235 | static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) | |
236 | { | |
237 | if (host->pwr_reg != pwr) { | |
238 | host->pwr_reg = pwr; | |
239 | writel(pwr, host->base + MMCIPOWER); | |
240 | } | |
241 | } | |
242 | ||
9cc639a2 UH |
243 | /* |
244 | * This must be called with host->lock held | |
245 | */ | |
246 | static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) | |
247 | { | |
01259620 UH |
248 | /* Keep ST Micro busy mode if enabled */ |
249 | datactrl |= host->datactrl_reg & MCI_ST_DPSM_BUSYMODE; | |
250 | ||
9cc639a2 UH |
251 | if (host->datactrl_reg != datactrl) { |
252 | host->datactrl_reg = datactrl; | |
253 | writel(datactrl, host->base + MMCIDATACTRL); | |
254 | } | |
255 | } | |
256 | ||
a6a6464a LW |
257 | /* |
258 | * This must be called with host->lock held | |
259 | */ | |
260 | static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) | |
261 | { | |
4956e109 RV |
262 | struct variant_data *variant = host->variant; |
263 | u32 clk = variant->clkreg; | |
a6a6464a | 264 | |
c58a8509 UH |
265 | /* Make sure cclk reflects the current calculated clock */ |
266 | host->cclk = 0; | |
267 | ||
a6a6464a LW |
268 | if (desired) { |
269 | if (desired >= host->mclk) { | |
991a86e1 | 270 | clk = MCI_CLK_BYPASS; |
399bc486 LW |
271 | if (variant->st_clkdiv) |
272 | clk |= MCI_ST_UX500_NEG_EDGE; | |
a6a6464a | 273 | host->cclk = host->mclk; |
b70a67f9 LW |
274 | } else if (variant->st_clkdiv) { |
275 | /* | |
276 | * DB8500 TRM says f = mclk / (clkdiv + 2) | |
277 | * => clkdiv = (mclk / f) - 2 | |
278 | * Round the divider up so we don't exceed the max | |
279 | * frequency | |
280 | */ | |
281 | clk = DIV_ROUND_UP(host->mclk, desired) - 2; | |
282 | if (clk >= 256) | |
283 | clk = 255; | |
284 | host->cclk = host->mclk / (clk + 2); | |
a6a6464a | 285 | } else { |
b70a67f9 LW |
286 | /* |
287 | * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) | |
288 | * => clkdiv = mclk / (2 * f) - 1 | |
289 | */ | |
a6a6464a LW |
290 | clk = host->mclk / (2 * desired) - 1; |
291 | if (clk >= 256) | |
292 | clk = 255; | |
293 | host->cclk = host->mclk / (2 * (clk + 1)); | |
294 | } | |
4380c14f RV |
295 | |
296 | clk |= variant->clkreg_enable; | |
a6a6464a LW |
297 | clk |= MCI_CLK_ENABLE; |
298 | /* This hasn't proven to be worthwhile */ | |
299 | /* clk |= MCI_CLK_PWRSAVE; */ | |
300 | } | |
301 | ||
c58a8509 UH |
302 | /* Set actual clock for debug */ |
303 | host->mmc->actual_clock = host->cclk; | |
304 | ||
9e6c82cd | 305 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) |
771dc157 LW |
306 | clk |= MCI_4BIT_BUS; |
307 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) | |
308 | clk |= MCI_ST_8BIT_BUS; | |
9e6c82cd | 309 | |
6dad6c95 SJ |
310 | if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || |
311 | host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) | |
6dbb6ee0 UH |
312 | clk |= MCI_ST_UX500_NEG_EDGE; |
313 | ||
7437cfa5 | 314 | mmci_write_clkreg(host, clk); |
a6a6464a LW |
315 | } |
316 | ||
1da177e4 LT |
317 | static void |
318 | mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) | |
319 | { | |
320 | writel(0, host->base + MMCICOMMAND); | |
321 | ||
e47c222b RK |
322 | BUG_ON(host->data); |
323 | ||
1da177e4 LT |
324 | host->mrq = NULL; |
325 | host->cmd = NULL; | |
326 | ||
1da177e4 | 327 | mmc_request_done(host->mmc, mrq); |
2cd976c4 UH |
328 | |
329 | pm_runtime_mark_last_busy(mmc_dev(host->mmc)); | |
330 | pm_runtime_put_autosuspend(mmc_dev(host->mmc)); | |
1da177e4 LT |
331 | } |
332 | ||
2686b4b4 LW |
333 | static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) |
334 | { | |
335 | void __iomem *base = host->base; | |
336 | ||
337 | if (host->singleirq) { | |
338 | unsigned int mask0 = readl(base + MMCIMASK0); | |
339 | ||
340 | mask0 &= ~MCI_IRQ1MASK; | |
341 | mask0 |= mask; | |
342 | ||
343 | writel(mask0, base + MMCIMASK0); | |
344 | } | |
345 | ||
346 | writel(mask, base + MMCIMASK1); | |
347 | } | |
348 | ||
1da177e4 LT |
349 | static void mmci_stop_data(struct mmci_host *host) |
350 | { | |
9cc639a2 | 351 | mmci_write_datactrlreg(host, 0); |
2686b4b4 | 352 | mmci_set_mask1(host, 0); |
1da177e4 LT |
353 | host->data = NULL; |
354 | } | |
355 | ||
4ce1d6cb RV |
356 | static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) |
357 | { | |
358 | unsigned int flags = SG_MITER_ATOMIC; | |
359 | ||
360 | if (data->flags & MMC_DATA_READ) | |
361 | flags |= SG_MITER_TO_SG; | |
362 | else | |
363 | flags |= SG_MITER_FROM_SG; | |
364 | ||
365 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); | |
366 | } | |
367 | ||
c8ebae37 RK |
368 | /* |
369 | * All the DMA operation mode stuff goes inside this ifdef. | |
370 | * This assumes that you have a generic DMA device interface, | |
371 | * no custom DMA interfaces are supported. | |
372 | */ | |
373 | #ifdef CONFIG_DMA_ENGINE | |
c3be1efd | 374 | static void mmci_dma_setup(struct mmci_host *host) |
c8ebae37 | 375 | { |
c8ebae37 RK |
376 | const char *rxname, *txname; |
377 | dma_cap_mask_t mask; | |
378 | ||
1fd83f0e LJ |
379 | host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx"); |
380 | host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx"); | |
c8ebae37 | 381 | |
58c7ccbf PF |
382 | /* initialize pre request cookie */ |
383 | host->next_data.cookie = 1; | |
384 | ||
c8ebae37 RK |
385 | /* Try to acquire a generic DMA engine slave channel */ |
386 | dma_cap_zero(mask); | |
387 | dma_cap_set(DMA_SLAVE, mask); | |
388 | ||
1fd83f0e LJ |
389 | /* |
390 | * If only an RX channel is specified, the driver will | |
391 | * attempt to use it bidirectionally, however if it is | |
392 | * is specified but cannot be located, DMA will be disabled. | |
393 | */ | |
394 | if (host->dma_rx_channel && !host->dma_tx_channel) | |
395 | host->dma_tx_channel = host->dma_rx_channel; | |
396 | ||
c8ebae37 RK |
397 | if (host->dma_rx_channel) |
398 | rxname = dma_chan_name(host->dma_rx_channel); | |
399 | else | |
400 | rxname = "none"; | |
401 | ||
402 | if (host->dma_tx_channel) | |
403 | txname = dma_chan_name(host->dma_tx_channel); | |
404 | else | |
405 | txname = "none"; | |
406 | ||
407 | dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", | |
408 | rxname, txname); | |
409 | ||
410 | /* | |
411 | * Limit the maximum segment size in any SG entry according to | |
412 | * the parameters of the DMA engine device. | |
413 | */ | |
414 | if (host->dma_tx_channel) { | |
415 | struct device *dev = host->dma_tx_channel->device->dev; | |
416 | unsigned int max_seg_size = dma_get_max_seg_size(dev); | |
417 | ||
418 | if (max_seg_size < host->mmc->max_seg_size) | |
419 | host->mmc->max_seg_size = max_seg_size; | |
420 | } | |
421 | if (host->dma_rx_channel) { | |
422 | struct device *dev = host->dma_rx_channel->device->dev; | |
423 | unsigned int max_seg_size = dma_get_max_seg_size(dev); | |
424 | ||
425 | if (max_seg_size < host->mmc->max_seg_size) | |
426 | host->mmc->max_seg_size = max_seg_size; | |
427 | } | |
428 | } | |
429 | ||
430 | /* | |
6e0ee714 | 431 | * This is used in or so inline it |
c8ebae37 RK |
432 | * so it can be discarded. |
433 | */ | |
434 | static inline void mmci_dma_release(struct mmci_host *host) | |
435 | { | |
c8ebae37 RK |
436 | if (host->dma_rx_channel) |
437 | dma_release_channel(host->dma_rx_channel); | |
8c3a05b4 | 438 | if (host->dma_tx_channel) |
c8ebae37 RK |
439 | dma_release_channel(host->dma_tx_channel); |
440 | host->dma_rx_channel = host->dma_tx_channel = NULL; | |
441 | } | |
442 | ||
653a761e UH |
443 | static void mmci_dma_data_error(struct mmci_host *host) |
444 | { | |
445 | dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); | |
446 | dmaengine_terminate_all(host->dma_current); | |
447 | host->dma_current = NULL; | |
448 | host->dma_desc_current = NULL; | |
449 | host->data->host_cookie = 0; | |
450 | } | |
451 | ||
c8ebae37 RK |
452 | static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) |
453 | { | |
653a761e | 454 | struct dma_chan *chan; |
c8ebae37 | 455 | enum dma_data_direction dir; |
653a761e UH |
456 | |
457 | if (data->flags & MMC_DATA_READ) { | |
458 | dir = DMA_FROM_DEVICE; | |
459 | chan = host->dma_rx_channel; | |
460 | } else { | |
461 | dir = DMA_TO_DEVICE; | |
462 | chan = host->dma_tx_channel; | |
463 | } | |
464 | ||
465 | dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); | |
466 | } | |
467 | ||
468 | static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) | |
469 | { | |
c8ebae37 RK |
470 | u32 status; |
471 | int i; | |
472 | ||
473 | /* Wait up to 1ms for the DMA to complete */ | |
474 | for (i = 0; ; i++) { | |
475 | status = readl(host->base + MMCISTATUS); | |
476 | if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) | |
477 | break; | |
478 | udelay(10); | |
479 | } | |
480 | ||
481 | /* | |
482 | * Check to see whether we still have some data left in the FIFO - | |
483 | * this catches DMA controllers which are unable to monitor the | |
484 | * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- | |
485 | * contiguous buffers. On TX, we'll get a FIFO underrun error. | |
486 | */ | |
487 | if (status & MCI_RXDATAAVLBLMASK) { | |
653a761e | 488 | mmci_dma_data_error(host); |
c8ebae37 RK |
489 | if (!data->error) |
490 | data->error = -EIO; | |
491 | } | |
492 | ||
58c7ccbf | 493 | if (!data->host_cookie) |
653a761e | 494 | mmci_dma_unmap(host, data); |
c8ebae37 RK |
495 | |
496 | /* | |
497 | * Use of DMA with scatter-gather is impossible. | |
498 | * Give up with DMA and switch back to PIO mode. | |
499 | */ | |
500 | if (status & MCI_RXDATAAVLBLMASK) { | |
501 | dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); | |
502 | mmci_dma_release(host); | |
503 | } | |
c8ebae37 | 504 | |
653a761e UH |
505 | host->dma_current = NULL; |
506 | host->dma_desc_current = NULL; | |
c8ebae37 RK |
507 | } |
508 | ||
653a761e UH |
509 | /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ |
510 | static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, | |
511 | struct dma_chan **dma_chan, | |
512 | struct dma_async_tx_descriptor **dma_desc) | |
c8ebae37 RK |
513 | { |
514 | struct variant_data *variant = host->variant; | |
515 | struct dma_slave_config conf = { | |
516 | .src_addr = host->phybase + MMCIFIFO, | |
517 | .dst_addr = host->phybase + MMCIFIFO, | |
518 | .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
519 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
520 | .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ | |
521 | .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ | |
258aea76 | 522 | .device_fc = false, |
c8ebae37 | 523 | }; |
c8ebae37 RK |
524 | struct dma_chan *chan; |
525 | struct dma_device *device; | |
526 | struct dma_async_tx_descriptor *desc; | |
05f5799c | 527 | enum dma_data_direction buffer_dirn; |
c8ebae37 RK |
528 | int nr_sg; |
529 | ||
c8ebae37 | 530 | if (data->flags & MMC_DATA_READ) { |
05f5799c VK |
531 | conf.direction = DMA_DEV_TO_MEM; |
532 | buffer_dirn = DMA_FROM_DEVICE; | |
c8ebae37 RK |
533 | chan = host->dma_rx_channel; |
534 | } else { | |
05f5799c VK |
535 | conf.direction = DMA_MEM_TO_DEV; |
536 | buffer_dirn = DMA_TO_DEVICE; | |
c8ebae37 RK |
537 | chan = host->dma_tx_channel; |
538 | } | |
539 | ||
540 | /* If there's no DMA channel, fall back to PIO */ | |
541 | if (!chan) | |
542 | return -EINVAL; | |
543 | ||
544 | /* If less than or equal to the fifo size, don't bother with DMA */ | |
58c7ccbf | 545 | if (data->blksz * data->blocks <= variant->fifosize) |
c8ebae37 RK |
546 | return -EINVAL; |
547 | ||
548 | device = chan->device; | |
05f5799c | 549 | nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); |
c8ebae37 RK |
550 | if (nr_sg == 0) |
551 | return -EINVAL; | |
552 | ||
553 | dmaengine_slave_config(chan, &conf); | |
16052827 | 554 | desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, |
c8ebae37 RK |
555 | conf.direction, DMA_CTRL_ACK); |
556 | if (!desc) | |
557 | goto unmap_exit; | |
558 | ||
653a761e UH |
559 | *dma_chan = chan; |
560 | *dma_desc = desc; | |
58c7ccbf PF |
561 | |
562 | return 0; | |
c8ebae37 | 563 | |
58c7ccbf | 564 | unmap_exit: |
05f5799c | 565 | dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); |
58c7ccbf PF |
566 | return -ENOMEM; |
567 | } | |
568 | ||
653a761e UH |
569 | static inline int mmci_dma_prep_data(struct mmci_host *host, |
570 | struct mmc_data *data) | |
571 | { | |
572 | /* Check if next job is already prepared. */ | |
573 | if (host->dma_current && host->dma_desc_current) | |
574 | return 0; | |
575 | ||
576 | /* No job were prepared thus do it now. */ | |
577 | return __mmci_dma_prep_data(host, data, &host->dma_current, | |
578 | &host->dma_desc_current); | |
579 | } | |
580 | ||
581 | static inline int mmci_dma_prep_next(struct mmci_host *host, | |
582 | struct mmc_data *data) | |
583 | { | |
584 | struct mmci_host_next *nd = &host->next_data; | |
585 | return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc); | |
586 | } | |
587 | ||
58c7ccbf PF |
588 | static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) |
589 | { | |
590 | int ret; | |
591 | struct mmc_data *data = host->data; | |
592 | ||
653a761e | 593 | ret = mmci_dma_prep_data(host, host->data); |
58c7ccbf PF |
594 | if (ret) |
595 | return ret; | |
596 | ||
597 | /* Okay, go for it. */ | |
c8ebae37 RK |
598 | dev_vdbg(mmc_dev(host->mmc), |
599 | "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", | |
600 | data->sg_len, data->blksz, data->blocks, data->flags); | |
58c7ccbf PF |
601 | dmaengine_submit(host->dma_desc_current); |
602 | dma_async_issue_pending(host->dma_current); | |
c8ebae37 RK |
603 | |
604 | datactrl |= MCI_DPSM_DMAENABLE; | |
605 | ||
606 | /* Trigger the DMA transfer */ | |
9cc639a2 | 607 | mmci_write_datactrlreg(host, datactrl); |
c8ebae37 RK |
608 | |
609 | /* | |
610 | * Let the MMCI say when the data is ended and it's time | |
611 | * to fire next DMA request. When that happens, MMCI will | |
612 | * call mmci_data_end() | |
613 | */ | |
614 | writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, | |
615 | host->base + MMCIMASK0); | |
616 | return 0; | |
58c7ccbf | 617 | } |
c8ebae37 | 618 | |
58c7ccbf PF |
619 | static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) |
620 | { | |
621 | struct mmci_host_next *next = &host->next_data; | |
622 | ||
653a761e UH |
623 | WARN_ON(data->host_cookie && data->host_cookie != next->cookie); |
624 | WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan)); | |
58c7ccbf PF |
625 | |
626 | host->dma_desc_current = next->dma_desc; | |
627 | host->dma_current = next->dma_chan; | |
58c7ccbf PF |
628 | next->dma_desc = NULL; |
629 | next->dma_chan = NULL; | |
c8ebae37 | 630 | } |
58c7ccbf PF |
631 | |
632 | static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, | |
633 | bool is_first_req) | |
634 | { | |
635 | struct mmci_host *host = mmc_priv(mmc); | |
636 | struct mmc_data *data = mrq->data; | |
637 | struct mmci_host_next *nd = &host->next_data; | |
638 | ||
639 | if (!data) | |
640 | return; | |
641 | ||
653a761e UH |
642 | BUG_ON(data->host_cookie); |
643 | ||
644 | if (mmci_validate_data(host, data)) | |
58c7ccbf | 645 | return; |
58c7ccbf | 646 | |
653a761e UH |
647 | if (!mmci_dma_prep_next(host, data)) |
648 | data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; | |
58c7ccbf PF |
649 | } |
650 | ||
651 | static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, | |
652 | int err) | |
653 | { | |
654 | struct mmci_host *host = mmc_priv(mmc); | |
655 | struct mmc_data *data = mrq->data; | |
58c7ccbf | 656 | |
653a761e | 657 | if (!data || !data->host_cookie) |
58c7ccbf PF |
658 | return; |
659 | ||
653a761e | 660 | mmci_dma_unmap(host, data); |
58c7ccbf | 661 | |
653a761e UH |
662 | if (err) { |
663 | struct mmci_host_next *next = &host->next_data; | |
664 | struct dma_chan *chan; | |
665 | if (data->flags & MMC_DATA_READ) | |
666 | chan = host->dma_rx_channel; | |
667 | else | |
668 | chan = host->dma_tx_channel; | |
669 | dmaengine_terminate_all(chan); | |
58c7ccbf | 670 | |
653a761e UH |
671 | next->dma_desc = NULL; |
672 | next->dma_chan = NULL; | |
58c7ccbf PF |
673 | } |
674 | } | |
675 | ||
c8ebae37 RK |
676 | #else |
677 | /* Blank functions if the DMA engine is not available */ | |
58c7ccbf PF |
678 | static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) |
679 | { | |
680 | } | |
c8ebae37 RK |
681 | static inline void mmci_dma_setup(struct mmci_host *host) |
682 | { | |
683 | } | |
684 | ||
685 | static inline void mmci_dma_release(struct mmci_host *host) | |
686 | { | |
687 | } | |
688 | ||
689 | static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) | |
690 | { | |
691 | } | |
692 | ||
653a761e UH |
693 | static inline void mmci_dma_finalize(struct mmci_host *host, |
694 | struct mmc_data *data) | |
695 | { | |
696 | } | |
697 | ||
c8ebae37 RK |
698 | static inline void mmci_dma_data_error(struct mmci_host *host) |
699 | { | |
700 | } | |
701 | ||
702 | static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) | |
703 | { | |
704 | return -ENOSYS; | |
705 | } | |
58c7ccbf PF |
706 | |
707 | #define mmci_pre_request NULL | |
708 | #define mmci_post_request NULL | |
709 | ||
c8ebae37 RK |
710 | #endif |
711 | ||
1da177e4 LT |
712 | static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) |
713 | { | |
8301bb68 | 714 | struct variant_data *variant = host->variant; |
1da177e4 | 715 | unsigned int datactrl, timeout, irqmask; |
7b09cdac | 716 | unsigned long long clks; |
1da177e4 | 717 | void __iomem *base; |
3bc87f24 | 718 | int blksz_bits; |
1da177e4 | 719 | |
64de0289 LW |
720 | dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", |
721 | data->blksz, data->blocks, data->flags); | |
1da177e4 LT |
722 | |
723 | host->data = data; | |
528320db | 724 | host->size = data->blksz * data->blocks; |
51d4375d | 725 | data->bytes_xfered = 0; |
1da177e4 | 726 | |
7b09cdac | 727 | clks = (unsigned long long)data->timeout_ns * host->cclk; |
c4a35769 | 728 | do_div(clks, NSEC_PER_SEC); |
7b09cdac RK |
729 | |
730 | timeout = data->timeout_clks + (unsigned int)clks; | |
1da177e4 LT |
731 | |
732 | base = host->base; | |
733 | writel(timeout, base + MMCIDATATIMER); | |
734 | writel(host->size, base + MMCIDATALENGTH); | |
735 | ||
3bc87f24 RK |
736 | blksz_bits = ffs(data->blksz) - 1; |
737 | BUG_ON(1 << blksz_bits != data->blksz); | |
738 | ||
1784b157 PL |
739 | if (variant->blksz_datactrl16) |
740 | datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); | |
ff783233 SK |
741 | else if (variant->blksz_datactrl4) |
742 | datactrl = MCI_DPSM_ENABLE | (data->blksz << 4); | |
1784b157 PL |
743 | else |
744 | datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; | |
c8ebae37 RK |
745 | |
746 | if (data->flags & MMC_DATA_READ) | |
1da177e4 | 747 | datactrl |= MCI_DPSM_DIRECTION; |
c8ebae37 | 748 | |
7258db7e UH |
749 | /* The ST Micro variants has a special bit to enable SDIO */ |
750 | if (variant->sdio && host->mmc->card) | |
06c1a121 UH |
751 | if (mmc_card_sdio(host->mmc->card)) { |
752 | /* | |
753 | * The ST Micro variants has a special bit | |
754 | * to enable SDIO. | |
755 | */ | |
756 | u32 clk; | |
757 | ||
7258db7e UH |
758 | datactrl |= MCI_ST_DPSM_SDIOEN; |
759 | ||
06c1a121 | 760 | /* |
70ac0935 UH |
761 | * The ST Micro variant for SDIO small write transfers |
762 | * needs to have clock H/W flow control disabled, | |
763 | * otherwise the transfer will not start. The threshold | |
764 | * depends on the rate of MCLK. | |
06c1a121 | 765 | */ |
70ac0935 UH |
766 | if (data->flags & MMC_DATA_WRITE && |
767 | (host->size < 8 || | |
768 | (host->size <= 8 && host->mclk > 50000000))) | |
06c1a121 UH |
769 | clk = host->clk_reg & ~variant->clkreg_enable; |
770 | else | |
771 | clk = host->clk_reg | variant->clkreg_enable; | |
772 | ||
773 | mmci_write_clkreg(host, clk); | |
774 | } | |
775 | ||
6dad6c95 SJ |
776 | if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || |
777 | host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) | |
e17dca2b | 778 | datactrl |= variant->datactrl_mask_ddrmode; |
6dbb6ee0 | 779 | |
c8ebae37 RK |
780 | /* |
781 | * Attempt to use DMA operation mode, if this | |
782 | * should fail, fall back to PIO mode | |
783 | */ | |
784 | if (!mmci_dma_start_data(host, datactrl)) | |
785 | return; | |
786 | ||
787 | /* IRQ mode, map the SG list for CPU reading/writing */ | |
788 | mmci_init_sg(host, data); | |
789 | ||
790 | if (data->flags & MMC_DATA_READ) { | |
1da177e4 | 791 | irqmask = MCI_RXFIFOHALFFULLMASK; |
0425a142 RK |
792 | |
793 | /* | |
c4d877c1 RK |
794 | * If we have less than the fifo 'half-full' threshold to |
795 | * transfer, trigger a PIO interrupt as soon as any data | |
796 | * is available. | |
0425a142 | 797 | */ |
c4d877c1 | 798 | if (host->size < variant->fifohalfsize) |
0425a142 | 799 | irqmask |= MCI_RXDATAAVLBLMASK; |
1da177e4 LT |
800 | } else { |
801 | /* | |
802 | * We don't actually need to include "FIFO empty" here | |
803 | * since its implicit in "FIFO half empty". | |
804 | */ | |
805 | irqmask = MCI_TXFIFOHALFEMPTYMASK; | |
806 | } | |
807 | ||
9cc639a2 | 808 | mmci_write_datactrlreg(host, datactrl); |
1da177e4 | 809 | writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); |
2686b4b4 | 810 | mmci_set_mask1(host, irqmask); |
1da177e4 LT |
811 | } |
812 | ||
813 | static void | |
814 | mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) | |
815 | { | |
816 | void __iomem *base = host->base; | |
817 | ||
64de0289 | 818 | dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", |
1da177e4 LT |
819 | cmd->opcode, cmd->arg, cmd->flags); |
820 | ||
821 | if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { | |
822 | writel(0, base + MMCICOMMAND); | |
6adb2a80 | 823 | mmci_reg_delay(host); |
1da177e4 LT |
824 | } |
825 | ||
826 | c |= cmd->opcode | MCI_CPSM_ENABLE; | |
e9225176 RK |
827 | if (cmd->flags & MMC_RSP_PRESENT) { |
828 | if (cmd->flags & MMC_RSP_136) | |
829 | c |= MCI_CPSM_LONGRSP; | |
1da177e4 | 830 | c |= MCI_CPSM_RESPONSE; |
1da177e4 LT |
831 | } |
832 | if (/*interrupt*/0) | |
833 | c |= MCI_CPSM_INTERRUPT; | |
834 | ||
835 | host->cmd = cmd; | |
836 | ||
837 | writel(cmd->arg, base + MMCIARGUMENT); | |
838 | writel(c, base + MMCICOMMAND); | |
839 | } | |
840 | ||
841 | static void | |
842 | mmci_data_irq(struct mmci_host *host, struct mmc_data *data, | |
843 | unsigned int status) | |
844 | { | |
f20f8f21 | 845 | /* First check for errors */ |
b63038d6 UH |
846 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| |
847 | MCI_TXUNDERRUN|MCI_RXOVERRUN)) { | |
8cb28155 | 848 | u32 remain, success; |
f20f8f21 | 849 | |
c8ebae37 | 850 | /* Terminate the DMA transfer */ |
653a761e | 851 | if (dma_inprogress(host)) { |
c8ebae37 | 852 | mmci_dma_data_error(host); |
653a761e UH |
853 | mmci_dma_unmap(host, data); |
854 | } | |
e9c091b4 RK |
855 | |
856 | /* | |
c8afc9d5 RK |
857 | * Calculate how far we are into the transfer. Note that |
858 | * the data counter gives the number of bytes transferred | |
859 | * on the MMC bus, not on the host side. On reads, this | |
860 | * can be as much as a FIFO-worth of data ahead. This | |
861 | * matters for FIFO overruns only. | |
e9c091b4 | 862 | */ |
f5a106d9 | 863 | remain = readl(host->base + MMCIDATACNT); |
8cb28155 LW |
864 | success = data->blksz * data->blocks - remain; |
865 | ||
c8afc9d5 RK |
866 | dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", |
867 | status, success); | |
8cb28155 LW |
868 | if (status & MCI_DATACRCFAIL) { |
869 | /* Last block was not successful */ | |
c8afc9d5 | 870 | success -= 1; |
17b0429d | 871 | data->error = -EILSEQ; |
8cb28155 | 872 | } else if (status & MCI_DATATIMEOUT) { |
17b0429d | 873 | data->error = -ETIMEDOUT; |
757df746 LW |
874 | } else if (status & MCI_STARTBITERR) { |
875 | data->error = -ECOMM; | |
c8afc9d5 RK |
876 | } else if (status & MCI_TXUNDERRUN) { |
877 | data->error = -EIO; | |
878 | } else if (status & MCI_RXOVERRUN) { | |
879 | if (success > host->variant->fifosize) | |
880 | success -= host->variant->fifosize; | |
881 | else | |
882 | success = 0; | |
17b0429d | 883 | data->error = -EIO; |
4ce1d6cb | 884 | } |
51d4375d | 885 | data->bytes_xfered = round_down(success, data->blksz); |
1da177e4 | 886 | } |
f20f8f21 | 887 | |
8cb28155 LW |
888 | if (status & MCI_DATABLOCKEND) |
889 | dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); | |
f20f8f21 | 890 | |
ccff9b51 | 891 | if (status & MCI_DATAEND || data->error) { |
c8ebae37 | 892 | if (dma_inprogress(host)) |
653a761e | 893 | mmci_dma_finalize(host, data); |
1da177e4 LT |
894 | mmci_stop_data(host); |
895 | ||
8cb28155 LW |
896 | if (!data->error) |
897 | /* The error clause is handled above, success! */ | |
51d4375d | 898 | data->bytes_xfered = data->blksz * data->blocks; |
f20f8f21 | 899 | |
024629c6 | 900 | if (!data->stop || host->mrq->sbc) { |
1da177e4 LT |
901 | mmci_request_end(host, data->mrq); |
902 | } else { | |
903 | mmci_start_command(host, data->stop, 0); | |
904 | } | |
905 | } | |
906 | } | |
907 | ||
908 | static void | |
909 | mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, | |
910 | unsigned int status) | |
911 | { | |
912 | void __iomem *base = host->base; | |
024629c6 | 913 | bool sbc = (cmd == host->mrq->sbc); |
8d94b54d UH |
914 | bool busy_resp = host->variant->busy_detect && |
915 | (cmd->flags & MMC_RSP_BUSY); | |
916 | ||
917 | /* Check if we need to wait for busy completion. */ | |
918 | if (host->busy_status && (status & MCI_ST_CARDBUSY)) | |
919 | return; | |
920 | ||
921 | /* Enable busy completion if needed and supported. */ | |
922 | if (!host->busy_status && busy_resp && | |
923 | !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) && | |
924 | (readl(base + MMCISTATUS) & MCI_ST_CARDBUSY)) { | |
925 | writel(readl(base + MMCIMASK0) | MCI_ST_BUSYEND, | |
926 | base + MMCIMASK0); | |
927 | host->busy_status = status & (MCI_CMDSENT|MCI_CMDRESPEND); | |
928 | return; | |
929 | } | |
930 | ||
931 | /* At busy completion, mask the IRQ and complete the request. */ | |
932 | if (host->busy_status) { | |
933 | writel(readl(base + MMCIMASK0) & ~MCI_ST_BUSYEND, | |
934 | base + MMCIMASK0); | |
935 | host->busy_status = 0; | |
936 | } | |
1da177e4 LT |
937 | |
938 | host->cmd = NULL; | |
939 | ||
1da177e4 | 940 | if (status & MCI_CMDTIMEOUT) { |
17b0429d | 941 | cmd->error = -ETIMEDOUT; |
1da177e4 | 942 | } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { |
17b0429d | 943 | cmd->error = -EILSEQ; |
9047b435 RKAL |
944 | } else { |
945 | cmd->resp[0] = readl(base + MMCIRESPONSE0); | |
946 | cmd->resp[1] = readl(base + MMCIRESPONSE1); | |
947 | cmd->resp[2] = readl(base + MMCIRESPONSE2); | |
948 | cmd->resp[3] = readl(base + MMCIRESPONSE3); | |
1da177e4 LT |
949 | } |
950 | ||
024629c6 | 951 | if ((!sbc && !cmd->data) || cmd->error) { |
3b6e3c73 UH |
952 | if (host->data) { |
953 | /* Terminate the DMA transfer */ | |
653a761e | 954 | if (dma_inprogress(host)) { |
3b6e3c73 | 955 | mmci_dma_data_error(host); |
653a761e UH |
956 | mmci_dma_unmap(host, host->data); |
957 | } | |
e47c222b | 958 | mmci_stop_data(host); |
3b6e3c73 | 959 | } |
024629c6 UH |
960 | mmci_request_end(host, host->mrq); |
961 | } else if (sbc) { | |
962 | mmci_start_command(host, host->mrq->cmd, 0); | |
1da177e4 LT |
963 | } else if (!(cmd->data->flags & MMC_DATA_READ)) { |
964 | mmci_start_data(host, cmd->data); | |
965 | } | |
966 | } | |
967 | ||
968 | static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) | |
969 | { | |
970 | void __iomem *base = host->base; | |
971 | char *ptr = buffer; | |
972 | u32 status; | |
26eed9a5 | 973 | int host_remain = host->size; |
1da177e4 LT |
974 | |
975 | do { | |
26eed9a5 | 976 | int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); |
1da177e4 LT |
977 | |
978 | if (count > remain) | |
979 | count = remain; | |
980 | ||
981 | if (count <= 0) | |
982 | break; | |
983 | ||
393e5e24 UH |
984 | /* |
985 | * SDIO especially may want to send something that is | |
986 | * not divisible by 4 (as opposed to card sectors | |
987 | * etc). Therefore make sure to always read the last bytes | |
988 | * while only doing full 32-bit reads towards the FIFO. | |
989 | */ | |
990 | if (unlikely(count & 0x3)) { | |
991 | if (count < 4) { | |
992 | unsigned char buf[4]; | |
4b85da08 | 993 | ioread32_rep(base + MMCIFIFO, buf, 1); |
393e5e24 UH |
994 | memcpy(ptr, buf, count); |
995 | } else { | |
4b85da08 | 996 | ioread32_rep(base + MMCIFIFO, ptr, count >> 2); |
393e5e24 UH |
997 | count &= ~0x3; |
998 | } | |
999 | } else { | |
4b85da08 | 1000 | ioread32_rep(base + MMCIFIFO, ptr, count >> 2); |
393e5e24 | 1001 | } |
1da177e4 LT |
1002 | |
1003 | ptr += count; | |
1004 | remain -= count; | |
26eed9a5 | 1005 | host_remain -= count; |
1da177e4 LT |
1006 | |
1007 | if (remain == 0) | |
1008 | break; | |
1009 | ||
1010 | status = readl(base + MMCISTATUS); | |
1011 | } while (status & MCI_RXDATAAVLBL); | |
1012 | ||
1013 | return ptr - buffer; | |
1014 | } | |
1015 | ||
1016 | static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) | |
1017 | { | |
8301bb68 | 1018 | struct variant_data *variant = host->variant; |
1da177e4 LT |
1019 | void __iomem *base = host->base; |
1020 | char *ptr = buffer; | |
1021 | ||
1022 | do { | |
1023 | unsigned int count, maxcnt; | |
1024 | ||
8301bb68 RV |
1025 | maxcnt = status & MCI_TXFIFOEMPTY ? |
1026 | variant->fifosize : variant->fifohalfsize; | |
1da177e4 LT |
1027 | count = min(remain, maxcnt); |
1028 | ||
34177802 LW |
1029 | /* |
1030 | * SDIO especially may want to send something that is | |
1031 | * not divisible by 4 (as opposed to card sectors | |
1032 | * etc), and the FIFO only accept full 32-bit writes. | |
1033 | * So compensate by adding +3 on the count, a single | |
1034 | * byte become a 32bit write, 7 bytes will be two | |
1035 | * 32bit writes etc. | |
1036 | */ | |
4b85da08 | 1037 | iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); |
1da177e4 LT |
1038 | |
1039 | ptr += count; | |
1040 | remain -= count; | |
1041 | ||
1042 | if (remain == 0) | |
1043 | break; | |
1044 | ||
1045 | status = readl(base + MMCISTATUS); | |
1046 | } while (status & MCI_TXFIFOHALFEMPTY); | |
1047 | ||
1048 | return ptr - buffer; | |
1049 | } | |
1050 | ||
1051 | /* | |
1052 | * PIO data transfer IRQ handler. | |
1053 | */ | |
7d12e780 | 1054 | static irqreturn_t mmci_pio_irq(int irq, void *dev_id) |
1da177e4 LT |
1055 | { |
1056 | struct mmci_host *host = dev_id; | |
4ce1d6cb | 1057 | struct sg_mapping_iter *sg_miter = &host->sg_miter; |
8301bb68 | 1058 | struct variant_data *variant = host->variant; |
1da177e4 | 1059 | void __iomem *base = host->base; |
4ce1d6cb | 1060 | unsigned long flags; |
1da177e4 LT |
1061 | u32 status; |
1062 | ||
1063 | status = readl(base + MMCISTATUS); | |
1064 | ||
64de0289 | 1065 | dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); |
1da177e4 | 1066 | |
4ce1d6cb RV |
1067 | local_irq_save(flags); |
1068 | ||
1da177e4 | 1069 | do { |
1da177e4 LT |
1070 | unsigned int remain, len; |
1071 | char *buffer; | |
1072 | ||
1073 | /* | |
1074 | * For write, we only need to test the half-empty flag | |
1075 | * here - if the FIFO is completely empty, then by | |
1076 | * definition it is more than half empty. | |
1077 | * | |
1078 | * For read, check for data available. | |
1079 | */ | |
1080 | if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) | |
1081 | break; | |
1082 | ||
4ce1d6cb RV |
1083 | if (!sg_miter_next(sg_miter)) |
1084 | break; | |
1085 | ||
1086 | buffer = sg_miter->addr; | |
1087 | remain = sg_miter->length; | |
1da177e4 LT |
1088 | |
1089 | len = 0; | |
1090 | if (status & MCI_RXACTIVE) | |
1091 | len = mmci_pio_read(host, buffer, remain); | |
1092 | if (status & MCI_TXACTIVE) | |
1093 | len = mmci_pio_write(host, buffer, remain, status); | |
1094 | ||
4ce1d6cb | 1095 | sg_miter->consumed = len; |
1da177e4 | 1096 | |
1da177e4 LT |
1097 | host->size -= len; |
1098 | remain -= len; | |
1099 | ||
1100 | if (remain) | |
1101 | break; | |
1102 | ||
1da177e4 LT |
1103 | status = readl(base + MMCISTATUS); |
1104 | } while (1); | |
1105 | ||
4ce1d6cb RV |
1106 | sg_miter_stop(sg_miter); |
1107 | ||
1108 | local_irq_restore(flags); | |
1109 | ||
1da177e4 | 1110 | /* |
c4d877c1 RK |
1111 | * If we have less than the fifo 'half-full' threshold to transfer, |
1112 | * trigger a PIO interrupt as soon as any data is available. | |
1da177e4 | 1113 | */ |
c4d877c1 | 1114 | if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) |
2686b4b4 | 1115 | mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); |
1da177e4 LT |
1116 | |
1117 | /* | |
1118 | * If we run out of data, disable the data IRQs; this | |
1119 | * prevents a race where the FIFO becomes empty before | |
1120 | * the chip itself has disabled the data path, and | |
1121 | * stops us racing with our data end IRQ. | |
1122 | */ | |
1123 | if (host->size == 0) { | |
2686b4b4 | 1124 | mmci_set_mask1(host, 0); |
1da177e4 LT |
1125 | writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); |
1126 | } | |
1127 | ||
1128 | return IRQ_HANDLED; | |
1129 | } | |
1130 | ||
1131 | /* | |
1132 | * Handle completion of command and data transfers. | |
1133 | */ | |
7d12e780 | 1134 | static irqreturn_t mmci_irq(int irq, void *dev_id) |
1da177e4 LT |
1135 | { |
1136 | struct mmci_host *host = dev_id; | |
1137 | u32 status; | |
1138 | int ret = 0; | |
1139 | ||
1140 | spin_lock(&host->lock); | |
1141 | ||
1142 | do { | |
1143 | struct mmc_command *cmd; | |
1144 | struct mmc_data *data; | |
1145 | ||
1146 | status = readl(host->base + MMCISTATUS); | |
2686b4b4 LW |
1147 | |
1148 | if (host->singleirq) { | |
1149 | if (status & readl(host->base + MMCIMASK1)) | |
1150 | mmci_pio_irq(irq, dev_id); | |
1151 | ||
1152 | status &= ~MCI_IRQ1MASK; | |
1153 | } | |
1154 | ||
8d94b54d UH |
1155 | /* |
1156 | * We intentionally clear the MCI_ST_CARDBUSY IRQ here (if it's | |
1157 | * enabled) since the HW seems to be triggering the IRQ on both | |
1158 | * edges while monitoring DAT0 for busy completion. | |
1159 | */ | |
1da177e4 LT |
1160 | status &= readl(host->base + MMCIMASK0); |
1161 | writel(status, host->base + MMCICLEAR); | |
1162 | ||
64de0289 | 1163 | dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); |
1da177e4 | 1164 | |
e7f3d222 | 1165 | cmd = host->cmd; |
8d94b54d UH |
1166 | if ((status|host->busy_status) & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT| |
1167 | MCI_CMDSENT|MCI_CMDRESPEND) && cmd) | |
e7f3d222 UH |
1168 | mmci_cmd_irq(host, cmd, status); |
1169 | ||
1da177e4 | 1170 | data = host->data; |
b63038d6 UH |
1171 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| |
1172 | MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND| | |
1173 | MCI_DATABLOCKEND) && data) | |
1da177e4 LT |
1174 | mmci_data_irq(host, data, status); |
1175 | ||
8d94b54d UH |
1176 | /* Don't poll for busy completion in irq context. */ |
1177 | if (host->busy_status) | |
1178 | status &= ~MCI_ST_CARDBUSY; | |
1179 | ||
1da177e4 LT |
1180 | ret = 1; |
1181 | } while (status); | |
1182 | ||
1183 | spin_unlock(&host->lock); | |
1184 | ||
1185 | return IRQ_RETVAL(ret); | |
1186 | } | |
1187 | ||
1188 | static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
1189 | { | |
1190 | struct mmci_host *host = mmc_priv(mmc); | |
9e943021 | 1191 | unsigned long flags; |
1da177e4 LT |
1192 | |
1193 | WARN_ON(host->mrq != NULL); | |
1194 | ||
653a761e UH |
1195 | mrq->cmd->error = mmci_validate_data(host, mrq->data); |
1196 | if (mrq->cmd->error) { | |
255d01af PO |
1197 | mmc_request_done(mmc, mrq); |
1198 | return; | |
1199 | } | |
1200 | ||
1c3be369 RK |
1201 | pm_runtime_get_sync(mmc_dev(mmc)); |
1202 | ||
9e943021 | 1203 | spin_lock_irqsave(&host->lock, flags); |
1da177e4 LT |
1204 | |
1205 | host->mrq = mrq; | |
1206 | ||
58c7ccbf PF |
1207 | if (mrq->data) |
1208 | mmci_get_next_data(host, mrq->data); | |
1209 | ||
1da177e4 LT |
1210 | if (mrq->data && mrq->data->flags & MMC_DATA_READ) |
1211 | mmci_start_data(host, mrq->data); | |
1212 | ||
024629c6 UH |
1213 | if (mrq->sbc) |
1214 | mmci_start_command(host, mrq->sbc, 0); | |
1215 | else | |
1216 | mmci_start_command(host, mrq->cmd, 0); | |
1da177e4 | 1217 | |
9e943021 | 1218 | spin_unlock_irqrestore(&host->lock, flags); |
1da177e4 LT |
1219 | } |
1220 | ||
1221 | static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
1222 | { | |
1223 | struct mmci_host *host = mmc_priv(mmc); | |
7d72a1d4 | 1224 | struct variant_data *variant = host->variant; |
a6a6464a LW |
1225 | u32 pwr = 0; |
1226 | unsigned long flags; | |
db90f91f | 1227 | int ret; |
1da177e4 | 1228 | |
2cd976c4 UH |
1229 | pm_runtime_get_sync(mmc_dev(mmc)); |
1230 | ||
bc521818 UH |
1231 | if (host->plat->ios_handler && |
1232 | host->plat->ios_handler(mmc_dev(mmc), ios)) | |
1233 | dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); | |
1234 | ||
1da177e4 LT |
1235 | switch (ios->power_mode) { |
1236 | case MMC_POWER_OFF: | |
599c1d5c UH |
1237 | if (!IS_ERR(mmc->supply.vmmc)) |
1238 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); | |
237fb5e6 | 1239 | |
7c0136ef | 1240 | if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { |
237fb5e6 | 1241 | regulator_disable(mmc->supply.vqmmc); |
7c0136ef UH |
1242 | host->vqmmc_enabled = false; |
1243 | } | |
237fb5e6 | 1244 | |
1da177e4 LT |
1245 | break; |
1246 | case MMC_POWER_UP: | |
599c1d5c UH |
1247 | if (!IS_ERR(mmc->supply.vmmc)) |
1248 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); | |
1249 | ||
7d72a1d4 UH |
1250 | /* |
1251 | * The ST Micro variant doesn't have the PL180s MCI_PWR_UP | |
1252 | * and instead uses MCI_PWR_ON so apply whatever value is | |
1253 | * configured in the variant data. | |
1254 | */ | |
1255 | pwr |= variant->pwrreg_powerup; | |
1256 | ||
1257 | break; | |
1da177e4 | 1258 | case MMC_POWER_ON: |
7c0136ef | 1259 | if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { |
db90f91f LJ |
1260 | ret = regulator_enable(mmc->supply.vqmmc); |
1261 | if (ret < 0) | |
1262 | dev_err(mmc_dev(mmc), | |
1263 | "failed to enable vqmmc regulator\n"); | |
7c0136ef UH |
1264 | else |
1265 | host->vqmmc_enabled = true; | |
db90f91f | 1266 | } |
237fb5e6 | 1267 | |
1da177e4 LT |
1268 | pwr |= MCI_PWR_ON; |
1269 | break; | |
1270 | } | |
1271 | ||
4d1a3a0d UH |
1272 | if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { |
1273 | /* | |
1274 | * The ST Micro variant has some additional bits | |
1275 | * indicating signal direction for the signals in | |
1276 | * the SD/MMC bus and feedback-clock usage. | |
1277 | */ | |
4593df29 | 1278 | pwr |= host->pwr_reg_add; |
4d1a3a0d UH |
1279 | |
1280 | if (ios->bus_width == MMC_BUS_WIDTH_4) | |
1281 | pwr &= ~MCI_ST_DATA74DIREN; | |
1282 | else if (ios->bus_width == MMC_BUS_WIDTH_1) | |
1283 | pwr &= (~MCI_ST_DATA74DIREN & | |
1284 | ~MCI_ST_DATA31DIREN & | |
1285 | ~MCI_ST_DATA2DIREN); | |
1286 | } | |
1287 | ||
cc30d60e | 1288 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { |
f17a1f06 | 1289 | if (host->hw_designer != AMBA_VENDOR_ST) |
cc30d60e LW |
1290 | pwr |= MCI_ROD; |
1291 | else { | |
1292 | /* | |
1293 | * The ST Micro variant use the ROD bit for something | |
1294 | * else and only has OD (Open Drain). | |
1295 | */ | |
1296 | pwr |= MCI_OD; | |
1297 | } | |
1298 | } | |
1da177e4 | 1299 | |
f4670dae UH |
1300 | /* |
1301 | * If clock = 0 and the variant requires the MMCIPOWER to be used for | |
1302 | * gating the clock, the MCI_PWR_ON bit is cleared. | |
1303 | */ | |
1304 | if (!ios->clock && variant->pwrreg_clkgate) | |
1305 | pwr &= ~MCI_PWR_ON; | |
1306 | ||
a6a6464a LW |
1307 | spin_lock_irqsave(&host->lock, flags); |
1308 | ||
1309 | mmci_set_clkreg(host, ios->clock); | |
7437cfa5 | 1310 | mmci_write_pwrreg(host, pwr); |
f829c042 | 1311 | mmci_reg_delay(host); |
a6a6464a LW |
1312 | |
1313 | spin_unlock_irqrestore(&host->lock, flags); | |
2cd976c4 | 1314 | |
2cd976c4 UH |
1315 | pm_runtime_mark_last_busy(mmc_dev(mmc)); |
1316 | pm_runtime_put_autosuspend(mmc_dev(mmc)); | |
1da177e4 LT |
1317 | } |
1318 | ||
89001446 RK |
1319 | static int mmci_get_cd(struct mmc_host *mmc) |
1320 | { | |
1321 | struct mmci_host *host = mmc_priv(mmc); | |
29719445 | 1322 | struct mmci_platform_data *plat = host->plat; |
d2762090 | 1323 | unsigned int status = mmc_gpio_get_cd(mmc); |
89001446 | 1324 | |
d2762090 | 1325 | if (status == -ENOSYS) { |
4b8caec0 RV |
1326 | if (!plat->status) |
1327 | return 1; /* Assume always present */ | |
1328 | ||
29719445 | 1329 | status = plat->status(mmc_dev(host->mmc)); |
d2762090 | 1330 | } |
74bc8093 | 1331 | return status; |
89001446 RK |
1332 | } |
1333 | ||
0f3ed7f7 UH |
1334 | static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) |
1335 | { | |
1336 | int ret = 0; | |
1337 | ||
1338 | if (!IS_ERR(mmc->supply.vqmmc)) { | |
1339 | ||
1340 | pm_runtime_get_sync(mmc_dev(mmc)); | |
1341 | ||
1342 | switch (ios->signal_voltage) { | |
1343 | case MMC_SIGNAL_VOLTAGE_330: | |
1344 | ret = regulator_set_voltage(mmc->supply.vqmmc, | |
1345 | 2700000, 3600000); | |
1346 | break; | |
1347 | case MMC_SIGNAL_VOLTAGE_180: | |
1348 | ret = regulator_set_voltage(mmc->supply.vqmmc, | |
1349 | 1700000, 1950000); | |
1350 | break; | |
1351 | case MMC_SIGNAL_VOLTAGE_120: | |
1352 | ret = regulator_set_voltage(mmc->supply.vqmmc, | |
1353 | 1100000, 1300000); | |
1354 | break; | |
1355 | } | |
1356 | ||
1357 | if (ret) | |
1358 | dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); | |
1359 | ||
1360 | pm_runtime_mark_last_busy(mmc_dev(mmc)); | |
1361 | pm_runtime_put_autosuspend(mmc_dev(mmc)); | |
1362 | } | |
1363 | ||
1364 | return ret; | |
1365 | } | |
1366 | ||
01259620 | 1367 | static struct mmc_host_ops mmci_ops = { |
1da177e4 | 1368 | .request = mmci_request, |
58c7ccbf PF |
1369 | .pre_req = mmci_pre_request, |
1370 | .post_req = mmci_post_request, | |
1da177e4 | 1371 | .set_ios = mmci_set_ios, |
d2762090 | 1372 | .get_ro = mmc_gpio_get_ro, |
89001446 | 1373 | .get_cd = mmci_get_cd, |
0f3ed7f7 | 1374 | .start_signal_voltage_switch = mmci_sig_volt_switch, |
1da177e4 LT |
1375 | }; |
1376 | ||
4593df29 | 1377 | static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) |
000bc9d5 | 1378 | { |
4593df29 UH |
1379 | struct mmci_host *host = mmc_priv(mmc); |
1380 | int ret = mmc_of_parse(mmc); | |
1381 | ||
1382 | if (ret) | |
1383 | return ret; | |
1384 | ||
ae94cafe | 1385 | if (of_get_property(np, "st,sig-dir-dat0", NULL)) |
4593df29 | 1386 | host->pwr_reg_add |= MCI_ST_DATA0DIREN; |
ae94cafe | 1387 | if (of_get_property(np, "st,sig-dir-dat2", NULL)) |
4593df29 | 1388 | host->pwr_reg_add |= MCI_ST_DATA2DIREN; |
ae94cafe | 1389 | if (of_get_property(np, "st,sig-dir-dat31", NULL)) |
4593df29 | 1390 | host->pwr_reg_add |= MCI_ST_DATA31DIREN; |
ae94cafe | 1391 | if (of_get_property(np, "st,sig-dir-dat74", NULL)) |
4593df29 | 1392 | host->pwr_reg_add |= MCI_ST_DATA74DIREN; |
ae94cafe | 1393 | if (of_get_property(np, "st,sig-dir-cmd", NULL)) |
4593df29 | 1394 | host->pwr_reg_add |= MCI_ST_CMDDIREN; |
1a7e99c1 | 1395 | if (of_get_property(np, "st,sig-pin-fbclk", NULL)) |
4593df29 | 1396 | host->pwr_reg_add |= MCI_ST_FBCLKEN; |
000bc9d5 LJ |
1397 | |
1398 | if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) | |
78f87df2 | 1399 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED; |
000bc9d5 | 1400 | if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) |
78f87df2 | 1401 | mmc->caps |= MMC_CAP_SD_HIGHSPEED; |
000bc9d5 | 1402 | |
78f87df2 | 1403 | return 0; |
c0a120a4 | 1404 | } |
000bc9d5 | 1405 | |
c3be1efd | 1406 | static int mmci_probe(struct amba_device *dev, |
aa25afad | 1407 | const struct amba_id *id) |
1da177e4 | 1408 | { |
6ef297f8 | 1409 | struct mmci_platform_data *plat = dev->dev.platform_data; |
000bc9d5 | 1410 | struct device_node *np = dev->dev.of_node; |
4956e109 | 1411 | struct variant_data *variant = id->data; |
1da177e4 LT |
1412 | struct mmci_host *host; |
1413 | struct mmc_host *mmc; | |
1414 | int ret; | |
1415 | ||
000bc9d5 LJ |
1416 | /* Must have platform data or Device Tree. */ |
1417 | if (!plat && !np) { | |
1418 | dev_err(&dev->dev, "No plat data or DT found\n"); | |
1419 | return -EINVAL; | |
1da177e4 LT |
1420 | } |
1421 | ||
b9b52918 LJ |
1422 | if (!plat) { |
1423 | plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); | |
1424 | if (!plat) | |
1425 | return -ENOMEM; | |
1426 | } | |
1427 | ||
1da177e4 | 1428 | mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); |
ef289982 UH |
1429 | if (!mmc) |
1430 | return -ENOMEM; | |
1da177e4 | 1431 | |
78f87df2 UH |
1432 | ret = mmci_of_parse(np, mmc); |
1433 | if (ret) | |
1434 | goto host_free; | |
1435 | ||
1da177e4 | 1436 | host = mmc_priv(mmc); |
4ea580f1 | 1437 | host->mmc = mmc; |
012b7d33 RK |
1438 | |
1439 | host->hw_designer = amba_manf(dev); | |
1440 | host->hw_revision = amba_rev(dev); | |
64de0289 LW |
1441 | dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); |
1442 | dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); | |
012b7d33 | 1443 | |
665ba56f | 1444 | host->clk = devm_clk_get(&dev->dev, NULL); |
1da177e4 LT |
1445 | if (IS_ERR(host->clk)) { |
1446 | ret = PTR_ERR(host->clk); | |
1da177e4 LT |
1447 | goto host_free; |
1448 | } | |
1449 | ||
ac940938 | 1450 | ret = clk_prepare_enable(host->clk); |
1da177e4 | 1451 | if (ret) |
665ba56f | 1452 | goto host_free; |
1da177e4 LT |
1453 | |
1454 | host->plat = plat; | |
4956e109 | 1455 | host->variant = variant; |
1da177e4 | 1456 | host->mclk = clk_get_rate(host->clk); |
c8df9a53 LW |
1457 | /* |
1458 | * According to the spec, mclk is max 100 MHz, | |
1459 | * so we try to adjust the clock down to this, | |
1460 | * (if possible). | |
1461 | */ | |
1462 | if (host->mclk > 100000000) { | |
1463 | ret = clk_set_rate(host->clk, 100000000); | |
1464 | if (ret < 0) | |
1465 | goto clk_disable; | |
1466 | host->mclk = clk_get_rate(host->clk); | |
64de0289 LW |
1467 | dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", |
1468 | host->mclk); | |
c8df9a53 | 1469 | } |
ef289982 | 1470 | |
c8ebae37 | 1471 | host->phybase = dev->res.start; |
ef289982 UH |
1472 | host->base = devm_ioremap_resource(&dev->dev, &dev->res); |
1473 | if (IS_ERR(host->base)) { | |
1474 | ret = PTR_ERR(host->base); | |
1da177e4 LT |
1475 | goto clk_disable; |
1476 | } | |
1477 | ||
7f294e49 LW |
1478 | /* |
1479 | * The ARM and ST versions of the block have slightly different | |
1480 | * clock divider equations which means that the minimum divider | |
1481 | * differs too. | |
1482 | */ | |
1483 | if (variant->st_clkdiv) | |
1484 | mmc->f_min = DIV_ROUND_UP(host->mclk, 257); | |
1485 | else | |
1486 | mmc->f_min = DIV_ROUND_UP(host->mclk, 512); | |
808d97cc | 1487 | /* |
78f87df2 UH |
1488 | * If no maximum operating frequency is supplied, fall back to use |
1489 | * the module parameter, which has a (low) default value in case it | |
1490 | * is not specified. Either value must not exceed the clock rate into | |
5080a08d | 1491 | * the block, of course. |
808d97cc | 1492 | */ |
78f87df2 UH |
1493 | if (mmc->f_max) |
1494 | mmc->f_max = min(host->mclk, mmc->f_max); | |
808d97cc LW |
1495 | else |
1496 | mmc->f_max = min(host->mclk, fmax); | |
64de0289 LW |
1497 | dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); |
1498 | ||
599c1d5c UH |
1499 | /* Get regulators and the supported OCR mask */ |
1500 | mmc_regulator_get_supply(mmc); | |
1501 | if (!mmc->ocr_avail) | |
34e84f39 | 1502 | mmc->ocr_avail = plat->ocr_mask; |
599c1d5c UH |
1503 | else if (plat->ocr_mask) |
1504 | dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); | |
1505 | ||
78f87df2 | 1506 | /* DT takes precedence over platform data. */ |
78f87df2 UH |
1507 | if (!np) { |
1508 | if (!plat->cd_invert) | |
1509 | mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH; | |
1510 | mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; | |
1511 | } | |
1da177e4 | 1512 | |
9dd8a8b8 UH |
1513 | /* We support these capabilities. */ |
1514 | mmc->caps |= MMC_CAP_CMD23; | |
1515 | ||
8d94b54d UH |
1516 | if (variant->busy_detect) { |
1517 | mmci_ops.card_busy = mmci_card_busy; | |
1518 | mmci_write_datactrlreg(host, MCI_ST_DPSM_BUSYMODE); | |
1519 | mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; | |
1520 | mmc->max_busy_timeout = 0; | |
1521 | } | |
1522 | ||
1523 | mmc->ops = &mmci_ops; | |
1524 | ||
70be208f | 1525 | /* We support these PM capabilities. */ |
78f87df2 | 1526 | mmc->pm_caps |= MMC_PM_KEEP_POWER; |
70be208f | 1527 | |
1da177e4 LT |
1528 | /* |
1529 | * We can do SGIO | |
1530 | */ | |
a36274e0 | 1531 | mmc->max_segs = NR_SG; |
1da177e4 LT |
1532 | |
1533 | /* | |
08458ef6 RV |
1534 | * Since only a certain number of bits are valid in the data length |
1535 | * register, we must ensure that we don't exceed 2^num-1 bytes in a | |
1536 | * single request. | |
1da177e4 | 1537 | */ |
08458ef6 | 1538 | mmc->max_req_size = (1 << variant->datalength_bits) - 1; |
1da177e4 LT |
1539 | |
1540 | /* | |
1541 | * Set the maximum segment size. Since we aren't doing DMA | |
1542 | * (yet) we are only limited by the data length register. | |
1543 | */ | |
55db890a | 1544 | mmc->max_seg_size = mmc->max_req_size; |
1da177e4 | 1545 | |
fe4a3c7a PO |
1546 | /* |
1547 | * Block size can be up to 2048 bytes, but must be a power of two. | |
1548 | */ | |
8f7f6b7e | 1549 | mmc->max_blk_size = 1 << 11; |
fe4a3c7a | 1550 | |
55db890a | 1551 | /* |
8f7f6b7e WD |
1552 | * Limit the number of blocks transferred so that we don't overflow |
1553 | * the maximum request size. | |
55db890a | 1554 | */ |
8f7f6b7e | 1555 | mmc->max_blk_count = mmc->max_req_size >> 11; |
55db890a | 1556 | |
1da177e4 LT |
1557 | spin_lock_init(&host->lock); |
1558 | ||
1559 | writel(0, host->base + MMCIMASK0); | |
1560 | writel(0, host->base + MMCIMASK1); | |
1561 | writel(0xfff, host->base + MMCICLEAR); | |
1562 | ||
78f87df2 UH |
1563 | /* If DT, cd/wp gpios must be supplied through it. */ |
1564 | if (!np && gpio_is_valid(plat->gpio_cd)) { | |
d2762090 UH |
1565 | ret = mmc_gpio_request_cd(mmc, plat->gpio_cd, 0); |
1566 | if (ret) | |
ef289982 | 1567 | goto clk_disable; |
89001446 | 1568 | } |
78f87df2 | 1569 | if (!np && gpio_is_valid(plat->gpio_wp)) { |
d2762090 UH |
1570 | ret = mmc_gpio_request_ro(mmc, plat->gpio_wp); |
1571 | if (ret) | |
ef289982 | 1572 | goto clk_disable; |
89001446 RK |
1573 | } |
1574 | ||
ef289982 UH |
1575 | ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED, |
1576 | DRIVER_NAME " (cmd)", host); | |
1da177e4 | 1577 | if (ret) |
ef289982 | 1578 | goto clk_disable; |
1da177e4 | 1579 | |
dfb85185 | 1580 | if (!dev->irq[1]) |
2686b4b4 LW |
1581 | host->singleirq = true; |
1582 | else { | |
ef289982 UH |
1583 | ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, |
1584 | IRQF_SHARED, DRIVER_NAME " (pio)", host); | |
2686b4b4 | 1585 | if (ret) |
ef289982 | 1586 | goto clk_disable; |
2686b4b4 | 1587 | } |
1da177e4 | 1588 | |
8cb28155 | 1589 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); |
1da177e4 LT |
1590 | |
1591 | amba_set_drvdata(dev, mmc); | |
1592 | ||
c8ebae37 RK |
1593 | dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", |
1594 | mmc_hostname(mmc), amba_part(dev), amba_manf(dev), | |
1595 | amba_rev(dev), (unsigned long long)dev->res.start, | |
1596 | dev->irq[0], dev->irq[1]); | |
1597 | ||
1598 | mmci_dma_setup(host); | |
1da177e4 | 1599 | |
2cd976c4 UH |
1600 | pm_runtime_set_autosuspend_delay(&dev->dev, 50); |
1601 | pm_runtime_use_autosuspend(&dev->dev); | |
1c3be369 RK |
1602 | pm_runtime_put(&dev->dev); |
1603 | ||
8c11a94d RK |
1604 | mmc_add_host(mmc); |
1605 | ||
1da177e4 LT |
1606 | return 0; |
1607 | ||
1da177e4 | 1608 | clk_disable: |
ac940938 | 1609 | clk_disable_unprepare(host->clk); |
1da177e4 LT |
1610 | host_free: |
1611 | mmc_free_host(mmc); | |
1da177e4 LT |
1612 | return ret; |
1613 | } | |
1614 | ||
6e0ee714 | 1615 | static int mmci_remove(struct amba_device *dev) |
1da177e4 LT |
1616 | { |
1617 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
1618 | ||
1da177e4 LT |
1619 | if (mmc) { |
1620 | struct mmci_host *host = mmc_priv(mmc); | |
1621 | ||
1c3be369 RK |
1622 | /* |
1623 | * Undo pm_runtime_put() in probe. We use the _sync | |
1624 | * version here so that we can access the primecell. | |
1625 | */ | |
1626 | pm_runtime_get_sync(&dev->dev); | |
1627 | ||
1da177e4 LT |
1628 | mmc_remove_host(mmc); |
1629 | ||
1630 | writel(0, host->base + MMCIMASK0); | |
1631 | writel(0, host->base + MMCIMASK1); | |
1632 | ||
1633 | writel(0, host->base + MMCICOMMAND); | |
1634 | writel(0, host->base + MMCIDATACTRL); | |
1635 | ||
c8ebae37 | 1636 | mmci_dma_release(host); |
ac940938 | 1637 | clk_disable_unprepare(host->clk); |
1da177e4 | 1638 | mmc_free_host(mmc); |
1da177e4 LT |
1639 | } |
1640 | ||
1641 | return 0; | |
1642 | } | |
1643 | ||
571dce4f | 1644 | #ifdef CONFIG_PM |
1ff44433 UH |
1645 | static void mmci_save(struct mmci_host *host) |
1646 | { | |
1647 | unsigned long flags; | |
1648 | ||
42dcc89a | 1649 | spin_lock_irqsave(&host->lock, flags); |
1ff44433 | 1650 | |
42dcc89a UH |
1651 | writel(0, host->base + MMCIMASK0); |
1652 | if (host->variant->pwrreg_nopower) { | |
1ff44433 UH |
1653 | writel(0, host->base + MMCIDATACTRL); |
1654 | writel(0, host->base + MMCIPOWER); | |
1655 | writel(0, host->base + MMCICLOCK); | |
1ff44433 | 1656 | } |
42dcc89a | 1657 | mmci_reg_delay(host); |
1ff44433 | 1658 | |
42dcc89a | 1659 | spin_unlock_irqrestore(&host->lock, flags); |
1ff44433 UH |
1660 | } |
1661 | ||
1662 | static void mmci_restore(struct mmci_host *host) | |
1663 | { | |
1664 | unsigned long flags; | |
1665 | ||
42dcc89a | 1666 | spin_lock_irqsave(&host->lock, flags); |
1ff44433 | 1667 | |
42dcc89a | 1668 | if (host->variant->pwrreg_nopower) { |
1ff44433 UH |
1669 | writel(host->clk_reg, host->base + MMCICLOCK); |
1670 | writel(host->datactrl_reg, host->base + MMCIDATACTRL); | |
1671 | writel(host->pwr_reg, host->base + MMCIPOWER); | |
1ff44433 | 1672 | } |
42dcc89a UH |
1673 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); |
1674 | mmci_reg_delay(host); | |
1675 | ||
1676 | spin_unlock_irqrestore(&host->lock, flags); | |
1ff44433 UH |
1677 | } |
1678 | ||
8259293a UH |
1679 | static int mmci_runtime_suspend(struct device *dev) |
1680 | { | |
1681 | struct amba_device *adev = to_amba_device(dev); | |
1682 | struct mmc_host *mmc = amba_get_drvdata(adev); | |
1683 | ||
1684 | if (mmc) { | |
1685 | struct mmci_host *host = mmc_priv(mmc); | |
e36bd9c6 | 1686 | pinctrl_pm_select_sleep_state(dev); |
1ff44433 | 1687 | mmci_save(host); |
8259293a UH |
1688 | clk_disable_unprepare(host->clk); |
1689 | } | |
1690 | ||
1691 | return 0; | |
1692 | } | |
1693 | ||
1694 | static int mmci_runtime_resume(struct device *dev) | |
1695 | { | |
1696 | struct amba_device *adev = to_amba_device(dev); | |
1697 | struct mmc_host *mmc = amba_get_drvdata(adev); | |
1698 | ||
1699 | if (mmc) { | |
1700 | struct mmci_host *host = mmc_priv(mmc); | |
1701 | clk_prepare_enable(host->clk); | |
1ff44433 | 1702 | mmci_restore(host); |
e36bd9c6 | 1703 | pinctrl_pm_select_default_state(dev); |
8259293a UH |
1704 | } |
1705 | ||
1706 | return 0; | |
1707 | } | |
1708 | #endif | |
1709 | ||
48fa7003 | 1710 | static const struct dev_pm_ops mmci_dev_pm_ops = { |
f3737fa3 UH |
1711 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, |
1712 | pm_runtime_force_resume) | |
571dce4f | 1713 | SET_PM_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) |
48fa7003 UH |
1714 | }; |
1715 | ||
1da177e4 LT |
1716 | static struct amba_id mmci_ids[] = { |
1717 | { | |
1718 | .id = 0x00041180, | |
768fbc18 | 1719 | .mask = 0xff0fffff, |
4956e109 | 1720 | .data = &variant_arm, |
1da177e4 | 1721 | }, |
768fbc18 PM |
1722 | { |
1723 | .id = 0x01041180, | |
1724 | .mask = 0xff0fffff, | |
1725 | .data = &variant_arm_extended_fifo, | |
1726 | }, | |
3a37298a PM |
1727 | { |
1728 | .id = 0x02041180, | |
1729 | .mask = 0xff0fffff, | |
1730 | .data = &variant_arm_extended_fifo_hwfc, | |
1731 | }, | |
1da177e4 LT |
1732 | { |
1733 | .id = 0x00041181, | |
1734 | .mask = 0x000fffff, | |
4956e109 | 1735 | .data = &variant_arm, |
1da177e4 | 1736 | }, |
cc30d60e LW |
1737 | /* ST Micro variants */ |
1738 | { | |
1739 | .id = 0x00180180, | |
1740 | .mask = 0x00ffffff, | |
4956e109 | 1741 | .data = &variant_u300, |
cc30d60e | 1742 | }, |
34fd4213 LW |
1743 | { |
1744 | .id = 0x10180180, | |
1745 | .mask = 0xf0ffffff, | |
1746 | .data = &variant_nomadik, | |
1747 | }, | |
cc30d60e LW |
1748 | { |
1749 | .id = 0x00280180, | |
1750 | .mask = 0x00ffffff, | |
4956e109 RV |
1751 | .data = &variant_u300, |
1752 | }, | |
1753 | { | |
1754 | .id = 0x00480180, | |
1784b157 | 1755 | .mask = 0xf0ffffff, |
4956e109 | 1756 | .data = &variant_ux500, |
cc30d60e | 1757 | }, |
1784b157 PL |
1758 | { |
1759 | .id = 0x10480180, | |
1760 | .mask = 0xf0ffffff, | |
1761 | .data = &variant_ux500v2, | |
1762 | }, | |
1da177e4 LT |
1763 | { 0, 0 }, |
1764 | }; | |
1765 | ||
9f99835f DM |
1766 | MODULE_DEVICE_TABLE(amba, mmci_ids); |
1767 | ||
1da177e4 LT |
1768 | static struct amba_driver mmci_driver = { |
1769 | .drv = { | |
1770 | .name = DRIVER_NAME, | |
48fa7003 | 1771 | .pm = &mmci_dev_pm_ops, |
1da177e4 LT |
1772 | }, |
1773 | .probe = mmci_probe, | |
0433c143 | 1774 | .remove = mmci_remove, |
1da177e4 LT |
1775 | .id_table = mmci_ids, |
1776 | }; | |
1777 | ||
9e5ed094 | 1778 | module_amba_driver(mmci_driver); |
1da177e4 | 1779 | |
1da177e4 LT |
1780 | module_param(fmax, uint, 0444); |
1781 | ||
1782 | MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); | |
1783 | MODULE_LICENSE("GPL"); |