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mmc: msm_sdcc: Enable SDC host->clk only after setting the rate.
[deliverable/linux.git] / drivers / mmc / host / msm_sdcc.c
CommitLineData
9d2bd738
SM		 1/*
2 * linux/drivers/mmc/host/msm_sdcc.c - Qualcomm MSM 7X00A SDCC Driver
3 *
4 * Copyright (C) 2007 Google Inc,
5 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
56a8b5b8 6 * Copyright (C) 2009, Code Aurora Forum. All Rights Reserved.
9d2bd738
SM		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Based on mmci.c
13 *
14 * Author: San Mehat (san@android.com)
15 *
16 */
17
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/init.h>
21#include <linux/ioport.h>
22#include <linux/device.h>
23#include <linux/interrupt.h>
24#include <linux/delay.h>
25#include <linux/err.h>
26#include <linux/highmem.h>
27#include <linux/log2.h>
28#include <linux/mmc/host.h>
29#include <linux/mmc/card.h>
b3fa5791 30#include <linux/mmc/sdio.h>
9d2bd738
SM		 31#include <linux/clk.h>
32#include <linux/scatterlist.h>
33#include <linux/platform_device.h>
34#include <linux/dma-mapping.h>
35#include <linux/debugfs.h>
36#include <linux/io.h>
37#include <linux/memory.h>
5a0e3ad6 38#include <linux/gfp.h>
7a89248a 39#include <linux/gpio.h>
9d2bd738
SM		 40
41#include <asm/cacheflush.h>
42#include <asm/div64.h>
43#include <asm/sizes.h>
44
3989d178 45#include <mach/mmc.h>
9d2bd738
SM		 46#include <mach/msm_iomap.h>
47#include <mach/dma.h>
b08bb35d 48#include <mach/clk.h>
9d2bd738 49
9d2bd738
SM		 50#include "msm_sdcc.h"
51
52#define DRIVER_NAME "msm-sdcc"
53
24bbd7d5 54#define BUSCLK_PWRSAVE 1
c7fc9370 55#define BUSCLK_TIMEOUT (HZ)
9d2bd738
SM		 56static unsigned int msmsdcc_fmin = 144000;
57static unsigned int msmsdcc_fmax = 50000000;
58static unsigned int msmsdcc_4bit = 1;
59static unsigned int msmsdcc_pwrsave = 1;
60static unsigned int msmsdcc_piopoll = 1;
61static unsigned int msmsdcc_sdioirq;
62
63#define PIO_SPINMAX 30
64#define CMD_SPINMAX 20
65
865c8064 66
d0719e59 67static inline void
c7fc9370 68msmsdcc_disable_clocks(struct msmsdcc_host *host, int deferr)
865c8064 69{
c7fc9370 70 WARN_ON(!host->clks_on);
8b1c2ba2 71
f4748499
SM		 72 BUG_ON(host->curr.mrq);
73
c7fc9370
SM		 74 if (deferr) {
75 mod_timer(&host->busclk_timer, jiffies + BUSCLK_TIMEOUT);
865c8064 76 } else {
c7fc9370 77 del_timer_sync(&host->busclk_timer);
d0719e59
SM		 78 /* Need to check clks_on again in case the busclk
79 * timer fired
80 */
81 if (host->clks_on) {
82 clk_disable(host->clk);
83 clk_disable(host->pclk);
84 host->clks_on = 0;
85 }
865c8064 86 }
c7fc9370
SM		 87}
88
89static inline int
90msmsdcc_enable_clocks(struct msmsdcc_host *host)
91{
92 int rc;
93
c7fc9370
SM		 94 del_timer_sync(&host->busclk_timer);
95
d0719e59
SM		 96 if (!host->clks_on) {
97 rc = clk_enable(host->pclk);
98 if (rc)
99 return rc;
100 rc = clk_enable(host->clk);
101 if (rc) {
102 clk_disable(host->pclk);
103 return rc;
104 }
105 udelay(1 + ((3 * USEC_PER_SEC) /
106 (host->clk_rate ? host->clk_rate : msmsdcc_fmin)));
107 host->clks_on = 1;
c7fc9370 108 }
865c8064
SM		 109 return 0;
110}
111
8b1c2ba2
SM		 112static inline unsigned int
113msmsdcc_readl(struct msmsdcc_host *host, unsigned int reg)
114{
115 return readl(host->base + reg);
116}
117
118static inline void
119msmsdcc_writel(struct msmsdcc_host *host, u32 data, unsigned int reg)
120{
121 writel(data, host->base + reg);
122 /* 3 clk delay required! */
123 udelay(1 + ((3 * USEC_PER_SEC) /
124 (host->clk_rate ? host->clk_rate : msmsdcc_fmin)));
125}
865c8064 126
9d2bd738
SM		 127static void
128msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd,
129 u32 c);
130
b08bb35d
ST		 131static void msmsdcc_reset_and_restore(struct msmsdcc_host *host)
132{
133 u32 mci_clk = 0;
134 u32 mci_mask0 = 0;
135 int ret = 0;
136
137 /* Save the controller state */
138 mci_clk = readl(host->base + MMCICLOCK);
139 mci_mask0 = readl(host->base + MMCIMASK0);
140
141 /* Reset the controller */
142 ret = clk_reset(host->clk, CLK_RESET_ASSERT);
143 if (ret)
144 pr_err("%s: Clock assert failed at %u Hz with err %d\n",
145 mmc_hostname(host->mmc), host->clk_rate, ret);
146
147 ret = clk_reset(host->clk, CLK_RESET_DEASSERT);
148 if (ret)
149 pr_err("%s: Clock deassert failed at %u Hz with err %d\n",
150 mmc_hostname(host->mmc), host->clk_rate, ret);
151
152 pr_info("%s: Controller has been re-initialiazed\n",
153 mmc_hostname(host->mmc));
154
155 /* Restore the contoller state */
156 writel(host->pwr, host->base + MMCIPOWER);
157 writel(mci_clk, host->base + MMCICLOCK);
158 writel(mci_mask0, host->base + MMCIMASK0);
159 ret = clk_set_rate(host->clk, host->clk_rate);
160 if (ret)
161 pr_err("%s: Failed to set clk rate %u Hz (%d)\n",
162 mmc_hostname(host->mmc), host->clk_rate, ret);
163}
164
9d2bd738
SM		 165static void
166msmsdcc_request_end(struct msmsdcc_host *host, struct mmc_request *mrq)
167{
9d2bd738
SM		 168 BUG_ON(host->curr.data);
169
170 host->curr.mrq = NULL;
171 host->curr.cmd = NULL;
172
173 if (mrq->data)
174 mrq->data->bytes_xfered = host->curr.data_xfered;
175 if (mrq->cmd->error == -ETIMEDOUT)
176 mdelay(5);
177
f4748499 178#if BUSCLK_PWRSAVE
c7fc9370 179 msmsdcc_disable_clocks(host, 1);
f4748499 180#endif
9d2bd738
SM		 181 /*
182 * Need to drop the host lock here; mmc_request_done may call
183 * back into the driver...
184 */
185 spin_unlock(&host->lock);
186 mmc_request_done(host->mmc, mrq);
187 spin_lock(&host->lock);
188}
189
190static void
191msmsdcc_stop_data(struct msmsdcc_host *host)
192{
9d2bd738 193 host->curr.data = NULL;
0c521ccb 194 host->curr.got_dataend = 0;
9d2bd738
SM		 195}
196
197uint32_t msmsdcc_fifo_addr(struct msmsdcc_host *host)
198{
edd4dd0e 199 return host->memres->start + MMCIFIFO;
9d2bd738
SM		 200}
201
56a8b5b8
SM		 202static inline void
203msmsdcc_start_command_exec(struct msmsdcc_host *host, u32 arg, u32 c) {
204 msmsdcc_writel(host, arg, MMCIARGUMENT);
205 msmsdcc_writel(host, c, MMCICOMMAND);
206}
207
208static void
209msmsdcc_dma_exec_func(struct msm_dmov_cmd *cmd)
210{
6ac9ea69 211 struct msmsdcc_host *host = (struct msmsdcc_host *)cmd->data;
56a8b5b8 212
6ac9ea69 213 msmsdcc_writel(host, host->cmd_timeout, MMCIDATATIMER);
d0719e59
SM		 214 msmsdcc_writel(host, (unsigned int)host->curr.xfer_size,
215 MMCIDATALENGTH);
6ac9ea69
SM		 216 msmsdcc_writel(host, host->cmd_pio_irqmask, MMCIMASK1);
217 msmsdcc_writel(host, host->cmd_datactrl, MMCIDATACTRL);
56a8b5b8 218
6ac9ea69
SM		 219 if (host->cmd_cmd) {
220 msmsdcc_start_command_exec(host,
221 (u32) host->cmd_cmd->arg,
222 (u32) host->cmd_c);
223 }
56a8b5b8
SM		 224 host->dma.active = 1;
225}
226
9d2bd738 227static void
62612cf9 228msmsdcc_dma_complete_tlet(unsigned long data)
9d2bd738 229{
62612cf9 230 struct msmsdcc_host *host = (struct msmsdcc_host *)data;
9d2bd738
SM		 231 unsigned long flags;
232 struct mmc_request *mrq;
62612cf9 233 struct msm_dmov_errdata err;
9d2bd738
SM		 234
235 spin_lock_irqsave(&host->lock, flags);
56a8b5b8
SM		 236 host->dma.active = 0;
237
62612cf9 238 err = host->dma.err;
9d2bd738
SM		 239 mrq = host->curr.mrq;
240 BUG_ON(!mrq);
b3b0ca84 241 WARN_ON(!mrq->data);
9d2bd738 242
62612cf9 243 if (!(host->dma.result & DMOV_RSLT_VALID)) {
0a7ff7c7 244 pr_err("msmsdcc: Invalid DataMover result\n");
9d2bd738
SM		 245 goto out;
246 }
247
62612cf9 248 if (host->dma.result & DMOV_RSLT_DONE) {
9d2bd738
SM		 249 host->curr.data_xfered = host->curr.xfer_size;
250 } else {
251 /* Error or flush */
62612cf9 252 if (host->dma.result & DMOV_RSLT_ERROR)
0a7ff7c7 253 pr_err("%s: DMA error (0x%.8x)\n",
62612cf9
ST		 254 mmc_hostname(host->mmc), host->dma.result);
255 if (host->dma.result & DMOV_RSLT_FLUSH)
0a7ff7c7 256 pr_err("%s: DMA channel flushed (0x%.8x)\n",
62612cf9
ST		 257 mmc_hostname(host->mmc), host->dma.result);
258
259 pr_err("Flush data: %.8x %.8x %.8x %.8x %.8x %.8x\n",
260 err.flush[0], err.flush[1], err.flush[2],
261 err.flush[3], err.flush[4], err.flush[5]);
b08bb35d
ST		 262
263 msmsdcc_reset_and_restore(host);
9d2bd738
SM		 264 if (!mrq->data->error)
265 mrq->data->error = -EIO;
266 }
9d2bd738
SM		 267 dma_unmap_sg(mmc_dev(host->mmc), host->dma.sg, host->dma.num_ents,
268 host->dma.dir);
269
9d2bd738 270 host->dma.sg = NULL;
56a8b5b8 271 host->dma.busy = 0;
9d2bd738 272
0c521ccb 273 if (host->curr.got_dataend || mrq->data->error) {
9d2bd738
SM		 274
275 /*
276 * If we've already gotten our DATAEND / DATABLKEND
277 * for this request, then complete it through here.
278 */
279 msmsdcc_stop_data(host);
280
281 if (!mrq->data->error)
282 host->curr.data_xfered = host->curr.xfer_size;
283 if (!mrq->data->stop || mrq->cmd->error) {
9d2bd738
SM		 284 host->curr.mrq = NULL;
285 host->curr.cmd = NULL;
286 mrq->data->bytes_xfered = host->curr.data_xfered;
287
288 spin_unlock_irqrestore(&host->lock, flags);
f4748499 289#if BUSCLK_PWRSAVE
c7fc9370 290 msmsdcc_disable_clocks(host, 1);
f4748499 291#endif
9d2bd738
SM		 292 mmc_request_done(host->mmc, mrq);
293 return;
294 } else
295 msmsdcc_start_command(host, mrq->data->stop, 0);
296 }
297
298out:
299 spin_unlock_irqrestore(&host->lock, flags);
300 return;
301}
302
62612cf9
ST		 303static void
304msmsdcc_dma_complete_func(struct msm_dmov_cmd *cmd,
305 unsigned int result,
306 struct msm_dmov_errdata *err)
307{
308 struct msmsdcc_dma_data *dma_data =
309 container_of(cmd, struct msmsdcc_dma_data, hdr);
310 struct msmsdcc_host *host = dma_data->host;
311
312 dma_data->result = result;
313 if (err)
314 memcpy(&dma_data->err, err, sizeof(struct msm_dmov_errdata));
315
316 tasklet_schedule(&host->dma_tlet);
317}
318
9d2bd738
SM		 319static int validate_dma(struct msmsdcc_host *host, struct mmc_data *data)
320{
321 if (host->dma.channel == -1)
322 return -ENOENT;
323
324 if ((data->blksz * data->blocks) < MCI_FIFOSIZE)
325 return -EINVAL;
326 if ((data->blksz * data->blocks) % MCI_FIFOSIZE)
327 return -EINVAL;
328 return 0;
329}
330
331static int msmsdcc_config_dma(struct msmsdcc_host *host, struct mmc_data *data)
332{
333 struct msmsdcc_nc_dmadata *nc;
334 dmov_box *box;
335 uint32_t rows;
336 uint32_t crci;
337 unsigned int n;
338 int i, rc;
339 struct scatterlist *sg = data->sg;
340
341 rc = validate_dma(host, data);
342 if (rc)
343 return rc;
344
345 host->dma.sg = data->sg;
346 host->dma.num_ents = data->sg_len;
347
56a8b5b8
SM		 348 BUG_ON(host->dma.num_ents > NR_SG); /* Prevent memory corruption */
349
9d2bd738
SM		 350 nc = host->dma.nc;
351
75d14528
JP		 352 switch (host->pdev_id) {
353 case 1:
9d2bd738 354 crci = MSMSDCC_CRCI_SDC1;
75d14528
JP		 355 break;
356 case 2:
9d2bd738 357 crci = MSMSDCC_CRCI_SDC2;
75d14528
JP		 358 break;
359 case 3:
9d2bd738 360 crci = MSMSDCC_CRCI_SDC3;
75d14528
JP		 361 break;
362 case 4:
9d2bd738 363 crci = MSMSDCC_CRCI_SDC4;
75d14528
JP		 364 break;
365 default:
9d2bd738
SM		 366 host->dma.sg = NULL;
367 host->dma.num_ents = 0;
368 return -ENOENT;
369 }
370
371 if (data->flags & MMC_DATA_READ)
372 host->dma.dir = DMA_FROM_DEVICE;
373 else
374 host->dma.dir = DMA_TO_DEVICE;
375
376 host->curr.user_pages = 0;
377
9d2bd738 378 box = &nc->cmd[0];
9d2bd738 379
208028de
DW		 380 /* location of command block must be 64 bit aligned */
381 BUG_ON(host->dma.cmd_busaddr & 0x07);
382
383 nc->cmdptr = (host->dma.cmd_busaddr >> 3) | CMD_PTR_LP;
384 host->dma.hdr.cmdptr = DMOV_CMD_PTR_LIST |
385 DMOV_CMD_ADDR(host->dma.cmdptr_busaddr);
386 host->dma.hdr.complete_func = msmsdcc_dma_complete_func;
387
388 n = dma_map_sg(mmc_dev(host->mmc), host->dma.sg,
389 host->dma.num_ents, host->dma.dir);
390 if (n == 0) {
391 printk(KERN_ERR "%s: Unable to map in all sg elements\n",
392 mmc_hostname(host->mmc));
393 host->dma.sg = NULL;
394 host->dma.num_ents = 0;
395 return -ENOMEM;
396 }
397
398 for_each_sg(host->dma.sg, sg, n, i) {
399
400 box->cmd = CMD_MODE_BOX;
56a8b5b8 401
208028de 402 if (i == n - 1)
9d2bd738
SM		 403 box->cmd |= CMD_LC;
404 rows = (sg_dma_len(sg) % MCI_FIFOSIZE) ?
405 (sg_dma_len(sg) / MCI_FIFOSIZE) + 1 :
406 (sg_dma_len(sg) / MCI_FIFOSIZE) ;
407
408 if (data->flags & MMC_DATA_READ) {
409 box->src_row_addr = msmsdcc_fifo_addr(host);
410 box->dst_row_addr = sg_dma_address(sg);
411
412 box->src_dst_len = (MCI_FIFOSIZE << 16) |
413 (MCI_FIFOSIZE);
414 box->row_offset = MCI_FIFOSIZE;
415
416 box->num_rows = rows * ((1 << 16) + 1);
417 box->cmd |= CMD_SRC_CRCI(crci);
418 } else {
419 box->src_row_addr = sg_dma_address(sg);
420 box->dst_row_addr = msmsdcc_fifo_addr(host);
421
422 box->src_dst_len = (MCI_FIFOSIZE << 16) |
423 (MCI_FIFOSIZE);
424 box->row_offset = (MCI_FIFOSIZE << 16);
425
426 box->num_rows = rows * ((1 << 16) + 1);
427 box->cmd |= CMD_DST_CRCI(crci);
428 }
429 box++;
56a8b5b8
SM		 430 }
431
432 return 0;
433}
434
435static int
436snoop_cccr_abort(struct mmc_command *cmd)
437{
438 if ((cmd->opcode == 52) &&
439 (cmd->arg & 0x80000000) &&
440 (((cmd->arg >> 9) & 0x1ffff) == SDIO_CCCR_ABORT))
441 return 1;
9d2bd738
SM		 442 return 0;
443}
444
445static void
56a8b5b8
SM		 446msmsdcc_start_command_deferred(struct msmsdcc_host *host,
447 struct mmc_command *cmd, u32 *c)
448{
449 *c |= (cmd->opcode | MCI_CPSM_ENABLE);
450
451 if (cmd->flags & MMC_RSP_PRESENT) {
452 if (cmd->flags & MMC_RSP_136)
453 *c |= MCI_CPSM_LONGRSP;
454 *c |= MCI_CPSM_RESPONSE;
455 }
456
457 if (/*interrupt*/0)
458 *c |= MCI_CPSM_INTERRUPT;
459
460 if ((((cmd->opcode == 17) || (cmd->opcode == 18)) ||
461 ((cmd->opcode == 24) || (cmd->opcode == 25))) ||
462 (cmd->opcode == 53))
463 *c |= MCI_CSPM_DATCMD;
464
d5137bdd
ST		 465 if (host->prog_scan && (cmd->opcode == 12)) {
466 *c |= MCI_CPSM_PROGENA;
467 host->prog_enable = true;
468 }
469
56a8b5b8
SM		 470 if (cmd == cmd->mrq->stop)
471 *c |= MCI_CSPM_MCIABORT;
472
473 if (snoop_cccr_abort(cmd))
474 *c |= MCI_CSPM_MCIABORT;
475
476 if (host->curr.cmd != NULL) {
477 printk(KERN_ERR "%s: Overlapping command requests\n",
478 mmc_hostname(host->mmc));
479 }
480 host->curr.cmd = cmd;
481}
482
483static void
484msmsdcc_start_data(struct msmsdcc_host *host, struct mmc_data *data,
485 struct mmc_command *cmd, u32 c)
9d2bd738
SM		 486{
487 unsigned int datactrl, timeout;
488 unsigned long long clks;
9d2bd738
SM		 489 unsigned int pio_irqmask = 0;
490
491 host->curr.data = data;
492 host->curr.xfer_size = data->blksz * data->blocks;
493 host->curr.xfer_remain = host->curr.xfer_size;
494 host->curr.data_xfered = 0;
495 host->curr.got_dataend = 0;
9d2bd738
SM		 496
497 memset(&host->pio, 0, sizeof(host->pio));
498
9d2bd738
SM		 499 datactrl = MCI_DPSM_ENABLE | (data->blksz << 4);
500
501 if (!msmsdcc_config_dma(host, data))
502 datactrl |= MCI_DPSM_DMAENABLE;
503 else {
504 host->pio.sg = data->sg;
505 host->pio.sg_len = data->sg_len;
506 host->pio.sg_off = 0;
507
508 if (data->flags & MMC_DATA_READ) {
509 pio_irqmask = MCI_RXFIFOHALFFULLMASK;
510 if (host->curr.xfer_remain < MCI_FIFOSIZE)
511 pio_irqmask |= MCI_RXDATAAVLBLMASK;
512 } else
513 pio_irqmask = MCI_TXFIFOHALFEMPTYMASK;
514 }
515
516 if (data->flags & MMC_DATA_READ)
517 datactrl |= MCI_DPSM_DIRECTION;
518
56a8b5b8
SM		 519 clks = (unsigned long long)data->timeout_ns * host->clk_rate;
520 do_div(clks, NSEC_PER_SEC);
521 timeout = data->timeout_clks + (unsigned int)clks*2 ;
9d2bd738
SM		 522
523 if (datactrl & MCI_DPSM_DMAENABLE) {
56a8b5b8
SM		 524 /* Save parameters for the exec function */
525 host->cmd_timeout = timeout;
526 host->cmd_pio_irqmask = pio_irqmask;
527 host->cmd_datactrl = datactrl;
528 host->cmd_cmd = cmd;
529
530 host->dma.hdr.execute_func = msmsdcc_dma_exec_func;
531 host->dma.hdr.data = (void *)host;
9d2bd738 532 host->dma.busy = 1;
56a8b5b8
SM		 533
534 if (cmd) {
535 msmsdcc_start_command_deferred(host, cmd, &c);
536 host->cmd_c = c;
537 }
9d2bd738 538 msm_dmov_enqueue_cmd(host->dma.channel, &host->dma.hdr);
d5137bdd
ST		 539 if (data->flags & MMC_DATA_WRITE)
540 host->prog_scan = true;
56a8b5b8
SM		 541 } else {
542 msmsdcc_writel(host, timeout, MMCIDATATIMER);
9d2bd738 543
56a8b5b8
SM		 544 msmsdcc_writel(host, host->curr.xfer_size, MMCIDATALENGTH);
545
546 msmsdcc_writel(host, pio_irqmask, MMCIMASK1);
547 msmsdcc_writel(host, datactrl, MMCIDATACTRL);
548
549 if (cmd) {
550 /* Daisy-chain the command if requested */
551 msmsdcc_start_command(host, cmd, c);
552 }
9d2bd738
SM		 553 }
554}
555
556static void
557msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd, u32 c)
558{
9d2bd738
SM		 559 if (cmd == cmd->mrq->stop)
560 c |= MCI_CSPM_MCIABORT;
561
9d2bd738
SM		 562 host->stats.cmds++;
563
56a8b5b8
SM		 564 msmsdcc_start_command_deferred(host, cmd, &c);
565 msmsdcc_start_command_exec(host, cmd->arg, c);
9d2bd738
SM		 566}
567
568static void
569msmsdcc_data_err(struct msmsdcc_host *host, struct mmc_data *data,
570 unsigned int status)
571{
572 if (status & MCI_DATACRCFAIL) {
0a7ff7c7
JP		 573 pr_err("%s: Data CRC error\n", mmc_hostname(host->mmc));
574 pr_err("%s: opcode 0x%.8x\n", __func__,
9d2bd738 575 data->mrq->cmd->opcode);
0a7ff7c7 576 pr_err("%s: blksz %d, blocks %d\n", __func__,
9d2bd738
SM		 577 data->blksz, data->blocks);
578 data->error = -EILSEQ;
579 } else if (status & MCI_DATATIMEOUT) {
0a7ff7c7 580 pr_err("%s: Data timeout\n", mmc_hostname(host->mmc));
9d2bd738
SM		 581 data->error = -ETIMEDOUT;
582 } else if (status & MCI_RXOVERRUN) {
0a7ff7c7 583 pr_err("%s: RX overrun\n", mmc_hostname(host->mmc));
9d2bd738
SM		 584 data->error = -EIO;
585 } else if (status & MCI_TXUNDERRUN) {
0a7ff7c7 586 pr_err("%s: TX underrun\n", mmc_hostname(host->mmc));
9d2bd738
SM		 587 data->error = -EIO;
588 } else {
0a7ff7c7
JP		 589 pr_err("%s: Unknown error (0x%.8x)\n",
590 mmc_hostname(host->mmc), status);
9d2bd738
SM		 591 data->error = -EIO;
592 }
593}
594
595
596static int
597msmsdcc_pio_read(struct msmsdcc_host *host, char *buffer, unsigned int remain)
598{
9d2bd738
SM		 599 uint32_t *ptr = (uint32_t *) buffer;
600 int count = 0;
601
71dd9106
ST		 602 if (remain % 4)
603 remain = ((remain >> 2) + 1) << 2;
604
8b1c2ba2
SM		 605 while (msmsdcc_readl(host, MMCISTATUS) & MCI_RXDATAAVLBL) {
606 *ptr = msmsdcc_readl(host, MMCIFIFO + (count % MCI_FIFOSIZE));
9d2bd738
SM		 607 ptr++;
608 count += sizeof(uint32_t);
609
610 remain -= sizeof(uint32_t);
611 if (remain == 0)
612 break;
613 }
614 return count;
615}
616
617static int
618msmsdcc_pio_write(struct msmsdcc_host *host, char *buffer,
619 unsigned int remain, u32 status)
620{
621 void __iomem *base = host->base;
622 char *ptr = buffer;
623
624 do {
71dd9106 625 unsigned int count, maxcnt, sz;
9d2bd738
SM		 626
627 maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE :
628 MCI_FIFOHALFSIZE;
629 count = min(remain, maxcnt);
630
71dd9106
ST		 631 sz = count % 4 ? (count >> 2) + 1 : (count >> 2);
632 writesl(base + MMCIFIFO, ptr, sz);
9d2bd738
SM		 633 ptr += count;
634 remain -= count;
635
636 if (remain == 0)
637 break;
638
8b1c2ba2 639 status = msmsdcc_readl(host, MMCISTATUS);
9d2bd738
SM		 640 } while (status & MCI_TXFIFOHALFEMPTY);
641
642 return ptr - buffer;
643}
644
645static int
646msmsdcc_spin_on_status(struct msmsdcc_host *host, uint32_t mask, int maxspin)
647{
648 while (maxspin) {
8b1c2ba2 649 if ((msmsdcc_readl(host, MMCISTATUS) & mask))
9d2bd738
SM		 650 return 0;
651 udelay(1);
652 --maxspin;
653 }
654 return -ETIMEDOUT;
655}
656
1cd22969 657static irqreturn_t
9d2bd738
SM		 658msmsdcc_pio_irq(int irq, void *dev_id)
659{
660 struct msmsdcc_host *host = dev_id;
9d2bd738
SM		 661 uint32_t status;
662
8b1c2ba2 663 status = msmsdcc_readl(host, MMCISTATUS);
9d2bd738
SM		 664
665 do {
666 unsigned long flags;
667 unsigned int remain, len;
668 char *buffer;
669
670 if (!(status & (MCI_TXFIFOHALFEMPTY | MCI_RXDATAAVLBL))) {
671 if (host->curr.xfer_remain == 0 || !msmsdcc_piopoll)
672 break;
673
674 if (msmsdcc_spin_on_status(host,
675 (MCI_TXFIFOHALFEMPTY |
676 MCI_RXDATAAVLBL),
677 PIO_SPINMAX)) {
678 break;
679 }
680 }
681
682 /* Map the current scatter buffer */
683 local_irq_save(flags);
684 buffer = kmap_atomic(sg_page(host->pio.sg),
685 KM_BIO_SRC_IRQ) + host->pio.sg->offset;
686 buffer += host->pio.sg_off;
687 remain = host->pio.sg->length - host->pio.sg_off;
688 len = 0;
689 if (status & MCI_RXACTIVE)
690 len = msmsdcc_pio_read(host, buffer, remain);
691 if (status & MCI_TXACTIVE)
692 len = msmsdcc_pio_write(host, buffer, remain, status);
693
694 /* Unmap the buffer */
695 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
696 local_irq_restore(flags);
697
698 host->pio.sg_off += len;
699 host->curr.xfer_remain -= len;
700 host->curr.data_xfered += len;
701 remain -= len;
702
703 if (remain == 0) {
704 /* This sg page is full - do some housekeeping */
705 if (status & MCI_RXACTIVE && host->curr.user_pages)
706 flush_dcache_page(sg_page(host->pio.sg));
707
708 if (!--host->pio.sg_len) {
709 memset(&host->pio, 0, sizeof(host->pio));
710 break;
711 }
712
713 /* Advance to next sg */
714 host->pio.sg++;
715 host->pio.sg_off = 0;
716 }
717
8b1c2ba2 718 status = msmsdcc_readl(host, MMCISTATUS);
9d2bd738
SM		 719 } while (1);
720
721 if (status & MCI_RXACTIVE && host->curr.xfer_remain < MCI_FIFOSIZE)
8b1c2ba2 722 msmsdcc_writel(host, MCI_RXDATAAVLBLMASK, MMCIMASK1);
9d2bd738
SM		 723
724 if (!host->curr.xfer_remain)
8b1c2ba2 725 msmsdcc_writel(host, 0, MMCIMASK1);
9d2bd738
SM		 726
727 return IRQ_HANDLED;
728}
729
730static void msmsdcc_do_cmdirq(struct msmsdcc_host *host, uint32_t status)
731{
732 struct mmc_command *cmd = host->curr.cmd;
9d2bd738
SM		 733
734 host->curr.cmd = NULL;
8b1c2ba2
SM		 735 cmd->resp[0] = msmsdcc_readl(host, MMCIRESPONSE0);
736 cmd->resp[1] = msmsdcc_readl(host, MMCIRESPONSE1);
737 cmd->resp[2] = msmsdcc_readl(host, MMCIRESPONSE2);
738 cmd->resp[3] = msmsdcc_readl(host, MMCIRESPONSE3);
9d2bd738 739
9d2bd738
SM		 740 if (status & MCI_CMDTIMEOUT) {
741 cmd->error = -ETIMEDOUT;
742 } else if (status & MCI_CMDCRCFAIL &&
743 cmd->flags & MMC_RSP_CRC) {
0a7ff7c7 744 pr_err("%s: Command CRC error\n", mmc_hostname(host->mmc));
9d2bd738
SM		 745 cmd->error = -EILSEQ;
746 }
747
748 if (!cmd->data || cmd->error) {
749 if (host->curr.data && host->dma.sg)
750 msm_dmov_stop_cmd(host->dma.channel,
751 &host->dma.hdr, 0);
752 else if (host->curr.data) { /* Non DMA */
b08bb35d 753 msmsdcc_reset_and_restore(host);
9d2bd738
SM		 754 msmsdcc_stop_data(host);
755 msmsdcc_request_end(host, cmd->mrq);
d5137bdd
ST		 756 } else { /* host->data == NULL */
757 if (!cmd->error && host->prog_enable) {
758 if (status & MCI_PROGDONE) {
759 host->prog_scan = false;
760 host->prog_enable = false;
761 msmsdcc_request_end(host, cmd->mrq);
762 } else {
763 host->curr.cmd = cmd;
764 }
765 } else {
766 if (host->prog_enable) {
767 host->prog_scan = false;
768 host->prog_enable = false;
769 }
770 msmsdcc_request_end(host, cmd->mrq);
771 }
772 }
56a8b5b8
SM		 773 } else if (cmd->data)
774 if (!(cmd->data->flags & MMC_DATA_READ))
775 msmsdcc_start_data(host, cmd->data,
776 NULL, 0);
9d2bd738
SM		 777}
778
b5a74d60
JP		 779static void
780msmsdcc_handle_irq_data(struct msmsdcc_host *host, u32 status,
781 void __iomem *base)
782{
783 struct mmc_data *data = host->curr.data;
784
56a8b5b8 785 if (status & (MCI_CMDSENT | MCI_CMDRESPEND | MCI_CMDCRCFAIL |
d5137bdd 786 MCI_CMDTIMEOUT | MCI_PROGDONE) && host->curr.cmd) {
56a8b5b8
SM		 787 msmsdcc_do_cmdirq(host, status);
788 }
789
b5a74d60
JP		 790 if (!data)
791 return;
792
793 /* Check for data errors */
794 if (status & (MCI_DATACRCFAIL | MCI_DATATIMEOUT |
795 MCI_TXUNDERRUN | MCI_RXOVERRUN)) {
796 msmsdcc_data_err(host, data, status);
797 host->curr.data_xfered = 0;
798 if (host->dma.sg)
799 msm_dmov_stop_cmd(host->dma.channel,
800 &host->dma.hdr, 0);
801 else {
b08bb35d 802 msmsdcc_reset_and_restore(host);
b3b0ca84
SM		 803 if (host->curr.data)
804 msmsdcc_stop_data(host);
b5a74d60
JP		 805 if (!data->stop)
806 msmsdcc_request_end(host, data->mrq);
807 else
808 msmsdcc_start_command(host, data->stop, 0);
809 }
810 }
811
812 /* Check for data done */
813 if (!host->curr.got_dataend && (status & MCI_DATAEND))
814 host->curr.got_dataend = 1;
815
b5a74d60
JP		 816 /*
817 * If DMA is still in progress, we complete via the completion handler
818 */
0c521ccb 819 if (host->curr.got_dataend && !host->dma.busy) {
b5a74d60
JP		 820 /*
821 * There appears to be an issue in the controller where
822 * if you request a small block transfer (< fifo size),
823 * you may get your DATAEND/DATABLKEND irq without the
824 * PIO data irq.
825 *
826 * Check to see if there is still data to be read,
827 * and simulate a PIO irq.
828 */
829 if (readl(base + MMCISTATUS) & MCI_RXDATAAVLBL)
830 msmsdcc_pio_irq(1, host);
831
832 msmsdcc_stop_data(host);
833 if (!data->error)
834 host->curr.data_xfered = host->curr.xfer_size;
835
836 if (!data->stop)
837 msmsdcc_request_end(host, data->mrq);
838 else
839 msmsdcc_start_command(host, data->stop, 0);
840 }
841}
842
9d2bd738
SM		 843static irqreturn_t
844msmsdcc_irq(int irq, void *dev_id)
845{
846 struct msmsdcc_host *host = dev_id;
847 void __iomem *base = host->base;
848 u32 status;
849 int ret = 0;
850 int cardint = 0;
851
852 spin_lock(&host->lock);
853
854 do {
8b1c2ba2 855 status = msmsdcc_readl(host, MMCISTATUS);
0c521ccb 856 status &= msmsdcc_readl(host, MMCIMASK0);
8b1c2ba2 857 msmsdcc_writel(host, status, MMCICLEAR);
9d2bd738 858
865c8064
SM		 859 if (status & MCI_SDIOINTR)
860 status &= ~MCI_SDIOINTR;
9d2bd738 861
865c8064
SM		 862 if (!status)
863 break;
9d2bd738 864
b5a74d60 865 msmsdcc_handle_irq_data(host, status, base);
9d2bd738
SM		 866
867 if (status & MCI_SDIOINTOPER) {
868 cardint = 1;
869 status &= ~MCI_SDIOINTOPER;
870 }
871 ret = 1;
872 } while (status);
873
874 spin_unlock(&host->lock);
875
876 /*
877 * We have to delay handling the card interrupt as it calls
878 * back into the driver.
879 */
880 if (cardint)
881 mmc_signal_sdio_irq(host->mmc);
882
883 return IRQ_RETVAL(ret);
884}
885
886static void
887msmsdcc_request(struct mmc_host *mmc, struct mmc_request *mrq)
888{
889 struct msmsdcc_host *host = mmc_priv(mmc);
890 unsigned long flags;
891
892 WARN_ON(host->curr.mrq != NULL);
893 WARN_ON(host->pwr == 0);
894
895 spin_lock_irqsave(&host->lock, flags);
896
897 host->stats.reqs++;
898
899 if (host->eject) {
900 if (mrq->data && !(mrq->data->flags & MMC_DATA_READ)) {
901 mrq->cmd->error = 0;
902 mrq->data->bytes_xfered = mrq->data->blksz *
903 mrq->data->blocks;
904 } else
905 mrq->cmd->error = -ENOMEDIUM;
906
907 spin_unlock_irqrestore(&host->lock, flags);
908 mmc_request_done(mmc, mrq);
909 return;
910 }
911
d0719e59 912 msmsdcc_enable_clocks(host);
9d2bd738 913
9d2bd738
SM		 914 host->curr.mrq = mrq;
915
916 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
56a8b5b8
SM		 917 /* Queue/read data, daisy-chain command when data starts */
918 msmsdcc_start_data(host, mrq->data, mrq->cmd, 0);
919 else
920 msmsdcc_start_command(host, mrq->cmd, 0);
9d2bd738
SM		 921
922 if (host->cmdpoll && !msmsdcc_spin_on_status(host,
923 MCI_CMDRESPEND|MCI_CMDCRCFAIL|MCI_CMDTIMEOUT,
924 CMD_SPINMAX)) {
8b1c2ba2 925 uint32_t status = msmsdcc_readl(host, MMCISTATUS);
9d2bd738 926 msmsdcc_do_cmdirq(host, status);
8b1c2ba2
SM		 927 msmsdcc_writel(host,
928 MCI_CMDRESPEND | MCI_CMDCRCFAIL | MCI_CMDTIMEOUT,
929 MMCICLEAR);
9d2bd738
SM		 930 host->stats.cmdpoll_hits++;
931 } else {
932 host->stats.cmdpoll_misses++;
9d2bd738
SM		 933 }
934 spin_unlock_irqrestore(&host->lock, flags);
935}
936
7a89248a
ST		 937static void msmsdcc_setup_gpio(struct msmsdcc_host *host, bool enable)
938{
939 struct msm_mmc_gpio_data *curr;
940 int i, rc = 0;
941
435f3e38 942 if (!host->plat->gpio_data || host->gpio_config_status == enable)
7a89248a
ST		 943 return;
944
945 curr = host->plat->gpio_data;
946 for (i = 0; i < curr->size; i++) {
947 if (enable) {
948 rc = gpio_request(curr->gpio[i].no,
949 curr->gpio[i].name);
950 if (rc) {
951 pr_err("%s: gpio_request(%d, %s) failed %d\n",
952 mmc_hostname(host->mmc),
953 curr->gpio[i].no,
954 curr->gpio[i].name, rc);
955 goto free_gpios;
956 }
957 } else {
958 gpio_free(curr->gpio[i].no);
959 }
960 }
961 host->gpio_config_status = enable;
962 return;
963
964free_gpios:
965 for (; i >= 0; i--)
966 gpio_free(curr->gpio[i].no);
967}
968
9d2bd738
SM		 969static void
970msmsdcc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
971{
972 struct msmsdcc_host *host = mmc_priv(mmc);
973 u32 clk = 0, pwr = 0;
974 int rc;
4adbbcc7 975 unsigned long flags;
9d2bd738 976
c7fc9370 977 spin_lock_irqsave(&host->lock, flags);
9d2bd738 978
d0719e59
SM		 979 msmsdcc_enable_clocks(host);
980
7a89248a
ST		 981 spin_unlock_irqrestore(&host->lock, flags);
982
865c8064 983 if (ios->clock) {
9d2bd738
SM		 984 if (ios->clock != host->clk_rate) {
985 rc = clk_set_rate(host->clk, ios->clock);
986 if (rc < 0)
0a7ff7c7
JP		 987 pr_err("%s: Error setting clock rate (%d)\n",
988 mmc_hostname(host->mmc), rc);
9d2bd738
SM		 989 else
990 host->clk_rate = ios->clock;
991 }
992 clk |= MCI_CLK_ENABLE;
993 }
994
995 if (ios->bus_width == MMC_BUS_WIDTH_4)
996 clk |= (2 << 10); /* Set WIDEBUS */
997
998 if (ios->clock > 400000 && msmsdcc_pwrsave)
999 clk |= (1 << 9); /* PWRSAVE */
1000
1001 clk |= (1 << 12); /* FLOW_ENA */
1002 clk |= (1 << 15); /* feedback clock */
1003
1004 if (host->plat->translate_vdd)
1005 pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
1006
1007 switch (ios->power_mode) {
1008 case MMC_POWER_OFF:
7a89248a 1009 msmsdcc_setup_gpio(host, false);
9d2bd738
SM		 1010 break;
1011 case MMC_POWER_UP:
1012 pwr |= MCI_PWR_UP;
7a89248a 1013 msmsdcc_setup_gpio(host, true);
9d2bd738
SM		 1014 break;
1015 case MMC_POWER_ON:
9d2bd738
SM		 1016 pwr |= MCI_PWR_ON;
1017 break;
1018 }
1019
1020 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1021 pwr |= MCI_OD;
1022
8b1c2ba2 1023 msmsdcc_writel(host, clk, MMCICLOCK);
9d2bd738
SM		 1024
1025 if (host->pwr != pwr) {
1026 host->pwr = pwr;
8b1c2ba2 1027 msmsdcc_writel(host, pwr, MMCIPOWER);
9d2bd738 1028 }
f4748499 1029#if BUSCLK_PWRSAVE
7a89248a 1030 spin_lock_irqsave(&host->lock, flags);
c7fc9370 1031 msmsdcc_disable_clocks(host, 1);
4adbbcc7 1032 spin_unlock_irqrestore(&host->lock, flags);
7a89248a 1033#endif
9d2bd738
SM		 1034}
1035
1036static void msmsdcc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1037{
1038 struct msmsdcc_host *host = mmc_priv(mmc);
1039 unsigned long flags;
1040 u32 status;
1041
1042 spin_lock_irqsave(&host->lock, flags);
1043 if (msmsdcc_sdioirq == 1) {
8b1c2ba2 1044 status = msmsdcc_readl(host, MMCIMASK0);
9d2bd738
SM		 1045 if (enable)
1046 status |= MCI_SDIOINTOPERMASK;
1047 else
1048 status &= ~MCI_SDIOINTOPERMASK;
1049 host->saved_irq0mask = status;
8b1c2ba2 1050 msmsdcc_writel(host, status, MMCIMASK0);
9d2bd738
SM		 1051 }
1052 spin_unlock_irqrestore(&host->lock, flags);
1053}
1054
e91957e7
AT		 1055static void msmsdcc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1056{
1057 struct msmsdcc_host *host = mmc_priv(mmc);
1058
1059 if (host->plat->init_card)
1060 host->plat->init_card(card);
1061}
1062
9d2bd738
SM		 1063static const struct mmc_host_ops msmsdcc_ops = {
1064 .request = msmsdcc_request,
1065 .set_ios = msmsdcc_set_ios,
1066 .enable_sdio_irq = msmsdcc_enable_sdio_irq,
e91957e7 1067 .init_card = msmsdcc_init_card,
9d2bd738
SM		 1068};
1069
1070static void
1071msmsdcc_check_status(unsigned long data)
1072{
1073 struct msmsdcc_host *host = (struct msmsdcc_host *)data;
1074 unsigned int status;
1075
1076 if (!host->plat->status) {
1077 mmc_detect_change(host->mmc, 0);
1078 goto out;
1079 }
1080
1081 status = host->plat->status(mmc_dev(host->mmc));
1082 host->eject = !status;
1083 if (status ^ host->oldstat) {
0a7ff7c7
JP		 1084 pr_info("%s: Slot status change detected (%d -> %d)\n",
1085 mmc_hostname(host->mmc), host->oldstat, status);
9d2bd738
SM		 1086 if (status)
1087 mmc_detect_change(host->mmc, (5 * HZ) / 2);
1088 else
1089 mmc_detect_change(host->mmc, 0);
1090 }
1091
1092 host->oldstat = status;
1093
1094out:
1095 if (host->timer.function)
1096 mod_timer(&host->timer, jiffies + HZ);
1097}
1098
1099static irqreturn_t
1100msmsdcc_platform_status_irq(int irq, void *dev_id)
1101{
1102 struct msmsdcc_host *host = dev_id;
1103
1104 printk(KERN_DEBUG "%s: %d\n", __func__, irq);
1105 msmsdcc_check_status((unsigned long) host);
1106 return IRQ_HANDLED;
1107}
1108
1109static void
1110msmsdcc_status_notify_cb(int card_present, void *dev_id)
1111{
1112 struct msmsdcc_host *host = dev_id;
1113
1114 printk(KERN_DEBUG "%s: card_present %d\n", mmc_hostname(host->mmc),
1115 card_present);
1116 msmsdcc_check_status((unsigned long) host);
1117}
1118
9d2bd738 1119static void
865c8064 1120msmsdcc_busclk_expired(unsigned long _data)
9d2bd738
SM		 1121{
1122 struct msmsdcc_host *host = (struct msmsdcc_host *) _data;
9d2bd738 1123
865c8064 1124 if (host->clks_on)
c7fc9370 1125 msmsdcc_disable_clocks(host, 0);
9d2bd738
SM		 1126}
1127
1128static int
1129msmsdcc_init_dma(struct msmsdcc_host *host)
1130{
1131 memset(&host->dma, 0, sizeof(struct msmsdcc_dma_data));
1132 host->dma.host = host;
1133 host->dma.channel = -1;
1134
1135 if (!host->dmares)
1136 return -ENODEV;
1137
1138 host->dma.nc = dma_alloc_coherent(NULL,
1139 sizeof(struct msmsdcc_nc_dmadata),
1140 &host->dma.nc_busaddr,
1141 GFP_KERNEL);
1142 if (host->dma.nc == NULL) {
0a7ff7c7 1143 pr_err("Unable to allocate DMA buffer\n");
9d2bd738
SM		 1144 return -ENOMEM;
1145 }
1146 memset(host->dma.nc, 0x00, sizeof(struct msmsdcc_nc_dmadata));
1147 host->dma.cmd_busaddr = host->dma.nc_busaddr;
1148 host->dma.cmdptr_busaddr = host->dma.nc_busaddr +
1149 offsetof(struct msmsdcc_nc_dmadata, cmdptr);
1150 host->dma.channel = host->dmares->start;
1151
1152 return 0;
1153}
1154
9d2bd738
SM		 1155static int
1156msmsdcc_probe(struct platform_device *pdev)
1157{
b5d643de 1158 struct msm_mmc_platform_data *plat = pdev->dev.platform_data;
9d2bd738
SM		 1159 struct msmsdcc_host *host;
1160 struct mmc_host *mmc;
1161 struct resource *cmd_irqres = NULL;
1162 struct resource *pio_irqres = NULL;
1163 struct resource *stat_irqres = NULL;
1164 struct resource *memres = NULL;
1165 struct resource *dmares = NULL;
1166 int ret;
1167
1168 /* must have platform data */
1169 if (!plat) {
0a7ff7c7 1170 pr_err("%s: Platform data not available\n", __func__);
9d2bd738
SM		 1171 ret = -EINVAL;
1172 goto out;
1173 }
1174
1175 if (pdev->id < 1 || pdev->id > 4)
1176 return -EINVAL;
1177
1178 if (pdev->resource == NULL || pdev->num_resources < 2) {
0a7ff7c7 1179 pr_err("%s: Invalid resource\n", __func__);
9d2bd738
SM		 1180 return -ENXIO;
1181 }
1182
1183 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1184 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1185 cmd_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1186 "cmd_irq");
1187 pio_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1188 "pio_irq");
1189 stat_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1190 "status_irq");
1191
1192 if (!cmd_irqres || !pio_irqres || !memres) {
0a7ff7c7 1193 pr_err("%s: Invalid resource\n", __func__);
9d2bd738
SM		 1194 return -ENXIO;
1195 }
1196
1197 /*
1198 * Setup our host structure
1199 */
1200
1201 mmc = mmc_alloc_host(sizeof(struct msmsdcc_host), &pdev->dev);
1202 if (!mmc) {
1203 ret = -ENOMEM;
1204 goto out;
1205 }
1206
1207 host = mmc_priv(mmc);
1208 host->pdev_id = pdev->id;
1209 host->plat = plat;
1210 host->mmc = mmc;
56a8b5b8 1211 host->curr.cmd = NULL;
9d2bd738
SM		 1212
1213 host->cmdpoll = 1;
1214
1215 host->base = ioremap(memres->start, PAGE_SIZE);
1216 if (!host->base) {
1217 ret = -ENOMEM;
dce7c756 1218 goto host_free;
9d2bd738
SM		 1219 }
1220
1221 host->cmd_irqres = cmd_irqres;
1222 host->pio_irqres = pio_irqres;
1223 host->memres = memres;
1224 host->dmares = dmares;
1225 spin_lock_init(&host->lock);
1226
62612cf9
ST		 1227 tasklet_init(&host->dma_tlet, msmsdcc_dma_complete_tlet,
1228 (unsigned long)host);
1229
9d2bd738
SM		 1230 /*
1231 * Setup DMA
1232 */
dce7c756
ST		 1233 ret = msmsdcc_init_dma(host);
1234 if (ret)
1235 goto ioremap_free;
9d2bd738 1236
4adbbcc7 1237 /* Get our clocks */
9d2bd738
SM		 1238 host->pclk = clk_get(&pdev->dev, "sdc_pclk");
1239 if (IS_ERR(host->pclk)) {
1240 ret = PTR_ERR(host->pclk);
dce7c756 1241 goto dma_free;
9d2bd738
SM		 1242 }
1243
9d2bd738
SM		 1244 host->clk = clk_get(&pdev->dev, "sdc_clk");
1245 if (IS_ERR(host->clk)) {
1246 ret = PTR_ERR(host->clk);
4adbbcc7 1247 goto pclk_put;
9d2bd738
SM		 1248 }
1249
9d2bd738
SM		 1250 ret = clk_set_rate(host->clk, msmsdcc_fmin);
1251 if (ret) {
0a7ff7c7 1252 pr_err("%s: Clock rate set failed (%d)\n", __func__, ret);
514d9eda 1253 goto clk_put;
9d2bd738
SM		 1254 }
1255
514d9eda
ST		 1256 /* Enable clocks */
1257 ret = msmsdcc_enable_clocks(host);
1258 if (ret)
1259 goto clk_put;
1260
4adbbcc7 1261 host->pclk_rate = clk_get_rate(host->pclk);
9d2bd738
SM		 1262 host->clk_rate = clk_get_rate(host->clk);
1263
9d2bd738
SM		 1264 /*
1265 * Setup MMC host structure
1266 */
1267 mmc->ops = &msmsdcc_ops;
1268 mmc->f_min = msmsdcc_fmin;
1269 mmc->f_max = msmsdcc_fmax;
1270 mmc->ocr_avail = plat->ocr_mask;
1271
1272 if (msmsdcc_4bit)
1273 mmc->caps |= MMC_CAP_4_BIT_DATA;
1274 if (msmsdcc_sdioirq)
1275 mmc->caps |= MMC_CAP_SDIO_IRQ;
1276 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1277
a36274e0 1278 mmc->max_segs = NR_SG;
9d2bd738
SM		 1279 mmc->max_blk_size = 4096; /* MCI_DATA_CTL BLOCKSIZE up to 4096 */
1280 mmc->max_blk_count = 65536;
1281
1282 mmc->max_req_size = 33554432; /* MCI_DATA_LENGTH is 25 bits */
1283 mmc->max_seg_size = mmc->max_req_size;
1284
8b1c2ba2
SM		 1285 msmsdcc_writel(host, 0, MMCIMASK0);
1286 msmsdcc_writel(host, 0x5e007ff, MMCICLEAR);
9d2bd738 1287
8b1c2ba2 1288 msmsdcc_writel(host, MCI_IRQENABLE, MMCIMASK0);
9d2bd738
SM		 1289 host->saved_irq0mask = MCI_IRQENABLE;
1290
1291 /*
1292 * Setup card detect change
1293 */
1294
1295 memset(&host->timer, 0, sizeof(host->timer));
1296
1297 if (stat_irqres && !(stat_irqres->flags & IORESOURCE_DISABLED)) {
1298 unsigned long irqflags = IRQF_SHARED |
1299 (stat_irqres->flags & IRQF_TRIGGER_MASK);
1300
1301 host->stat_irq = stat_irqres->start;
1302 ret = request_irq(host->stat_irq,
1303 msmsdcc_platform_status_irq,
1304 irqflags,
1305 DRIVER_NAME " (slot)",
1306 host);
1307 if (ret) {
0a7ff7c7
JP		 1308 pr_err("%s: Unable to get slot IRQ %d (%d)\n",
1309 mmc_hostname(mmc), host->stat_irq, ret);
9d2bd738
SM		 1310 goto clk_disable;
1311 }
1312 } else if (plat->register_status_notify) {
1313 plat->register_status_notify(msmsdcc_status_notify_cb, host);
1314 } else if (!plat->status)
0a7ff7c7 1315 pr_err("%s: No card detect facilities available\n",
9d2bd738
SM		 1316 mmc_hostname(mmc));
1317 else {
1318 init_timer(&host->timer);
1319 host->timer.data = (unsigned long)host;
1320 host->timer.function = msmsdcc_check_status;
1321 host->timer.expires = jiffies + HZ;
1322 add_timer(&host->timer);
1323 }
1324
1325 if (plat->status) {
1326 host->oldstat = host->plat->status(mmc_dev(host->mmc));
1327 host->eject = !host->oldstat;
1328 }
1329
865c8064
SM		 1330 init_timer(&host->busclk_timer);
1331 host->busclk_timer.data = (unsigned long) host;
1332 host->busclk_timer.function = msmsdcc_busclk_expired;
9d2bd738
SM		 1333
1334 ret = request_irq(cmd_irqres->start, msmsdcc_irq, IRQF_SHARED,
1335 DRIVER_NAME " (cmd)", host);
1336 if (ret)
1337 goto stat_irq_free;
1338
1339 ret = request_irq(pio_irqres->start, msmsdcc_pio_irq, IRQF_SHARED,
1340 DRIVER_NAME " (pio)", host);
1341 if (ret)
1342 goto cmd_irq_free;
1343
1344 mmc_set_drvdata(pdev, mmc);
1345 mmc_add_host(mmc);
1346
0a7ff7c7
JP		 1347 pr_info("%s: Qualcomm MSM SDCC at 0x%016llx irq %d,%d dma %d\n",
1348 mmc_hostname(mmc), (unsigned long long)memres->start,
1349 (unsigned int) cmd_irqres->start,
1350 (unsigned int) host->stat_irq, host->dma.channel);
1351 pr_info("%s: 4 bit data mode %s\n", mmc_hostname(mmc),
1352 (mmc->caps & MMC_CAP_4_BIT_DATA ? "enabled" : "disabled"));
1353 pr_info("%s: MMC clock %u -> %u Hz, PCLK %u Hz\n",
1354 mmc_hostname(mmc), msmsdcc_fmin, msmsdcc_fmax, host->pclk_rate);
1355 pr_info("%s: Slot eject status = %d\n", mmc_hostname(mmc), host->eject);
1356 pr_info("%s: Power save feature enable = %d\n",
1357 mmc_hostname(mmc), msmsdcc_pwrsave);
9d2bd738
SM		 1358
1359 if (host->dma.channel != -1) {
0a7ff7c7
JP		 1360 pr_info("%s: DM non-cached buffer at %p, dma_addr 0x%.8x\n",
1361 mmc_hostname(mmc), host->dma.nc, host->dma.nc_busaddr);
1362 pr_info("%s: DM cmd busaddr 0x%.8x, cmdptr busaddr 0x%.8x\n",
1363 mmc_hostname(mmc), host->dma.cmd_busaddr,
1364 host->dma.cmdptr_busaddr);
9d2bd738 1365 } else
0a7ff7c7 1366 pr_info("%s: PIO transfer enabled\n", mmc_hostname(mmc));
9d2bd738 1367 if (host->timer.function)
0a7ff7c7 1368 pr_info("%s: Polling status mode enabled\n", mmc_hostname(mmc));
9d2bd738
SM		 1369
1370 return 0;
1371 cmd_irq_free:
1372 free_irq(cmd_irqres->start, host);
1373 stat_irq_free:
1374 if (host->stat_irq)
1375 free_irq(host->stat_irq, host);
1376 clk_disable:
c7fc9370 1377 msmsdcc_disable_clocks(host, 0);
9d2bd738
SM		 1378 clk_put:
1379 clk_put(host->clk);
9d2bd738
SM		 1380 pclk_put:
1381 clk_put(host->pclk);
dce7c756
ST		 1382dma_free:
1383 dma_free_coherent(NULL, sizeof(struct msmsdcc_nc_dmadata),
1384 host->dma.nc, host->dma.nc_busaddr);
1385ioremap_free:
1386 tasklet_kill(&host->dma_tlet);
1387 iounmap(host->base);
9d2bd738
SM		 1388 host_free:
1389 mmc_free_host(mmc);
1390 out:
1391 return ret;
1392}
1393
08ecfde4
DW		 1394#ifdef CONFIG_PM
1395#ifdef CONFIG_MMC_MSM7X00A_RESUME_IN_WQ
1396static void
1397do_resume_work(struct work_struct *work)
1398{
1399 struct msmsdcc_host *host =
1400 container_of(work, struct msmsdcc_host, resume_task);
1401 struct mmc_host *mmc = host->mmc;
1402
1403 if (mmc) {
1404 mmc_resume_host(mmc);
1405 if (host->stat_irq)
1406 enable_irq(host->stat_irq);
1407 }
1408}
1409#endif
1410
1411
9d2bd738
SM		 1412static int
1413msmsdcc_suspend(struct platform_device *dev, pm_message_t state)
1414{
1415 struct mmc_host *mmc = mmc_get_drvdata(dev);
1416 int rc = 0;
1417
1418 if (mmc) {
1419 struct msmsdcc_host *host = mmc_priv(mmc);
1420
1421 if (host->stat_irq)
1422 disable_irq(host->stat_irq);
1423
1424 if (mmc->card && mmc->card->type != MMC_TYPE_SDIO)
1a13f8fa 1425 rc = mmc_suspend_host(mmc);
d0719e59 1426 if (!rc)
8b1c2ba2 1427 msmsdcc_writel(host, 0, MMCIMASK0);
c7fc9370
SM		 1428 if (host->clks_on)
1429 msmsdcc_disable_clocks(host, 0);
9d2bd738
SM		 1430 }
1431 return rc;
1432}
1433
1434static int
1435msmsdcc_resume(struct platform_device *dev)
1436{
1437 struct mmc_host *mmc = mmc_get_drvdata(dev);
9d2bd738
SM		 1438
1439 if (mmc) {
1440 struct msmsdcc_host *host = mmc_priv(mmc);
1441
c7fc9370 1442 msmsdcc_enable_clocks(host);
9d2bd738 1443
8b1c2ba2 1444 msmsdcc_writel(host, host->saved_irq0mask, MMCIMASK0);
9d2bd738
SM		 1445
1446 if (mmc->card && mmc->card->type != MMC_TYPE_SDIO)
1447 mmc_resume_host(mmc);
5b8a2fb3 1448 if (host->stat_irq)
9d2bd738 1449 enable_irq(host->stat_irq);
f4748499 1450#if BUSCLK_PWRSAVE
c7fc9370 1451 msmsdcc_disable_clocks(host, 1);
f4748499 1452#endif
9d2bd738
SM		 1453 }
1454 return 0;
1455}
08ecfde4
DW		 1456#else
1457#define msmsdcc_suspend 0
1458#define msmsdcc_resume 0
1459#endif
9d2bd738
SM		 1460
1461static struct platform_driver msmsdcc_driver = {
1462 .probe = msmsdcc_probe,
1463 .suspend = msmsdcc_suspend,
1464 .resume = msmsdcc_resume,
1465 .driver = {
1466 .name = "msm_sdcc",
1467 },
1468};
1469
1470static int __init msmsdcc_init(void)
1471{
1472 return platform_driver_register(&msmsdcc_driver);
1473}
1474
1475static void __exit msmsdcc_exit(void)
1476{
1477 platform_driver_unregister(&msmsdcc_driver);
1478}
1479
1480module_init(msmsdcc_init);
1481module_exit(msmsdcc_exit);
1482
1483MODULE_DESCRIPTION("Qualcomm MSM 7X00A Multimedia Card Interface driver");
1484MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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