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20848903 CJ |
1 | /* |
2 | * Copyright (c) 2014-2015 MediaTek Inc. | |
3 | * Author: Chaotian.Jing <chaotian.jing@mediatek.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
15 | #include <linux/module.h> | |
16 | #include <linux/clk.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/dma-mapping.h> | |
19 | #include <linux/ioport.h> | |
20 | #include <linux/irq.h> | |
21 | #include <linux/of_address.h> | |
22 | #include <linux/of_irq.h> | |
23 | #include <linux/of_gpio.h> | |
24 | #include <linux/pinctrl/consumer.h> | |
25 | #include <linux/platform_device.h> | |
4b8a43e9 CJ |
26 | #include <linux/pm.h> |
27 | #include <linux/pm_runtime.h> | |
20848903 | 28 | #include <linux/regulator/consumer.h> |
6397b7f5 | 29 | #include <linux/slab.h> |
20848903 CJ |
30 | #include <linux/spinlock.h> |
31 | ||
32 | #include <linux/mmc/card.h> | |
33 | #include <linux/mmc/core.h> | |
34 | #include <linux/mmc/host.h> | |
35 | #include <linux/mmc/mmc.h> | |
36 | #include <linux/mmc/sd.h> | |
37 | #include <linux/mmc/sdio.h> | |
8d53e412 | 38 | #include <linux/mmc/slot-gpio.h> |
20848903 CJ |
39 | |
40 | #define MAX_BD_NUM 1024 | |
41 | ||
42 | /*--------------------------------------------------------------------------*/ | |
43 | /* Common Definition */ | |
44 | /*--------------------------------------------------------------------------*/ | |
45 | #define MSDC_BUS_1BITS 0x0 | |
46 | #define MSDC_BUS_4BITS 0x1 | |
47 | #define MSDC_BUS_8BITS 0x2 | |
48 | ||
49 | #define MSDC_BURST_64B 0x6 | |
50 | ||
51 | /*--------------------------------------------------------------------------*/ | |
52 | /* Register Offset */ | |
53 | /*--------------------------------------------------------------------------*/ | |
54 | #define MSDC_CFG 0x0 | |
55 | #define MSDC_IOCON 0x04 | |
56 | #define MSDC_PS 0x08 | |
57 | #define MSDC_INT 0x0c | |
58 | #define MSDC_INTEN 0x10 | |
59 | #define MSDC_FIFOCS 0x14 | |
60 | #define SDC_CFG 0x30 | |
61 | #define SDC_CMD 0x34 | |
62 | #define SDC_ARG 0x38 | |
63 | #define SDC_STS 0x3c | |
64 | #define SDC_RESP0 0x40 | |
65 | #define SDC_RESP1 0x44 | |
66 | #define SDC_RESP2 0x48 | |
67 | #define SDC_RESP3 0x4c | |
68 | #define SDC_BLK_NUM 0x50 | |
c9b5061e | 69 | #define EMMC_IOCON 0x7c |
20848903 CJ |
70 | #define SDC_ACMD_RESP 0x80 |
71 | #define MSDC_DMA_SA 0x90 | |
72 | #define MSDC_DMA_CTRL 0x98 | |
73 | #define MSDC_DMA_CFG 0x9c | |
74 | #define MSDC_PATCH_BIT 0xb0 | |
75 | #define MSDC_PATCH_BIT1 0xb4 | |
76 | #define MSDC_PAD_TUNE 0xec | |
6397b7f5 CJ |
77 | #define PAD_DS_TUNE 0x188 |
78 | #define EMMC50_CFG0 0x208 | |
20848903 CJ |
79 | |
80 | /*--------------------------------------------------------------------------*/ | |
81 | /* Register Mask */ | |
82 | /*--------------------------------------------------------------------------*/ | |
83 | ||
84 | /* MSDC_CFG mask */ | |
85 | #define MSDC_CFG_MODE (0x1 << 0) /* RW */ | |
86 | #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ | |
87 | #define MSDC_CFG_RST (0x1 << 2) /* RW */ | |
88 | #define MSDC_CFG_PIO (0x1 << 3) /* RW */ | |
89 | #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ | |
90 | #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ | |
91 | #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ | |
92 | #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ | |
93 | #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ | |
94 | #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ | |
6397b7f5 | 95 | #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */ |
20848903 CJ |
96 | |
97 | /* MSDC_IOCON mask */ | |
98 | #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ | |
99 | #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ | |
100 | #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ | |
101 | #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ | |
102 | #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ | |
103 | #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ | |
104 | #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ | |
105 | #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ | |
106 | #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ | |
107 | #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ | |
108 | #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ | |
109 | #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ | |
110 | #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ | |
111 | #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ | |
112 | #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ | |
113 | #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ | |
114 | ||
115 | /* MSDC_PS mask */ | |
116 | #define MSDC_PS_CDEN (0x1 << 0) /* RW */ | |
117 | #define MSDC_PS_CDSTS (0x1 << 1) /* R */ | |
118 | #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ | |
119 | #define MSDC_PS_DAT (0xff << 16) /* R */ | |
120 | #define MSDC_PS_CMD (0x1 << 24) /* R */ | |
121 | #define MSDC_PS_WP (0x1 << 31) /* R */ | |
122 | ||
123 | /* MSDC_INT mask */ | |
124 | #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ | |
125 | #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ | |
126 | #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ | |
127 | #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ | |
128 | #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ | |
129 | #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ | |
130 | #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ | |
131 | #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ | |
132 | #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ | |
133 | #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ | |
134 | #define MSDC_INT_CSTA (0x1 << 11) /* R */ | |
135 | #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ | |
136 | #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ | |
137 | #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ | |
138 | #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ | |
139 | #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ | |
140 | #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ | |
141 | #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ | |
142 | #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ | |
143 | ||
144 | /* MSDC_INTEN mask */ | |
145 | #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ | |
146 | #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ | |
147 | #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ | |
148 | #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ | |
149 | #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ | |
150 | #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ | |
151 | #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ | |
152 | #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ | |
153 | #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ | |
154 | #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ | |
155 | #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ | |
156 | #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ | |
157 | #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ | |
158 | #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ | |
159 | #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ | |
160 | #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ | |
161 | #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ | |
162 | #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ | |
163 | #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ | |
164 | ||
165 | /* MSDC_FIFOCS mask */ | |
166 | #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ | |
167 | #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ | |
168 | #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ | |
169 | ||
170 | /* SDC_CFG mask */ | |
171 | #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ | |
172 | #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ | |
173 | #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ | |
174 | #define SDC_CFG_SDIO (0x1 << 19) /* RW */ | |
175 | #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ | |
176 | #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ | |
177 | #define SDC_CFG_DTOC (0xff << 24) /* RW */ | |
178 | ||
179 | /* SDC_STS mask */ | |
180 | #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ | |
181 | #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ | |
182 | #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ | |
183 | ||
184 | /* MSDC_DMA_CTRL mask */ | |
185 | #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ | |
186 | #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ | |
187 | #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ | |
188 | #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ | |
189 | #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ | |
190 | #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ | |
191 | ||
192 | /* MSDC_DMA_CFG mask */ | |
193 | #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ | |
194 | #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ | |
195 | #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ | |
196 | #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ | |
197 | #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ | |
198 | ||
199 | /* MSDC_PATCH_BIT mask */ | |
200 | #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ | |
201 | #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) | |
202 | #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) | |
203 | #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ | |
204 | #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ | |
205 | #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ | |
206 | #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ | |
207 | #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ | |
208 | #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ | |
209 | #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ | |
210 | #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ | |
211 | #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ | |
212 | ||
6397b7f5 CJ |
213 | #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */ |
214 | #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */ | |
215 | ||
216 | #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */ | |
217 | #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */ | |
218 | #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */ | |
219 | ||
220 | #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */ | |
221 | #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */ | |
222 | #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ | |
223 | ||
20848903 CJ |
224 | #define REQ_CMD_EIO (0x1 << 0) |
225 | #define REQ_CMD_TMO (0x1 << 1) | |
226 | #define REQ_DAT_ERR (0x1 << 2) | |
227 | #define REQ_STOP_EIO (0x1 << 3) | |
228 | #define REQ_STOP_TMO (0x1 << 4) | |
229 | #define REQ_CMD_BUSY (0x1 << 5) | |
230 | ||
231 | #define MSDC_PREPARE_FLAG (0x1 << 0) | |
232 | #define MSDC_ASYNC_FLAG (0x1 << 1) | |
233 | #define MSDC_MMAP_FLAG (0x1 << 2) | |
234 | ||
4b8a43e9 | 235 | #define MTK_MMC_AUTOSUSPEND_DELAY 50 |
20848903 CJ |
236 | #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ |
237 | #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ | |
238 | ||
6397b7f5 | 239 | #define PAD_DELAY_MAX 32 /* PAD delay cells */ |
20848903 CJ |
240 | /*--------------------------------------------------------------------------*/ |
241 | /* Descriptor Structure */ | |
242 | /*--------------------------------------------------------------------------*/ | |
243 | struct mt_gpdma_desc { | |
244 | u32 gpd_info; | |
245 | #define GPDMA_DESC_HWO (0x1 << 0) | |
246 | #define GPDMA_DESC_BDP (0x1 << 1) | |
247 | #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ | |
248 | #define GPDMA_DESC_INT (0x1 << 16) | |
249 | u32 next; | |
250 | u32 ptr; | |
251 | u32 gpd_data_len; | |
252 | #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ | |
253 | #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ | |
254 | u32 arg; | |
255 | u32 blknum; | |
256 | u32 cmd; | |
257 | }; | |
258 | ||
259 | struct mt_bdma_desc { | |
260 | u32 bd_info; | |
261 | #define BDMA_DESC_EOL (0x1 << 0) | |
262 | #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ | |
263 | #define BDMA_DESC_BLKPAD (0x1 << 17) | |
264 | #define BDMA_DESC_DWPAD (0x1 << 18) | |
265 | u32 next; | |
266 | u32 ptr; | |
267 | u32 bd_data_len; | |
268 | #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ | |
269 | }; | |
270 | ||
271 | struct msdc_dma { | |
272 | struct scatterlist *sg; /* I/O scatter list */ | |
273 | struct mt_gpdma_desc *gpd; /* pointer to gpd array */ | |
274 | struct mt_bdma_desc *bd; /* pointer to bd array */ | |
275 | dma_addr_t gpd_addr; /* the physical address of gpd array */ | |
276 | dma_addr_t bd_addr; /* the physical address of bd array */ | |
277 | }; | |
278 | ||
4b8a43e9 CJ |
279 | struct msdc_save_para { |
280 | u32 msdc_cfg; | |
281 | u32 iocon; | |
282 | u32 sdc_cfg; | |
283 | u32 pad_tune; | |
284 | u32 patch_bit0; | |
285 | u32 patch_bit1; | |
6397b7f5 CJ |
286 | u32 pad_ds_tune; |
287 | u32 emmc50_cfg0; | |
288 | }; | |
289 | ||
290 | struct msdc_delay_phase { | |
291 | u8 maxlen; | |
292 | u8 start; | |
293 | u8 final_phase; | |
4b8a43e9 CJ |
294 | }; |
295 | ||
20848903 CJ |
296 | struct msdc_host { |
297 | struct device *dev; | |
298 | struct mmc_host *mmc; /* mmc structure */ | |
299 | int cmd_rsp; | |
300 | ||
301 | spinlock_t lock; | |
302 | struct mmc_request *mrq; | |
303 | struct mmc_command *cmd; | |
304 | struct mmc_data *data; | |
305 | int error; | |
306 | ||
307 | void __iomem *base; /* host base address */ | |
308 | ||
309 | struct msdc_dma dma; /* dma channel */ | |
310 | u64 dma_mask; | |
311 | ||
312 | u32 timeout_ns; /* data timeout ns */ | |
313 | u32 timeout_clks; /* data timeout clks */ | |
314 | ||
315 | struct pinctrl *pinctrl; | |
316 | struct pinctrl_state *pins_default; | |
317 | struct pinctrl_state *pins_uhs; | |
318 | struct delayed_work req_timeout; | |
319 | int irq; /* host interrupt */ | |
320 | ||
321 | struct clk *src_clk; /* msdc source clock */ | |
322 | struct clk *h_clk; /* msdc h_clk */ | |
323 | u32 mclk; /* mmc subsystem clock frequency */ | |
324 | u32 src_clk_freq; /* source clock frequency */ | |
325 | u32 sclk; /* SD/MS bus clock frequency */ | |
6e622947 | 326 | unsigned char timing; |
20848903 | 327 | bool vqmmc_enabled; |
6397b7f5 | 328 | u32 hs400_ds_delay; |
4b8a43e9 | 329 | struct msdc_save_para save_para; /* used when gate HCLK */ |
20848903 CJ |
330 | }; |
331 | ||
332 | static void sdr_set_bits(void __iomem *reg, u32 bs) | |
333 | { | |
334 | u32 val = readl(reg); | |
335 | ||
336 | val |= bs; | |
337 | writel(val, reg); | |
338 | } | |
339 | ||
340 | static void sdr_clr_bits(void __iomem *reg, u32 bs) | |
341 | { | |
342 | u32 val = readl(reg); | |
343 | ||
344 | val &= ~bs; | |
345 | writel(val, reg); | |
346 | } | |
347 | ||
348 | static void sdr_set_field(void __iomem *reg, u32 field, u32 val) | |
349 | { | |
350 | unsigned int tv = readl(reg); | |
351 | ||
352 | tv &= ~field; | |
353 | tv |= ((val) << (ffs((unsigned int)field) - 1)); | |
354 | writel(tv, reg); | |
355 | } | |
356 | ||
357 | static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) | |
358 | { | |
359 | unsigned int tv = readl(reg); | |
360 | ||
361 | *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); | |
362 | } | |
363 | ||
364 | static void msdc_reset_hw(struct msdc_host *host) | |
365 | { | |
366 | u32 val; | |
367 | ||
368 | sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); | |
369 | while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) | |
370 | cpu_relax(); | |
371 | ||
372 | sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); | |
373 | while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) | |
374 | cpu_relax(); | |
375 | ||
376 | val = readl(host->base + MSDC_INT); | |
377 | writel(val, host->base + MSDC_INT); | |
378 | } | |
379 | ||
380 | static void msdc_cmd_next(struct msdc_host *host, | |
381 | struct mmc_request *mrq, struct mmc_command *cmd); | |
382 | ||
726a9aac CJ |
383 | static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | |
384 | MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | | |
385 | MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; | |
386 | static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | | |
20848903 CJ |
387 | MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | |
388 | MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; | |
389 | ||
390 | static u8 msdc_dma_calcs(u8 *buf, u32 len) | |
391 | { | |
392 | u32 i, sum = 0; | |
393 | ||
394 | for (i = 0; i < len; i++) | |
395 | sum += buf[i]; | |
396 | return 0xff - (u8) sum; | |
397 | } | |
398 | ||
399 | static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, | |
400 | struct mmc_data *data) | |
401 | { | |
402 | unsigned int j, dma_len; | |
403 | dma_addr_t dma_address; | |
404 | u32 dma_ctrl; | |
405 | struct scatterlist *sg; | |
406 | struct mt_gpdma_desc *gpd; | |
407 | struct mt_bdma_desc *bd; | |
408 | ||
409 | sg = data->sg; | |
410 | ||
411 | gpd = dma->gpd; | |
412 | bd = dma->bd; | |
413 | ||
414 | /* modify gpd */ | |
415 | gpd->gpd_info |= GPDMA_DESC_HWO; | |
416 | gpd->gpd_info |= GPDMA_DESC_BDP; | |
417 | /* need to clear first. use these bits to calc checksum */ | |
418 | gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; | |
419 | gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; | |
420 | ||
421 | /* modify bd */ | |
422 | for_each_sg(data->sg, sg, data->sg_count, j) { | |
423 | dma_address = sg_dma_address(sg); | |
424 | dma_len = sg_dma_len(sg); | |
425 | ||
426 | /* init bd */ | |
427 | bd[j].bd_info &= ~BDMA_DESC_BLKPAD; | |
428 | bd[j].bd_info &= ~BDMA_DESC_DWPAD; | |
429 | bd[j].ptr = (u32)dma_address; | |
430 | bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; | |
431 | bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); | |
432 | ||
433 | if (j == data->sg_count - 1) /* the last bd */ | |
434 | bd[j].bd_info |= BDMA_DESC_EOL; | |
435 | else | |
436 | bd[j].bd_info &= ~BDMA_DESC_EOL; | |
437 | ||
438 | /* checksume need to clear first */ | |
439 | bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; | |
440 | bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; | |
441 | } | |
442 | ||
443 | sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); | |
444 | dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); | |
445 | dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); | |
446 | dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); | |
447 | writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); | |
448 | writel((u32)dma->gpd_addr, host->base + MSDC_DMA_SA); | |
449 | } | |
450 | ||
451 | static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq) | |
452 | { | |
453 | struct mmc_data *data = mrq->data; | |
454 | ||
455 | if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { | |
456 | bool read = (data->flags & MMC_DATA_READ) != 0; | |
457 | ||
458 | data->host_cookie |= MSDC_PREPARE_FLAG; | |
459 | data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, | |
460 | read ? DMA_FROM_DEVICE : DMA_TO_DEVICE); | |
461 | } | |
462 | } | |
463 | ||
464 | static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) | |
465 | { | |
466 | struct mmc_data *data = mrq->data; | |
467 | ||
468 | if (data->host_cookie & MSDC_ASYNC_FLAG) | |
469 | return; | |
470 | ||
471 | if (data->host_cookie & MSDC_PREPARE_FLAG) { | |
472 | bool read = (data->flags & MMC_DATA_READ) != 0; | |
473 | ||
474 | dma_unmap_sg(host->dev, data->sg, data->sg_len, | |
475 | read ? DMA_FROM_DEVICE : DMA_TO_DEVICE); | |
476 | data->host_cookie &= ~MSDC_PREPARE_FLAG; | |
477 | } | |
478 | } | |
479 | ||
480 | /* clock control primitives */ | |
481 | static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) | |
482 | { | |
483 | u32 timeout, clk_ns; | |
484 | u32 mode = 0; | |
485 | ||
486 | host->timeout_ns = ns; | |
487 | host->timeout_clks = clks; | |
488 | if (host->sclk == 0) { | |
489 | timeout = 0; | |
490 | } else { | |
491 | clk_ns = 1000000000UL / host->sclk; | |
492 | timeout = (ns + clk_ns - 1) / clk_ns + clks; | |
493 | /* in 1048576 sclk cycle unit */ | |
494 | timeout = (timeout + (0x1 << 20) - 1) >> 20; | |
495 | sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode); | |
496 | /*DDR mode will double the clk cycles for data timeout */ | |
497 | timeout = mode >= 2 ? timeout * 2 : timeout; | |
498 | timeout = timeout > 1 ? timeout - 1 : 0; | |
499 | timeout = timeout > 255 ? 255 : timeout; | |
500 | } | |
501 | sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout); | |
502 | } | |
503 | ||
504 | static void msdc_gate_clock(struct msdc_host *host) | |
505 | { | |
506 | clk_disable_unprepare(host->src_clk); | |
507 | clk_disable_unprepare(host->h_clk); | |
508 | } | |
509 | ||
510 | static void msdc_ungate_clock(struct msdc_host *host) | |
511 | { | |
512 | clk_prepare_enable(host->h_clk); | |
513 | clk_prepare_enable(host->src_clk); | |
514 | while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) | |
515 | cpu_relax(); | |
516 | } | |
517 | ||
6e622947 | 518 | static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) |
20848903 CJ |
519 | { |
520 | u32 mode; | |
521 | u32 flags; | |
522 | u32 div; | |
523 | u32 sclk; | |
524 | ||
525 | if (!hz) { | |
526 | dev_dbg(host->dev, "set mclk to 0\n"); | |
527 | host->mclk = 0; | |
528 | sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); | |
529 | return; | |
530 | } | |
531 | ||
532 | flags = readl(host->base + MSDC_INTEN); | |
533 | sdr_clr_bits(host->base + MSDC_INTEN, flags); | |
6397b7f5 | 534 | sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); |
6e622947 | 535 | if (timing == MMC_TIMING_UHS_DDR50 || |
6397b7f5 CJ |
536 | timing == MMC_TIMING_MMC_DDR52 || |
537 | timing == MMC_TIMING_MMC_HS400) { | |
538 | if (timing == MMC_TIMING_MMC_HS400) | |
539 | mode = 0x3; | |
540 | else | |
541 | mode = 0x2; /* ddr mode and use divisor */ | |
542 | ||
20848903 CJ |
543 | if (hz >= (host->src_clk_freq >> 2)) { |
544 | div = 0; /* mean div = 1/4 */ | |
545 | sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ | |
546 | } else { | |
547 | div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); | |
548 | sclk = (host->src_clk_freq >> 2) / div; | |
549 | div = (div >> 1); | |
550 | } | |
6397b7f5 CJ |
551 | |
552 | if (timing == MMC_TIMING_MMC_HS400 && | |
553 | hz >= (host->src_clk_freq >> 1)) { | |
554 | sdr_set_bits(host->base + MSDC_CFG, | |
555 | MSDC_CFG_HS400_CK_MODE); | |
556 | sclk = host->src_clk_freq >> 1; | |
557 | div = 0; /* div is ignore when bit18 is set */ | |
558 | } | |
20848903 CJ |
559 | } else if (hz >= host->src_clk_freq) { |
560 | mode = 0x1; /* no divisor */ | |
561 | div = 0; | |
562 | sclk = host->src_clk_freq; | |
563 | } else { | |
564 | mode = 0x0; /* use divisor */ | |
565 | if (hz >= (host->src_clk_freq >> 1)) { | |
566 | div = 0; /* mean div = 1/2 */ | |
567 | sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ | |
568 | } else { | |
569 | div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); | |
570 | sclk = (host->src_clk_freq >> 2) / div; | |
571 | } | |
572 | } | |
573 | sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, | |
574 | (mode << 8) | (div % 0xff)); | |
575 | sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); | |
576 | while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) | |
577 | cpu_relax(); | |
578 | host->sclk = sclk; | |
579 | host->mclk = hz; | |
6e622947 | 580 | host->timing = timing; |
20848903 CJ |
581 | /* need because clk changed. */ |
582 | msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); | |
583 | sdr_set_bits(host->base + MSDC_INTEN, flags); | |
584 | ||
6e622947 | 585 | dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->sclk, timing); |
20848903 CJ |
586 | } |
587 | ||
588 | static inline u32 msdc_cmd_find_resp(struct msdc_host *host, | |
589 | struct mmc_request *mrq, struct mmc_command *cmd) | |
590 | { | |
591 | u32 resp; | |
592 | ||
593 | switch (mmc_resp_type(cmd)) { | |
594 | /* Actually, R1, R5, R6, R7 are the same */ | |
595 | case MMC_RSP_R1: | |
596 | resp = 0x1; | |
597 | break; | |
598 | case MMC_RSP_R1B: | |
599 | resp = 0x7; | |
600 | break; | |
601 | case MMC_RSP_R2: | |
602 | resp = 0x2; | |
603 | break; | |
604 | case MMC_RSP_R3: | |
605 | resp = 0x3; | |
606 | break; | |
607 | case MMC_RSP_NONE: | |
608 | default: | |
609 | resp = 0x0; | |
610 | break; | |
611 | } | |
612 | ||
613 | return resp; | |
614 | } | |
615 | ||
616 | static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, | |
617 | struct mmc_request *mrq, struct mmc_command *cmd) | |
618 | { | |
619 | /* rawcmd : | |
620 | * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | | |
621 | * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode | |
622 | */ | |
623 | u32 opcode = cmd->opcode; | |
624 | u32 resp = msdc_cmd_find_resp(host, mrq, cmd); | |
625 | u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); | |
626 | ||
627 | host->cmd_rsp = resp; | |
628 | ||
629 | if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || | |
630 | opcode == MMC_STOP_TRANSMISSION) | |
631 | rawcmd |= (0x1 << 14); | |
632 | else if (opcode == SD_SWITCH_VOLTAGE) | |
633 | rawcmd |= (0x1 << 30); | |
634 | else if (opcode == SD_APP_SEND_SCR || | |
635 | opcode == SD_APP_SEND_NUM_WR_BLKS || | |
636 | (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || | |
637 | (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || | |
638 | (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) | |
639 | rawcmd |= (0x1 << 11); | |
640 | ||
641 | if (cmd->data) { | |
642 | struct mmc_data *data = cmd->data; | |
643 | ||
644 | if (mmc_op_multi(opcode)) { | |
645 | if (mmc_card_mmc(host->mmc->card) && mrq->sbc && | |
646 | !(mrq->sbc->arg & 0xFFFF0000)) | |
647 | rawcmd |= 0x2 << 28; /* AutoCMD23 */ | |
648 | } | |
649 | ||
650 | rawcmd |= ((data->blksz & 0xFFF) << 16); | |
651 | if (data->flags & MMC_DATA_WRITE) | |
652 | rawcmd |= (0x1 << 13); | |
653 | if (data->blocks > 1) | |
654 | rawcmd |= (0x2 << 11); | |
655 | else | |
656 | rawcmd |= (0x1 << 11); | |
657 | /* Always use dma mode */ | |
658 | sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); | |
659 | ||
660 | if (host->timeout_ns != data->timeout_ns || | |
661 | host->timeout_clks != data->timeout_clks) | |
662 | msdc_set_timeout(host, data->timeout_ns, | |
663 | data->timeout_clks); | |
664 | ||
665 | writel(data->blocks, host->base + SDC_BLK_NUM); | |
666 | } | |
667 | return rawcmd; | |
668 | } | |
669 | ||
670 | static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, | |
671 | struct mmc_command *cmd, struct mmc_data *data) | |
672 | { | |
673 | bool read; | |
674 | ||
675 | WARN_ON(host->data); | |
676 | host->data = data; | |
677 | read = data->flags & MMC_DATA_READ; | |
678 | ||
679 | mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); | |
680 | msdc_dma_setup(host, &host->dma, data); | |
681 | sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); | |
682 | sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); | |
683 | dev_dbg(host->dev, "DMA start\n"); | |
684 | dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", | |
685 | __func__, cmd->opcode, data->blocks, read); | |
686 | } | |
687 | ||
688 | static int msdc_auto_cmd_done(struct msdc_host *host, int events, | |
689 | struct mmc_command *cmd) | |
690 | { | |
691 | u32 *rsp = cmd->resp; | |
692 | ||
693 | rsp[0] = readl(host->base + SDC_ACMD_RESP); | |
694 | ||
695 | if (events & MSDC_INT_ACMDRDY) { | |
696 | cmd->error = 0; | |
697 | } else { | |
698 | msdc_reset_hw(host); | |
699 | if (events & MSDC_INT_ACMDCRCERR) { | |
700 | cmd->error = -EILSEQ; | |
701 | host->error |= REQ_STOP_EIO; | |
702 | } else if (events & MSDC_INT_ACMDTMO) { | |
703 | cmd->error = -ETIMEDOUT; | |
704 | host->error |= REQ_STOP_TMO; | |
705 | } | |
706 | dev_err(host->dev, | |
707 | "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", | |
708 | __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); | |
709 | } | |
710 | return cmd->error; | |
711 | } | |
712 | ||
713 | static void msdc_track_cmd_data(struct msdc_host *host, | |
714 | struct mmc_command *cmd, struct mmc_data *data) | |
715 | { | |
716 | if (host->error) | |
717 | dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", | |
718 | __func__, cmd->opcode, cmd->arg, host->error); | |
719 | } | |
720 | ||
721 | static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) | |
722 | { | |
723 | unsigned long flags; | |
724 | bool ret; | |
725 | ||
726 | ret = cancel_delayed_work(&host->req_timeout); | |
727 | if (!ret) { | |
728 | /* delay work already running */ | |
729 | return; | |
730 | } | |
731 | spin_lock_irqsave(&host->lock, flags); | |
732 | host->mrq = NULL; | |
733 | spin_unlock_irqrestore(&host->lock, flags); | |
734 | ||
735 | msdc_track_cmd_data(host, mrq->cmd, mrq->data); | |
736 | if (mrq->data) | |
737 | msdc_unprepare_data(host, mrq); | |
738 | mmc_request_done(host->mmc, mrq); | |
739 | } | |
740 | ||
741 | /* returns true if command is fully handled; returns false otherwise */ | |
742 | static bool msdc_cmd_done(struct msdc_host *host, int events, | |
743 | struct mmc_request *mrq, struct mmc_command *cmd) | |
744 | { | |
745 | bool done = false; | |
746 | bool sbc_error; | |
747 | unsigned long flags; | |
748 | u32 *rsp = cmd->resp; | |
749 | ||
750 | if (mrq->sbc && cmd == mrq->cmd && | |
751 | (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | |
752 | | MSDC_INT_ACMDTMO))) | |
753 | msdc_auto_cmd_done(host, events, mrq->sbc); | |
754 | ||
755 | sbc_error = mrq->sbc && mrq->sbc->error; | |
756 | ||
757 | if (!sbc_error && !(events & (MSDC_INT_CMDRDY | |
758 | | MSDC_INT_RSPCRCERR | |
759 | | MSDC_INT_CMDTMO))) | |
760 | return done; | |
761 | ||
762 | spin_lock_irqsave(&host->lock, flags); | |
763 | done = !host->cmd; | |
764 | host->cmd = NULL; | |
765 | spin_unlock_irqrestore(&host->lock, flags); | |
766 | ||
767 | if (done) | |
768 | return true; | |
769 | ||
726a9aac | 770 | sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); |
20848903 CJ |
771 | |
772 | if (cmd->flags & MMC_RSP_PRESENT) { | |
773 | if (cmd->flags & MMC_RSP_136) { | |
774 | rsp[0] = readl(host->base + SDC_RESP3); | |
775 | rsp[1] = readl(host->base + SDC_RESP2); | |
776 | rsp[2] = readl(host->base + SDC_RESP1); | |
777 | rsp[3] = readl(host->base + SDC_RESP0); | |
778 | } else { | |
779 | rsp[0] = readl(host->base + SDC_RESP0); | |
780 | } | |
781 | } | |
782 | ||
783 | if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { | |
784 | msdc_reset_hw(host); | |
785 | if (events & MSDC_INT_RSPCRCERR) { | |
786 | cmd->error = -EILSEQ; | |
787 | host->error |= REQ_CMD_EIO; | |
788 | } else if (events & MSDC_INT_CMDTMO) { | |
789 | cmd->error = -ETIMEDOUT; | |
790 | host->error |= REQ_CMD_TMO; | |
791 | } | |
792 | } | |
793 | if (cmd->error) | |
794 | dev_dbg(host->dev, | |
795 | "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", | |
796 | __func__, cmd->opcode, cmd->arg, rsp[0], | |
797 | cmd->error); | |
798 | ||
799 | msdc_cmd_next(host, mrq, cmd); | |
800 | return true; | |
801 | } | |
802 | ||
803 | /* It is the core layer's responsibility to ensure card status | |
804 | * is correct before issue a request. but host design do below | |
805 | * checks recommended. | |
806 | */ | |
807 | static inline bool msdc_cmd_is_ready(struct msdc_host *host, | |
808 | struct mmc_request *mrq, struct mmc_command *cmd) | |
809 | { | |
810 | /* The max busy time we can endure is 20ms */ | |
811 | unsigned long tmo = jiffies + msecs_to_jiffies(20); | |
812 | ||
813 | while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && | |
814 | time_before(jiffies, tmo)) | |
815 | cpu_relax(); | |
816 | if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { | |
817 | dev_err(host->dev, "CMD bus busy detected\n"); | |
818 | host->error |= REQ_CMD_BUSY; | |
819 | msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); | |
820 | return false; | |
821 | } | |
822 | ||
823 | if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { | |
824 | tmo = jiffies + msecs_to_jiffies(20); | |
825 | /* R1B or with data, should check SDCBUSY */ | |
826 | while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && | |
827 | time_before(jiffies, tmo)) | |
828 | cpu_relax(); | |
829 | if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { | |
830 | dev_err(host->dev, "Controller busy detected\n"); | |
831 | host->error |= REQ_CMD_BUSY; | |
832 | msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); | |
833 | return false; | |
834 | } | |
835 | } | |
836 | return true; | |
837 | } | |
838 | ||
839 | static void msdc_start_command(struct msdc_host *host, | |
840 | struct mmc_request *mrq, struct mmc_command *cmd) | |
841 | { | |
842 | u32 rawcmd; | |
843 | ||
844 | WARN_ON(host->cmd); | |
845 | host->cmd = cmd; | |
846 | ||
847 | if (!msdc_cmd_is_ready(host, mrq, cmd)) | |
848 | return; | |
849 | ||
850 | if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || | |
851 | readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { | |
852 | dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); | |
853 | msdc_reset_hw(host); | |
854 | } | |
855 | ||
856 | cmd->error = 0; | |
857 | rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); | |
858 | mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); | |
859 | ||
726a9aac | 860 | sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); |
20848903 CJ |
861 | writel(cmd->arg, host->base + SDC_ARG); |
862 | writel(rawcmd, host->base + SDC_CMD); | |
863 | } | |
864 | ||
865 | static void msdc_cmd_next(struct msdc_host *host, | |
866 | struct mmc_request *mrq, struct mmc_command *cmd) | |
867 | { | |
868 | if (cmd->error || (mrq->sbc && mrq->sbc->error)) | |
869 | msdc_request_done(host, mrq); | |
870 | else if (cmd == mrq->sbc) | |
871 | msdc_start_command(host, mrq, mrq->cmd); | |
872 | else if (!cmd->data) | |
873 | msdc_request_done(host, mrq); | |
874 | else | |
875 | msdc_start_data(host, mrq, cmd, cmd->data); | |
876 | } | |
877 | ||
878 | static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
879 | { | |
880 | struct msdc_host *host = mmc_priv(mmc); | |
881 | ||
882 | host->error = 0; | |
883 | WARN_ON(host->mrq); | |
884 | host->mrq = mrq; | |
885 | ||
886 | if (mrq->data) | |
887 | msdc_prepare_data(host, mrq); | |
888 | ||
889 | /* if SBC is required, we have HW option and SW option. | |
890 | * if HW option is enabled, and SBC does not have "special" flags, | |
891 | * use HW option, otherwise use SW option | |
892 | */ | |
893 | if (mrq->sbc && (!mmc_card_mmc(mmc->card) || | |
894 | (mrq->sbc->arg & 0xFFFF0000))) | |
895 | msdc_start_command(host, mrq, mrq->sbc); | |
896 | else | |
897 | msdc_start_command(host, mrq, mrq->cmd); | |
898 | } | |
899 | ||
900 | static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, | |
901 | bool is_first_req) | |
902 | { | |
903 | struct msdc_host *host = mmc_priv(mmc); | |
904 | struct mmc_data *data = mrq->data; | |
905 | ||
906 | if (!data) | |
907 | return; | |
908 | ||
909 | msdc_prepare_data(host, mrq); | |
910 | data->host_cookie |= MSDC_ASYNC_FLAG; | |
911 | } | |
912 | ||
913 | static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, | |
914 | int err) | |
915 | { | |
916 | struct msdc_host *host = mmc_priv(mmc); | |
917 | struct mmc_data *data; | |
918 | ||
919 | data = mrq->data; | |
920 | if (!data) | |
921 | return; | |
922 | if (data->host_cookie) { | |
923 | data->host_cookie &= ~MSDC_ASYNC_FLAG; | |
924 | msdc_unprepare_data(host, mrq); | |
925 | } | |
926 | } | |
927 | ||
928 | static void msdc_data_xfer_next(struct msdc_host *host, | |
929 | struct mmc_request *mrq, struct mmc_data *data) | |
930 | { | |
931 | if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && | |
6397b7f5 | 932 | !mrq->sbc) |
20848903 CJ |
933 | msdc_start_command(host, mrq, mrq->stop); |
934 | else | |
935 | msdc_request_done(host, mrq); | |
936 | } | |
937 | ||
938 | static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, | |
939 | struct mmc_request *mrq, struct mmc_data *data) | |
940 | { | |
941 | struct mmc_command *stop = data->stop; | |
942 | unsigned long flags; | |
943 | bool done; | |
944 | unsigned int check_data = events & | |
945 | (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO | |
946 | | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR | |
947 | | MSDC_INT_DMA_PROTECT); | |
948 | ||
949 | spin_lock_irqsave(&host->lock, flags); | |
950 | done = !host->data; | |
951 | if (check_data) | |
952 | host->data = NULL; | |
953 | spin_unlock_irqrestore(&host->lock, flags); | |
954 | ||
955 | if (done) | |
956 | return true; | |
957 | ||
958 | if (check_data || (stop && stop->error)) { | |
959 | dev_dbg(host->dev, "DMA status: 0x%8X\n", | |
960 | readl(host->base + MSDC_DMA_CFG)); | |
961 | sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, | |
962 | 1); | |
963 | while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) | |
964 | cpu_relax(); | |
965 | sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); | |
966 | dev_dbg(host->dev, "DMA stop\n"); | |
967 | ||
968 | if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { | |
969 | data->bytes_xfered = data->blocks * data->blksz; | |
970 | } else { | |
2066fd28 | 971 | dev_dbg(host->dev, "interrupt events: %x\n", events); |
20848903 CJ |
972 | msdc_reset_hw(host); |
973 | host->error |= REQ_DAT_ERR; | |
974 | data->bytes_xfered = 0; | |
975 | ||
976 | if (events & MSDC_INT_DATTMO) | |
977 | data->error = -ETIMEDOUT; | |
6397b7f5 CJ |
978 | else if (events & MSDC_INT_DATCRCERR) |
979 | data->error = -EILSEQ; | |
20848903 | 980 | |
2066fd28 | 981 | dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", |
20848903 | 982 | __func__, mrq->cmd->opcode, data->blocks); |
2066fd28 CJ |
983 | dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", |
984 | (int)data->error, data->bytes_xfered); | |
20848903 CJ |
985 | } |
986 | ||
987 | msdc_data_xfer_next(host, mrq, data); | |
988 | done = true; | |
989 | } | |
990 | return done; | |
991 | } | |
992 | ||
993 | static void msdc_set_buswidth(struct msdc_host *host, u32 width) | |
994 | { | |
995 | u32 val = readl(host->base + SDC_CFG); | |
996 | ||
997 | val &= ~SDC_CFG_BUSWIDTH; | |
998 | ||
999 | switch (width) { | |
1000 | default: | |
1001 | case MMC_BUS_WIDTH_1: | |
1002 | val |= (MSDC_BUS_1BITS << 16); | |
1003 | break; | |
1004 | case MMC_BUS_WIDTH_4: | |
1005 | val |= (MSDC_BUS_4BITS << 16); | |
1006 | break; | |
1007 | case MMC_BUS_WIDTH_8: | |
1008 | val |= (MSDC_BUS_8BITS << 16); | |
1009 | break; | |
1010 | } | |
1011 | ||
1012 | writel(val, host->base + SDC_CFG); | |
1013 | dev_dbg(host->dev, "Bus Width = %d", width); | |
1014 | } | |
1015 | ||
1016 | static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) | |
1017 | { | |
1018 | struct msdc_host *host = mmc_priv(mmc); | |
20848903 CJ |
1019 | int ret = 0; |
1020 | ||
1021 | if (!IS_ERR(mmc->supply.vqmmc)) { | |
fac49ce5 NB |
1022 | if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && |
1023 | ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { | |
20848903 CJ |
1024 | dev_err(host->dev, "Unsupported signal voltage!\n"); |
1025 | return -EINVAL; | |
1026 | } | |
1027 | ||
fac49ce5 | 1028 | ret = mmc_regulator_set_vqmmc(mmc, ios); |
20848903 | 1029 | if (ret) { |
fac49ce5 NB |
1030 | dev_dbg(host->dev, "Regulator set error %d (%d)\n", |
1031 | ret, ios->signal_voltage); | |
20848903 CJ |
1032 | } else { |
1033 | /* Apply different pinctrl settings for different signal voltage */ | |
1034 | if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) | |
1035 | pinctrl_select_state(host->pinctrl, host->pins_uhs); | |
1036 | else | |
1037 | pinctrl_select_state(host->pinctrl, host->pins_default); | |
1038 | } | |
1039 | } | |
1040 | return ret; | |
1041 | } | |
1042 | ||
1043 | static int msdc_card_busy(struct mmc_host *mmc) | |
1044 | { | |
1045 | struct msdc_host *host = mmc_priv(mmc); | |
1046 | u32 status = readl(host->base + MSDC_PS); | |
1047 | ||
1048 | /* check if any pin between dat[0:3] is low */ | |
1049 | if (((status >> 16) & 0xf) != 0xf) | |
1050 | return 1; | |
1051 | ||
1052 | return 0; | |
1053 | } | |
1054 | ||
1055 | static void msdc_request_timeout(struct work_struct *work) | |
1056 | { | |
1057 | struct msdc_host *host = container_of(work, struct msdc_host, | |
1058 | req_timeout.work); | |
1059 | ||
1060 | /* simulate HW timeout status */ | |
1061 | dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); | |
1062 | if (host->mrq) { | |
1063 | dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, | |
1064 | host->mrq, host->mrq->cmd->opcode); | |
1065 | if (host->cmd) { | |
1066 | dev_err(host->dev, "%s: aborting cmd=%d\n", | |
1067 | __func__, host->cmd->opcode); | |
1068 | msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, | |
1069 | host->cmd); | |
1070 | } else if (host->data) { | |
1071 | dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", | |
1072 | __func__, host->mrq->cmd->opcode, | |
1073 | host->data->blocks); | |
1074 | msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, | |
1075 | host->data); | |
1076 | } | |
1077 | } | |
1078 | } | |
1079 | ||
1080 | static irqreturn_t msdc_irq(int irq, void *dev_id) | |
1081 | { | |
1082 | struct msdc_host *host = (struct msdc_host *) dev_id; | |
1083 | ||
1084 | while (true) { | |
1085 | unsigned long flags; | |
1086 | struct mmc_request *mrq; | |
1087 | struct mmc_command *cmd; | |
1088 | struct mmc_data *data; | |
1089 | u32 events, event_mask; | |
1090 | ||
1091 | spin_lock_irqsave(&host->lock, flags); | |
1092 | events = readl(host->base + MSDC_INT); | |
1093 | event_mask = readl(host->base + MSDC_INTEN); | |
1094 | /* clear interrupts */ | |
1095 | writel(events & event_mask, host->base + MSDC_INT); | |
1096 | ||
1097 | mrq = host->mrq; | |
1098 | cmd = host->cmd; | |
1099 | data = host->data; | |
1100 | spin_unlock_irqrestore(&host->lock, flags); | |
1101 | ||
1102 | if (!(events & event_mask)) | |
1103 | break; | |
1104 | ||
1105 | if (!mrq) { | |
1106 | dev_err(host->dev, | |
1107 | "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", | |
1108 | __func__, events, event_mask); | |
1109 | WARN_ON(1); | |
1110 | break; | |
1111 | } | |
1112 | ||
1113 | dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); | |
1114 | ||
1115 | if (cmd) | |
1116 | msdc_cmd_done(host, events, mrq, cmd); | |
1117 | else if (data) | |
1118 | msdc_data_xfer_done(host, events, mrq, data); | |
1119 | } | |
1120 | ||
1121 | return IRQ_HANDLED; | |
1122 | } | |
1123 | ||
1124 | static void msdc_init_hw(struct msdc_host *host) | |
1125 | { | |
1126 | u32 val; | |
1127 | ||
1128 | /* Configure to MMC/SD mode, clock free running */ | |
1129 | sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); | |
1130 | ||
1131 | /* Reset */ | |
1132 | msdc_reset_hw(host); | |
1133 | ||
1134 | /* Disable card detection */ | |
1135 | sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); | |
1136 | ||
1137 | /* Disable and clear all interrupts */ | |
1138 | writel(0, host->base + MSDC_INTEN); | |
1139 | val = readl(host->base + MSDC_INT); | |
1140 | writel(val, host->base + MSDC_INT); | |
1141 | ||
1142 | writel(0, host->base + MSDC_PAD_TUNE); | |
1143 | writel(0, host->base + MSDC_IOCON); | |
6397b7f5 CJ |
1144 | sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); |
1145 | writel(0x403c0046, host->base + MSDC_PATCH_BIT); | |
20848903 CJ |
1146 | sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); |
1147 | writel(0xffff0089, host->base + MSDC_PATCH_BIT1); | |
6397b7f5 CJ |
1148 | sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); |
1149 | ||
20848903 CJ |
1150 | /* Configure to enable SDIO mode. |
1151 | * it's must otherwise sdio cmd5 failed | |
1152 | */ | |
1153 | sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); | |
1154 | ||
1155 | /* disable detect SDIO device interrupt function */ | |
1156 | sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); | |
1157 | ||
1158 | /* Configure to default data timeout */ | |
1159 | sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); | |
1160 | ||
1161 | dev_dbg(host->dev, "init hardware done!"); | |
1162 | } | |
1163 | ||
1164 | static void msdc_deinit_hw(struct msdc_host *host) | |
1165 | { | |
1166 | u32 val; | |
1167 | /* Disable and clear all interrupts */ | |
1168 | writel(0, host->base + MSDC_INTEN); | |
1169 | ||
1170 | val = readl(host->base + MSDC_INT); | |
1171 | writel(val, host->base + MSDC_INT); | |
1172 | } | |
1173 | ||
1174 | /* init gpd and bd list in msdc_drv_probe */ | |
1175 | static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) | |
1176 | { | |
1177 | struct mt_gpdma_desc *gpd = dma->gpd; | |
1178 | struct mt_bdma_desc *bd = dma->bd; | |
1179 | int i; | |
1180 | ||
62b0d27a | 1181 | memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); |
20848903 CJ |
1182 | |
1183 | gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ | |
1184 | gpd->ptr = (u32)dma->bd_addr; /* physical address */ | |
62b0d27a CJ |
1185 | /* gpd->next is must set for desc DMA |
1186 | * That's why must alloc 2 gpd structure. | |
1187 | */ | |
1188 | gpd->next = (u32)dma->gpd_addr + sizeof(struct mt_gpdma_desc); | |
20848903 CJ |
1189 | memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); |
1190 | for (i = 0; i < (MAX_BD_NUM - 1); i++) | |
1191 | bd[i].next = (u32)dma->bd_addr + sizeof(*bd) * (i + 1); | |
1192 | } | |
1193 | ||
1194 | static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
1195 | { | |
1196 | struct msdc_host *host = mmc_priv(mmc); | |
1197 | int ret; | |
20848903 | 1198 | |
20848903 CJ |
1199 | msdc_set_buswidth(host, ios->bus_width); |
1200 | ||
1201 | /* Suspend/Resume will do power off/on */ | |
1202 | switch (ios->power_mode) { | |
1203 | case MMC_POWER_UP: | |
1204 | if (!IS_ERR(mmc->supply.vmmc)) { | |
6397b7f5 | 1205 | msdc_init_hw(host); |
20848903 CJ |
1206 | ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, |
1207 | ios->vdd); | |
1208 | if (ret) { | |
1209 | dev_err(host->dev, "Failed to set vmmc power!\n"); | |
567979fb | 1210 | return; |
20848903 CJ |
1211 | } |
1212 | } | |
1213 | break; | |
1214 | case MMC_POWER_ON: | |
1215 | if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { | |
1216 | ret = regulator_enable(mmc->supply.vqmmc); | |
1217 | if (ret) | |
1218 | dev_err(host->dev, "Failed to set vqmmc power!\n"); | |
1219 | else | |
1220 | host->vqmmc_enabled = true; | |
1221 | } | |
1222 | break; | |
1223 | case MMC_POWER_OFF: | |
1224 | if (!IS_ERR(mmc->supply.vmmc)) | |
1225 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); | |
1226 | ||
1227 | if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { | |
1228 | regulator_disable(mmc->supply.vqmmc); | |
1229 | host->vqmmc_enabled = false; | |
1230 | } | |
1231 | break; | |
1232 | default: | |
1233 | break; | |
1234 | } | |
1235 | ||
6e622947 CJ |
1236 | if (host->mclk != ios->clock || host->timing != ios->timing) |
1237 | msdc_set_mclk(host, ios->timing, ios->clock); | |
20848903 CJ |
1238 | } |
1239 | ||
6397b7f5 CJ |
1240 | static u32 test_delay_bit(u32 delay, u32 bit) |
1241 | { | |
1242 | bit %= PAD_DELAY_MAX; | |
1243 | return delay & (1 << bit); | |
1244 | } | |
1245 | ||
1246 | static int get_delay_len(u32 delay, u32 start_bit) | |
1247 | { | |
1248 | int i; | |
1249 | ||
1250 | for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { | |
1251 | if (test_delay_bit(delay, start_bit + i) == 0) | |
1252 | return i; | |
1253 | } | |
1254 | return PAD_DELAY_MAX - start_bit; | |
1255 | } | |
1256 | ||
1257 | static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) | |
1258 | { | |
1259 | int start = 0, len = 0; | |
1260 | int start_final = 0, len_final = 0; | |
1261 | u8 final_phase = 0xff; | |
62d494ca | 1262 | struct msdc_delay_phase delay_phase = { 0, }; |
6397b7f5 CJ |
1263 | |
1264 | if (delay == 0) { | |
1265 | dev_err(host->dev, "phase error: [map:%x]\n", delay); | |
1266 | delay_phase.final_phase = final_phase; | |
1267 | return delay_phase; | |
1268 | } | |
1269 | ||
1270 | while (start < PAD_DELAY_MAX) { | |
1271 | len = get_delay_len(delay, start); | |
1272 | if (len_final < len) { | |
1273 | start_final = start; | |
1274 | len_final = len; | |
1275 | } | |
1276 | start += len ? len : 1; | |
1277 | if (len >= 8 && start_final < 4) | |
1278 | break; | |
1279 | } | |
1280 | ||
1281 | /* The rule is that to find the smallest delay cell */ | |
1282 | if (start_final == 0) | |
1283 | final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; | |
1284 | else | |
1285 | final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; | |
1286 | dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", | |
1287 | delay, len_final, final_phase); | |
1288 | ||
1289 | delay_phase.maxlen = len_final; | |
1290 | delay_phase.start = start_final; | |
1291 | delay_phase.final_phase = final_phase; | |
1292 | return delay_phase; | |
1293 | } | |
1294 | ||
1295 | static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) | |
1296 | { | |
1297 | struct msdc_host *host = mmc_priv(mmc); | |
1298 | u32 rise_delay = 0, fall_delay = 0; | |
1299 | struct msdc_delay_phase final_rise_delay, final_fall_delay; | |
1300 | u8 final_delay, final_maxlen; | |
1301 | int cmd_err; | |
1302 | int i; | |
1303 | ||
1304 | sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); | |
1305 | for (i = 0 ; i < PAD_DELAY_MAX; i++) { | |
1306 | sdr_set_field(host->base + MSDC_PAD_TUNE, | |
1307 | MSDC_PAD_TUNE_CMDRDLY, i); | |
1308 | mmc_send_tuning(mmc, opcode, &cmd_err); | |
1309 | if (!cmd_err) | |
1310 | rise_delay |= (1 << i); | |
1311 | } | |
1312 | ||
1313 | sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); | |
1314 | for (i = 0; i < PAD_DELAY_MAX; i++) { | |
1315 | sdr_set_field(host->base + MSDC_PAD_TUNE, | |
1316 | MSDC_PAD_TUNE_CMDRDLY, i); | |
1317 | mmc_send_tuning(mmc, opcode, &cmd_err); | |
1318 | if (!cmd_err) | |
1319 | fall_delay |= (1 << i); | |
1320 | } | |
1321 | ||
1322 | final_rise_delay = get_best_delay(host, rise_delay); | |
1323 | final_fall_delay = get_best_delay(host, fall_delay); | |
1324 | ||
1325 | final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); | |
1326 | if (final_maxlen == final_rise_delay.maxlen) { | |
1327 | sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); | |
1328 | sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY, | |
1329 | final_rise_delay.final_phase); | |
1330 | final_delay = final_rise_delay.final_phase; | |
1331 | } else { | |
1332 | sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); | |
1333 | sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY, | |
1334 | final_fall_delay.final_phase); | |
1335 | final_delay = final_fall_delay.final_phase; | |
1336 | } | |
1337 | ||
1338 | return final_delay == 0xff ? -EIO : 0; | |
1339 | } | |
1340 | ||
1341 | static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) | |
1342 | { | |
1343 | struct msdc_host *host = mmc_priv(mmc); | |
1344 | u32 rise_delay = 0, fall_delay = 0; | |
1345 | struct msdc_delay_phase final_rise_delay, final_fall_delay; | |
1346 | u8 final_delay, final_maxlen; | |
1347 | int i, ret; | |
1348 | ||
1349 | sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); | |
1350 | sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); | |
1351 | for (i = 0 ; i < PAD_DELAY_MAX; i++) { | |
1352 | sdr_set_field(host->base + MSDC_PAD_TUNE, | |
1353 | MSDC_PAD_TUNE_DATRRDLY, i); | |
1354 | ret = mmc_send_tuning(mmc, opcode, NULL); | |
1355 | if (!ret) | |
1356 | rise_delay |= (1 << i); | |
1357 | } | |
1358 | ||
1359 | sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); | |
1360 | sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); | |
1361 | for (i = 0; i < PAD_DELAY_MAX; i++) { | |
1362 | sdr_set_field(host->base + MSDC_PAD_TUNE, | |
1363 | MSDC_PAD_TUNE_DATRRDLY, i); | |
1364 | ret = mmc_send_tuning(mmc, opcode, NULL); | |
1365 | if (!ret) | |
1366 | fall_delay |= (1 << i); | |
1367 | } | |
1368 | ||
1369 | final_rise_delay = get_best_delay(host, rise_delay); | |
1370 | final_fall_delay = get_best_delay(host, fall_delay); | |
1371 | ||
1372 | final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); | |
1373 | /* Rising edge is more stable, prefer to use it */ | |
1374 | if (final_rise_delay.maxlen >= 10) | |
1375 | final_maxlen = final_rise_delay.maxlen; | |
1376 | if (final_maxlen == final_rise_delay.maxlen) { | |
1377 | sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); | |
1378 | sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); | |
1379 | sdr_set_field(host->base + MSDC_PAD_TUNE, | |
1380 | MSDC_PAD_TUNE_DATRRDLY, | |
1381 | final_rise_delay.final_phase); | |
1382 | final_delay = final_rise_delay.final_phase; | |
1383 | } else { | |
1384 | sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); | |
1385 | sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); | |
1386 | sdr_set_field(host->base + MSDC_PAD_TUNE, | |
1387 | MSDC_PAD_TUNE_DATRRDLY, | |
1388 | final_fall_delay.final_phase); | |
1389 | final_delay = final_fall_delay.final_phase; | |
1390 | } | |
1391 | ||
1392 | return final_delay == 0xff ? -EIO : 0; | |
1393 | } | |
1394 | ||
1395 | static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) | |
1396 | { | |
1397 | struct msdc_host *host = mmc_priv(mmc); | |
1398 | int ret; | |
1399 | ||
6397b7f5 CJ |
1400 | ret = msdc_tune_response(mmc, opcode); |
1401 | if (ret == -EIO) { | |
1402 | dev_err(host->dev, "Tune response fail!\n"); | |
567979fb | 1403 | return ret; |
6397b7f5 CJ |
1404 | } |
1405 | ret = msdc_tune_data(mmc, opcode); | |
1406 | if (ret == -EIO) | |
1407 | dev_err(host->dev, "Tune data fail!\n"); | |
1408 | ||
6397b7f5 CJ |
1409 | return ret; |
1410 | } | |
1411 | ||
1412 | static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) | |
1413 | { | |
1414 | struct msdc_host *host = mmc_priv(mmc); | |
1415 | ||
1416 | writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); | |
1417 | return 0; | |
1418 | } | |
1419 | ||
c9b5061e CJ |
1420 | static void msdc_hw_reset(struct mmc_host *mmc) |
1421 | { | |
1422 | struct msdc_host *host = mmc_priv(mmc); | |
1423 | ||
1424 | sdr_set_bits(host->base + EMMC_IOCON, 1); | |
1425 | udelay(10); /* 10us is enough */ | |
1426 | sdr_clr_bits(host->base + EMMC_IOCON, 1); | |
1427 | } | |
1428 | ||
20848903 CJ |
1429 | static struct mmc_host_ops mt_msdc_ops = { |
1430 | .post_req = msdc_post_req, | |
1431 | .pre_req = msdc_pre_req, | |
1432 | .request = msdc_ops_request, | |
1433 | .set_ios = msdc_ops_set_ios, | |
8d53e412 | 1434 | .get_ro = mmc_gpio_get_ro, |
20848903 CJ |
1435 | .start_signal_voltage_switch = msdc_ops_switch_volt, |
1436 | .card_busy = msdc_card_busy, | |
6397b7f5 CJ |
1437 | .execute_tuning = msdc_execute_tuning, |
1438 | .prepare_hs400_tuning = msdc_prepare_hs400_tuning, | |
c9b5061e | 1439 | .hw_reset = msdc_hw_reset, |
20848903 CJ |
1440 | }; |
1441 | ||
1442 | static int msdc_drv_probe(struct platform_device *pdev) | |
1443 | { | |
1444 | struct mmc_host *mmc; | |
1445 | struct msdc_host *host; | |
1446 | struct resource *res; | |
1447 | int ret; | |
1448 | ||
1449 | if (!pdev->dev.of_node) { | |
1450 | dev_err(&pdev->dev, "No DT found\n"); | |
1451 | return -EINVAL; | |
1452 | } | |
1453 | /* Allocate MMC host for this device */ | |
1454 | mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); | |
1455 | if (!mmc) | |
1456 | return -ENOMEM; | |
1457 | ||
1458 | host = mmc_priv(mmc); | |
1459 | ret = mmc_of_parse(mmc); | |
1460 | if (ret) | |
1461 | goto host_free; | |
1462 | ||
1463 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1464 | host->base = devm_ioremap_resource(&pdev->dev, res); | |
1465 | if (IS_ERR(host->base)) { | |
1466 | ret = PTR_ERR(host->base); | |
1467 | goto host_free; | |
1468 | } | |
1469 | ||
1470 | ret = mmc_regulator_get_supply(mmc); | |
1471 | if (ret == -EPROBE_DEFER) | |
1472 | goto host_free; | |
1473 | ||
1474 | host->src_clk = devm_clk_get(&pdev->dev, "source"); | |
1475 | if (IS_ERR(host->src_clk)) { | |
1476 | ret = PTR_ERR(host->src_clk); | |
1477 | goto host_free; | |
1478 | } | |
1479 | ||
1480 | host->h_clk = devm_clk_get(&pdev->dev, "hclk"); | |
1481 | if (IS_ERR(host->h_clk)) { | |
1482 | ret = PTR_ERR(host->h_clk); | |
1483 | goto host_free; | |
1484 | } | |
1485 | ||
1486 | host->irq = platform_get_irq(pdev, 0); | |
1487 | if (host->irq < 0) { | |
1488 | ret = -EINVAL; | |
1489 | goto host_free; | |
1490 | } | |
1491 | ||
1492 | host->pinctrl = devm_pinctrl_get(&pdev->dev); | |
1493 | if (IS_ERR(host->pinctrl)) { | |
1494 | ret = PTR_ERR(host->pinctrl); | |
1495 | dev_err(&pdev->dev, "Cannot find pinctrl!\n"); | |
1496 | goto host_free; | |
1497 | } | |
1498 | ||
1499 | host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); | |
1500 | if (IS_ERR(host->pins_default)) { | |
1501 | ret = PTR_ERR(host->pins_default); | |
1502 | dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); | |
1503 | goto host_free; | |
1504 | } | |
1505 | ||
1506 | host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); | |
1507 | if (IS_ERR(host->pins_uhs)) { | |
1508 | ret = PTR_ERR(host->pins_uhs); | |
1509 | dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); | |
1510 | goto host_free; | |
1511 | } | |
1512 | ||
6397b7f5 CJ |
1513 | if (!of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", |
1514 | &host->hs400_ds_delay)) | |
1515 | dev_dbg(&pdev->dev, "hs400-ds-delay: %x\n", | |
1516 | host->hs400_ds_delay); | |
1517 | ||
20848903 CJ |
1518 | host->dev = &pdev->dev; |
1519 | host->mmc = mmc; | |
1520 | host->src_clk_freq = clk_get_rate(host->src_clk); | |
1521 | /* Set host parameters to mmc */ | |
1522 | mmc->ops = &mt_msdc_ops; | |
1523 | mmc->f_min = host->src_clk_freq / (4 * 255); | |
1524 | ||
1525 | mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; | |
1526 | /* MMC core transfer sizes tunable parameters */ | |
1527 | mmc->max_segs = MAX_BD_NUM; | |
1528 | mmc->max_seg_size = BDMA_DESC_BUFLEN; | |
1529 | mmc->max_blk_size = 2048; | |
1530 | mmc->max_req_size = 512 * 1024; | |
1531 | mmc->max_blk_count = mmc->max_req_size / 512; | |
1532 | host->dma_mask = DMA_BIT_MASK(32); | |
1533 | mmc_dev(mmc)->dma_mask = &host->dma_mask; | |
1534 | ||
1535 | host->timeout_clks = 3 * 1048576; | |
1536 | host->dma.gpd = dma_alloc_coherent(&pdev->dev, | |
62b0d27a | 1537 | 2 * sizeof(struct mt_gpdma_desc), |
20848903 CJ |
1538 | &host->dma.gpd_addr, GFP_KERNEL); |
1539 | host->dma.bd = dma_alloc_coherent(&pdev->dev, | |
1540 | MAX_BD_NUM * sizeof(struct mt_bdma_desc), | |
1541 | &host->dma.bd_addr, GFP_KERNEL); | |
1542 | if (!host->dma.gpd || !host->dma.bd) { | |
1543 | ret = -ENOMEM; | |
1544 | goto release_mem; | |
1545 | } | |
1546 | msdc_init_gpd_bd(host, &host->dma); | |
1547 | INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); | |
1548 | spin_lock_init(&host->lock); | |
1549 | ||
1550 | platform_set_drvdata(pdev, mmc); | |
1551 | msdc_ungate_clock(host); | |
1552 | msdc_init_hw(host); | |
1553 | ||
1554 | ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, | |
1555 | IRQF_TRIGGER_LOW | IRQF_ONESHOT, pdev->name, host); | |
1556 | if (ret) | |
1557 | goto release; | |
1558 | ||
4b8a43e9 CJ |
1559 | pm_runtime_set_active(host->dev); |
1560 | pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); | |
1561 | pm_runtime_use_autosuspend(host->dev); | |
1562 | pm_runtime_enable(host->dev); | |
20848903 | 1563 | ret = mmc_add_host(mmc); |
4b8a43e9 | 1564 | |
20848903 | 1565 | if (ret) |
4b8a43e9 | 1566 | goto end; |
20848903 CJ |
1567 | |
1568 | return 0; | |
4b8a43e9 CJ |
1569 | end: |
1570 | pm_runtime_disable(host->dev); | |
20848903 CJ |
1571 | release: |
1572 | platform_set_drvdata(pdev, NULL); | |
1573 | msdc_deinit_hw(host); | |
1574 | msdc_gate_clock(host); | |
1575 | release_mem: | |
1576 | if (host->dma.gpd) | |
1577 | dma_free_coherent(&pdev->dev, | |
62b0d27a | 1578 | 2 * sizeof(struct mt_gpdma_desc), |
20848903 CJ |
1579 | host->dma.gpd, host->dma.gpd_addr); |
1580 | if (host->dma.bd) | |
1581 | dma_free_coherent(&pdev->dev, | |
1582 | MAX_BD_NUM * sizeof(struct mt_bdma_desc), | |
1583 | host->dma.bd, host->dma.bd_addr); | |
1584 | host_free: | |
1585 | mmc_free_host(mmc); | |
1586 | ||
1587 | return ret; | |
1588 | } | |
1589 | ||
1590 | static int msdc_drv_remove(struct platform_device *pdev) | |
1591 | { | |
1592 | struct mmc_host *mmc; | |
1593 | struct msdc_host *host; | |
1594 | ||
1595 | mmc = platform_get_drvdata(pdev); | |
1596 | host = mmc_priv(mmc); | |
1597 | ||
4b8a43e9 CJ |
1598 | pm_runtime_get_sync(host->dev); |
1599 | ||
20848903 CJ |
1600 | platform_set_drvdata(pdev, NULL); |
1601 | mmc_remove_host(host->mmc); | |
1602 | msdc_deinit_hw(host); | |
1603 | msdc_gate_clock(host); | |
1604 | ||
4b8a43e9 CJ |
1605 | pm_runtime_disable(host->dev); |
1606 | pm_runtime_put_noidle(host->dev); | |
20848903 CJ |
1607 | dma_free_coherent(&pdev->dev, |
1608 | sizeof(struct mt_gpdma_desc), | |
1609 | host->dma.gpd, host->dma.gpd_addr); | |
1610 | dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), | |
1611 | host->dma.bd, host->dma.bd_addr); | |
1612 | ||
1613 | mmc_free_host(host->mmc); | |
1614 | ||
1615 | return 0; | |
1616 | } | |
1617 | ||
4b8a43e9 CJ |
1618 | #ifdef CONFIG_PM |
1619 | static void msdc_save_reg(struct msdc_host *host) | |
1620 | { | |
1621 | host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); | |
1622 | host->save_para.iocon = readl(host->base + MSDC_IOCON); | |
1623 | host->save_para.sdc_cfg = readl(host->base + SDC_CFG); | |
1624 | host->save_para.pad_tune = readl(host->base + MSDC_PAD_TUNE); | |
1625 | host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); | |
1626 | host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); | |
6397b7f5 CJ |
1627 | host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); |
1628 | host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); | |
4b8a43e9 CJ |
1629 | } |
1630 | ||
1631 | static void msdc_restore_reg(struct msdc_host *host) | |
1632 | { | |
1633 | writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); | |
1634 | writel(host->save_para.iocon, host->base + MSDC_IOCON); | |
1635 | writel(host->save_para.sdc_cfg, host->base + SDC_CFG); | |
1636 | writel(host->save_para.pad_tune, host->base + MSDC_PAD_TUNE); | |
1637 | writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); | |
1638 | writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); | |
6397b7f5 CJ |
1639 | writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); |
1640 | writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); | |
4b8a43e9 CJ |
1641 | } |
1642 | ||
1643 | static int msdc_runtime_suspend(struct device *dev) | |
1644 | { | |
1645 | struct mmc_host *mmc = dev_get_drvdata(dev); | |
1646 | struct msdc_host *host = mmc_priv(mmc); | |
1647 | ||
1648 | msdc_save_reg(host); | |
1649 | msdc_gate_clock(host); | |
1650 | return 0; | |
1651 | } | |
1652 | ||
1653 | static int msdc_runtime_resume(struct device *dev) | |
1654 | { | |
1655 | struct mmc_host *mmc = dev_get_drvdata(dev); | |
1656 | struct msdc_host *host = mmc_priv(mmc); | |
1657 | ||
1658 | msdc_ungate_clock(host); | |
1659 | msdc_restore_reg(host); | |
1660 | return 0; | |
1661 | } | |
1662 | #endif | |
1663 | ||
1664 | static const struct dev_pm_ops msdc_dev_pm_ops = { | |
1665 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, | |
1666 | pm_runtime_force_resume) | |
1667 | SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) | |
1668 | }; | |
1669 | ||
20848903 CJ |
1670 | static const struct of_device_id msdc_of_ids[] = { |
1671 | { .compatible = "mediatek,mt8135-mmc", }, | |
1672 | {} | |
1673 | }; | |
1674 | ||
1675 | static struct platform_driver mt_msdc_driver = { | |
1676 | .probe = msdc_drv_probe, | |
1677 | .remove = msdc_drv_remove, | |
1678 | .driver = { | |
1679 | .name = "mtk-msdc", | |
1680 | .of_match_table = msdc_of_ids, | |
4b8a43e9 | 1681 | .pm = &msdc_dev_pm_ops, |
20848903 CJ |
1682 | }, |
1683 | }; | |
1684 | ||
1685 | module_platform_driver(mt_msdc_driver); | |
1686 | MODULE_LICENSE("GPL v2"); | |
1687 | MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); |