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mmc: mediatek: Preinitialize delay_phase in get_best_delay()
[deliverable/linux.git] / drivers / mmc / host / mtk-sd.c
CommitLineData
20848903
CJ		 1/*
2 * Copyright (c) 2014-2015 MediaTek Inc.
3 * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/module.h>
16#include <linux/clk.h>
17#include <linux/delay.h>
18#include <linux/dma-mapping.h>
19#include <linux/ioport.h>
20#include <linux/irq.h>
21#include <linux/of_address.h>
22#include <linux/of_irq.h>
23#include <linux/of_gpio.h>
24#include <linux/pinctrl/consumer.h>
25#include <linux/platform_device.h>
4b8a43e9
CJ		 26#include <linux/pm.h>
27#include <linux/pm_runtime.h>
20848903 28#include <linux/regulator/consumer.h>
6397b7f5 29#include <linux/slab.h>
20848903
CJ		 30#include <linux/spinlock.h>
31
32#include <linux/mmc/card.h>
33#include <linux/mmc/core.h>
34#include <linux/mmc/host.h>
35#include <linux/mmc/mmc.h>
36#include <linux/mmc/sd.h>
37#include <linux/mmc/sdio.h>
38
39#define MAX_BD_NUM 1024
40
41/*--------------------------------------------------------------------------*/
42/* Common Definition */
43/*--------------------------------------------------------------------------*/
44#define MSDC_BUS_1BITS 0x0
45#define MSDC_BUS_4BITS 0x1
46#define MSDC_BUS_8BITS 0x2
47
48#define MSDC_BURST_64B 0x6
49
50/*--------------------------------------------------------------------------*/
51/* Register Offset */
52/*--------------------------------------------------------------------------*/
53#define MSDC_CFG 0x0
54#define MSDC_IOCON 0x04
55#define MSDC_PS 0x08
56#define MSDC_INT 0x0c
57#define MSDC_INTEN 0x10
58#define MSDC_FIFOCS 0x14
59#define SDC_CFG 0x30
60#define SDC_CMD 0x34
61#define SDC_ARG 0x38
62#define SDC_STS 0x3c
63#define SDC_RESP0 0x40
64#define SDC_RESP1 0x44
65#define SDC_RESP2 0x48
66#define SDC_RESP3 0x4c
67#define SDC_BLK_NUM 0x50
c9b5061e 68#define EMMC_IOCON 0x7c
20848903
CJ		 69#define SDC_ACMD_RESP 0x80
70#define MSDC_DMA_SA 0x90
71#define MSDC_DMA_CTRL 0x98
72#define MSDC_DMA_CFG 0x9c
73#define MSDC_PATCH_BIT 0xb0
74#define MSDC_PATCH_BIT1 0xb4
75#define MSDC_PAD_TUNE 0xec
6397b7f5
CJ		 76#define PAD_DS_TUNE 0x188
77#define EMMC50_CFG0 0x208
20848903
CJ		 78
79/*--------------------------------------------------------------------------*/
80/* Register Mask */
81/*--------------------------------------------------------------------------*/
82
83/* MSDC_CFG mask */
84#define MSDC_CFG_MODE (0x1 << 0) /* RW */
85#define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
86#define MSDC_CFG_RST (0x1 << 2) /* RW */
87#define MSDC_CFG_PIO (0x1 << 3) /* RW */
88#define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
89#define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
90#define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
91#define MSDC_CFG_CKSTB (0x1 << 7) /* R */
92#define MSDC_CFG_CKDIV (0xff << 8) /* RW */
93#define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
6397b7f5 94#define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */
20848903
CJ		 95
96/* MSDC_IOCON mask */
97#define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
98#define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
99#define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
100#define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
101#define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
102#define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
103#define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */
104#define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
105#define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
106#define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
107#define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
108#define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
109#define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
110#define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
111#define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
112#define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
113
114/* MSDC_PS mask */
115#define MSDC_PS_CDEN (0x1 << 0) /* RW */
116#define MSDC_PS_CDSTS (0x1 << 1) /* R */
117#define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
118#define MSDC_PS_DAT (0xff << 16) /* R */
119#define MSDC_PS_CMD (0x1 << 24) /* R */
120#define MSDC_PS_WP (0x1 << 31) /* R */
121
122/* MSDC_INT mask */
123#define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
124#define MSDC_INT_CDSC (0x1 << 1) /* W1C */
125#define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
126#define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
127#define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
128#define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
129#define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
130#define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
131#define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
132#define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
133#define MSDC_INT_CSTA (0x1 << 11) /* R */
134#define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
135#define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
136#define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
137#define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
138#define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
139#define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */
140#define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */
141#define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */
142
143/* MSDC_INTEN mask */
144#define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
145#define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
146#define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
147#define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
148#define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
149#define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
150#define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
151#define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
152#define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
153#define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
154#define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
155#define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
156#define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
157#define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
158#define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
159#define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
160#define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */
161#define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */
162#define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */
163
164/* MSDC_FIFOCS mask */
165#define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
166#define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
167#define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */
168
169/* SDC_CFG mask */
170#define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
171#define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
172#define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
173#define SDC_CFG_SDIO (0x1 << 19) /* RW */
174#define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
175#define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
176#define SDC_CFG_DTOC (0xff << 24) /* RW */
177
178/* SDC_STS mask */
179#define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
180#define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
181#define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
182
183/* MSDC_DMA_CTRL mask */
184#define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
185#define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
186#define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
187#define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
188#define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
189#define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
190
191/* MSDC_DMA_CFG mask */
192#define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
193#define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
194#define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */
195#define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */
196#define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */
197
198/* MSDC_PATCH_BIT mask */
199#define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
200#define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7)
201#define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10)
202#define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
203#define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
204#define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
205#define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
206#define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
207#define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
208#define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
209#define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
210#define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
211
6397b7f5
CJ		 212#define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */
213#define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */
214
215#define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */
216#define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */
217#define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */
218
219#define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */
220#define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */
221#define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */
222
20848903
CJ		 223#define REQ_CMD_EIO (0x1 << 0)
224#define REQ_CMD_TMO (0x1 << 1)
225#define REQ_DAT_ERR (0x1 << 2)
226#define REQ_STOP_EIO (0x1 << 3)
227#define REQ_STOP_TMO (0x1 << 4)
228#define REQ_CMD_BUSY (0x1 << 5)
229
230#define MSDC_PREPARE_FLAG (0x1 << 0)
231#define MSDC_ASYNC_FLAG (0x1 << 1)
232#define MSDC_MMAP_FLAG (0x1 << 2)
233
4b8a43e9 234#define MTK_MMC_AUTOSUSPEND_DELAY 50
20848903
CJ		 235#define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */
236#define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */
237
6397b7f5 238#define PAD_DELAY_MAX 32 /* PAD delay cells */
20848903
CJ		 239/*--------------------------------------------------------------------------*/
240/* Descriptor Structure */
241/*--------------------------------------------------------------------------*/
242struct mt_gpdma_desc {
243 u32 gpd_info;
244#define GPDMA_DESC_HWO (0x1 << 0)
245#define GPDMA_DESC_BDP (0x1 << 1)
246#define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
247#define GPDMA_DESC_INT (0x1 << 16)
248 u32 next;
249 u32 ptr;
250 u32 gpd_data_len;
251#define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
252#define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */
253 u32 arg;
254 u32 blknum;
255 u32 cmd;
256};
257
258struct mt_bdma_desc {
259 u32 bd_info;
260#define BDMA_DESC_EOL (0x1 << 0)
261#define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
262#define BDMA_DESC_BLKPAD (0x1 << 17)
263#define BDMA_DESC_DWPAD (0x1 << 18)
264 u32 next;
265 u32 ptr;
266 u32 bd_data_len;
267#define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
268};
269
270struct msdc_dma {
271 struct scatterlist *sg; /* I/O scatter list */
272 struct mt_gpdma_desc *gpd; /* pointer to gpd array */
273 struct mt_bdma_desc *bd; /* pointer to bd array */
274 dma_addr_t gpd_addr; /* the physical address of gpd array */
275 dma_addr_t bd_addr; /* the physical address of bd array */
276};
277
4b8a43e9
CJ		 278struct msdc_save_para {
279 u32 msdc_cfg;
280 u32 iocon;
281 u32 sdc_cfg;
282 u32 pad_tune;
283 u32 patch_bit0;
284 u32 patch_bit1;
6397b7f5
CJ		 285 u32 pad_ds_tune;
286 u32 emmc50_cfg0;
287};
288
289struct msdc_delay_phase {
290 u8 maxlen;
291 u8 start;
292 u8 final_phase;
4b8a43e9
CJ		 293};
294
20848903
CJ		 295struct msdc_host {
296 struct device *dev;
297 struct mmc_host *mmc; /* mmc structure */
298 int cmd_rsp;
299
300 spinlock_t lock;
301 struct mmc_request *mrq;
302 struct mmc_command *cmd;
303 struct mmc_data *data;
304 int error;
305
306 void __iomem *base; /* host base address */
307
308 struct msdc_dma dma; /* dma channel */
309 u64 dma_mask;
310
311 u32 timeout_ns; /* data timeout ns */
312 u32 timeout_clks; /* data timeout clks */
313
314 struct pinctrl *pinctrl;
315 struct pinctrl_state *pins_default;
316 struct pinctrl_state *pins_uhs;
317 struct delayed_work req_timeout;
318 int irq; /* host interrupt */
319
320 struct clk *src_clk; /* msdc source clock */
321 struct clk *h_clk; /* msdc h_clk */
322 u32 mclk; /* mmc subsystem clock frequency */
323 u32 src_clk_freq; /* source clock frequency */
324 u32 sclk; /* SD/MS bus clock frequency */
6e622947 325 unsigned char timing;
20848903 326 bool vqmmc_enabled;
6397b7f5 327 u32 hs400_ds_delay;
4b8a43e9 328 struct msdc_save_para save_para; /* used when gate HCLK */
20848903
CJ		 329};
330
331static void sdr_set_bits(void __iomem *reg, u32 bs)
332{
333 u32 val = readl(reg);
334
335 val |= bs;
336 writel(val, reg);
337}
338
339static void sdr_clr_bits(void __iomem *reg, u32 bs)
340{
341 u32 val = readl(reg);
342
343 val &= ~bs;
344 writel(val, reg);
345}
346
347static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
348{
349 unsigned int tv = readl(reg);
350
351 tv &= ~field;
352 tv |= ((val) << (ffs((unsigned int)field) - 1));
353 writel(tv, reg);
354}
355
356static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
357{
358 unsigned int tv = readl(reg);
359
360 *val = ((tv & field) >> (ffs((unsigned int)field) - 1));
361}
362
363static void msdc_reset_hw(struct msdc_host *host)
364{
365 u32 val;
366
367 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
368 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST)
369 cpu_relax();
370
371 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
372 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR)
373 cpu_relax();
374
375 val = readl(host->base + MSDC_INT);
376 writel(val, host->base + MSDC_INT);
377}
378
379static void msdc_cmd_next(struct msdc_host *host,
380 struct mmc_request *mrq, struct mmc_command *cmd);
381
726a9aac
CJ		 382static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
383 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
384 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
385static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
20848903
CJ		 386 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
387 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
388
389static u8 msdc_dma_calcs(u8 *buf, u32 len)
390{
391 u32 i, sum = 0;
392
393 for (i = 0; i < len; i++)
394 sum += buf[i];
395 return 0xff - (u8) sum;
396}
397
398static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
399 struct mmc_data *data)
400{
401 unsigned int j, dma_len;
402 dma_addr_t dma_address;
403 u32 dma_ctrl;
404 struct scatterlist *sg;
405 struct mt_gpdma_desc *gpd;
406 struct mt_bdma_desc *bd;
407
408 sg = data->sg;
409
410 gpd = dma->gpd;
411 bd = dma->bd;
412
413 /* modify gpd */
414 gpd->gpd_info |= GPDMA_DESC_HWO;
415 gpd->gpd_info |= GPDMA_DESC_BDP;
416 /* need to clear first. use these bits to calc checksum */
417 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
418 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
419
420 /* modify bd */
421 for_each_sg(data->sg, sg, data->sg_count, j) {
422 dma_address = sg_dma_address(sg);
423 dma_len = sg_dma_len(sg);
424
425 /* init bd */
426 bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
427 bd[j].bd_info &= ~BDMA_DESC_DWPAD;
428 bd[j].ptr = (u32)dma_address;
429 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
430 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
431
432 if (j == data->sg_count - 1) /* the last bd */
433 bd[j].bd_info |= BDMA_DESC_EOL;
434 else
435 bd[j].bd_info &= ~BDMA_DESC_EOL;
436
437 /* checksume need to clear first */
438 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
439 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
440 }
441
442 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
443 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
444 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
445 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8);
446 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
447 writel((u32)dma->gpd_addr, host->base + MSDC_DMA_SA);
448}
449
450static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq)
451{
452 struct mmc_data *data = mrq->data;
453
454 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
455 bool read = (data->flags & MMC_DATA_READ) != 0;
456
457 data->host_cookie |= MSDC_PREPARE_FLAG;
458 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
459 read ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
460 }
461}
462
463static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq)
464{
465 struct mmc_data *data = mrq->data;
466
467 if (data->host_cookie & MSDC_ASYNC_FLAG)
468 return;
469
470 if (data->host_cookie & MSDC_PREPARE_FLAG) {
471 bool read = (data->flags & MMC_DATA_READ) != 0;
472
473 dma_unmap_sg(host->dev, data->sg, data->sg_len,
474 read ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
475 data->host_cookie &= ~MSDC_PREPARE_FLAG;
476 }
477}
478
479/* clock control primitives */
480static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
481{
482 u32 timeout, clk_ns;
483 u32 mode = 0;
484
485 host->timeout_ns = ns;
486 host->timeout_clks = clks;
487 if (host->sclk == 0) {
488 timeout = 0;
489 } else {
490 clk_ns = 1000000000UL / host->sclk;
491 timeout = (ns + clk_ns - 1) / clk_ns + clks;
492 /* in 1048576 sclk cycle unit */
493 timeout = (timeout + (0x1 << 20) - 1) >> 20;
494 sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode);
495 /*DDR mode will double the clk cycles for data timeout */
496 timeout = mode >= 2 ? timeout * 2 : timeout;
497 timeout = timeout > 1 ? timeout - 1 : 0;
498 timeout = timeout > 255 ? 255 : timeout;
499 }
500 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout);
501}
502
503static void msdc_gate_clock(struct msdc_host *host)
504{
505 clk_disable_unprepare(host->src_clk);
506 clk_disable_unprepare(host->h_clk);
507}
508
509static void msdc_ungate_clock(struct msdc_host *host)
510{
511 clk_prepare_enable(host->h_clk);
512 clk_prepare_enable(host->src_clk);
513 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
514 cpu_relax();
515}
516
6e622947 517static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
20848903
CJ		 518{
519 u32 mode;
520 u32 flags;
521 u32 div;
522 u32 sclk;
523
524 if (!hz) {
525 dev_dbg(host->dev, "set mclk to 0\n");
526 host->mclk = 0;
527 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
528 return;
529 }
530
531 flags = readl(host->base + MSDC_INTEN);
532 sdr_clr_bits(host->base + MSDC_INTEN, flags);
6397b7f5 533 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
6e622947 534 if (timing == MMC_TIMING_UHS_DDR50 ||
6397b7f5
CJ		 535 timing == MMC_TIMING_MMC_DDR52 ||
536 timing == MMC_TIMING_MMC_HS400) {
537 if (timing == MMC_TIMING_MMC_HS400)
538 mode = 0x3;
539 else
540 mode = 0x2; /* ddr mode and use divisor */
541
20848903
CJ		 542 if (hz >= (host->src_clk_freq >> 2)) {
543 div = 0; /* mean div = 1/4 */
544 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
545 } else {
546 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
547 sclk = (host->src_clk_freq >> 2) / div;
548 div = (div >> 1);
549 }
6397b7f5
CJ		 550
551 if (timing == MMC_TIMING_MMC_HS400 &&
552 hz >= (host->src_clk_freq >> 1)) {
553 sdr_set_bits(host->base + MSDC_CFG,
554 MSDC_CFG_HS400_CK_MODE);
555 sclk = host->src_clk_freq >> 1;
556 div = 0; /* div is ignore when bit18 is set */
557 }
20848903
CJ		 558 } else if (hz >= host->src_clk_freq) {
559 mode = 0x1; /* no divisor */
560 div = 0;
561 sclk = host->src_clk_freq;
562 } else {
563 mode = 0x0; /* use divisor */
564 if (hz >= (host->src_clk_freq >> 1)) {
565 div = 0; /* mean div = 1/2 */
566 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
567 } else {
568 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
569 sclk = (host->src_clk_freq >> 2) / div;
570 }
571 }
572 sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
573 (mode << 8) | (div % 0xff));
574 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
575 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
576 cpu_relax();
577 host->sclk = sclk;
578 host->mclk = hz;
6e622947 579 host->timing = timing;
20848903
CJ		 580 /* need because clk changed. */
581 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
582 sdr_set_bits(host->base + MSDC_INTEN, flags);
583
6e622947 584 dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->sclk, timing);
20848903
CJ		 585}
586
587static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
588 struct mmc_request *mrq, struct mmc_command *cmd)
589{
590 u32 resp;
591
592 switch (mmc_resp_type(cmd)) {
593 /* Actually, R1, R5, R6, R7 are the same */
594 case MMC_RSP_R1:
595 resp = 0x1;
596 break;
597 case MMC_RSP_R1B:
598 resp = 0x7;
599 break;
600 case MMC_RSP_R2:
601 resp = 0x2;
602 break;
603 case MMC_RSP_R3:
604 resp = 0x3;
605 break;
606 case MMC_RSP_NONE:
607 default:
608 resp = 0x0;
609 break;
610 }
611
612 return resp;
613}
614
615static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
616 struct mmc_request *mrq, struct mmc_command *cmd)
617{
618 /* rawcmd :
619 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
620 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
621 */
622 u32 opcode = cmd->opcode;
623 u32 resp = msdc_cmd_find_resp(host, mrq, cmd);
624 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
625
626 host->cmd_rsp = resp;
627
628 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
629 opcode == MMC_STOP_TRANSMISSION)
630 rawcmd |= (0x1 << 14);
631 else if (opcode == SD_SWITCH_VOLTAGE)
632 rawcmd |= (0x1 << 30);
633 else if (opcode == SD_APP_SEND_SCR ||
634 opcode == SD_APP_SEND_NUM_WR_BLKS ||
635 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
636 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
637 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
638 rawcmd |= (0x1 << 11);
639
640 if (cmd->data) {
641 struct mmc_data *data = cmd->data;
642
643 if (mmc_op_multi(opcode)) {
644 if (mmc_card_mmc(host->mmc->card) && mrq->sbc &&
645 !(mrq->sbc->arg & 0xFFFF0000))
646 rawcmd |= 0x2 << 28; /* AutoCMD23 */
647 }
648
649 rawcmd |= ((data->blksz & 0xFFF) << 16);
650 if (data->flags & MMC_DATA_WRITE)
651 rawcmd |= (0x1 << 13);
652 if (data->blocks > 1)
653 rawcmd |= (0x2 << 11);
654 else
655 rawcmd |= (0x1 << 11);
656 /* Always use dma mode */
657 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
658
659 if (host->timeout_ns != data->timeout_ns ||
660 host->timeout_clks != data->timeout_clks)
661 msdc_set_timeout(host, data->timeout_ns,
662 data->timeout_clks);
663
664 writel(data->blocks, host->base + SDC_BLK_NUM);
665 }
666 return rawcmd;
667}
668
669static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq,
670 struct mmc_command *cmd, struct mmc_data *data)
671{
672 bool read;
673
674 WARN_ON(host->data);
675 host->data = data;
676 read = data->flags & MMC_DATA_READ;
677
678 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
679 msdc_dma_setup(host, &host->dma, data);
680 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
681 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
682 dev_dbg(host->dev, "DMA start\n");
683 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
684 __func__, cmd->opcode, data->blocks, read);
685}
686
687static int msdc_auto_cmd_done(struct msdc_host *host, int events,
688 struct mmc_command *cmd)
689{
690 u32 *rsp = cmd->resp;
691
692 rsp[0] = readl(host->base + SDC_ACMD_RESP);
693
694 if (events & MSDC_INT_ACMDRDY) {
695 cmd->error = 0;
696 } else {
697 msdc_reset_hw(host);
698 if (events & MSDC_INT_ACMDCRCERR) {
699 cmd->error = -EILSEQ;
700 host->error |= REQ_STOP_EIO;
701 } else if (events & MSDC_INT_ACMDTMO) {
702 cmd->error = -ETIMEDOUT;
703 host->error |= REQ_STOP_TMO;
704 }
705 dev_err(host->dev,
706 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
707 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
708 }
709 return cmd->error;
710}
711
712static void msdc_track_cmd_data(struct msdc_host *host,
713 struct mmc_command *cmd, struct mmc_data *data)
714{
715 if (host->error)
716 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
717 __func__, cmd->opcode, cmd->arg, host->error);
718}
719
720static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
721{
722 unsigned long flags;
723 bool ret;
724
725 ret = cancel_delayed_work(&host->req_timeout);
726 if (!ret) {
727 /* delay work already running */
728 return;
729 }
730 spin_lock_irqsave(&host->lock, flags);
731 host->mrq = NULL;
732 spin_unlock_irqrestore(&host->lock, flags);
733
734 msdc_track_cmd_data(host, mrq->cmd, mrq->data);
735 if (mrq->data)
736 msdc_unprepare_data(host, mrq);
737 mmc_request_done(host->mmc, mrq);
4b8a43e9
CJ		 738
739 pm_runtime_mark_last_busy(host->dev);
740 pm_runtime_put_autosuspend(host->dev);
20848903
CJ		 741}
742
743/* returns true if command is fully handled; returns false otherwise */
744static bool msdc_cmd_done(struct msdc_host *host, int events,
745 struct mmc_request *mrq, struct mmc_command *cmd)
746{
747 bool done = false;
748 bool sbc_error;
749 unsigned long flags;
750 u32 *rsp = cmd->resp;
751
752 if (mrq->sbc && cmd == mrq->cmd &&
753 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
754 | MSDC_INT_ACMDTMO)))
755 msdc_auto_cmd_done(host, events, mrq->sbc);
756
757 sbc_error = mrq->sbc && mrq->sbc->error;
758
759 if (!sbc_error && !(events & (MSDC_INT_CMDRDY
760 | MSDC_INT_RSPCRCERR
761 | MSDC_INT_CMDTMO)))
762 return done;
763
764 spin_lock_irqsave(&host->lock, flags);
765 done = !host->cmd;
766 host->cmd = NULL;
767 spin_unlock_irqrestore(&host->lock, flags);
768
769 if (done)
770 return true;
771
726a9aac 772 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
20848903
CJ		 773
774 if (cmd->flags & MMC_RSP_PRESENT) {
775 if (cmd->flags & MMC_RSP_136) {
776 rsp[0] = readl(host->base + SDC_RESP3);
777 rsp[1] = readl(host->base + SDC_RESP2);
778 rsp[2] = readl(host->base + SDC_RESP1);
779 rsp[3] = readl(host->base + SDC_RESP0);
780 } else {
781 rsp[0] = readl(host->base + SDC_RESP0);
782 }
783 }
784
785 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
786 msdc_reset_hw(host);
787 if (events & MSDC_INT_RSPCRCERR) {
788 cmd->error = -EILSEQ;
789 host->error |= REQ_CMD_EIO;
790 } else if (events & MSDC_INT_CMDTMO) {
791 cmd->error = -ETIMEDOUT;
792 host->error |= REQ_CMD_TMO;
793 }
794 }
795 if (cmd->error)
796 dev_dbg(host->dev,
797 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
798 __func__, cmd->opcode, cmd->arg, rsp[0],
799 cmd->error);
800
801 msdc_cmd_next(host, mrq, cmd);
802 return true;
803}
804
805/* It is the core layer's responsibility to ensure card status
806 * is correct before issue a request. but host design do below
807 * checks recommended.
808 */
809static inline bool msdc_cmd_is_ready(struct msdc_host *host,
810 struct mmc_request *mrq, struct mmc_command *cmd)
811{
812 /* The max busy time we can endure is 20ms */
813 unsigned long tmo = jiffies + msecs_to_jiffies(20);
814
815 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) &&
816 time_before(jiffies, tmo))
817 cpu_relax();
818 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) {
819 dev_err(host->dev, "CMD bus busy detected\n");
820 host->error |= REQ_CMD_BUSY;
821 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
822 return false;
823 }
824
825 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
826 tmo = jiffies + msecs_to_jiffies(20);
827 /* R1B or with data, should check SDCBUSY */
828 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) &&
829 time_before(jiffies, tmo))
830 cpu_relax();
831 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) {
832 dev_err(host->dev, "Controller busy detected\n");
833 host->error |= REQ_CMD_BUSY;
834 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
835 return false;
836 }
837 }
838 return true;
839}
840
841static void msdc_start_command(struct msdc_host *host,
842 struct mmc_request *mrq, struct mmc_command *cmd)
843{
844 u32 rawcmd;
845
846 WARN_ON(host->cmd);
847 host->cmd = cmd;
848
849 if (!msdc_cmd_is_ready(host, mrq, cmd))
850 return;
851
852 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
853 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
854 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
855 msdc_reset_hw(host);
856 }
857
858 cmd->error = 0;
859 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
860 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
861
726a9aac 862 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
20848903
CJ		 863 writel(cmd->arg, host->base + SDC_ARG);
864 writel(rawcmd, host->base + SDC_CMD);
865}
866
867static void msdc_cmd_next(struct msdc_host *host,
868 struct mmc_request *mrq, struct mmc_command *cmd)
869{
870 if (cmd->error || (mrq->sbc && mrq->sbc->error))
871 msdc_request_done(host, mrq);
872 else if (cmd == mrq->sbc)
873 msdc_start_command(host, mrq, mrq->cmd);
874 else if (!cmd->data)
875 msdc_request_done(host, mrq);
876 else
877 msdc_start_data(host, mrq, cmd, cmd->data);
878}
879
880static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
881{
882 struct msdc_host *host = mmc_priv(mmc);
883
884 host->error = 0;
885 WARN_ON(host->mrq);
886 host->mrq = mrq;
887
4b8a43e9
CJ		 888 pm_runtime_get_sync(host->dev);
889
20848903
CJ		 890 if (mrq->data)
891 msdc_prepare_data(host, mrq);
892
893 /* if SBC is required, we have HW option and SW option.
894 * if HW option is enabled, and SBC does not have "special" flags,
895 * use HW option, otherwise use SW option
896 */
897 if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
898 (mrq->sbc->arg & 0xFFFF0000)))
899 msdc_start_command(host, mrq, mrq->sbc);
900 else
901 msdc_start_command(host, mrq, mrq->cmd);
902}
903
904static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
905 bool is_first_req)
906{
907 struct msdc_host *host = mmc_priv(mmc);
908 struct mmc_data *data = mrq->data;
909
910 if (!data)
911 return;
912
913 msdc_prepare_data(host, mrq);
914 data->host_cookie |= MSDC_ASYNC_FLAG;
915}
916
917static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
918 int err)
919{
920 struct msdc_host *host = mmc_priv(mmc);
921 struct mmc_data *data;
922
923 data = mrq->data;
924 if (!data)
925 return;
926 if (data->host_cookie) {
927 data->host_cookie &= ~MSDC_ASYNC_FLAG;
928 msdc_unprepare_data(host, mrq);
929 }
930}
931
932static void msdc_data_xfer_next(struct msdc_host *host,
933 struct mmc_request *mrq, struct mmc_data *data)
934{
935 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
6397b7f5 936 !mrq->sbc)
20848903
CJ		 937 msdc_start_command(host, mrq, mrq->stop);
938 else
939 msdc_request_done(host, mrq);
940}
941
942static bool msdc_data_xfer_done(struct msdc_host *host, u32 events,
943 struct mmc_request *mrq, struct mmc_data *data)
944{
945 struct mmc_command *stop = data->stop;
946 unsigned long flags;
947 bool done;
948 unsigned int check_data = events &
949 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
950 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
951 | MSDC_INT_DMA_PROTECT);
952
953 spin_lock_irqsave(&host->lock, flags);
954 done = !host->data;
955 if (check_data)
956 host->data = NULL;
957 spin_unlock_irqrestore(&host->lock, flags);
958
959 if (done)
960 return true;
961
962 if (check_data || (stop && stop->error)) {
963 dev_dbg(host->dev, "DMA status: 0x%8X\n",
964 readl(host->base + MSDC_DMA_CFG));
965 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
966 1);
967 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS)
968 cpu_relax();
969 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
970 dev_dbg(host->dev, "DMA stop\n");
971
972 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
973 data->bytes_xfered = data->blocks * data->blksz;
974 } else {
975 dev_err(host->dev, "interrupt events: %x\n", events);
976 msdc_reset_hw(host);
977 host->error |= REQ_DAT_ERR;
978 data->bytes_xfered = 0;
979
980 if (events & MSDC_INT_DATTMO)
981 data->error = -ETIMEDOUT;
6397b7f5
CJ		 982 else if (events & MSDC_INT_DATCRCERR)
983 data->error = -EILSEQ;
20848903
CJ		 984
985 dev_err(host->dev, "%s: cmd=%d; blocks=%d",
986 __func__, mrq->cmd->opcode, data->blocks);
987 dev_err(host->dev, "data_error=%d xfer_size=%d\n",
988 (int)data->error, data->bytes_xfered);
989 }
990
991 msdc_data_xfer_next(host, mrq, data);
992 done = true;
993 }
994 return done;
995}
996
997static void msdc_set_buswidth(struct msdc_host *host, u32 width)
998{
999 u32 val = readl(host->base + SDC_CFG);
1000
1001 val &= ~SDC_CFG_BUSWIDTH;
1002
1003 switch (width) {
1004 default:
1005 case MMC_BUS_WIDTH_1:
1006 val |= (MSDC_BUS_1BITS << 16);
1007 break;
1008 case MMC_BUS_WIDTH_4:
1009 val |= (MSDC_BUS_4BITS << 16);
1010 break;
1011 case MMC_BUS_WIDTH_8:
1012 val |= (MSDC_BUS_8BITS << 16);
1013 break;
1014 }
1015
1016 writel(val, host->base + SDC_CFG);
1017 dev_dbg(host->dev, "Bus Width = %d", width);
1018}
1019
1020static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
1021{
1022 struct msdc_host *host = mmc_priv(mmc);
1023 int min_uv, max_uv;
1024 int ret = 0;
1025
1026 if (!IS_ERR(mmc->supply.vqmmc)) {
1027 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1028 min_uv = 3300000;
1029 max_uv = 3300000;
1030 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
1031 min_uv = 1800000;
1032 max_uv = 1800000;
1033 } else {
1034 dev_err(host->dev, "Unsupported signal voltage!\n");
1035 return -EINVAL;
1036 }
1037
1038 ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv);
1039 if (ret) {
1040 dev_err(host->dev,
1041 "Regulator set error %d: %d - %d\n",
1042 ret, min_uv, max_uv);
1043 } else {
1044 /* Apply different pinctrl settings for different signal voltage */
1045 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
1046 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1047 else
1048 pinctrl_select_state(host->pinctrl, host->pins_default);
1049 }
1050 }
1051 return ret;
1052}
1053
1054static int msdc_card_busy(struct mmc_host *mmc)
1055{
1056 struct msdc_host *host = mmc_priv(mmc);
1057 u32 status = readl(host->base + MSDC_PS);
1058
1059 /* check if any pin between dat[0:3] is low */
1060 if (((status >> 16) & 0xf) != 0xf)
1061 return 1;
1062
1063 return 0;
1064}
1065
1066static void msdc_request_timeout(struct work_struct *work)
1067{
1068 struct msdc_host *host = container_of(work, struct msdc_host,
1069 req_timeout.work);
1070
1071 /* simulate HW timeout status */
1072 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1073 if (host->mrq) {
1074 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1075 host->mrq, host->mrq->cmd->opcode);
1076 if (host->cmd) {
1077 dev_err(host->dev, "%s: aborting cmd=%d\n",
1078 __func__, host->cmd->opcode);
1079 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1080 host->cmd);
1081 } else if (host->data) {
1082 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1083 __func__, host->mrq->cmd->opcode,
1084 host->data->blocks);
1085 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1086 host->data);
1087 }
1088 }
1089}
1090
1091static irqreturn_t msdc_irq(int irq, void *dev_id)
1092{
1093 struct msdc_host *host = (struct msdc_host *) dev_id;
1094
1095 while (true) {
1096 unsigned long flags;
1097 struct mmc_request *mrq;
1098 struct mmc_command *cmd;
1099 struct mmc_data *data;
1100 u32 events, event_mask;
1101
1102 spin_lock_irqsave(&host->lock, flags);
1103 events = readl(host->base + MSDC_INT);
1104 event_mask = readl(host->base + MSDC_INTEN);
1105 /* clear interrupts */
1106 writel(events & event_mask, host->base + MSDC_INT);
1107
1108 mrq = host->mrq;
1109 cmd = host->cmd;
1110 data = host->data;
1111 spin_unlock_irqrestore(&host->lock, flags);
1112
1113 if (!(events & event_mask))
1114 break;
1115
1116 if (!mrq) {
1117 dev_err(host->dev,
1118 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
1119 __func__, events, event_mask);
1120 WARN_ON(1);
1121 break;
1122 }
1123
1124 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1125
1126 if (cmd)
1127 msdc_cmd_done(host, events, mrq, cmd);
1128 else if (data)
1129 msdc_data_xfer_done(host, events, mrq, data);
1130 }
1131
1132 return IRQ_HANDLED;
1133}
1134
1135static void msdc_init_hw(struct msdc_host *host)
1136{
1137 u32 val;
1138
1139 /* Configure to MMC/SD mode, clock free running */
1140 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1141
1142 /* Reset */
1143 msdc_reset_hw(host);
1144
1145 /* Disable card detection */
1146 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1147
1148 /* Disable and clear all interrupts */
1149 writel(0, host->base + MSDC_INTEN);
1150 val = readl(host->base + MSDC_INT);
1151 writel(val, host->base + MSDC_INT);
1152
1153 writel(0, host->base + MSDC_PAD_TUNE);
1154 writel(0, host->base + MSDC_IOCON);
6397b7f5
CJ		 1155 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1156 writel(0x403c0046, host->base + MSDC_PATCH_BIT);
20848903
CJ		 1157 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1158 writel(0xffff0089, host->base + MSDC_PATCH_BIT1);
6397b7f5
CJ		 1159 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1160
20848903
CJ		 1161 /* Configure to enable SDIO mode.
1162 * it's must otherwise sdio cmd5 failed
1163 */
1164 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1165
1166 /* disable detect SDIO device interrupt function */
1167 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1168
1169 /* Configure to default data timeout */
1170 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1171
1172 dev_dbg(host->dev, "init hardware done!");
1173}
1174
1175static void msdc_deinit_hw(struct msdc_host *host)
1176{
1177 u32 val;
1178 /* Disable and clear all interrupts */
1179 writel(0, host->base + MSDC_INTEN);
1180
1181 val = readl(host->base + MSDC_INT);
1182 writel(val, host->base + MSDC_INT);
1183}
1184
1185/* init gpd and bd list in msdc_drv_probe */
1186static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
1187{
1188 struct mt_gpdma_desc *gpd = dma->gpd;
1189 struct mt_bdma_desc *bd = dma->bd;
1190 int i;
1191
62b0d27a 1192 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
20848903
CJ		 1193
1194 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
1195 gpd->ptr = (u32)dma->bd_addr; /* physical address */
62b0d27a
CJ		 1196 /* gpd->next is must set for desc DMA
1197 * That's why must alloc 2 gpd structure.
1198 */
1199 gpd->next = (u32)dma->gpd_addr + sizeof(struct mt_gpdma_desc);
20848903
CJ		 1200 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
1201 for (i = 0; i < (MAX_BD_NUM - 1); i++)
1202 bd[i].next = (u32)dma->bd_addr + sizeof(*bd) * (i + 1);
1203}
1204
1205static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1206{
1207 struct msdc_host *host = mmc_priv(mmc);
1208 int ret;
20848903 1209
4b8a43e9
CJ		 1210 pm_runtime_get_sync(host->dev);
1211
20848903
CJ		 1212 msdc_set_buswidth(host, ios->bus_width);
1213
1214 /* Suspend/Resume will do power off/on */
1215 switch (ios->power_mode) {
1216 case MMC_POWER_UP:
1217 if (!IS_ERR(mmc->supply.vmmc)) {
6397b7f5 1218 msdc_init_hw(host);
20848903
CJ		 1219 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1220 ios->vdd);
1221 if (ret) {
1222 dev_err(host->dev, "Failed to set vmmc power!\n");
4b8a43e9 1223 goto end;
20848903
CJ		 1224 }
1225 }
1226 break;
1227 case MMC_POWER_ON:
1228 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1229 ret = regulator_enable(mmc->supply.vqmmc);
1230 if (ret)
1231 dev_err(host->dev, "Failed to set vqmmc power!\n");
1232 else
1233 host->vqmmc_enabled = true;
1234 }
1235 break;
1236 case MMC_POWER_OFF:
1237 if (!IS_ERR(mmc->supply.vmmc))
1238 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1239
1240 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1241 regulator_disable(mmc->supply.vqmmc);
1242 host->vqmmc_enabled = false;
1243 }
1244 break;
1245 default:
1246 break;
1247 }
1248
6e622947
CJ		 1249 if (host->mclk != ios->clock || host->timing != ios->timing)
1250 msdc_set_mclk(host, ios->timing, ios->clock);
4b8a43e9
CJ		 1251
1252end:
1253 pm_runtime_mark_last_busy(host->dev);
1254 pm_runtime_put_autosuspend(host->dev);
20848903
CJ		 1255}
1256
6397b7f5
CJ		 1257static u32 test_delay_bit(u32 delay, u32 bit)
1258{
1259 bit %= PAD_DELAY_MAX;
1260 return delay & (1 << bit);
1261}
1262
1263static int get_delay_len(u32 delay, u32 start_bit)
1264{
1265 int i;
1266
1267 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
1268 if (test_delay_bit(delay, start_bit + i) == 0)
1269 return i;
1270 }
1271 return PAD_DELAY_MAX - start_bit;
1272}
1273
1274static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
1275{
1276 int start = 0, len = 0;
1277 int start_final = 0, len_final = 0;
1278 u8 final_phase = 0xff;
62d494ca 1279 struct msdc_delay_phase delay_phase = { 0, };
6397b7f5
CJ		 1280
1281 if (delay == 0) {
1282 dev_err(host->dev, "phase error: [map:%x]\n", delay);
1283 delay_phase.final_phase = final_phase;
1284 return delay_phase;
1285 }
1286
1287 while (start < PAD_DELAY_MAX) {
1288 len = get_delay_len(delay, start);
1289 if (len_final < len) {
1290 start_final = start;
1291 len_final = len;
1292 }
1293 start += len ? len : 1;
1294 if (len >= 8 && start_final < 4)
1295 break;
1296 }
1297
1298 /* The rule is that to find the smallest delay cell */
1299 if (start_final == 0)
1300 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
1301 else
1302 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
1303 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
1304 delay, len_final, final_phase);
1305
1306 delay_phase.maxlen = len_final;
1307 delay_phase.start = start_final;
1308 delay_phase.final_phase = final_phase;
1309 return delay_phase;
1310}
1311
1312static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
1313{
1314 struct msdc_host *host = mmc_priv(mmc);
1315 u32 rise_delay = 0, fall_delay = 0;
1316 struct msdc_delay_phase final_rise_delay, final_fall_delay;
1317 u8 final_delay, final_maxlen;
1318 int cmd_err;
1319 int i;
1320
1321 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1322 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1323 sdr_set_field(host->base + MSDC_PAD_TUNE,
1324 MSDC_PAD_TUNE_CMDRDLY, i);
1325 mmc_send_tuning(mmc, opcode, &cmd_err);
1326 if (!cmd_err)
1327 rise_delay |= (1 << i);
1328 }
1329
1330 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1331 for (i = 0; i < PAD_DELAY_MAX; i++) {
1332 sdr_set_field(host->base + MSDC_PAD_TUNE,
1333 MSDC_PAD_TUNE_CMDRDLY, i);
1334 mmc_send_tuning(mmc, opcode, &cmd_err);
1335 if (!cmd_err)
1336 fall_delay |= (1 << i);
1337 }
1338
1339 final_rise_delay = get_best_delay(host, rise_delay);
1340 final_fall_delay = get_best_delay(host, fall_delay);
1341
1342 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1343 if (final_maxlen == final_rise_delay.maxlen) {
1344 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1345 sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY,
1346 final_rise_delay.final_phase);
1347 final_delay = final_rise_delay.final_phase;
1348 } else {
1349 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1350 sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY,
1351 final_fall_delay.final_phase);
1352 final_delay = final_fall_delay.final_phase;
1353 }
1354
1355 return final_delay == 0xff ? -EIO : 0;
1356}
1357
1358static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
1359{
1360 struct msdc_host *host = mmc_priv(mmc);
1361 u32 rise_delay = 0, fall_delay = 0;
1362 struct msdc_delay_phase final_rise_delay, final_fall_delay;
1363 u8 final_delay, final_maxlen;
1364 int i, ret;
1365
1366 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1367 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1368 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1369 sdr_set_field(host->base + MSDC_PAD_TUNE,
1370 MSDC_PAD_TUNE_DATRRDLY, i);
1371 ret = mmc_send_tuning(mmc, opcode, NULL);
1372 if (!ret)
1373 rise_delay |= (1 << i);
1374 }
1375
1376 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1377 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1378 for (i = 0; i < PAD_DELAY_MAX; i++) {
1379 sdr_set_field(host->base + MSDC_PAD_TUNE,
1380 MSDC_PAD_TUNE_DATRRDLY, i);
1381 ret = mmc_send_tuning(mmc, opcode, NULL);
1382 if (!ret)
1383 fall_delay |= (1 << i);
1384 }
1385
1386 final_rise_delay = get_best_delay(host, rise_delay);
1387 final_fall_delay = get_best_delay(host, fall_delay);
1388
1389 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1390 /* Rising edge is more stable, prefer to use it */
1391 if (final_rise_delay.maxlen >= 10)
1392 final_maxlen = final_rise_delay.maxlen;
1393 if (final_maxlen == final_rise_delay.maxlen) {
1394 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1395 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1396 sdr_set_field(host->base + MSDC_PAD_TUNE,
1397 MSDC_PAD_TUNE_DATRRDLY,
1398 final_rise_delay.final_phase);
1399 final_delay = final_rise_delay.final_phase;
1400 } else {
1401 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1402 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1403 sdr_set_field(host->base + MSDC_PAD_TUNE,
1404 MSDC_PAD_TUNE_DATRRDLY,
1405 final_fall_delay.final_phase);
1406 final_delay = final_fall_delay.final_phase;
1407 }
1408
1409 return final_delay == 0xff ? -EIO : 0;
1410}
1411
1412static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1413{
1414 struct msdc_host *host = mmc_priv(mmc);
1415 int ret;
1416
1417 pm_runtime_get_sync(host->dev);
1418 ret = msdc_tune_response(mmc, opcode);
1419 if (ret == -EIO) {
1420 dev_err(host->dev, "Tune response fail!\n");
1421 goto out;
1422 }
1423 ret = msdc_tune_data(mmc, opcode);
1424 if (ret == -EIO)
1425 dev_err(host->dev, "Tune data fail!\n");
1426
1427out:
1428 pm_runtime_mark_last_busy(host->dev);
1429 pm_runtime_put_autosuspend(host->dev);
1430 return ret;
1431}
1432
1433static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1434{
1435 struct msdc_host *host = mmc_priv(mmc);
1436
1437 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
1438 return 0;
1439}
1440
c9b5061e
CJ		 1441static void msdc_hw_reset(struct mmc_host *mmc)
1442{
1443 struct msdc_host *host = mmc_priv(mmc);
1444
1445 sdr_set_bits(host->base + EMMC_IOCON, 1);
1446 udelay(10); /* 10us is enough */
1447 sdr_clr_bits(host->base + EMMC_IOCON, 1);
1448}
1449
20848903
CJ		 1450static struct mmc_host_ops mt_msdc_ops = {
1451 .post_req = msdc_post_req,
1452 .pre_req = msdc_pre_req,
1453 .request = msdc_ops_request,
1454 .set_ios = msdc_ops_set_ios,
1455 .start_signal_voltage_switch = msdc_ops_switch_volt,
1456 .card_busy = msdc_card_busy,
6397b7f5
CJ		 1457 .execute_tuning = msdc_execute_tuning,
1458 .prepare_hs400_tuning = msdc_prepare_hs400_tuning,
c9b5061e 1459 .hw_reset = msdc_hw_reset,
20848903
CJ		 1460};
1461
1462static int msdc_drv_probe(struct platform_device *pdev)
1463{
1464 struct mmc_host *mmc;
1465 struct msdc_host *host;
1466 struct resource *res;
1467 int ret;
1468
1469 if (!pdev->dev.of_node) {
1470 dev_err(&pdev->dev, "No DT found\n");
1471 return -EINVAL;
1472 }
1473 /* Allocate MMC host for this device */
1474 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
1475 if (!mmc)
1476 return -ENOMEM;
1477
1478 host = mmc_priv(mmc);
1479 ret = mmc_of_parse(mmc);
1480 if (ret)
1481 goto host_free;
1482
1483 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1484 host->base = devm_ioremap_resource(&pdev->dev, res);
1485 if (IS_ERR(host->base)) {
1486 ret = PTR_ERR(host->base);
1487 goto host_free;
1488 }
1489
1490 ret = mmc_regulator_get_supply(mmc);
1491 if (ret == -EPROBE_DEFER)
1492 goto host_free;
1493
1494 host->src_clk = devm_clk_get(&pdev->dev, "source");
1495 if (IS_ERR(host->src_clk)) {
1496 ret = PTR_ERR(host->src_clk);
1497 goto host_free;
1498 }
1499
1500 host->h_clk = devm_clk_get(&pdev->dev, "hclk");
1501 if (IS_ERR(host->h_clk)) {
1502 ret = PTR_ERR(host->h_clk);
1503 goto host_free;
1504 }
1505
1506 host->irq = platform_get_irq(pdev, 0);
1507 if (host->irq < 0) {
1508 ret = -EINVAL;
1509 goto host_free;
1510 }
1511
1512 host->pinctrl = devm_pinctrl_get(&pdev->dev);
1513 if (IS_ERR(host->pinctrl)) {
1514 ret = PTR_ERR(host->pinctrl);
1515 dev_err(&pdev->dev, "Cannot find pinctrl!\n");
1516 goto host_free;
1517 }
1518
1519 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
1520 if (IS_ERR(host->pins_default)) {
1521 ret = PTR_ERR(host->pins_default);
1522 dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
1523 goto host_free;
1524 }
1525
1526 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
1527 if (IS_ERR(host->pins_uhs)) {
1528 ret = PTR_ERR(host->pins_uhs);
1529 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
1530 goto host_free;
1531 }
1532
6397b7f5
CJ		 1533 if (!of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
1534 &host->hs400_ds_delay))
1535 dev_dbg(&pdev->dev, "hs400-ds-delay: %x\n",
1536 host->hs400_ds_delay);
1537
20848903
CJ		 1538 host->dev = &pdev->dev;
1539 host->mmc = mmc;
1540 host->src_clk_freq = clk_get_rate(host->src_clk);
1541 /* Set host parameters to mmc */
1542 mmc->ops = &mt_msdc_ops;
1543 mmc->f_min = host->src_clk_freq / (4 * 255);
1544
1545 mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23;
8131e815 1546 mmc->caps |= MMC_CAP_RUNTIME_RESUME;
20848903
CJ		 1547 /* MMC core transfer sizes tunable parameters */
1548 mmc->max_segs = MAX_BD_NUM;
1549 mmc->max_seg_size = BDMA_DESC_BUFLEN;
1550 mmc->max_blk_size = 2048;
1551 mmc->max_req_size = 512 * 1024;
1552 mmc->max_blk_count = mmc->max_req_size / 512;
1553 host->dma_mask = DMA_BIT_MASK(32);
1554 mmc_dev(mmc)->dma_mask = &host->dma_mask;
1555
1556 host->timeout_clks = 3 * 1048576;
1557 host->dma.gpd = dma_alloc_coherent(&pdev->dev,
62b0d27a 1558 2 * sizeof(struct mt_gpdma_desc),
20848903
CJ		 1559 &host->dma.gpd_addr, GFP_KERNEL);
1560 host->dma.bd = dma_alloc_coherent(&pdev->dev,
1561 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
1562 &host->dma.bd_addr, GFP_KERNEL);
1563 if (!host->dma.gpd || !host->dma.bd) {
1564 ret = -ENOMEM;
1565 goto release_mem;
1566 }
1567 msdc_init_gpd_bd(host, &host->dma);
1568 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
1569 spin_lock_init(&host->lock);
1570
1571 platform_set_drvdata(pdev, mmc);
1572 msdc_ungate_clock(host);
1573 msdc_init_hw(host);
1574
1575 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
1576 IRQF_TRIGGER_LOW | IRQF_ONESHOT, pdev->name, host);
1577 if (ret)
1578 goto release;
1579
4b8a43e9
CJ		 1580 pm_runtime_set_active(host->dev);
1581 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
1582 pm_runtime_use_autosuspend(host->dev);
1583 pm_runtime_enable(host->dev);
20848903 1584 ret = mmc_add_host(mmc);
4b8a43e9 1585
20848903 1586 if (ret)
4b8a43e9 1587 goto end;
20848903
CJ		 1588
1589 return 0;
4b8a43e9
CJ		 1590end:
1591 pm_runtime_disable(host->dev);
20848903
CJ		 1592release:
1593 platform_set_drvdata(pdev, NULL);
1594 msdc_deinit_hw(host);
1595 msdc_gate_clock(host);
1596release_mem:
1597 if (host->dma.gpd)
1598 dma_free_coherent(&pdev->dev,
62b0d27a 1599 2 * sizeof(struct mt_gpdma_desc),
20848903
CJ		 1600 host->dma.gpd, host->dma.gpd_addr);
1601 if (host->dma.bd)
1602 dma_free_coherent(&pdev->dev,
1603 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
1604 host->dma.bd, host->dma.bd_addr);
1605host_free:
1606 mmc_free_host(mmc);
1607
1608 return ret;
1609}
1610
1611static int msdc_drv_remove(struct platform_device *pdev)
1612{
1613 struct mmc_host *mmc;
1614 struct msdc_host *host;
1615
1616 mmc = platform_get_drvdata(pdev);
1617 host = mmc_priv(mmc);
1618
4b8a43e9
CJ		 1619 pm_runtime_get_sync(host->dev);
1620
20848903
CJ		 1621 platform_set_drvdata(pdev, NULL);
1622 mmc_remove_host(host->mmc);
1623 msdc_deinit_hw(host);
1624 msdc_gate_clock(host);
1625
4b8a43e9
CJ		 1626 pm_runtime_disable(host->dev);
1627 pm_runtime_put_noidle(host->dev);
20848903
CJ		 1628 dma_free_coherent(&pdev->dev,
1629 sizeof(struct mt_gpdma_desc),
1630 host->dma.gpd, host->dma.gpd_addr);
1631 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
1632 host->dma.bd, host->dma.bd_addr);
1633
1634 mmc_free_host(host->mmc);
1635
1636 return 0;
1637}
1638
4b8a43e9
CJ		 1639#ifdef CONFIG_PM
1640static void msdc_save_reg(struct msdc_host *host)
1641{
1642 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
1643 host->save_para.iocon = readl(host->base + MSDC_IOCON);
1644 host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
1645 host->save_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
1646 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
1647 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
6397b7f5
CJ		 1648 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
1649 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
4b8a43e9
CJ		 1650}
1651
1652static void msdc_restore_reg(struct msdc_host *host)
1653{
1654 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
1655 writel(host->save_para.iocon, host->base + MSDC_IOCON);
1656 writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
1657 writel(host->save_para.pad_tune, host->base + MSDC_PAD_TUNE);
1658 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
1659 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
6397b7f5
CJ		 1660 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
1661 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
4b8a43e9
CJ		 1662}
1663
1664static int msdc_runtime_suspend(struct device *dev)
1665{
1666 struct mmc_host *mmc = dev_get_drvdata(dev);
1667 struct msdc_host *host = mmc_priv(mmc);
1668
1669 msdc_save_reg(host);
1670 msdc_gate_clock(host);
1671 return 0;
1672}
1673
1674static int msdc_runtime_resume(struct device *dev)
1675{
1676 struct mmc_host *mmc = dev_get_drvdata(dev);
1677 struct msdc_host *host = mmc_priv(mmc);
1678
1679 msdc_ungate_clock(host);
1680 msdc_restore_reg(host);
1681 return 0;
1682}
1683#endif
1684
1685static const struct dev_pm_ops msdc_dev_pm_ops = {
1686 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1687 pm_runtime_force_resume)
1688 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
1689};
1690
20848903
CJ		 1691static const struct of_device_id msdc_of_ids[] = {
1692 { .compatible = "mediatek,mt8135-mmc", },
1693 {}
1694};
1695
1696static struct platform_driver mt_msdc_driver = {
1697 .probe = msdc_drv_probe,
1698 .remove = msdc_drv_remove,
1699 .driver = {
1700 .name = "mtk-msdc",
1701 .of_match_table = msdc_of_ids,
4b8a43e9 1702 .pm = &msdc_dev_pm_ops,
20848903
CJ		 1703 },
1704};
1705
1706module_platform_driver(mt_msdc_driver);
1707MODULE_LICENSE("GPL v2");
1708MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");
Linux kernel - Deliverables
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