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mmc: mvsdio: use slot-gpio for card detect gpio
[deliverable/linux.git] / drivers / mmc / host / mvsdio.c
CommitLineData
236caa7c
MS		 1/*
2 * Marvell MMC/SD/SDIO driver
3 *
4 * Authors: Maen Suleiman, Nicolas Pitre
5 * Copyright (C) 2008-2009 Marvell Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/platform_device.h>
16#include <linux/mbus.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/dma-mapping.h>
20#include <linux/scatterlist.h>
21#include <linux/irq.h>
f4f7561e 22#include <linux/clk.h>
236caa7c
MS		 23#include <linux/gpio.h>
24#include <linux/mmc/host.h>
3724482d 25#include <linux/mmc/slot-gpio.h>
236caa7c
MS		 26
27#include <asm/sizes.h>
28#include <asm/unaligned.h>
c02cecb9 29#include <linux/platform_data/mmc-mvsdio.h>
236caa7c
MS		 30
31#include "mvsdio.h"
32
33#define DRIVER_NAME "mvsdio"
34
35static int maxfreq = MVSD_CLOCKRATE_MAX;
36static int nodma;
37
38struct mvsd_host {
39 void __iomem *base;
40 struct mmc_request *mrq;
41 spinlock_t lock;
42 unsigned int xfer_mode;
43 unsigned int intr_en;
44 unsigned int ctrl;
45 unsigned int pio_size;
46 void *pio_ptr;
47 unsigned int sg_frags;
48 unsigned int ns_per_clk;
49 unsigned int clock;
50 unsigned int base_clock;
51 struct timer_list timer;
52 struct mmc_host *mmc;
53 struct device *dev;
f4f7561e 54 struct clk *clk;
236caa7c
MS		 55};
56
57#define mvsd_write(offs, val) writel(val, iobase + (offs))
58#define mvsd_read(offs) readl(iobase + (offs))
59
60static int mvsd_setup_data(struct mvsd_host *host, struct mmc_data *data)
61{
62 void __iomem *iobase = host->base;
63 unsigned int tmout;
64 int tmout_index;
65
a6d297f0
NP		 66 /*
67 * Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE
68 * register is sometimes not set before a while when some
69 * "unusual" data block sizes are used (such as with the SWITCH
70 * command), even despite the fact that the XFER_DONE interrupt
71 * was raised. And if another data transfer starts before
72 * this bit comes to good sense (which eventually happens by
73 * itself) then the new transfer simply fails with a timeout.
74 */
75 if (!(mvsd_read(MVSD_HW_STATE) & (1 << 13))) {
76 unsigned long t = jiffies + HZ;
77 unsigned int hw_state, count = 0;
78 do {
79 if (time_after(jiffies, t)) {
80 dev_warn(host->dev, "FIFO_EMPTY bit missing\n");
81 break;
82 }
83 hw_state = mvsd_read(MVSD_HW_STATE);
84 count++;
85 } while (!(hw_state & (1 << 13)));
86 dev_dbg(host->dev, "*** wait for FIFO_EMPTY bit "
87 "(hw=0x%04x, count=%d, jiffies=%ld)\n",
88 hw_state, count, jiffies - (t - HZ));
89 }
90
236caa7c
MS		 91 /* If timeout=0 then maximum timeout index is used. */
92 tmout = DIV_ROUND_UP(data->timeout_ns, host->ns_per_clk);
93 tmout += data->timeout_clks;
94 tmout_index = fls(tmout - 1) - 12;
95 if (tmout_index < 0)
96 tmout_index = 0;
97 if (tmout_index > MVSD_HOST_CTRL_TMOUT_MAX)
98 tmout_index = MVSD_HOST_CTRL_TMOUT_MAX;
99
100 dev_dbg(host->dev, "data %s at 0x%08x: blocks=%d blksz=%d tmout=%u (%d)\n",
101 (data->flags & MMC_DATA_READ) ? "read" : "write",
102 (u32)sg_virt(data->sg), data->blocks, data->blksz,
103 tmout, tmout_index);
104
105 host->ctrl &= ~MVSD_HOST_CTRL_TMOUT_MASK;
106 host->ctrl |= MVSD_HOST_CTRL_TMOUT(tmout_index);
107 mvsd_write(MVSD_HOST_CTRL, host->ctrl);
108 mvsd_write(MVSD_BLK_COUNT, data->blocks);
109 mvsd_write(MVSD_BLK_SIZE, data->blksz);
110
111 if (nodma || (data->blksz | data->sg->offset) & 3) {
112 /*
113 * We cannot do DMA on a buffer which offset or size
114 * is not aligned on a 4-byte boundary.
115 */
116 host->pio_size = data->blocks * data->blksz;
117 host->pio_ptr = sg_virt(data->sg);
118 if (!nodma)
a3c76eb9 119 pr_debug("%s: fallback to PIO for data "
236caa7c
MS		 120 "at 0x%p size %d\n",
121 mmc_hostname(host->mmc),
122 host->pio_ptr, host->pio_size);
123 return 1;
124 } else {
125 dma_addr_t phys_addr;
126 int dma_dir = (data->flags & MMC_DATA_READ) ?
127 DMA_FROM_DEVICE : DMA_TO_DEVICE;
128 host->sg_frags = dma_map_sg(mmc_dev(host->mmc), data->sg,
129 data->sg_len, dma_dir);
130 phys_addr = sg_dma_address(data->sg);
131 mvsd_write(MVSD_SYS_ADDR_LOW, (u32)phys_addr & 0xffff);
132 mvsd_write(MVSD_SYS_ADDR_HI, (u32)phys_addr >> 16);
133 return 0;
134 }
135}
136
137static void mvsd_request(struct mmc_host *mmc, struct mmc_request *mrq)
138{
139 struct mvsd_host *host = mmc_priv(mmc);
140 void __iomem *iobase = host->base;
141 struct mmc_command *cmd = mrq->cmd;
142 u32 cmdreg = 0, xfer = 0, intr = 0;
143 unsigned long flags;
144
145 BUG_ON(host->mrq != NULL);
146 host->mrq = mrq;
147
148 dev_dbg(host->dev, "cmd %d (hw state 0x%04x)\n",
149 cmd->opcode, mvsd_read(MVSD_HW_STATE));
150
151 cmdreg = MVSD_CMD_INDEX(cmd->opcode);
152
153 if (cmd->flags & MMC_RSP_BUSY)
154 cmdreg |= MVSD_CMD_RSP_48BUSY;
155 else if (cmd->flags & MMC_RSP_136)
156 cmdreg |= MVSD_CMD_RSP_136;
157 else if (cmd->flags & MMC_RSP_PRESENT)
158 cmdreg |= MVSD_CMD_RSP_48;
159 else
160 cmdreg |= MVSD_CMD_RSP_NONE;
161
162 if (cmd->flags & MMC_RSP_CRC)
163 cmdreg |= MVSD_CMD_CHECK_CMDCRC;
164
165 if (cmd->flags & MMC_RSP_OPCODE)
166 cmdreg |= MVSD_CMD_INDX_CHECK;
167
168 if (cmd->flags & MMC_RSP_PRESENT) {
169 cmdreg |= MVSD_UNEXPECTED_RESP;
170 intr |= MVSD_NOR_UNEXP_RSP;
171 }
172
173 if (mrq->data) {
174 struct mmc_data *data = mrq->data;
175 int pio;
176
177 cmdreg |= MVSD_CMD_DATA_PRESENT | MVSD_CMD_CHECK_DATACRC16;
178 xfer |= MVSD_XFER_MODE_HW_WR_DATA_EN;
179 if (data->flags & MMC_DATA_READ)
180 xfer |= MVSD_XFER_MODE_TO_HOST;
181
182 pio = mvsd_setup_data(host, data);
183 if (pio) {
184 xfer |= MVSD_XFER_MODE_PIO;
185 /* PIO section of mvsd_irq has comments on those bits */
186 if (data->flags & MMC_DATA_WRITE)
187 intr |= MVSD_NOR_TX_AVAIL;
188 else if (host->pio_size > 32)
189 intr |= MVSD_NOR_RX_FIFO_8W;
190 else
191 intr |= MVSD_NOR_RX_READY;
192 }
193
194 if (data->stop) {
195 struct mmc_command *stop = data->stop;
196 u32 cmd12reg = 0;
197
198 mvsd_write(MVSD_AUTOCMD12_ARG_LOW, stop->arg & 0xffff);
199 mvsd_write(MVSD_AUTOCMD12_ARG_HI, stop->arg >> 16);
200
201 if (stop->flags & MMC_RSP_BUSY)
202 cmd12reg |= MVSD_AUTOCMD12_BUSY;
203 if (stop->flags & MMC_RSP_OPCODE)
204 cmd12reg |= MVSD_AUTOCMD12_INDX_CHECK;
205 cmd12reg |= MVSD_AUTOCMD12_INDEX(stop->opcode);
206 mvsd_write(MVSD_AUTOCMD12_CMD, cmd12reg);
207
208 xfer |= MVSD_XFER_MODE_AUTO_CMD12;
209 intr |= MVSD_NOR_AUTOCMD12_DONE;
210 } else {
211 intr |= MVSD_NOR_XFER_DONE;
212 }
213 } else {
214 intr |= MVSD_NOR_CMD_DONE;
215 }
216
217 mvsd_write(MVSD_ARG_LOW, cmd->arg & 0xffff);
218 mvsd_write(MVSD_ARG_HI, cmd->arg >> 16);
219
220 spin_lock_irqsave(&host->lock, flags);
221
222 host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
223 host->xfer_mode |= xfer;
224 mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
225
226 mvsd_write(MVSD_NOR_INTR_STATUS, ~MVSD_NOR_CARD_INT);
227 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
228 mvsd_write(MVSD_CMD, cmdreg);
229
230 host->intr_en &= MVSD_NOR_CARD_INT;
231 host->intr_en |= intr | MVSD_NOR_ERROR;
232 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
233 mvsd_write(MVSD_ERR_INTR_EN, 0xffff);
234
235 mod_timer(&host->timer, jiffies + 5 * HZ);
236
237 spin_unlock_irqrestore(&host->lock, flags);
238}
239
240static u32 mvsd_finish_cmd(struct mvsd_host *host, struct mmc_command *cmd,
241 u32 err_status)
242{
243 void __iomem *iobase = host->base;
244
245 if (cmd->flags & MMC_RSP_136) {
246 unsigned int response[8], i;
247 for (i = 0; i < 8; i++)
248 response[i] = mvsd_read(MVSD_RSP(i));
249 cmd->resp[0] = ((response[0] & 0x03ff) << 22) |
250 ((response[1] & 0xffff) << 6) |
251 ((response[2] & 0xfc00) >> 10);
252 cmd->resp[1] = ((response[2] & 0x03ff) << 22) |
253 ((response[3] & 0xffff) << 6) |
254 ((response[4] & 0xfc00) >> 10);
255 cmd->resp[2] = ((response[4] & 0x03ff) << 22) |
256 ((response[5] & 0xffff) << 6) |
257 ((response[6] & 0xfc00) >> 10);
258 cmd->resp[3] = ((response[6] & 0x03ff) << 22) |
259 ((response[7] & 0x3fff) << 8);
260 } else if (cmd->flags & MMC_RSP_PRESENT) {
261 unsigned int response[3], i;
262 for (i = 0; i < 3; i++)
263 response[i] = mvsd_read(MVSD_RSP(i));
264 cmd->resp[0] = ((response[2] & 0x003f) << (8 - 8)) |
265 ((response[1] & 0xffff) << (14 - 8)) |
266 ((response[0] & 0x03ff) << (30 - 8));
267 cmd->resp[1] = ((response[0] & 0xfc00) >> 10);
268 cmd->resp[2] = 0;
269 cmd->resp[3] = 0;
270 }
271
272 if (err_status & MVSD_ERR_CMD_TIMEOUT) {
273 cmd->error = -ETIMEDOUT;
274 } else if (err_status & (MVSD_ERR_CMD_CRC | MVSD_ERR_CMD_ENDBIT |
275 MVSD_ERR_CMD_INDEX | MVSD_ERR_CMD_STARTBIT)) {
276 cmd->error = -EILSEQ;
277 }
278 err_status &= ~(MVSD_ERR_CMD_TIMEOUT | MVSD_ERR_CMD_CRC |
279 MVSD_ERR_CMD_ENDBIT | MVSD_ERR_CMD_INDEX |
280 MVSD_ERR_CMD_STARTBIT);
281
282 return err_status;
283}
284
285static u32 mvsd_finish_data(struct mvsd_host *host, struct mmc_data *data,
286 u32 err_status)
287{
288 void __iomem *iobase = host->base;
289
290 if (host->pio_ptr) {
291 host->pio_ptr = NULL;
292 host->pio_size = 0;
293 } else {
294 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_frags,
295 (data->flags & MMC_DATA_READ) ?
296 DMA_FROM_DEVICE : DMA_TO_DEVICE);
297 }
298
299 if (err_status & MVSD_ERR_DATA_TIMEOUT)
300 data->error = -ETIMEDOUT;
301 else if (err_status & (MVSD_ERR_DATA_CRC | MVSD_ERR_DATA_ENDBIT))
302 data->error = -EILSEQ;
303 else if (err_status & MVSD_ERR_XFER_SIZE)
304 data->error = -EBADE;
305 err_status &= ~(MVSD_ERR_DATA_TIMEOUT | MVSD_ERR_DATA_CRC |
306 MVSD_ERR_DATA_ENDBIT | MVSD_ERR_XFER_SIZE);
307
308 dev_dbg(host->dev, "data done: blocks_left=%d, bytes_left=%d\n",
309 mvsd_read(MVSD_CURR_BLK_LEFT), mvsd_read(MVSD_CURR_BYTE_LEFT));
310 data->bytes_xfered =
311 (data->blocks - mvsd_read(MVSD_CURR_BLK_LEFT)) * data->blksz;
312 /* We can't be sure about the last block when errors are detected */
313 if (data->bytes_xfered && data->error)
314 data->bytes_xfered -= data->blksz;
315
316 /* Handle Auto cmd 12 response */
317 if (data->stop) {
318 unsigned int response[3], i;
319 for (i = 0; i < 3; i++)
320 response[i] = mvsd_read(MVSD_AUTO_RSP(i));
321 data->stop->resp[0] = ((response[2] & 0x003f) << (8 - 8)) |
322 ((response[1] & 0xffff) << (14 - 8)) |
323 ((response[0] & 0x03ff) << (30 - 8));
324 data->stop->resp[1] = ((response[0] & 0xfc00) >> 10);
325 data->stop->resp[2] = 0;
326 data->stop->resp[3] = 0;
327
328 if (err_status & MVSD_ERR_AUTOCMD12) {
329 u32 err_cmd12 = mvsd_read(MVSD_AUTOCMD12_ERR_STATUS);
330 dev_dbg(host->dev, "c12err 0x%04x\n", err_cmd12);
331 if (err_cmd12 & MVSD_AUTOCMD12_ERR_NOTEXE)
332 data->stop->error = -ENOEXEC;
333 else if (err_cmd12 & MVSD_AUTOCMD12_ERR_TIMEOUT)
334 data->stop->error = -ETIMEDOUT;
335 else if (err_cmd12)
336 data->stop->error = -EILSEQ;
337 err_status &= ~MVSD_ERR_AUTOCMD12;
338 }
339 }
340
341 return err_status;
342}
343
344static irqreturn_t mvsd_irq(int irq, void *dev)
345{
346 struct mvsd_host *host = dev;
347 void __iomem *iobase = host->base;
348 u32 intr_status, intr_done_mask;
349 int irq_handled = 0;
350
351 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
352 dev_dbg(host->dev, "intr 0x%04x intr_en 0x%04x hw_state 0x%04x\n",
353 intr_status, mvsd_read(MVSD_NOR_INTR_EN),
354 mvsd_read(MVSD_HW_STATE));
355
356 spin_lock(&host->lock);
357
358 /* PIO handling, if needed. Messy business... */
359 if (host->pio_size &&
360 (intr_status & host->intr_en &
361 (MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W))) {
362 u16 *p = host->pio_ptr;
363 int s = host->pio_size;
364 while (s >= 32 && (intr_status & MVSD_NOR_RX_FIFO_8W)) {
365 readsw(iobase + MVSD_FIFO, p, 16);
366 p += 16;
367 s -= 32;
368 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
369 }
370 /*
371 * Normally we'd use < 32 here, but the RX_FIFO_8W bit
372 * doesn't appear to assert when there is exactly 32 bytes
373 * (8 words) left to fetch in a transfer.
374 */
375 if (s <= 32) {
376 while (s >= 4 && (intr_status & MVSD_NOR_RX_READY)) {
377 put_unaligned(mvsd_read(MVSD_FIFO), p++);
378 put_unaligned(mvsd_read(MVSD_FIFO), p++);
379 s -= 4;
380 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
381 }
382 if (s && s < 4 && (intr_status & MVSD_NOR_RX_READY)) {
383 u16 val[2] = {0, 0};
384 val[0] = mvsd_read(MVSD_FIFO);
385 val[1] = mvsd_read(MVSD_FIFO);
6cdbf734 386 memcpy(p, ((void *)&val) + 4 - s, s);
236caa7c
MS		 387 s = 0;
388 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
389 }
390 if (s == 0) {
391 host->intr_en &=
392 ~(MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W);
393 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
394 } else if (host->intr_en & MVSD_NOR_RX_FIFO_8W) {
395 host->intr_en &= ~MVSD_NOR_RX_FIFO_8W;
396 host->intr_en |= MVSD_NOR_RX_READY;
397 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
398 }
399 }
400 dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
401 s, intr_status, mvsd_read(MVSD_HW_STATE));
402 host->pio_ptr = p;
403 host->pio_size = s;
404 irq_handled = 1;
405 } else if (host->pio_size &&
406 (intr_status & host->intr_en &
407 (MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W))) {
408 u16 *p = host->pio_ptr;
409 int s = host->pio_size;
410 /*
411 * The TX_FIFO_8W bit is unreliable. When set, bursting
412 * 16 halfwords all at once in the FIFO drops data. Actually
413 * TX_AVAIL does go off after only one word is pushed even if
414 * TX_FIFO_8W remains set.
415 */
416 while (s >= 4 && (intr_status & MVSD_NOR_TX_AVAIL)) {
417 mvsd_write(MVSD_FIFO, get_unaligned(p++));
418 mvsd_write(MVSD_FIFO, get_unaligned(p++));
419 s -= 4;
420 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
421 }
422 if (s < 4) {
423 if (s && (intr_status & MVSD_NOR_TX_AVAIL)) {
424 u16 val[2] = {0, 0};
6cdbf734 425 memcpy(((void *)&val) + 4 - s, p, s);
236caa7c
MS		 426 mvsd_write(MVSD_FIFO, val[0]);
427 mvsd_write(MVSD_FIFO, val[1]);
428 s = 0;
429 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
430 }
431 if (s == 0) {
432 host->intr_en &=
433 ~(MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W);
434 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
435 }
436 }
437 dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
438 s, intr_status, mvsd_read(MVSD_HW_STATE));
439 host->pio_ptr = p;
440 host->pio_size = s;
441 irq_handled = 1;
442 }
443
444 mvsd_write(MVSD_NOR_INTR_STATUS, intr_status);
445
446 intr_done_mask = MVSD_NOR_CARD_INT | MVSD_NOR_RX_READY |
447 MVSD_NOR_RX_FIFO_8W | MVSD_NOR_TX_FIFO_8W;
448 if (intr_status & host->intr_en & ~intr_done_mask) {
449 struct mmc_request *mrq = host->mrq;
450 struct mmc_command *cmd = mrq->cmd;
451 u32 err_status = 0;
452
453 del_timer(&host->timer);
454 host->mrq = NULL;
455
456 host->intr_en &= MVSD_NOR_CARD_INT;
457 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
458 mvsd_write(MVSD_ERR_INTR_EN, 0);
459
460 spin_unlock(&host->lock);
461
462 if (intr_status & MVSD_NOR_UNEXP_RSP) {
463 cmd->error = -EPROTO;
464 } else if (intr_status & MVSD_NOR_ERROR) {
465 err_status = mvsd_read(MVSD_ERR_INTR_STATUS);
466 dev_dbg(host->dev, "err 0x%04x\n", err_status);
467 }
468
469 err_status = mvsd_finish_cmd(host, cmd, err_status);
470 if (mrq->data)
471 err_status = mvsd_finish_data(host, mrq->data, err_status);
472 if (err_status) {
a3c76eb9 473 pr_err("%s: unhandled error status %#04x\n",
236caa7c
MS		 474 mmc_hostname(host->mmc), err_status);
475 cmd->error = -ENOMSG;
476 }
477
478 mmc_request_done(host->mmc, mrq);
479 irq_handled = 1;
480 } else
481 spin_unlock(&host->lock);
482
483 if (intr_status & MVSD_NOR_CARD_INT) {
484 mmc_signal_sdio_irq(host->mmc);
485 irq_handled = 1;
486 }
487
488 if (irq_handled)
489 return IRQ_HANDLED;
490
a3c76eb9 491 pr_err("%s: unhandled interrupt status=0x%04x en=0x%04x "
236caa7c
MS		 492 "pio=%d\n", mmc_hostname(host->mmc), intr_status,
493 host->intr_en, host->pio_size);
494 return IRQ_NONE;
495}
496
497static void mvsd_timeout_timer(unsigned long data)
498{
499 struct mvsd_host *host = (struct mvsd_host *)data;
500 void __iomem *iobase = host->base;
501 struct mmc_request *mrq;
502 unsigned long flags;
503
504 spin_lock_irqsave(&host->lock, flags);
505 mrq = host->mrq;
506 if (mrq) {
a3c76eb9 507 pr_err("%s: Timeout waiting for hardware interrupt.\n",
236caa7c 508 mmc_hostname(host->mmc));
a3c76eb9 509 pr_err("%s: hw_state=0x%04x, intr_status=0x%04x "
236caa7c
MS		 510 "intr_en=0x%04x\n", mmc_hostname(host->mmc),
511 mvsd_read(MVSD_HW_STATE),
512 mvsd_read(MVSD_NOR_INTR_STATUS),
513 mvsd_read(MVSD_NOR_INTR_EN));
514
515 host->mrq = NULL;
516
517 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
518
519 host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
520 mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
521
522 host->intr_en &= MVSD_NOR_CARD_INT;
523 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
524 mvsd_write(MVSD_ERR_INTR_EN, 0);
525 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
526
527 mrq->cmd->error = -ETIMEDOUT;
528 mvsd_finish_cmd(host, mrq->cmd, 0);
529 if (mrq->data) {
530 mrq->data->error = -ETIMEDOUT;
531 mvsd_finish_data(host, mrq->data, 0);
532 }
533 }
534 spin_unlock_irqrestore(&host->lock, flags);
535
536 if (mrq)
537 mmc_request_done(host->mmc, mrq);
538}
539
236caa7c
MS		 540static void mvsd_enable_sdio_irq(struct mmc_host *mmc, int enable)
541{
542 struct mvsd_host *host = mmc_priv(mmc);
543 void __iomem *iobase = host->base;
544 unsigned long flags;
545
546 spin_lock_irqsave(&host->lock, flags);
547 if (enable) {
548 host->xfer_mode |= MVSD_XFER_MODE_INT_CHK_EN;
549 host->intr_en |= MVSD_NOR_CARD_INT;
550 } else {
551 host->xfer_mode &= ~MVSD_XFER_MODE_INT_CHK_EN;
552 host->intr_en &= ~MVSD_NOR_CARD_INT;
553 }
554 mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
555 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
556 spin_unlock_irqrestore(&host->lock, flags);
557}
558
236caa7c
MS		 559static void mvsd_power_up(struct mvsd_host *host)
560{
561 void __iomem *iobase = host->base;
562 dev_dbg(host->dev, "power up\n");
563 mvsd_write(MVSD_NOR_INTR_EN, 0);
564 mvsd_write(MVSD_ERR_INTR_EN, 0);
565 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
566 mvsd_write(MVSD_XFER_MODE, 0);
567 mvsd_write(MVSD_NOR_STATUS_EN, 0xffff);
568 mvsd_write(MVSD_ERR_STATUS_EN, 0xffff);
569 mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
570 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
571}
572
573static void mvsd_power_down(struct mvsd_host *host)
574{
575 void __iomem *iobase = host->base;
576 dev_dbg(host->dev, "power down\n");
577 mvsd_write(MVSD_NOR_INTR_EN, 0);
578 mvsd_write(MVSD_ERR_INTR_EN, 0);
579 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
580 mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
581 mvsd_write(MVSD_NOR_STATUS_EN, 0);
582 mvsd_write(MVSD_ERR_STATUS_EN, 0);
583 mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
584 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
585}
586
587static void mvsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
588{
589 struct mvsd_host *host = mmc_priv(mmc);
590 void __iomem *iobase = host->base;
591 u32 ctrl_reg = 0;
592
593 if (ios->power_mode == MMC_POWER_UP)
594 mvsd_power_up(host);
595
596 if (ios->clock == 0) {
597 mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
598 mvsd_write(MVSD_CLK_DIV, MVSD_BASE_DIV_MAX);
599 host->clock = 0;
600 dev_dbg(host->dev, "clock off\n");
601 } else if (ios->clock != host->clock) {
602 u32 m = DIV_ROUND_UP(host->base_clock, ios->clock) - 1;
603 if (m > MVSD_BASE_DIV_MAX)
604 m = MVSD_BASE_DIV_MAX;
605 mvsd_write(MVSD_CLK_DIV, m);
606 host->clock = ios->clock;
607 host->ns_per_clk = 1000000000 / (host->base_clock / (m+1));
608 dev_dbg(host->dev, "clock=%d (%d), div=0x%04x\n",
609 ios->clock, host->base_clock / (m+1), m);
610 }
611
612 /* default transfer mode */
613 ctrl_reg |= MVSD_HOST_CTRL_BIG_ENDIAN;
614 ctrl_reg &= ~MVSD_HOST_CTRL_LSB_FIRST;
615
616 /* default to maximum timeout */
617 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_MASK;
618 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_EN;
619
620 if (ios->bus_mode == MMC_BUSMODE_PUSHPULL)
621 ctrl_reg |= MVSD_HOST_CTRL_PUSH_PULL_EN;
622
623 if (ios->bus_width == MMC_BUS_WIDTH_4)
624 ctrl_reg |= MVSD_HOST_CTRL_DATA_WIDTH_4_BITS;
625
9ca6944c
NP		 626 /*
627 * The HI_SPEED_EN bit is causing trouble with many (but not all)
628 * high speed SD, SDHC and SDIO cards. Not enabling that bit
629 * makes all cards work. So let's just ignore that bit for now
630 * and revisit this issue if problems for not enabling this bit
631 * are ever reported.
632 */
633#if 0
236caa7c
MS		 634 if (ios->timing == MMC_TIMING_MMC_HS ||
635 ios->timing == MMC_TIMING_SD_HS)
636 ctrl_reg |= MVSD_HOST_CTRL_HI_SPEED_EN;
9ca6944c 637#endif
236caa7c
MS		 638
639 host->ctrl = ctrl_reg;
640 mvsd_write(MVSD_HOST_CTRL, ctrl_reg);
641 dev_dbg(host->dev, "ctrl 0x%04x: %s %s %s\n", ctrl_reg,
642 (ctrl_reg & MVSD_HOST_CTRL_PUSH_PULL_EN) ?
643 "push-pull" : "open-drain",
644 (ctrl_reg & MVSD_HOST_CTRL_DATA_WIDTH_4_BITS) ?
645 "4bit-width" : "1bit-width",
646 (ctrl_reg & MVSD_HOST_CTRL_HI_SPEED_EN) ?
647 "high-speed" : "");
648
649 if (ios->power_mode == MMC_POWER_OFF)
650 mvsd_power_down(host);
651}
652
653static const struct mmc_host_ops mvsd_ops = {
654 .request = mvsd_request,
3724482d 655 .get_ro = mmc_gpio_get_ro,
236caa7c
MS		 656 .set_ios = mvsd_set_ios,
657 .enable_sdio_irq = mvsd_enable_sdio_irq,
658};
659
63a9332b
AL		 660static void __init
661mv_conf_mbus_windows(struct mvsd_host *host,
662 const struct mbus_dram_target_info *dram)
236caa7c
MS		 663{
664 void __iomem *iobase = host->base;
665 int i;
666
667 for (i = 0; i < 4; i++) {
668 writel(0, iobase + MVSD_WINDOW_CTRL(i));
669 writel(0, iobase + MVSD_WINDOW_BASE(i));
670 }
671
672 for (i = 0; i < dram->num_cs; i++) {
63a9332b 673 const struct mbus_dram_window *cs = dram->cs + i;
236caa7c
MS		 674 writel(((cs->size - 1) & 0xffff0000) |
675 (cs->mbus_attr << 8) |
676 (dram->mbus_dram_target_id << 4) | 1,
677 iobase + MVSD_WINDOW_CTRL(i));
678 writel(cs->base, iobase + MVSD_WINDOW_BASE(i));
679 }
680}
681
682static int __init mvsd_probe(struct platform_device *pdev)
683{
684 struct mmc_host *mmc = NULL;
685 struct mvsd_host *host = NULL;
686 const struct mvsdio_platform_data *mvsd_data;
63a9332b 687 const struct mbus_dram_target_info *dram;
236caa7c
MS		 688 struct resource *r;
689 int ret, irq;
690
691 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
692 irq = platform_get_irq(pdev, 0);
693 mvsd_data = pdev->dev.platform_data;
694 if (!r || irq < 0 || !mvsd_data)
695 return -ENXIO;
696
236caa7c
MS		 697 mmc = mmc_alloc_host(sizeof(struct mvsd_host), &pdev->dev);
698 if (!mmc) {
699 ret = -ENOMEM;
700 goto out;
701 }
702
703 host = mmc_priv(mmc);
704 host->mmc = mmc;
705 host->dev = &pdev->dev;
236caa7c 706 host->base_clock = mvsd_data->clock / 2;
f42abc72 707 host->clk = ERR_PTR(-EINVAL);
236caa7c
MS		 708
709 mmc->ops = &mvsd_ops;
710
711 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
712 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
713 MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
714
715 mmc->f_min = DIV_ROUND_UP(host->base_clock, MVSD_BASE_DIV_MAX);
716 mmc->f_max = maxfreq;
717
718 mmc->max_blk_size = 2048;
719 mmc->max_blk_count = 65535;
720
a36274e0 721 mmc->max_segs = 1;
236caa7c
MS		 722 mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
723 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
724
725 spin_lock_init(&host->lock);
726
f42abc72 727 host->base = devm_request_and_ioremap(&pdev->dev, r);
236caa7c
MS		 728 if (!host->base) {
729 ret = -ENOMEM;
730 goto out;
731 }
732
733 /* (Re-)program MBUS remapping windows if we are asked to. */
63a9332b
AL		 734 dram = mv_mbus_dram_info();
735 if (dram)
736 mv_conf_mbus_windows(host, dram);
236caa7c
MS		 737
738 mvsd_power_down(host);
739
f42abc72 740 ret = devm_request_irq(&pdev->dev, irq, mvsd_irq, 0, DRIVER_NAME, host);
236caa7c 741 if (ret) {
a3c76eb9 742 pr_err("%s: cannot assign irq %d\n", DRIVER_NAME, irq);
236caa7c 743 goto out;
f42abc72 744 }
236caa7c 745
f4f7561e
AL		 746 /* Not all platforms can gate the clock, so it is not
747 an error if the clock does not exists. */
f42abc72
AL		 748 host->clk = devm_clk_get(&pdev->dev, NULL);
749 if (!IS_ERR(host->clk))
f4f7561e 750 clk_prepare_enable(host->clk);
f4f7561e 751
07728b77
TP		 752 if (gpio_is_valid(mvsd_data->gpio_card_detect)) {
753 ret = mmc_gpio_request_cd(mmc, mvsd_data->gpio_card_detect);
754 if (ret)
755 goto out;
756 } else
236caa7c
MS		 757 mmc->caps |= MMC_CAP_NEEDS_POLL;
758
3724482d 759 mmc_gpio_request_ro(mmc, mvsd_data->gpio_write_protect);
236caa7c
MS		 760
761 setup_timer(&host->timer, mvsd_timeout_timer, (unsigned long)host);
762 platform_set_drvdata(pdev, mmc);
763 ret = mmc_add_host(mmc);
764 if (ret)
765 goto out;
766
a3c76eb9 767 pr_notice("%s: %s driver initialized, ",
236caa7c 768 mmc_hostname(mmc), DRIVER_NAME);
07728b77 769 if (!(mmc->caps & MMC_CAP_NEEDS_POLL))
236caa7c 770 printk("using GPIO %d for card detection\n",
07728b77 771 mvsd_data->gpio_card_detect);
236caa7c
MS		 772 else
773 printk("lacking card detect (fall back to polling)\n");
774 return 0;
775
776out:
f42abc72 777 if (mmc) {
07728b77 778 mmc_gpio_free_cd(mmc);
3724482d 779 mmc_gpio_free_ro(mmc);
f42abc72 780 if (!IS_ERR(host->clk))
baffab28 781 clk_disable_unprepare(host->clk);
236caa7c 782 mmc_free_host(mmc);
f42abc72 783 }
236caa7c
MS		 784
785 return ret;
786}
787
788static int __exit mvsd_remove(struct platform_device *pdev)
789{
790 struct mmc_host *mmc = platform_get_drvdata(pdev);
791
f42abc72 792 struct mvsd_host *host = mmc_priv(mmc);
236caa7c 793
07728b77 794 mmc_gpio_free_cd(mmc);
3724482d 795 mmc_gpio_free_ro(mmc);
f42abc72
AL		 796 mmc_remove_host(mmc);
797 del_timer_sync(&host->timer);
798 mvsd_power_down(host);
799
800 if (!IS_ERR(host->clk))
801 clk_disable_unprepare(host->clk);
802 mmc_free_host(mmc);
f4f7561e 803
236caa7c
MS		 804 platform_set_drvdata(pdev, NULL);
805 return 0;
806}
807
808#ifdef CONFIG_PM
2e058a6f 809static int mvsd_suspend(struct platform_device *dev, pm_message_t state)
236caa7c
MS		 810{
811 struct mmc_host *mmc = platform_get_drvdata(dev);
812 int ret = 0;
813
2e058a6f 814 if (mmc)
1a13f8fa 815 ret = mmc_suspend_host(mmc);
236caa7c
MS		 816
817 return ret;
818}
819
2e058a6f 820static int mvsd_resume(struct platform_device *dev)
236caa7c 821{
2e058a6f 822 struct mmc_host *mmc = platform_get_drvdata(dev);
236caa7c
MS		 823 int ret = 0;
824
2e058a6f 825 if (mmc)
236caa7c
MS		 826 ret = mmc_resume_host(mmc);
827
828 return ret;
829}
830#else
831#define mvsd_suspend NULL
832#define mvsd_resume NULL
833#endif
834
835static struct platform_driver mvsd_driver = {
836 .remove = __exit_p(mvsd_remove),
837 .suspend = mvsd_suspend,
838 .resume = mvsd_resume,
839 .driver = {
840 .name = DRIVER_NAME,
841 },
842};
843
844static int __init mvsd_init(void)
845{
846 return platform_driver_probe(&mvsd_driver, mvsd_probe);
847}
848
849static void __exit mvsd_exit(void)
850{
851 platform_driver_unregister(&mvsd_driver);
852}
853
854module_init(mvsd_init);
855module_exit(mvsd_exit);
856
857/* maximum card clock frequency (default 50MHz) */
858module_param(maxfreq, int, 0);
859
860/* force PIO transfers all the time */
861module_param(nodma, int, 0);
862
863MODULE_AUTHOR("Maen Suleiman, Nicolas Pitre");
864MODULE_DESCRIPTION("Marvell MMC,SD,SDIO Host Controller driver");
865MODULE_LICENSE("GPL");
703aaced 866MODULE_ALIAS("platform:mvsdio");
Linux kernel - Deliverables
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