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236caa7c MS |
1 | /* |
2 | * Marvell MMC/SD/SDIO driver | |
3 | * | |
4 | * Authors: Maen Suleiman, Nicolas Pitre | |
5 | * Copyright (C) 2008-2009 Marvell Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/mbus.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/dma-mapping.h> | |
20 | #include <linux/scatterlist.h> | |
21 | #include <linux/irq.h> | |
f4f7561e | 22 | #include <linux/clk.h> |
236caa7c MS |
23 | #include <linux/gpio.h> |
24 | #include <linux/mmc/host.h> | |
25 | ||
26 | #include <asm/sizes.h> | |
27 | #include <asm/unaligned.h> | |
c02cecb9 | 28 | #include <linux/platform_data/mmc-mvsdio.h> |
236caa7c MS |
29 | |
30 | #include "mvsdio.h" | |
31 | ||
32 | #define DRIVER_NAME "mvsdio" | |
33 | ||
34 | static int maxfreq = MVSD_CLOCKRATE_MAX; | |
35 | static int nodma; | |
36 | ||
37 | struct mvsd_host { | |
38 | void __iomem *base; | |
39 | struct mmc_request *mrq; | |
40 | spinlock_t lock; | |
41 | unsigned int xfer_mode; | |
42 | unsigned int intr_en; | |
43 | unsigned int ctrl; | |
44 | unsigned int pio_size; | |
45 | void *pio_ptr; | |
46 | unsigned int sg_frags; | |
47 | unsigned int ns_per_clk; | |
48 | unsigned int clock; | |
49 | unsigned int base_clock; | |
50 | struct timer_list timer; | |
51 | struct mmc_host *mmc; | |
52 | struct device *dev; | |
53 | struct resource *res; | |
54 | int irq; | |
f4f7561e | 55 | struct clk *clk; |
236caa7c MS |
56 | int gpio_card_detect; |
57 | int gpio_write_protect; | |
58 | }; | |
59 | ||
60 | #define mvsd_write(offs, val) writel(val, iobase + (offs)) | |
61 | #define mvsd_read(offs) readl(iobase + (offs)) | |
62 | ||
63 | static int mvsd_setup_data(struct mvsd_host *host, struct mmc_data *data) | |
64 | { | |
65 | void __iomem *iobase = host->base; | |
66 | unsigned int tmout; | |
67 | int tmout_index; | |
68 | ||
a6d297f0 NP |
69 | /* |
70 | * Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE | |
71 | * register is sometimes not set before a while when some | |
72 | * "unusual" data block sizes are used (such as with the SWITCH | |
73 | * command), even despite the fact that the XFER_DONE interrupt | |
74 | * was raised. And if another data transfer starts before | |
75 | * this bit comes to good sense (which eventually happens by | |
76 | * itself) then the new transfer simply fails with a timeout. | |
77 | */ | |
78 | if (!(mvsd_read(MVSD_HW_STATE) & (1 << 13))) { | |
79 | unsigned long t = jiffies + HZ; | |
80 | unsigned int hw_state, count = 0; | |
81 | do { | |
82 | if (time_after(jiffies, t)) { | |
83 | dev_warn(host->dev, "FIFO_EMPTY bit missing\n"); | |
84 | break; | |
85 | } | |
86 | hw_state = mvsd_read(MVSD_HW_STATE); | |
87 | count++; | |
88 | } while (!(hw_state & (1 << 13))); | |
89 | dev_dbg(host->dev, "*** wait for FIFO_EMPTY bit " | |
90 | "(hw=0x%04x, count=%d, jiffies=%ld)\n", | |
91 | hw_state, count, jiffies - (t - HZ)); | |
92 | } | |
93 | ||
236caa7c MS |
94 | /* If timeout=0 then maximum timeout index is used. */ |
95 | tmout = DIV_ROUND_UP(data->timeout_ns, host->ns_per_clk); | |
96 | tmout += data->timeout_clks; | |
97 | tmout_index = fls(tmout - 1) - 12; | |
98 | if (tmout_index < 0) | |
99 | tmout_index = 0; | |
100 | if (tmout_index > MVSD_HOST_CTRL_TMOUT_MAX) | |
101 | tmout_index = MVSD_HOST_CTRL_TMOUT_MAX; | |
102 | ||
103 | dev_dbg(host->dev, "data %s at 0x%08x: blocks=%d blksz=%d tmout=%u (%d)\n", | |
104 | (data->flags & MMC_DATA_READ) ? "read" : "write", | |
105 | (u32)sg_virt(data->sg), data->blocks, data->blksz, | |
106 | tmout, tmout_index); | |
107 | ||
108 | host->ctrl &= ~MVSD_HOST_CTRL_TMOUT_MASK; | |
109 | host->ctrl |= MVSD_HOST_CTRL_TMOUT(tmout_index); | |
110 | mvsd_write(MVSD_HOST_CTRL, host->ctrl); | |
111 | mvsd_write(MVSD_BLK_COUNT, data->blocks); | |
112 | mvsd_write(MVSD_BLK_SIZE, data->blksz); | |
113 | ||
114 | if (nodma || (data->blksz | data->sg->offset) & 3) { | |
115 | /* | |
116 | * We cannot do DMA on a buffer which offset or size | |
117 | * is not aligned on a 4-byte boundary. | |
118 | */ | |
119 | host->pio_size = data->blocks * data->blksz; | |
120 | host->pio_ptr = sg_virt(data->sg); | |
121 | if (!nodma) | |
a3c76eb9 | 122 | pr_debug("%s: fallback to PIO for data " |
236caa7c MS |
123 | "at 0x%p size %d\n", |
124 | mmc_hostname(host->mmc), | |
125 | host->pio_ptr, host->pio_size); | |
126 | return 1; | |
127 | } else { | |
128 | dma_addr_t phys_addr; | |
129 | int dma_dir = (data->flags & MMC_DATA_READ) ? | |
130 | DMA_FROM_DEVICE : DMA_TO_DEVICE; | |
131 | host->sg_frags = dma_map_sg(mmc_dev(host->mmc), data->sg, | |
132 | data->sg_len, dma_dir); | |
133 | phys_addr = sg_dma_address(data->sg); | |
134 | mvsd_write(MVSD_SYS_ADDR_LOW, (u32)phys_addr & 0xffff); | |
135 | mvsd_write(MVSD_SYS_ADDR_HI, (u32)phys_addr >> 16); | |
136 | return 0; | |
137 | } | |
138 | } | |
139 | ||
140 | static void mvsd_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
141 | { | |
142 | struct mvsd_host *host = mmc_priv(mmc); | |
143 | void __iomem *iobase = host->base; | |
144 | struct mmc_command *cmd = mrq->cmd; | |
145 | u32 cmdreg = 0, xfer = 0, intr = 0; | |
146 | unsigned long flags; | |
147 | ||
148 | BUG_ON(host->mrq != NULL); | |
149 | host->mrq = mrq; | |
150 | ||
151 | dev_dbg(host->dev, "cmd %d (hw state 0x%04x)\n", | |
152 | cmd->opcode, mvsd_read(MVSD_HW_STATE)); | |
153 | ||
154 | cmdreg = MVSD_CMD_INDEX(cmd->opcode); | |
155 | ||
156 | if (cmd->flags & MMC_RSP_BUSY) | |
157 | cmdreg |= MVSD_CMD_RSP_48BUSY; | |
158 | else if (cmd->flags & MMC_RSP_136) | |
159 | cmdreg |= MVSD_CMD_RSP_136; | |
160 | else if (cmd->flags & MMC_RSP_PRESENT) | |
161 | cmdreg |= MVSD_CMD_RSP_48; | |
162 | else | |
163 | cmdreg |= MVSD_CMD_RSP_NONE; | |
164 | ||
165 | if (cmd->flags & MMC_RSP_CRC) | |
166 | cmdreg |= MVSD_CMD_CHECK_CMDCRC; | |
167 | ||
168 | if (cmd->flags & MMC_RSP_OPCODE) | |
169 | cmdreg |= MVSD_CMD_INDX_CHECK; | |
170 | ||
171 | if (cmd->flags & MMC_RSP_PRESENT) { | |
172 | cmdreg |= MVSD_UNEXPECTED_RESP; | |
173 | intr |= MVSD_NOR_UNEXP_RSP; | |
174 | } | |
175 | ||
176 | if (mrq->data) { | |
177 | struct mmc_data *data = mrq->data; | |
178 | int pio; | |
179 | ||
180 | cmdreg |= MVSD_CMD_DATA_PRESENT | MVSD_CMD_CHECK_DATACRC16; | |
181 | xfer |= MVSD_XFER_MODE_HW_WR_DATA_EN; | |
182 | if (data->flags & MMC_DATA_READ) | |
183 | xfer |= MVSD_XFER_MODE_TO_HOST; | |
184 | ||
185 | pio = mvsd_setup_data(host, data); | |
186 | if (pio) { | |
187 | xfer |= MVSD_XFER_MODE_PIO; | |
188 | /* PIO section of mvsd_irq has comments on those bits */ | |
189 | if (data->flags & MMC_DATA_WRITE) | |
190 | intr |= MVSD_NOR_TX_AVAIL; | |
191 | else if (host->pio_size > 32) | |
192 | intr |= MVSD_NOR_RX_FIFO_8W; | |
193 | else | |
194 | intr |= MVSD_NOR_RX_READY; | |
195 | } | |
196 | ||
197 | if (data->stop) { | |
198 | struct mmc_command *stop = data->stop; | |
199 | u32 cmd12reg = 0; | |
200 | ||
201 | mvsd_write(MVSD_AUTOCMD12_ARG_LOW, stop->arg & 0xffff); | |
202 | mvsd_write(MVSD_AUTOCMD12_ARG_HI, stop->arg >> 16); | |
203 | ||
204 | if (stop->flags & MMC_RSP_BUSY) | |
205 | cmd12reg |= MVSD_AUTOCMD12_BUSY; | |
206 | if (stop->flags & MMC_RSP_OPCODE) | |
207 | cmd12reg |= MVSD_AUTOCMD12_INDX_CHECK; | |
208 | cmd12reg |= MVSD_AUTOCMD12_INDEX(stop->opcode); | |
209 | mvsd_write(MVSD_AUTOCMD12_CMD, cmd12reg); | |
210 | ||
211 | xfer |= MVSD_XFER_MODE_AUTO_CMD12; | |
212 | intr |= MVSD_NOR_AUTOCMD12_DONE; | |
213 | } else { | |
214 | intr |= MVSD_NOR_XFER_DONE; | |
215 | } | |
216 | } else { | |
217 | intr |= MVSD_NOR_CMD_DONE; | |
218 | } | |
219 | ||
220 | mvsd_write(MVSD_ARG_LOW, cmd->arg & 0xffff); | |
221 | mvsd_write(MVSD_ARG_HI, cmd->arg >> 16); | |
222 | ||
223 | spin_lock_irqsave(&host->lock, flags); | |
224 | ||
225 | host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN; | |
226 | host->xfer_mode |= xfer; | |
227 | mvsd_write(MVSD_XFER_MODE, host->xfer_mode); | |
228 | ||
229 | mvsd_write(MVSD_NOR_INTR_STATUS, ~MVSD_NOR_CARD_INT); | |
230 | mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff); | |
231 | mvsd_write(MVSD_CMD, cmdreg); | |
232 | ||
233 | host->intr_en &= MVSD_NOR_CARD_INT; | |
234 | host->intr_en |= intr | MVSD_NOR_ERROR; | |
235 | mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); | |
236 | mvsd_write(MVSD_ERR_INTR_EN, 0xffff); | |
237 | ||
238 | mod_timer(&host->timer, jiffies + 5 * HZ); | |
239 | ||
240 | spin_unlock_irqrestore(&host->lock, flags); | |
241 | } | |
242 | ||
243 | static u32 mvsd_finish_cmd(struct mvsd_host *host, struct mmc_command *cmd, | |
244 | u32 err_status) | |
245 | { | |
246 | void __iomem *iobase = host->base; | |
247 | ||
248 | if (cmd->flags & MMC_RSP_136) { | |
249 | unsigned int response[8], i; | |
250 | for (i = 0; i < 8; i++) | |
251 | response[i] = mvsd_read(MVSD_RSP(i)); | |
252 | cmd->resp[0] = ((response[0] & 0x03ff) << 22) | | |
253 | ((response[1] & 0xffff) << 6) | | |
254 | ((response[2] & 0xfc00) >> 10); | |
255 | cmd->resp[1] = ((response[2] & 0x03ff) << 22) | | |
256 | ((response[3] & 0xffff) << 6) | | |
257 | ((response[4] & 0xfc00) >> 10); | |
258 | cmd->resp[2] = ((response[4] & 0x03ff) << 22) | | |
259 | ((response[5] & 0xffff) << 6) | | |
260 | ((response[6] & 0xfc00) >> 10); | |
261 | cmd->resp[3] = ((response[6] & 0x03ff) << 22) | | |
262 | ((response[7] & 0x3fff) << 8); | |
263 | } else if (cmd->flags & MMC_RSP_PRESENT) { | |
264 | unsigned int response[3], i; | |
265 | for (i = 0; i < 3; i++) | |
266 | response[i] = mvsd_read(MVSD_RSP(i)); | |
267 | cmd->resp[0] = ((response[2] & 0x003f) << (8 - 8)) | | |
268 | ((response[1] & 0xffff) << (14 - 8)) | | |
269 | ((response[0] & 0x03ff) << (30 - 8)); | |
270 | cmd->resp[1] = ((response[0] & 0xfc00) >> 10); | |
271 | cmd->resp[2] = 0; | |
272 | cmd->resp[3] = 0; | |
273 | } | |
274 | ||
275 | if (err_status & MVSD_ERR_CMD_TIMEOUT) { | |
276 | cmd->error = -ETIMEDOUT; | |
277 | } else if (err_status & (MVSD_ERR_CMD_CRC | MVSD_ERR_CMD_ENDBIT | | |
278 | MVSD_ERR_CMD_INDEX | MVSD_ERR_CMD_STARTBIT)) { | |
279 | cmd->error = -EILSEQ; | |
280 | } | |
281 | err_status &= ~(MVSD_ERR_CMD_TIMEOUT | MVSD_ERR_CMD_CRC | | |
282 | MVSD_ERR_CMD_ENDBIT | MVSD_ERR_CMD_INDEX | | |
283 | MVSD_ERR_CMD_STARTBIT); | |
284 | ||
285 | return err_status; | |
286 | } | |
287 | ||
288 | static u32 mvsd_finish_data(struct mvsd_host *host, struct mmc_data *data, | |
289 | u32 err_status) | |
290 | { | |
291 | void __iomem *iobase = host->base; | |
292 | ||
293 | if (host->pio_ptr) { | |
294 | host->pio_ptr = NULL; | |
295 | host->pio_size = 0; | |
296 | } else { | |
297 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_frags, | |
298 | (data->flags & MMC_DATA_READ) ? | |
299 | DMA_FROM_DEVICE : DMA_TO_DEVICE); | |
300 | } | |
301 | ||
302 | if (err_status & MVSD_ERR_DATA_TIMEOUT) | |
303 | data->error = -ETIMEDOUT; | |
304 | else if (err_status & (MVSD_ERR_DATA_CRC | MVSD_ERR_DATA_ENDBIT)) | |
305 | data->error = -EILSEQ; | |
306 | else if (err_status & MVSD_ERR_XFER_SIZE) | |
307 | data->error = -EBADE; | |
308 | err_status &= ~(MVSD_ERR_DATA_TIMEOUT | MVSD_ERR_DATA_CRC | | |
309 | MVSD_ERR_DATA_ENDBIT | MVSD_ERR_XFER_SIZE); | |
310 | ||
311 | dev_dbg(host->dev, "data done: blocks_left=%d, bytes_left=%d\n", | |
312 | mvsd_read(MVSD_CURR_BLK_LEFT), mvsd_read(MVSD_CURR_BYTE_LEFT)); | |
313 | data->bytes_xfered = | |
314 | (data->blocks - mvsd_read(MVSD_CURR_BLK_LEFT)) * data->blksz; | |
315 | /* We can't be sure about the last block when errors are detected */ | |
316 | if (data->bytes_xfered && data->error) | |
317 | data->bytes_xfered -= data->blksz; | |
318 | ||
319 | /* Handle Auto cmd 12 response */ | |
320 | if (data->stop) { | |
321 | unsigned int response[3], i; | |
322 | for (i = 0; i < 3; i++) | |
323 | response[i] = mvsd_read(MVSD_AUTO_RSP(i)); | |
324 | data->stop->resp[0] = ((response[2] & 0x003f) << (8 - 8)) | | |
325 | ((response[1] & 0xffff) << (14 - 8)) | | |
326 | ((response[0] & 0x03ff) << (30 - 8)); | |
327 | data->stop->resp[1] = ((response[0] & 0xfc00) >> 10); | |
328 | data->stop->resp[2] = 0; | |
329 | data->stop->resp[3] = 0; | |
330 | ||
331 | if (err_status & MVSD_ERR_AUTOCMD12) { | |
332 | u32 err_cmd12 = mvsd_read(MVSD_AUTOCMD12_ERR_STATUS); | |
333 | dev_dbg(host->dev, "c12err 0x%04x\n", err_cmd12); | |
334 | if (err_cmd12 & MVSD_AUTOCMD12_ERR_NOTEXE) | |
335 | data->stop->error = -ENOEXEC; | |
336 | else if (err_cmd12 & MVSD_AUTOCMD12_ERR_TIMEOUT) | |
337 | data->stop->error = -ETIMEDOUT; | |
338 | else if (err_cmd12) | |
339 | data->stop->error = -EILSEQ; | |
340 | err_status &= ~MVSD_ERR_AUTOCMD12; | |
341 | } | |
342 | } | |
343 | ||
344 | return err_status; | |
345 | } | |
346 | ||
347 | static irqreturn_t mvsd_irq(int irq, void *dev) | |
348 | { | |
349 | struct mvsd_host *host = dev; | |
350 | void __iomem *iobase = host->base; | |
351 | u32 intr_status, intr_done_mask; | |
352 | int irq_handled = 0; | |
353 | ||
354 | intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); | |
355 | dev_dbg(host->dev, "intr 0x%04x intr_en 0x%04x hw_state 0x%04x\n", | |
356 | intr_status, mvsd_read(MVSD_NOR_INTR_EN), | |
357 | mvsd_read(MVSD_HW_STATE)); | |
358 | ||
359 | spin_lock(&host->lock); | |
360 | ||
361 | /* PIO handling, if needed. Messy business... */ | |
362 | if (host->pio_size && | |
363 | (intr_status & host->intr_en & | |
364 | (MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W))) { | |
365 | u16 *p = host->pio_ptr; | |
366 | int s = host->pio_size; | |
367 | while (s >= 32 && (intr_status & MVSD_NOR_RX_FIFO_8W)) { | |
368 | readsw(iobase + MVSD_FIFO, p, 16); | |
369 | p += 16; | |
370 | s -= 32; | |
371 | intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); | |
372 | } | |
373 | /* | |
374 | * Normally we'd use < 32 here, but the RX_FIFO_8W bit | |
375 | * doesn't appear to assert when there is exactly 32 bytes | |
376 | * (8 words) left to fetch in a transfer. | |
377 | */ | |
378 | if (s <= 32) { | |
379 | while (s >= 4 && (intr_status & MVSD_NOR_RX_READY)) { | |
380 | put_unaligned(mvsd_read(MVSD_FIFO), p++); | |
381 | put_unaligned(mvsd_read(MVSD_FIFO), p++); | |
382 | s -= 4; | |
383 | intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); | |
384 | } | |
385 | if (s && s < 4 && (intr_status & MVSD_NOR_RX_READY)) { | |
386 | u16 val[2] = {0, 0}; | |
387 | val[0] = mvsd_read(MVSD_FIFO); | |
388 | val[1] = mvsd_read(MVSD_FIFO); | |
6cdbf734 | 389 | memcpy(p, ((void *)&val) + 4 - s, s); |
236caa7c MS |
390 | s = 0; |
391 | intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); | |
392 | } | |
393 | if (s == 0) { | |
394 | host->intr_en &= | |
395 | ~(MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W); | |
396 | mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); | |
397 | } else if (host->intr_en & MVSD_NOR_RX_FIFO_8W) { | |
398 | host->intr_en &= ~MVSD_NOR_RX_FIFO_8W; | |
399 | host->intr_en |= MVSD_NOR_RX_READY; | |
400 | mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); | |
401 | } | |
402 | } | |
403 | dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n", | |
404 | s, intr_status, mvsd_read(MVSD_HW_STATE)); | |
405 | host->pio_ptr = p; | |
406 | host->pio_size = s; | |
407 | irq_handled = 1; | |
408 | } else if (host->pio_size && | |
409 | (intr_status & host->intr_en & | |
410 | (MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W))) { | |
411 | u16 *p = host->pio_ptr; | |
412 | int s = host->pio_size; | |
413 | /* | |
414 | * The TX_FIFO_8W bit is unreliable. When set, bursting | |
415 | * 16 halfwords all at once in the FIFO drops data. Actually | |
416 | * TX_AVAIL does go off after only one word is pushed even if | |
417 | * TX_FIFO_8W remains set. | |
418 | */ | |
419 | while (s >= 4 && (intr_status & MVSD_NOR_TX_AVAIL)) { | |
420 | mvsd_write(MVSD_FIFO, get_unaligned(p++)); | |
421 | mvsd_write(MVSD_FIFO, get_unaligned(p++)); | |
422 | s -= 4; | |
423 | intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); | |
424 | } | |
425 | if (s < 4) { | |
426 | if (s && (intr_status & MVSD_NOR_TX_AVAIL)) { | |
427 | u16 val[2] = {0, 0}; | |
6cdbf734 | 428 | memcpy(((void *)&val) + 4 - s, p, s); |
236caa7c MS |
429 | mvsd_write(MVSD_FIFO, val[0]); |
430 | mvsd_write(MVSD_FIFO, val[1]); | |
431 | s = 0; | |
432 | intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); | |
433 | } | |
434 | if (s == 0) { | |
435 | host->intr_en &= | |
436 | ~(MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W); | |
437 | mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); | |
438 | } | |
439 | } | |
440 | dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n", | |
441 | s, intr_status, mvsd_read(MVSD_HW_STATE)); | |
442 | host->pio_ptr = p; | |
443 | host->pio_size = s; | |
444 | irq_handled = 1; | |
445 | } | |
446 | ||
447 | mvsd_write(MVSD_NOR_INTR_STATUS, intr_status); | |
448 | ||
449 | intr_done_mask = MVSD_NOR_CARD_INT | MVSD_NOR_RX_READY | | |
450 | MVSD_NOR_RX_FIFO_8W | MVSD_NOR_TX_FIFO_8W; | |
451 | if (intr_status & host->intr_en & ~intr_done_mask) { | |
452 | struct mmc_request *mrq = host->mrq; | |
453 | struct mmc_command *cmd = mrq->cmd; | |
454 | u32 err_status = 0; | |
455 | ||
456 | del_timer(&host->timer); | |
457 | host->mrq = NULL; | |
458 | ||
459 | host->intr_en &= MVSD_NOR_CARD_INT; | |
460 | mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); | |
461 | mvsd_write(MVSD_ERR_INTR_EN, 0); | |
462 | ||
463 | spin_unlock(&host->lock); | |
464 | ||
465 | if (intr_status & MVSD_NOR_UNEXP_RSP) { | |
466 | cmd->error = -EPROTO; | |
467 | } else if (intr_status & MVSD_NOR_ERROR) { | |
468 | err_status = mvsd_read(MVSD_ERR_INTR_STATUS); | |
469 | dev_dbg(host->dev, "err 0x%04x\n", err_status); | |
470 | } | |
471 | ||
472 | err_status = mvsd_finish_cmd(host, cmd, err_status); | |
473 | if (mrq->data) | |
474 | err_status = mvsd_finish_data(host, mrq->data, err_status); | |
475 | if (err_status) { | |
a3c76eb9 | 476 | pr_err("%s: unhandled error status %#04x\n", |
236caa7c MS |
477 | mmc_hostname(host->mmc), err_status); |
478 | cmd->error = -ENOMSG; | |
479 | } | |
480 | ||
481 | mmc_request_done(host->mmc, mrq); | |
482 | irq_handled = 1; | |
483 | } else | |
484 | spin_unlock(&host->lock); | |
485 | ||
486 | if (intr_status & MVSD_NOR_CARD_INT) { | |
487 | mmc_signal_sdio_irq(host->mmc); | |
488 | irq_handled = 1; | |
489 | } | |
490 | ||
491 | if (irq_handled) | |
492 | return IRQ_HANDLED; | |
493 | ||
a3c76eb9 | 494 | pr_err("%s: unhandled interrupt status=0x%04x en=0x%04x " |
236caa7c MS |
495 | "pio=%d\n", mmc_hostname(host->mmc), intr_status, |
496 | host->intr_en, host->pio_size); | |
497 | return IRQ_NONE; | |
498 | } | |
499 | ||
500 | static void mvsd_timeout_timer(unsigned long data) | |
501 | { | |
502 | struct mvsd_host *host = (struct mvsd_host *)data; | |
503 | void __iomem *iobase = host->base; | |
504 | struct mmc_request *mrq; | |
505 | unsigned long flags; | |
506 | ||
507 | spin_lock_irqsave(&host->lock, flags); | |
508 | mrq = host->mrq; | |
509 | if (mrq) { | |
a3c76eb9 | 510 | pr_err("%s: Timeout waiting for hardware interrupt.\n", |
236caa7c | 511 | mmc_hostname(host->mmc)); |
a3c76eb9 | 512 | pr_err("%s: hw_state=0x%04x, intr_status=0x%04x " |
236caa7c MS |
513 | "intr_en=0x%04x\n", mmc_hostname(host->mmc), |
514 | mvsd_read(MVSD_HW_STATE), | |
515 | mvsd_read(MVSD_NOR_INTR_STATUS), | |
516 | mvsd_read(MVSD_NOR_INTR_EN)); | |
517 | ||
518 | host->mrq = NULL; | |
519 | ||
520 | mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW); | |
521 | ||
522 | host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN; | |
523 | mvsd_write(MVSD_XFER_MODE, host->xfer_mode); | |
524 | ||
525 | host->intr_en &= MVSD_NOR_CARD_INT; | |
526 | mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); | |
527 | mvsd_write(MVSD_ERR_INTR_EN, 0); | |
528 | mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff); | |
529 | ||
530 | mrq->cmd->error = -ETIMEDOUT; | |
531 | mvsd_finish_cmd(host, mrq->cmd, 0); | |
532 | if (mrq->data) { | |
533 | mrq->data->error = -ETIMEDOUT; | |
534 | mvsd_finish_data(host, mrq->data, 0); | |
535 | } | |
536 | } | |
537 | spin_unlock_irqrestore(&host->lock, flags); | |
538 | ||
539 | if (mrq) | |
540 | mmc_request_done(host->mmc, mrq); | |
541 | } | |
542 | ||
543 | static irqreturn_t mvsd_card_detect_irq(int irq, void *dev) | |
544 | { | |
545 | struct mvsd_host *host = dev; | |
546 | mmc_detect_change(host->mmc, msecs_to_jiffies(100)); | |
547 | return IRQ_HANDLED; | |
548 | } | |
549 | ||
550 | static void mvsd_enable_sdio_irq(struct mmc_host *mmc, int enable) | |
551 | { | |
552 | struct mvsd_host *host = mmc_priv(mmc); | |
553 | void __iomem *iobase = host->base; | |
554 | unsigned long flags; | |
555 | ||
556 | spin_lock_irqsave(&host->lock, flags); | |
557 | if (enable) { | |
558 | host->xfer_mode |= MVSD_XFER_MODE_INT_CHK_EN; | |
559 | host->intr_en |= MVSD_NOR_CARD_INT; | |
560 | } else { | |
561 | host->xfer_mode &= ~MVSD_XFER_MODE_INT_CHK_EN; | |
562 | host->intr_en &= ~MVSD_NOR_CARD_INT; | |
563 | } | |
564 | mvsd_write(MVSD_XFER_MODE, host->xfer_mode); | |
565 | mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); | |
566 | spin_unlock_irqrestore(&host->lock, flags); | |
567 | } | |
568 | ||
569 | static int mvsd_get_ro(struct mmc_host *mmc) | |
570 | { | |
571 | struct mvsd_host *host = mmc_priv(mmc); | |
572 | ||
573 | if (host->gpio_write_protect) | |
574 | return gpio_get_value(host->gpio_write_protect); | |
575 | ||
576 | /* | |
577 | * Board doesn't support read only detection; let the mmc core | |
578 | * decide what to do. | |
579 | */ | |
580 | return -ENOSYS; | |
581 | } | |
582 | ||
583 | static void mvsd_power_up(struct mvsd_host *host) | |
584 | { | |
585 | void __iomem *iobase = host->base; | |
586 | dev_dbg(host->dev, "power up\n"); | |
587 | mvsd_write(MVSD_NOR_INTR_EN, 0); | |
588 | mvsd_write(MVSD_ERR_INTR_EN, 0); | |
589 | mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW); | |
590 | mvsd_write(MVSD_XFER_MODE, 0); | |
591 | mvsd_write(MVSD_NOR_STATUS_EN, 0xffff); | |
592 | mvsd_write(MVSD_ERR_STATUS_EN, 0xffff); | |
593 | mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff); | |
594 | mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff); | |
595 | } | |
596 | ||
597 | static void mvsd_power_down(struct mvsd_host *host) | |
598 | { | |
599 | void __iomem *iobase = host->base; | |
600 | dev_dbg(host->dev, "power down\n"); | |
601 | mvsd_write(MVSD_NOR_INTR_EN, 0); | |
602 | mvsd_write(MVSD_ERR_INTR_EN, 0); | |
603 | mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW); | |
604 | mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK); | |
605 | mvsd_write(MVSD_NOR_STATUS_EN, 0); | |
606 | mvsd_write(MVSD_ERR_STATUS_EN, 0); | |
607 | mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff); | |
608 | mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff); | |
609 | } | |
610 | ||
611 | static void mvsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
612 | { | |
613 | struct mvsd_host *host = mmc_priv(mmc); | |
614 | void __iomem *iobase = host->base; | |
615 | u32 ctrl_reg = 0; | |
616 | ||
617 | if (ios->power_mode == MMC_POWER_UP) | |
618 | mvsd_power_up(host); | |
619 | ||
620 | if (ios->clock == 0) { | |
621 | mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK); | |
622 | mvsd_write(MVSD_CLK_DIV, MVSD_BASE_DIV_MAX); | |
623 | host->clock = 0; | |
624 | dev_dbg(host->dev, "clock off\n"); | |
625 | } else if (ios->clock != host->clock) { | |
626 | u32 m = DIV_ROUND_UP(host->base_clock, ios->clock) - 1; | |
627 | if (m > MVSD_BASE_DIV_MAX) | |
628 | m = MVSD_BASE_DIV_MAX; | |
629 | mvsd_write(MVSD_CLK_DIV, m); | |
630 | host->clock = ios->clock; | |
631 | host->ns_per_clk = 1000000000 / (host->base_clock / (m+1)); | |
632 | dev_dbg(host->dev, "clock=%d (%d), div=0x%04x\n", | |
633 | ios->clock, host->base_clock / (m+1), m); | |
634 | } | |
635 | ||
636 | /* default transfer mode */ | |
637 | ctrl_reg |= MVSD_HOST_CTRL_BIG_ENDIAN; | |
638 | ctrl_reg &= ~MVSD_HOST_CTRL_LSB_FIRST; | |
639 | ||
640 | /* default to maximum timeout */ | |
641 | ctrl_reg |= MVSD_HOST_CTRL_TMOUT_MASK; | |
642 | ctrl_reg |= MVSD_HOST_CTRL_TMOUT_EN; | |
643 | ||
644 | if (ios->bus_mode == MMC_BUSMODE_PUSHPULL) | |
645 | ctrl_reg |= MVSD_HOST_CTRL_PUSH_PULL_EN; | |
646 | ||
647 | if (ios->bus_width == MMC_BUS_WIDTH_4) | |
648 | ctrl_reg |= MVSD_HOST_CTRL_DATA_WIDTH_4_BITS; | |
649 | ||
9ca6944c NP |
650 | /* |
651 | * The HI_SPEED_EN bit is causing trouble with many (but not all) | |
652 | * high speed SD, SDHC and SDIO cards. Not enabling that bit | |
653 | * makes all cards work. So let's just ignore that bit for now | |
654 | * and revisit this issue if problems for not enabling this bit | |
655 | * are ever reported. | |
656 | */ | |
657 | #if 0 | |
236caa7c MS |
658 | if (ios->timing == MMC_TIMING_MMC_HS || |
659 | ios->timing == MMC_TIMING_SD_HS) | |
660 | ctrl_reg |= MVSD_HOST_CTRL_HI_SPEED_EN; | |
9ca6944c | 661 | #endif |
236caa7c MS |
662 | |
663 | host->ctrl = ctrl_reg; | |
664 | mvsd_write(MVSD_HOST_CTRL, ctrl_reg); | |
665 | dev_dbg(host->dev, "ctrl 0x%04x: %s %s %s\n", ctrl_reg, | |
666 | (ctrl_reg & MVSD_HOST_CTRL_PUSH_PULL_EN) ? | |
667 | "push-pull" : "open-drain", | |
668 | (ctrl_reg & MVSD_HOST_CTRL_DATA_WIDTH_4_BITS) ? | |
669 | "4bit-width" : "1bit-width", | |
670 | (ctrl_reg & MVSD_HOST_CTRL_HI_SPEED_EN) ? | |
671 | "high-speed" : ""); | |
672 | ||
673 | if (ios->power_mode == MMC_POWER_OFF) | |
674 | mvsd_power_down(host); | |
675 | } | |
676 | ||
677 | static const struct mmc_host_ops mvsd_ops = { | |
678 | .request = mvsd_request, | |
679 | .get_ro = mvsd_get_ro, | |
680 | .set_ios = mvsd_set_ios, | |
681 | .enable_sdio_irq = mvsd_enable_sdio_irq, | |
682 | }; | |
683 | ||
63a9332b AL |
684 | static void __init |
685 | mv_conf_mbus_windows(struct mvsd_host *host, | |
686 | const struct mbus_dram_target_info *dram) | |
236caa7c MS |
687 | { |
688 | void __iomem *iobase = host->base; | |
689 | int i; | |
690 | ||
691 | for (i = 0; i < 4; i++) { | |
692 | writel(0, iobase + MVSD_WINDOW_CTRL(i)); | |
693 | writel(0, iobase + MVSD_WINDOW_BASE(i)); | |
694 | } | |
695 | ||
696 | for (i = 0; i < dram->num_cs; i++) { | |
63a9332b | 697 | const struct mbus_dram_window *cs = dram->cs + i; |
236caa7c MS |
698 | writel(((cs->size - 1) & 0xffff0000) | |
699 | (cs->mbus_attr << 8) | | |
700 | (dram->mbus_dram_target_id << 4) | 1, | |
701 | iobase + MVSD_WINDOW_CTRL(i)); | |
702 | writel(cs->base, iobase + MVSD_WINDOW_BASE(i)); | |
703 | } | |
704 | } | |
705 | ||
706 | static int __init mvsd_probe(struct platform_device *pdev) | |
707 | { | |
708 | struct mmc_host *mmc = NULL; | |
709 | struct mvsd_host *host = NULL; | |
710 | const struct mvsdio_platform_data *mvsd_data; | |
63a9332b | 711 | const struct mbus_dram_target_info *dram; |
236caa7c MS |
712 | struct resource *r; |
713 | int ret, irq; | |
714 | ||
715 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
716 | irq = platform_get_irq(pdev, 0); | |
717 | mvsd_data = pdev->dev.platform_data; | |
718 | if (!r || irq < 0 || !mvsd_data) | |
719 | return -ENXIO; | |
720 | ||
721 | r = request_mem_region(r->start, SZ_1K, DRIVER_NAME); | |
722 | if (!r) | |
723 | return -EBUSY; | |
724 | ||
725 | mmc = mmc_alloc_host(sizeof(struct mvsd_host), &pdev->dev); | |
726 | if (!mmc) { | |
727 | ret = -ENOMEM; | |
728 | goto out; | |
729 | } | |
730 | ||
731 | host = mmc_priv(mmc); | |
732 | host->mmc = mmc; | |
733 | host->dev = &pdev->dev; | |
734 | host->res = r; | |
735 | host->base_clock = mvsd_data->clock / 2; | |
736 | ||
737 | mmc->ops = &mvsd_ops; | |
738 | ||
739 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; | |
740 | mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ | | |
741 | MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; | |
742 | ||
743 | mmc->f_min = DIV_ROUND_UP(host->base_clock, MVSD_BASE_DIV_MAX); | |
744 | mmc->f_max = maxfreq; | |
745 | ||
746 | mmc->max_blk_size = 2048; | |
747 | mmc->max_blk_count = 65535; | |
748 | ||
a36274e0 | 749 | mmc->max_segs = 1; |
236caa7c MS |
750 | mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count; |
751 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; | |
752 | ||
753 | spin_lock_init(&host->lock); | |
754 | ||
755 | host->base = ioremap(r->start, SZ_4K); | |
756 | if (!host->base) { | |
757 | ret = -ENOMEM; | |
758 | goto out; | |
759 | } | |
760 | ||
761 | /* (Re-)program MBUS remapping windows if we are asked to. */ | |
63a9332b AL |
762 | dram = mv_mbus_dram_info(); |
763 | if (dram) | |
764 | mv_conf_mbus_windows(host, dram); | |
236caa7c MS |
765 | |
766 | mvsd_power_down(host); | |
767 | ||
768 | ret = request_irq(irq, mvsd_irq, 0, DRIVER_NAME, host); | |
769 | if (ret) { | |
a3c76eb9 | 770 | pr_err("%s: cannot assign irq %d\n", DRIVER_NAME, irq); |
236caa7c MS |
771 | goto out; |
772 | } else | |
773 | host->irq = irq; | |
774 | ||
f4f7561e AL |
775 | /* Not all platforms can gate the clock, so it is not |
776 | an error if the clock does not exists. */ | |
777 | host->clk = clk_get(&pdev->dev, NULL); | |
778 | if (!IS_ERR(host->clk)) { | |
779 | clk_prepare_enable(host->clk); | |
780 | } | |
781 | ||
236caa7c MS |
782 | if (mvsd_data->gpio_card_detect) { |
783 | ret = gpio_request(mvsd_data->gpio_card_detect, | |
784 | DRIVER_NAME " cd"); | |
785 | if (ret == 0) { | |
786 | gpio_direction_input(mvsd_data->gpio_card_detect); | |
787 | irq = gpio_to_irq(mvsd_data->gpio_card_detect); | |
788 | ret = request_irq(irq, mvsd_card_detect_irq, | |
789 | IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING, | |
790 | DRIVER_NAME " cd", host); | |
791 | if (ret == 0) | |
792 | host->gpio_card_detect = | |
793 | mvsd_data->gpio_card_detect; | |
794 | else | |
795 | gpio_free(mvsd_data->gpio_card_detect); | |
796 | } | |
797 | } | |
798 | if (!host->gpio_card_detect) | |
799 | mmc->caps |= MMC_CAP_NEEDS_POLL; | |
800 | ||
801 | if (mvsd_data->gpio_write_protect) { | |
802 | ret = gpio_request(mvsd_data->gpio_write_protect, | |
803 | DRIVER_NAME " wp"); | |
804 | if (ret == 0) { | |
805 | gpio_direction_input(mvsd_data->gpio_write_protect); | |
806 | host->gpio_write_protect = | |
807 | mvsd_data->gpio_write_protect; | |
808 | } | |
809 | } | |
810 | ||
811 | setup_timer(&host->timer, mvsd_timeout_timer, (unsigned long)host); | |
812 | platform_set_drvdata(pdev, mmc); | |
813 | ret = mmc_add_host(mmc); | |
814 | if (ret) | |
815 | goto out; | |
816 | ||
a3c76eb9 | 817 | pr_notice("%s: %s driver initialized, ", |
236caa7c MS |
818 | mmc_hostname(mmc), DRIVER_NAME); |
819 | if (host->gpio_card_detect) | |
820 | printk("using GPIO %d for card detection\n", | |
821 | host->gpio_card_detect); | |
822 | else | |
823 | printk("lacking card detect (fall back to polling)\n"); | |
824 | return 0; | |
825 | ||
826 | out: | |
827 | if (host) { | |
828 | if (host->irq) | |
829 | free_irq(host->irq, host); | |
830 | if (host->gpio_card_detect) { | |
831 | free_irq(gpio_to_irq(host->gpio_card_detect), host); | |
832 | gpio_free(host->gpio_card_detect); | |
833 | } | |
834 | if (host->gpio_write_protect) | |
835 | gpio_free(host->gpio_write_protect); | |
836 | if (host->base) | |
837 | iounmap(host->base); | |
838 | } | |
839 | if (r) | |
840 | release_resource(r); | |
841 | if (mmc) | |
baffab28 SB |
842 | if (!IS_ERR_OR_NULL(host->clk)) { |
843 | clk_disable_unprepare(host->clk); | |
844 | clk_put(host->clk); | |
845 | } | |
236caa7c MS |
846 | mmc_free_host(mmc); |
847 | ||
848 | return ret; | |
849 | } | |
850 | ||
851 | static int __exit mvsd_remove(struct platform_device *pdev) | |
852 | { | |
853 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
854 | ||
855 | if (mmc) { | |
856 | struct mvsd_host *host = mmc_priv(mmc); | |
857 | ||
858 | if (host->gpio_card_detect) { | |
859 | free_irq(gpio_to_irq(host->gpio_card_detect), host); | |
860 | gpio_free(host->gpio_card_detect); | |
861 | } | |
862 | mmc_remove_host(mmc); | |
863 | free_irq(host->irq, host); | |
864 | if (host->gpio_write_protect) | |
865 | gpio_free(host->gpio_write_protect); | |
866 | del_timer_sync(&host->timer); | |
867 | mvsd_power_down(host); | |
868 | iounmap(host->base); | |
869 | release_resource(host->res); | |
f4f7561e AL |
870 | |
871 | if (!IS_ERR(host->clk)) { | |
872 | clk_disable_unprepare(host->clk); | |
873 | clk_put(host->clk); | |
874 | } | |
236caa7c MS |
875 | mmc_free_host(mmc); |
876 | } | |
877 | platform_set_drvdata(pdev, NULL); | |
878 | return 0; | |
879 | } | |
880 | ||
881 | #ifdef CONFIG_PM | |
2e058a6f | 882 | static int mvsd_suspend(struct platform_device *dev, pm_message_t state) |
236caa7c MS |
883 | { |
884 | struct mmc_host *mmc = platform_get_drvdata(dev); | |
885 | int ret = 0; | |
886 | ||
2e058a6f | 887 | if (mmc) |
1a13f8fa | 888 | ret = mmc_suspend_host(mmc); |
236caa7c MS |
889 | |
890 | return ret; | |
891 | } | |
892 | ||
2e058a6f | 893 | static int mvsd_resume(struct platform_device *dev) |
236caa7c | 894 | { |
2e058a6f | 895 | struct mmc_host *mmc = platform_get_drvdata(dev); |
236caa7c MS |
896 | int ret = 0; |
897 | ||
2e058a6f | 898 | if (mmc) |
236caa7c MS |
899 | ret = mmc_resume_host(mmc); |
900 | ||
901 | return ret; | |
902 | } | |
903 | #else | |
904 | #define mvsd_suspend NULL | |
905 | #define mvsd_resume NULL | |
906 | #endif | |
907 | ||
908 | static struct platform_driver mvsd_driver = { | |
909 | .remove = __exit_p(mvsd_remove), | |
910 | .suspend = mvsd_suspend, | |
911 | .resume = mvsd_resume, | |
912 | .driver = { | |
913 | .name = DRIVER_NAME, | |
914 | }, | |
915 | }; | |
916 | ||
917 | static int __init mvsd_init(void) | |
918 | { | |
919 | return platform_driver_probe(&mvsd_driver, mvsd_probe); | |
920 | } | |
921 | ||
922 | static void __exit mvsd_exit(void) | |
923 | { | |
924 | platform_driver_unregister(&mvsd_driver); | |
925 | } | |
926 | ||
927 | module_init(mvsd_init); | |
928 | module_exit(mvsd_exit); | |
929 | ||
930 | /* maximum card clock frequency (default 50MHz) */ | |
931 | module_param(maxfreq, int, 0); | |
932 | ||
933 | /* force PIO transfers all the time */ | |
934 | module_param(nodma, int, 0); | |
935 | ||
936 | MODULE_AUTHOR("Maen Suleiman, Nicolas Pitre"); | |
937 | MODULE_DESCRIPTION("Marvell MMC,SD,SDIO Host Controller driver"); | |
938 | MODULE_LICENSE("GPL"); | |
703aaced | 939 | MODULE_ALIAS("platform:mvsdio"); |