projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mmc: mxcmmc: constify mxcmci_devtype
[deliverable/linux.git] / drivers / mmc / host / mxcmmc.c
CommitLineData
d96be879
SH		 1/*
2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
3 *
4 * This is a driver for the SDHC controller found in Freescale MX2/MX3
5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
6 * Unlike the hardware found on MX1, this hardware just works and does
3ad2f3fb 7 * not need all the quirks found in imxmmc.c, hence the separate driver.
d96be879
SH		 8 *
9 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
10 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
11 *
12 * derived from pxamci.c by Russell King
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 *
18 */
19
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/ioport.h>
23#include <linux/platform_device.h>
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/blkdev.h>
27#include <linux/dma-mapping.h>
28#include <linux/mmc/host.h>
29#include <linux/mmc/card.h>
30#include <linux/delay.h>
31#include <linux/clk.h>
32#include <linux/io.h>
33#include <linux/gpio.h>
74b66954 34#include <linux/regulator/consumer.h>
f53fbde4 35#include <linux/dmaengine.h>
258aea76 36#include <linux/types.h>
7ff747c4
MP		 37#include <linux/of.h>
38#include <linux/of_device.h>
39#include <linux/of_dma.h>
40#include <linux/of_gpio.h>
bcf53524 41#include <linux/mmc/slot-gpio.h>
d96be879
SH		 42
43#include <asm/dma.h>
44#include <asm/irq.h>
82906b13 45#include <linux/platform_data/mmc-mxcmmc.h>
d96be879 46
82906b13 47#include <linux/platform_data/dma-imx.h>
d96be879 48
9563b1db 49#define DRIVER_NAME "mxc-mmc"
f6ad0a48 50#define MXCMCI_TIMEOUT_MS 10000
d96be879
SH		 51
52#define MMC_REG_STR_STP_CLK 0x00
53#define MMC_REG_STATUS 0x04
54#define MMC_REG_CLK_RATE 0x08
55#define MMC_REG_CMD_DAT_CONT 0x0C
56#define MMC_REG_RES_TO 0x10
57#define MMC_REG_READ_TO 0x14
58#define MMC_REG_BLK_LEN 0x18
59#define MMC_REG_NOB 0x1C
60#define MMC_REG_REV_NO 0x20
61#define MMC_REG_INT_CNTR 0x24
62#define MMC_REG_CMD 0x28
63#define MMC_REG_ARG 0x2C
64#define MMC_REG_RES_FIFO 0x34
65#define MMC_REG_BUFFER_ACCESS 0x38
66
67#define STR_STP_CLK_RESET (1 << 3)
68#define STR_STP_CLK_START_CLK (1 << 1)
69#define STR_STP_CLK_STOP_CLK (1 << 0)
70
71#define STATUS_CARD_INSERTION (1 << 31)
72#define STATUS_CARD_REMOVAL (1 << 30)
73#define STATUS_YBUF_EMPTY (1 << 29)
74#define STATUS_XBUF_EMPTY (1 << 28)
75#define STATUS_YBUF_FULL (1 << 27)
76#define STATUS_XBUF_FULL (1 << 26)
77#define STATUS_BUF_UND_RUN (1 << 25)
78#define STATUS_BUF_OVFL (1 << 24)
79#define STATUS_SDIO_INT_ACTIVE (1 << 14)
80#define STATUS_END_CMD_RESP (1 << 13)
81#define STATUS_WRITE_OP_DONE (1 << 12)
82#define STATUS_DATA_TRANS_DONE (1 << 11)
83#define STATUS_READ_OP_DONE (1 << 11)
84#define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
85#define STATUS_CARD_BUS_CLK_RUN (1 << 8)
86#define STATUS_BUF_READ_RDY (1 << 7)
87#define STATUS_BUF_WRITE_RDY (1 << 6)
88#define STATUS_RESP_CRC_ERR (1 << 5)
89#define STATUS_CRC_READ_ERR (1 << 3)
90#define STATUS_CRC_WRITE_ERR (1 << 2)
91#define STATUS_TIME_OUT_RESP (1 << 1)
92#define STATUS_TIME_OUT_READ (1 << 0)
93#define STATUS_ERR_MASK 0x2f
94
95#define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
96#define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
97#define CMD_DAT_CONT_START_READWAIT (1 << 10)
98#define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
99#define CMD_DAT_CONT_INIT (1 << 7)
100#define CMD_DAT_CONT_WRITE (1 << 4)
101#define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
102#define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
103#define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
104#define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
105
106#define INT_SDIO_INT_WKP_EN (1 << 18)
107#define INT_CARD_INSERTION_WKP_EN (1 << 17)
108#define INT_CARD_REMOVAL_WKP_EN (1 << 16)
109#define INT_CARD_INSERTION_EN (1 << 15)
110#define INT_CARD_REMOVAL_EN (1 << 14)
111#define INT_SDIO_IRQ_EN (1 << 13)
112#define INT_DAT0_EN (1 << 12)
113#define INT_BUF_READ_EN (1 << 4)
114#define INT_BUF_WRITE_EN (1 << 3)
115#define INT_END_CMD_RES_EN (1 << 2)
116#define INT_WRITE_OP_DONE_EN (1 << 1)
117#define INT_READ_OP_EN (1 << 0)
118
7f917a8d
SG		 119enum mxcmci_type {
120 IMX21_MMC,
121 IMX31_MMC,
c7ceab02 122 MPC512X_MMC,
7f917a8d
SG		 123};
124
d96be879
SH		 125struct mxcmci_host {
126 struct mmc_host *mmc;
127 struct resource *res;
128 void __iomem *base;
129 int irq;
130 int detect_irq;
f53fbde4
SH		 131 struct dma_chan *dma;
132 struct dma_async_tx_descriptor *desc;
d96be879 133 int do_dma;
16b3bf8c 134 int default_irq_mask;
f441b993 135 int use_sdio;
d96be879
SH		 136 unsigned int power_mode;
137 struct imxmmc_platform_data *pdata;
138
139 struct mmc_request *req;
140 struct mmc_command *cmd;
141 struct mmc_data *data;
142
d96be879
SH		 143 unsigned int datasize;
144 unsigned int dma_dir;
145
146 u16 rev_no;
147 unsigned int cmdat;
148
529aa29e
SH		 149 struct clk *clk_ipg;
150 struct clk *clk_per;
d96be879
SH		 151
152 int clock;
153
154 struct work_struct datawork;
f441b993 155 spinlock_t lock;
74b66954
AP		 156
157 struct regulator *vcc;
f53fbde4
SH		 158
159 int burstlen;
160 int dmareq;
161 struct dma_slave_config dma_slave_config;
162 struct imx_dma_data dma_data;
f6ad0a48
JM		 163
164 struct timer_list watchdog;
7f917a8d
SG		 165 enum mxcmci_type devtype;
166};
167
42477053 168static const struct platform_device_id mxcmci_devtype[] = {
7f917a8d
SG		 169 {
170 .name = "imx21-mmc",
171 .driver_data = IMX21_MMC,
172 }, {
173 .name = "imx31-mmc",
174 .driver_data = IMX31_MMC,
c7ceab02
AG		 175 }, {
176 .name = "mpc512x-sdhc",
177 .driver_data = MPC512X_MMC,
7f917a8d
SG		 178 }, {
179 /* sentinel */
180 }
d96be879 181};
7f917a8d
SG		 182MODULE_DEVICE_TABLE(platform, mxcmci_devtype);
183
7ff747c4
MP		 184static const struct of_device_id mxcmci_of_match[] = {
185 {
186 .compatible = "fsl,imx21-mmc",
187 .data = &mxcmci_devtype[IMX21_MMC],
188 }, {
189 .compatible = "fsl,imx31-mmc",
190 .data = &mxcmci_devtype[IMX31_MMC],
c7ceab02
AG		 191 }, {
192 .compatible = "fsl,mpc5121-sdhc",
193 .data = &mxcmci_devtype[MPC512X_MMC],
7ff747c4
MP		 194 }, {
195 /* sentinel */
196 }
197};
198MODULE_DEVICE_TABLE(of, mxcmci_of_match);
199
7f917a8d
SG		 200static inline int is_imx31_mmc(struct mxcmci_host *host)
201{
202 return host->devtype == IMX31_MMC;
203}
d96be879 204
c7ceab02
AG		 205static inline int is_mpc512x_mmc(struct mxcmci_host *host)
206{
207 return host->devtype == MPC512X_MMC;
208}
209
210static inline u32 mxcmci_readl(struct mxcmci_host *host, int reg)
211{
212 if (IS_ENABLED(CONFIG_PPC_MPC512x))
213 return ioread32be(host->base + reg);
214 else
215 return readl(host->base + reg);
216}
217
218static inline void mxcmci_writel(struct mxcmci_host *host, u32 val, int reg)
219{
220 if (IS_ENABLED(CONFIG_PPC_MPC512x))
221 iowrite32be(val, host->base + reg);
222 else
223 writel(val, host->base + reg);
224}
225
226static inline u16 mxcmci_readw(struct mxcmci_host *host, int reg)
227{
228 if (IS_ENABLED(CONFIG_PPC_MPC512x))
229 return ioread32be(host->base + reg);
230 else
231 return readw(host->base + reg);
232}
233
234static inline void mxcmci_writew(struct mxcmci_host *host, u16 val, int reg)
235{
236 if (IS_ENABLED(CONFIG_PPC_MPC512x))
237 iowrite32be(val, host->base + reg);
238 else
239 writew(val, host->base + reg);
240}
241
18489fa2
MF		 242static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
243
74b66954
AP		 244static inline void mxcmci_init_ocr(struct mxcmci_host *host)
245{
74b66954
AP		 246 host->vcc = regulator_get(mmc_dev(host->mmc), "vmmc");
247
248 if (IS_ERR(host->vcc)) {
249 host->vcc = NULL;
250 } else {
251 host->mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vcc);
252 if (host->pdata && host->pdata->ocr_avail)
253 dev_warn(mmc_dev(host->mmc),
254 "pdata->ocr_avail will not be used\n");
255 }
d078d242 256
74b66954
AP		 257 if (host->vcc == NULL) {
258 /* fall-back to platform data */
259 if (host->pdata && host->pdata->ocr_avail)
260 host->mmc->ocr_avail = host->pdata->ocr_avail;
261 else
262 host->mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
263 }
264}
265
d078d242
AP		 266static inline void mxcmci_set_power(struct mxcmci_host *host,
267 unsigned char power_mode,
268 unsigned int vdd)
74b66954 269{
d078d242
AP		 270 if (host->vcc) {
271 if (power_mode == MMC_POWER_UP)
272 mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
273 else if (power_mode == MMC_POWER_OFF)
274 mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
275 }
276
74b66954
AP		 277 if (host->pdata && host->pdata->setpower)
278 host->pdata->setpower(mmc_dev(host->mmc), vdd);
279}
280
d96be879
SH		 281static inline int mxcmci_use_dma(struct mxcmci_host *host)
282{
283 return host->do_dma;
284}
285
286static void mxcmci_softreset(struct mxcmci_host *host)
287{
288 int i;
289
4725f6f1
DM		 290 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n");
291
d96be879 292 /* reset sequence */
c7ceab02
AG		 293 mxcmci_writew(host, STR_STP_CLK_RESET, MMC_REG_STR_STP_CLK);
294 mxcmci_writew(host, STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
295 MMC_REG_STR_STP_CLK);
d96be879
SH		 296
297 for (i = 0; i < 8; i++)
c7ceab02 298 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
d96be879 299
c7ceab02 300 mxcmci_writew(host, 0xff, MMC_REG_RES_TO);
d96be879 301}
f53fbde4 302static int mxcmci_setup_dma(struct mmc_host *mmc);
d96be879 303
656217d2 304static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
d96be879
SH		 305{
306 unsigned int nob = data->blocks;
307 unsigned int blksz = data->blksz;
308 unsigned int datasize = nob * blksz;
d96be879 309 struct scatterlist *sg;
05f5799c 310 enum dma_transfer_direction slave_dirn;
f53fbde4
SH		 311 int i, nents;
312
d96be879
SH		 313 if (data->flags & MMC_DATA_STREAM)
314 nob = 0xffff;
315
316 host->data = data;
317 data->bytes_xfered = 0;
318
c7ceab02
AG		 319 mxcmci_writew(host, nob, MMC_REG_NOB);
320 mxcmci_writew(host, blksz, MMC_REG_BLK_LEN);
d96be879
SH		 321 host->datasize = datasize;
322
f53fbde4
SH		 323 if (!mxcmci_use_dma(host))
324 return 0;
325
d96be879 326 for_each_sg(data->sg, sg, data->sg_len, i) {
2cb53552 327 if (sg->offset & 3 || sg->length & 3 || sg->length < 512) {
d96be879 328 host->do_dma = 0;
656217d2 329 return 0;
d96be879
SH		 330 }
331 }
332
05f5799c 333 if (data->flags & MMC_DATA_READ) {
d96be879 334 host->dma_dir = DMA_FROM_DEVICE;
05f5799c
VK		 335 slave_dirn = DMA_DEV_TO_MEM;
336 } else {
d96be879 337 host->dma_dir = DMA_TO_DEVICE;
05f5799c
VK		 338 slave_dirn = DMA_MEM_TO_DEV;
339 }
d96be879 340
f53fbde4
SH		 341 nents = dma_map_sg(host->dma->device->dev, data->sg,
342 data->sg_len, host->dma_dir);
343 if (nents != data->sg_len)
344 return -EINVAL;
345
16052827 346 host->desc = dmaengine_prep_slave_sg(host->dma,
05f5799c 347 data->sg, data->sg_len, slave_dirn,
f53fbde4 348 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
d96be879 349
f53fbde4
SH		 350 if (!host->desc) {
351 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
352 host->dma_dir);
353 host->do_dma = 0;
354 return 0; /* Fall back to PIO */
656217d2 355 }
d96be879
SH		 356 wmb();
357
f53fbde4 358 dmaengine_submit(host->desc);
439aa0ef 359 dma_async_issue_pending(host->dma);
f53fbde4 360
f6ad0a48
JM		 361 mod_timer(&host->watchdog, jiffies + msecs_to_jiffies(MXCMCI_TIMEOUT_MS));
362
656217d2 363 return 0;
d96be879
SH		 364}
365
f6ad0a48
JM		 366static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat);
367static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat);
368
369static void mxcmci_dma_callback(void *data)
370{
371 struct mxcmci_host *host = data;
372 u32 stat;
373
374 del_timer(&host->watchdog);
375
c7ceab02
AG		 376 stat = mxcmci_readl(host, MMC_REG_STATUS);
377 mxcmci_writel(host, stat & ~STATUS_DATA_TRANS_DONE, MMC_REG_STATUS);
f6ad0a48
JM		 378
379 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
380
381 if (stat & STATUS_READ_OP_DONE)
c7ceab02 382 mxcmci_writel(host, STATUS_READ_OP_DONE, MMC_REG_STATUS);
f6ad0a48
JM		 383
384 mxcmci_data_done(host, stat);
385}
386
d96be879
SH		 387static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
388 unsigned int cmdat)
389{
16b3bf8c 390 u32 int_cntr = host->default_irq_mask;
f441b993
DM		 391 unsigned long flags;
392
d96be879
SH		 393 WARN_ON(host->cmd != NULL);
394 host->cmd = cmd;
395
396 switch (mmc_resp_type(cmd)) {
397 case MMC_RSP_R1: /* short CRC, OPCODE */
398 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
399 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
400 break;
401 case MMC_RSP_R2: /* long 136 bit + CRC */
402 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
403 break;
404 case MMC_RSP_R3: /* short */
405 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
406 break;
407 case MMC_RSP_NONE:
408 break;
409 default:
410 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n",
411 mmc_resp_type(cmd));
412 cmd->error = -EINVAL;
413 return -EINVAL;
414 }
415
f441b993
DM		 416 int_cntr = INT_END_CMD_RES_EN;
417
f6ad0a48
JM		 418 if (mxcmci_use_dma(host)) {
419 if (host->dma_dir == DMA_FROM_DEVICE) {
420 host->desc->callback = mxcmci_dma_callback;
421 host->desc->callback_param = host;
422 } else {
423 int_cntr |= INT_WRITE_OP_DONE_EN;
424 }
425 }
f441b993
DM		 426
427 spin_lock_irqsave(&host->lock, flags);
428 if (host->use_sdio)
429 int_cntr |= INT_SDIO_IRQ_EN;
c7ceab02 430 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
f441b993 431 spin_unlock_irqrestore(&host->lock, flags);
d96be879 432
c7ceab02
AG		 433 mxcmci_writew(host, cmd->opcode, MMC_REG_CMD);
434 mxcmci_writel(host, cmd->arg, MMC_REG_ARG);
435 mxcmci_writew(host, cmdat, MMC_REG_CMD_DAT_CONT);
d96be879
SH		 436
437 return 0;
438}
439
440static void mxcmci_finish_request(struct mxcmci_host *host,
441 struct mmc_request *req)
442{
16b3bf8c 443 u32 int_cntr = host->default_irq_mask;
f441b993
DM		 444 unsigned long flags;
445
446 spin_lock_irqsave(&host->lock, flags);
447 if (host->use_sdio)
448 int_cntr |= INT_SDIO_IRQ_EN;
c7ceab02 449 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
f441b993 450 spin_unlock_irqrestore(&host->lock, flags);
d96be879
SH		 451
452 host->req = NULL;
453 host->cmd = NULL;
454 host->data = NULL;
455
456 mmc_request_done(host->mmc, req);
457}
458
459static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
460{
461 struct mmc_data *data = host->data;
462 int data_error;
463
f6ad0a48 464 if (mxcmci_use_dma(host))
f53fbde4 465 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
d96be879 466 host->dma_dir);
d96be879
SH		 467
468 if (stat & STATUS_ERR_MASK) {
469 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
470 stat);
471 if (stat & STATUS_CRC_READ_ERR) {
4725f6f1 472 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__);
d96be879
SH		 473 data->error = -EILSEQ;
474 } else if (stat & STATUS_CRC_WRITE_ERR) {
475 u32 err_code = (stat >> 9) & 0x3;
4725f6f1
DM		 476 if (err_code == 2) { /* No CRC response */
477 dev_err(mmc_dev(host->mmc),
478 "%s: No CRC -ETIMEDOUT\n", __func__);
d96be879 479 data->error = -ETIMEDOUT;
4725f6f1
DM		 480 } else {
481 dev_err(mmc_dev(host->mmc),
482 "%s: -EILSEQ\n", __func__);
d96be879 483 data->error = -EILSEQ;
4725f6f1 484 }
d96be879 485 } else if (stat & STATUS_TIME_OUT_READ) {
4725f6f1
DM		 486 dev_err(mmc_dev(host->mmc),
487 "%s: read -ETIMEDOUT\n", __func__);
d96be879
SH		 488 data->error = -ETIMEDOUT;
489 } else {
4725f6f1 490 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__);
d96be879
SH		 491 data->error = -EIO;
492 }
493 } else {
494 data->bytes_xfered = host->datasize;
495 }
496
497 data_error = data->error;
498
499 host->data = NULL;
500
501 return data_error;
502}
503
504static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
505{
506 struct mmc_command *cmd = host->cmd;
507 int i;
508 u32 a, b, c;
509
510 if (!cmd)
511 return;
512
513 if (stat & STATUS_TIME_OUT_RESP) {
514 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
515 cmd->error = -ETIMEDOUT;
516 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
517 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
518 cmd->error = -EILSEQ;
519 }
520
521 if (cmd->flags & MMC_RSP_PRESENT) {
522 if (cmd->flags & MMC_RSP_136) {
523 for (i = 0; i < 4; i++) {
c7ceab02
AG		 524 a = mxcmci_readw(host, MMC_REG_RES_FIFO);
525 b = mxcmci_readw(host, MMC_REG_RES_FIFO);
d96be879
SH		 526 cmd->resp[i] = a << 16 | b;
527 }
528 } else {
c7ceab02
AG		 529 a = mxcmci_readw(host, MMC_REG_RES_FIFO);
530 b = mxcmci_readw(host, MMC_REG_RES_FIFO);
531 c = mxcmci_readw(host, MMC_REG_RES_FIFO);
d96be879
SH		 532 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
533 }
534 }
535}
536
537static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
538{
539 u32 stat;
540 unsigned long timeout = jiffies + HZ;
541
542 do {
c7ceab02 543 stat = mxcmci_readl(host, MMC_REG_STATUS);
d96be879
SH		 544 if (stat & STATUS_ERR_MASK)
545 return stat;
18489fa2
MF		 546 if (time_after(jiffies, timeout)) {
547 mxcmci_softreset(host);
548 mxcmci_set_clk_rate(host, host->clock);
d96be879 549 return STATUS_TIME_OUT_READ;
18489fa2 550 }
d96be879
SH		 551 if (stat & mask)
552 return 0;
553 cpu_relax();
554 } while (1);
555}
556
557static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
558{
559 unsigned int stat;
560 u32 *buf = _buf;
561
562 while (bytes > 3) {
563 stat = mxcmci_poll_status(host,
564 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
565 if (stat)
566 return stat;
c7ceab02 567 *buf++ = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
d96be879
SH		 568 bytes -= 4;
569 }
570
571 if (bytes) {
572 u8 *b = (u8 *)buf;
573 u32 tmp;
574
575 stat = mxcmci_poll_status(host,
576 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
577 if (stat)
578 return stat;
c7ceab02 579 tmp = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
d96be879
SH		 580 memcpy(b, &tmp, bytes);
581 }
582
583 return 0;
584}
585
586static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes)
587{
588 unsigned int stat;
589 u32 *buf = _buf;
590
591 while (bytes > 3) {
592 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
593 if (stat)
594 return stat;
c7ceab02 595 mxcmci_writel(host, cpu_to_le32(*buf++), MMC_REG_BUFFER_ACCESS);
d96be879
SH		 596 bytes -= 4;
597 }
598
599 if (bytes) {
600 u8 *b = (u8 *)buf;
601 u32 tmp;
602
603 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
604 if (stat)
605 return stat;
606
607 memcpy(&tmp, b, bytes);
c7ceab02 608 mxcmci_writel(host, cpu_to_le32(tmp), MMC_REG_BUFFER_ACCESS);
d96be879
SH		 609 }
610
611 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
612 if (stat)
613 return stat;
614
615 return 0;
616}
617
618static int mxcmci_transfer_data(struct mxcmci_host *host)
619{
620 struct mmc_data *data = host->req->data;
621 struct scatterlist *sg;
622 int stat, i;
623
d96be879
SH		 624 host->data = data;
625 host->datasize = 0;
626
627 if (data->flags & MMC_DATA_READ) {
628 for_each_sg(data->sg, sg, data->sg_len, i) {
629 stat = mxcmci_pull(host, sg_virt(sg), sg->length);
630 if (stat)
631 return stat;
632 host->datasize += sg->length;
633 }
634 } else {
635 for_each_sg(data->sg, sg, data->sg_len, i) {
636 stat = mxcmci_push(host, sg_virt(sg), sg->length);
637 if (stat)
638 return stat;
639 host->datasize += sg->length;
640 }
641 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
642 if (stat)
643 return stat;
644 }
645 return 0;
646}
647
648static void mxcmci_datawork(struct work_struct *work)
649{
650 struct mxcmci_host *host = container_of(work, struct mxcmci_host,
651 datawork);
652 int datastat = mxcmci_transfer_data(host);
4a31f2ef 653
c7ceab02
AG		 654 mxcmci_writel(host, STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
655 MMC_REG_STATUS);
d96be879
SH		 656 mxcmci_finish_data(host, datastat);
657
658 if (host->req->stop) {
659 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
660 mxcmci_finish_request(host, host->req);
661 return;
662 }
663 } else {
664 mxcmci_finish_request(host, host->req);
665 }
666}
667
d96be879
SH		 668static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
669{
70aa6109 670 struct mmc_request *req;
d96be879 671 int data_error;
70aa6109
AG		 672 unsigned long flags;
673
674 spin_lock_irqsave(&host->lock, flags);
d96be879 675
70aa6109
AG		 676 if (!host->data) {
677 spin_unlock_irqrestore(&host->lock, flags);
d96be879 678 return;
70aa6109
AG		 679 }
680
681 if (!host->req) {
682 spin_unlock_irqrestore(&host->lock, flags);
683 return;
684 }
685
686 req = host->req;
687 if (!req->stop)
688 host->req = NULL; /* we will handle finish req below */
d96be879
SH		 689
690 data_error = mxcmci_finish_data(host, stat);
691
70aa6109
AG		 692 spin_unlock_irqrestore(&host->lock, flags);
693
d96be879
SH		 694 mxcmci_read_response(host, stat);
695 host->cmd = NULL;
696
70aa6109
AG		 697 if (req->stop) {
698 if (mxcmci_start_cmd(host, req->stop, 0)) {
699 mxcmci_finish_request(host, req);
d96be879
SH		 700 return;
701 }
702 } else {
70aa6109 703 mxcmci_finish_request(host, req);
d96be879
SH		 704 }
705}
d96be879
SH		 706
707static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
708{
709 mxcmci_read_response(host, stat);
710 host->cmd = NULL;
711
712 if (!host->data && host->req) {
713 mxcmci_finish_request(host, host->req);
714 return;
715 }
716
717 /* For the DMA case the DMA engine handles the data transfer
fd589a8f 718 * automatically. For non DMA we have to do it ourselves.
d96be879
SH		 719 * Don't do it in interrupt context though.
720 */
721 if (!mxcmci_use_dma(host) && host->data)
722 schedule_work(&host->datawork);
723
724}
725
726static irqreturn_t mxcmci_irq(int irq, void *devid)
727{
728 struct mxcmci_host *host = devid;
f441b993
DM		 729 unsigned long flags;
730 bool sdio_irq;
d96be879
SH		 731 u32 stat;
732
c7ceab02
AG		 733 stat = mxcmci_readl(host, MMC_REG_STATUS);
734 mxcmci_writel(host,
735 stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE |
736 STATUS_WRITE_OP_DONE),
737 MMC_REG_STATUS);
d96be879
SH		 738
739 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
740
f441b993
DM		 741 spin_lock_irqsave(&host->lock, flags);
742 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio;
743 spin_unlock_irqrestore(&host->lock, flags);
744
4a31f2ef
DM		 745 if (mxcmci_use_dma(host) &&
746 (stat & (STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE)))
c7ceab02
AG		 747 mxcmci_writel(host, STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
748 MMC_REG_STATUS);
4a31f2ef 749
f441b993 750 if (sdio_irq) {
c7ceab02 751 mxcmci_writel(host, STATUS_SDIO_INT_ACTIVE, MMC_REG_STATUS);
f441b993
DM		 752 mmc_signal_sdio_irq(host->mmc);
753 }
754
d96be879
SH		 755 if (stat & STATUS_END_CMD_RESP)
756 mxcmci_cmd_done(host, stat);
f441b993 757
d96be879 758 if (mxcmci_use_dma(host) &&
f6ad0a48
JM		 759 (stat & (STATUS_DATA_TRANS_DONE | STATUS_WRITE_OP_DONE))) {
760 del_timer(&host->watchdog);
d96be879 761 mxcmci_data_done(host, stat);
f6ad0a48 762 }
f53fbde4 763
16b3bf8c
EB		 764 if (host->default_irq_mask &&
765 (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL)))
766 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
f53fbde4 767
d96be879
SH		 768 return IRQ_HANDLED;
769}
770
771static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
772{
773 struct mxcmci_host *host = mmc_priv(mmc);
774 unsigned int cmdat = host->cmdat;
656217d2 775 int error;
d96be879
SH		 776
777 WARN_ON(host->req != NULL);
778
779 host->req = req;
780 host->cmdat &= ~CMD_DAT_CONT_INIT;
f53fbde4
SH		 781
782 if (host->dma)
783 host->do_dma = 1;
784
d96be879 785 if (req->data) {
656217d2
MF		 786 error = mxcmci_setup_data(host, req->data);
787 if (error) {
788 req->cmd->error = error;
789 goto out;
790 }
791
d96be879
SH		 792
793 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
794
795 if (req->data->flags & MMC_DATA_WRITE)
796 cmdat |= CMD_DAT_CONT_WRITE;
797 }
798
656217d2 799 error = mxcmci_start_cmd(host, req->cmd, cmdat);
f53fbde4 800
656217d2
MF		 801out:
802 if (error)
d96be879
SH		 803 mxcmci_finish_request(host, req);
804}
805
806static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
807{
808 unsigned int divider;
809 int prescaler = 0;
529aa29e 810 unsigned int clk_in = clk_get_rate(host->clk_per);
d96be879
SH		 811
812 while (prescaler <= 0x800) {
813 for (divider = 1; divider <= 0xF; divider++) {
814 int x;
815
816 x = (clk_in / (divider + 1));
817
818 if (prescaler)
819 x /= (prescaler * 2);
820
821 if (x <= clk_ios)
822 break;
823 }
824 if (divider < 0x10)
825 break;
826
827 if (prescaler == 0)
828 prescaler = 1;
829 else
830 prescaler <<= 1;
831 }
832
c7ceab02 833 mxcmci_writew(host, (prescaler << 4) | divider, MMC_REG_CLK_RATE);
d96be879
SH		 834
835 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
836 prescaler, divider, clk_in, clk_ios);
837}
838
f53fbde4
SH		 839static int mxcmci_setup_dma(struct mmc_host *mmc)
840{
841 struct mxcmci_host *host = mmc_priv(mmc);
842 struct dma_slave_config *config = &host->dma_slave_config;
843
844 config->dst_addr = host->res->start + MMC_REG_BUFFER_ACCESS;
845 config->src_addr = host->res->start + MMC_REG_BUFFER_ACCESS;
846 config->dst_addr_width = 4;
847 config->src_addr_width = 4;
848 config->dst_maxburst = host->burstlen;
849 config->src_maxburst = host->burstlen;
258aea76 850 config->device_fc = false;
f53fbde4
SH		 851
852 return dmaengine_slave_config(host->dma, config);
853}
854
d96be879
SH		 855static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
856{
857 struct mxcmci_host *host = mmc_priv(mmc);
f53fbde4
SH		 858 int burstlen, ret;
859
d96be879 860 /*
6584cb88
SH		 861 * use burstlen of 64 (16 words) in 4 bit mode (--> reg value 0)
862 * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16)
d96be879
SH		 863 */
864 if (ios->bus_width == MMC_BUS_WIDTH_4)
f53fbde4 865 burstlen = 16;
6584cb88
SH		 866 else
867 burstlen = 4;
f53fbde4
SH		 868
869 if (mxcmci_use_dma(host) && burstlen != host->burstlen) {
870 host->burstlen = burstlen;
871 ret = mxcmci_setup_dma(mmc);
872 if (ret) {
873 dev_err(mmc_dev(host->mmc),
874 "failed to config DMA channel. Falling back to PIO\n");
875 dma_release_channel(host->dma);
876 host->do_dma = 0;
e58f516f 877 host->dma = NULL;
f53fbde4
SH		 878 }
879 }
d96be879 880
d96be879
SH		 881 if (ios->bus_width == MMC_BUS_WIDTH_4)
882 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
883 else
884 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
885
886 if (host->power_mode != ios->power_mode) {
d078d242 887 mxcmci_set_power(host, ios->power_mode, ios->vdd);
d96be879 888 host->power_mode = ios->power_mode;
74b66954 889
d96be879
SH		 890 if (ios->power_mode == MMC_POWER_ON)
891 host->cmdat |= CMD_DAT_CONT_INIT;
892 }
893
894 if (ios->clock) {
895 mxcmci_set_clk_rate(host, ios->clock);
c7ceab02 896 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
d96be879 897 } else {
c7ceab02 898 mxcmci_writew(host, STR_STP_CLK_STOP_CLK, MMC_REG_STR_STP_CLK);
d96be879
SH		 899 }
900
901 host->clock = ios->clock;
902}
903
904static irqreturn_t mxcmci_detect_irq(int irq, void *data)
905{
906 struct mmc_host *mmc = data;
907
908 dev_dbg(mmc_dev(mmc), "%s\n", __func__);
909
910 mmc_detect_change(mmc, msecs_to_jiffies(250));
911 return IRQ_HANDLED;
912}
913
914static int mxcmci_get_ro(struct mmc_host *mmc)
915{
916 struct mxcmci_host *host = mmc_priv(mmc);
917
918 if (host->pdata && host->pdata->get_ro)
919 return !!host->pdata->get_ro(mmc_dev(mmc));
920 /*
bcf53524
AG		 921 * If board doesn't support read only detection (no mmc_gpio
922 * context or gpio is invalid), then let the mmc core decide
923 * what to do.
d96be879 924 */
bcf53524 925 return mmc_gpio_get_ro(mmc);
d96be879
SH		 926}
927
f441b993
DM		 928static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
929{
930 struct mxcmci_host *host = mmc_priv(mmc);
931 unsigned long flags;
932 u32 int_cntr;
933
934 spin_lock_irqsave(&host->lock, flags);
935 host->use_sdio = enable;
c7ceab02 936 int_cntr = mxcmci_readl(host, MMC_REG_INT_CNTR);
f441b993
DM		 937
938 if (enable)
939 int_cntr |= INT_SDIO_IRQ_EN;
940 else
941 int_cntr &= ~INT_SDIO_IRQ_EN;
942
c7ceab02 943 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
f441b993
DM		 944 spin_unlock_irqrestore(&host->lock, flags);
945}
d96be879 946
3fcb027d
DM		 947static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card)
948{
7f917a8d
SG		 949 struct mxcmci_host *mxcmci = mmc_priv(host);
950
3fcb027d
DM		 951 /*
952 * MX3 SoCs have a silicon bug which corrupts CRC calculation of
953 * multi-block transfers when connected SDIO peripheral doesn't
954 * drive the BUSY line as required by the specs.
955 * One way to prevent this is to only allow 1-bit transfers.
956 */
957
7f917a8d 958 if (is_imx31_mmc(mxcmci) && card->type == MMC_TYPE_SDIO)
3fcb027d
DM		 959 host->caps &= ~MMC_CAP_4_BIT_DATA;
960 else
961 host->caps |= MMC_CAP_4_BIT_DATA;
962}
963
f53fbde4
SH		 964static bool filter(struct dma_chan *chan, void *param)
965{
966 struct mxcmci_host *host = param;
967
968 if (!imx_dma_is_general_purpose(chan))
969 return false;
970
971 chan->private = &host->dma_data;
972
973 return true;
974}
975
f6ad0a48
JM		 976static void mxcmci_watchdog(unsigned long data)
977{
978 struct mmc_host *mmc = (struct mmc_host *)data;
979 struct mxcmci_host *host = mmc_priv(mmc);
980 struct mmc_request *req = host->req;
c7ceab02 981 unsigned int stat = mxcmci_readl(host, MMC_REG_STATUS);
f6ad0a48
JM		 982
983 if (host->dma_dir == DMA_FROM_DEVICE) {
984 dmaengine_terminate_all(host->dma);
985 dev_err(mmc_dev(host->mmc),
986 "%s: read time out (status = 0x%08x)\n",
987 __func__, stat);
988 } else {
989 dev_err(mmc_dev(host->mmc),
990 "%s: write time out (status = 0x%08x)\n",
991 __func__, stat);
992 mxcmci_softreset(host);
993 }
994
995 /* Mark transfer as erroneus and inform the upper layers */
996
70aa6109
AG		 997 if (host->data)
998 host->data->error = -ETIMEDOUT;
f6ad0a48
JM		 999 host->req = NULL;
1000 host->cmd = NULL;
1001 host->data = NULL;
1002 mmc_request_done(host->mmc, req);
1003}
1004
d96be879 1005static const struct mmc_host_ops mxcmci_ops = {
f441b993
DM		 1006 .request = mxcmci_request,
1007 .set_ios = mxcmci_set_ios,
1008 .get_ro = mxcmci_get_ro,
1009 .enable_sdio_irq = mxcmci_enable_sdio_irq,
3fcb027d 1010 .init_card = mxcmci_init_card,
d96be879
SH		 1011};
1012
1013static int mxcmci_probe(struct platform_device *pdev)
1014{
1015 struct mmc_host *mmc;
1016 struct mxcmci_host *host = NULL;
c0521baf 1017 struct resource *iores, *r;
d96be879 1018 int ret = 0, irq;
7ff747c4 1019 bool dat3_card_detect = false;
f53fbde4 1020 dma_cap_mask_t mask;
7ff747c4
MP		 1021 const struct of_device_id *of_id;
1022 struct imxmmc_platform_data *pdata = pdev->dev.platform_data;
d96be879 1023
c7ceab02 1024 pr_info("i.MX/MPC512x SDHC driver\n");
d96be879 1025
7ff747c4
MP		 1026 of_id = of_match_device(mxcmci_of_match, &pdev->dev);
1027
c0521baf 1028 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d96be879 1029 irq = platform_get_irq(pdev, 0);
c0521baf 1030 if (!iores || irq < 0)
d96be879
SH		 1031 return -EINVAL;
1032
c0521baf 1033 r = request_mem_region(iores->start, resource_size(iores), pdev->name);
d96be879
SH		 1034 if (!r)
1035 return -EBUSY;
1036
1037 mmc = mmc_alloc_host(sizeof(struct mxcmci_host), &pdev->dev);
1038 if (!mmc) {
1039 ret = -ENOMEM;
1040 goto out_release_mem;
1041 }
1042
7ff747c4 1043 mmc_of_parse(mmc);
d96be879 1044 mmc->ops = &mxcmci_ops;
7ff747c4
MP		 1045
1046 /* For devicetree parsing, the bus width is read from devicetree */
1047 if (pdata)
1048 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1049 else
1050 mmc->caps |= MMC_CAP_SDIO_IRQ;
d96be879
SH		 1051
1052 /* MMC core transfer sizes tunable parameters */
a36274e0 1053 mmc->max_segs = 64;
d96be879
SH		 1054 mmc->max_blk_size = 2048;
1055 mmc->max_blk_count = 65535;
1056 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
d759c374 1057 mmc->max_seg_size = mmc->max_req_size;
d96be879
SH		 1058
1059 host = mmc_priv(mmc);
1060 host->base = ioremap(r->start, resource_size(r));
1061 if (!host->base) {
1062 ret = -ENOMEM;
1063 goto out_free;
1064 }
1065
7ff747c4
MP		 1066 if (of_id) {
1067 const struct platform_device_id *id_entry = of_id->data;
1068 host->devtype = id_entry->driver_data;
1069 } else {
1070 host->devtype = pdev->id_entry->driver_data;
1071 }
d96be879 1072 host->mmc = mmc;
7ff747c4 1073 host->pdata = pdata;
f441b993 1074 spin_lock_init(&host->lock);
d96be879 1075
7ff747c4
MP		 1076 if (pdata)
1077 dat3_card_detect = pdata->dat3_card_detect;
1078 else if (!(mmc->caps & MMC_CAP_NONREMOVABLE)
1079 && !of_property_read_bool(pdev->dev.of_node, "cd-gpios"))
1080 dat3_card_detect = true;
1081
74b66954 1082 mxcmci_init_ocr(host);
d96be879 1083
7ff747c4 1084 if (dat3_card_detect)
16b3bf8c
EB		 1085 host->default_irq_mask =
1086 INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN;
1087 else
1088 host->default_irq_mask = 0;
1089
d96be879
SH		 1090 host->res = r;
1091 host->irq = irq;
1092
529aa29e
SH		 1093 host->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1094 if (IS_ERR(host->clk_ipg)) {
1095 ret = PTR_ERR(host->clk_ipg);
d96be879
SH		 1096 goto out_iounmap;
1097 }
529aa29e
SH		 1098
1099 host->clk_per = devm_clk_get(&pdev->dev, "per");
1100 if (IS_ERR(host->clk_per)) {
1101 ret = PTR_ERR(host->clk_per);
1102 goto out_iounmap;
1103 }
1104
1105 clk_prepare_enable(host->clk_per);
1106 clk_prepare_enable(host->clk_ipg);
d96be879
SH		 1107
1108 mxcmci_softreset(host);
1109
c7ceab02 1110 host->rev_no = mxcmci_readw(host, MMC_REG_REV_NO);
d96be879
SH		 1111 if (host->rev_no != 0x400) {
1112 ret = -ENODEV;
1113 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
1114 host->rev_no);
1115 goto out_clk_put;
1116 }
1117
529aa29e
SH		 1118 mmc->f_min = clk_get_rate(host->clk_per) >> 16;
1119 mmc->f_max = clk_get_rate(host->clk_per) >> 1;
d96be879
SH		 1120
1121 /* recommended in data sheet */
c7ceab02 1122 mxcmci_writew(host, 0x2db4, MMC_REG_READ_TO);
d96be879 1123
c7ceab02 1124 mxcmci_writel(host, host->default_irq_mask, MMC_REG_INT_CNTR);
d96be879 1125
7ff747c4
MP		 1126 if (!host->pdata) {
1127 host->dma = dma_request_slave_channel(&pdev->dev, "rx-tx");
1128 } else {
1129 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1130 if (r) {
1131 host->dmareq = r->start;
1132 host->dma_data.peripheral_type = IMX_DMATYPE_SDHC;
1133 host->dma_data.priority = DMA_PRIO_LOW;
1134 host->dma_data.dma_request = host->dmareq;
1135 dma_cap_zero(mask);
1136 dma_cap_set(DMA_SLAVE, mask);
1137 host->dma = dma_request_channel(mask, filter, host);
1138 }
f53fbde4 1139 }
7ff747c4
MP		 1140 if (host->dma)
1141 mmc->max_seg_size = dma_get_max_seg_size(
1142 host->dma->device->dev);
1143 else
f53fbde4 1144 dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n");
d96be879 1145
d96be879
SH		 1146 INIT_WORK(&host->datawork, mxcmci_datawork);
1147
1148 ret = request_irq(host->irq, mxcmci_irq, 0, DRIVER_NAME, host);
1149 if (ret)
1150 goto out_free_dma;
1151
1152 platform_set_drvdata(pdev, mmc);
1153
1154 if (host->pdata && host->pdata->init) {
1155 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq,
1156 host->mmc);
1157 if (ret)
1158 goto out_free_irq;
1159 }
1160
f6ad0a48
JM		 1161 init_timer(&host->watchdog);
1162 host->watchdog.function = &mxcmci_watchdog;
1163 host->watchdog.data = (unsigned long)mmc;
1164
abd4190f
AS		 1165 mmc_add_host(mmc);
1166
d96be879
SH		 1167 return 0;
1168
1169out_free_irq:
1170 free_irq(host->irq, host);
1171out_free_dma:
f53fbde4
SH		 1172 if (host->dma)
1173 dma_release_channel(host->dma);
d96be879 1174out_clk_put:
529aa29e
SH		 1175 clk_disable_unprepare(host->clk_per);
1176 clk_disable_unprepare(host->clk_ipg);
d96be879
SH		 1177out_iounmap:
1178 iounmap(host->base);
1179out_free:
1180 mmc_free_host(mmc);
1181out_release_mem:
c0521baf 1182 release_mem_region(iores->start, resource_size(iores));
d96be879
SH		 1183 return ret;
1184}
1185
1186static int mxcmci_remove(struct platform_device *pdev)
1187{
1188 struct mmc_host *mmc = platform_get_drvdata(pdev);
1189 struct mxcmci_host *host = mmc_priv(mmc);
1190
1191 platform_set_drvdata(pdev, NULL);
1192
1193 mmc_remove_host(mmc);
1194
74b66954
AP		 1195 if (host->vcc)
1196 regulator_put(host->vcc);
1197
d96be879
SH		 1198 if (host->pdata && host->pdata->exit)
1199 host->pdata->exit(&pdev->dev, mmc);
1200
1201 free_irq(host->irq, host);
1202 iounmap(host->base);
f53fbde4
SH		 1203
1204 if (host->dma)
1205 dma_release_channel(host->dma);
1206
529aa29e
SH		 1207 clk_disable_unprepare(host->clk_per);
1208 clk_disable_unprepare(host->clk_ipg);
d96be879
SH		 1209
1210 release_mem_region(host->res->start, resource_size(host->res));
d96be879
SH		 1211
1212 mmc_free_host(mmc);
1213
1214 return 0;
1215}
1216
1217#ifdef CONFIG_PM
a7d403cf 1218static int mxcmci_suspend(struct device *dev)
d96be879 1219{
a7d403cf
EB		 1220 struct mmc_host *mmc = dev_get_drvdata(dev);
1221 struct mxcmci_host *host = mmc_priv(mmc);
d96be879
SH		 1222 int ret = 0;
1223
1224 if (mmc)
1a13f8fa 1225 ret = mmc_suspend_host(mmc);
529aa29e
SH		 1226 clk_disable_unprepare(host->clk_per);
1227 clk_disable_unprepare(host->clk_ipg);
d96be879
SH		 1228
1229 return ret;
1230}
1231
a7d403cf 1232static int mxcmci_resume(struct device *dev)
d96be879 1233{
a7d403cf
EB		 1234 struct mmc_host *mmc = dev_get_drvdata(dev);
1235 struct mxcmci_host *host = mmc_priv(mmc);
d96be879
SH		 1236 int ret = 0;
1237
529aa29e
SH		 1238 clk_prepare_enable(host->clk_per);
1239 clk_prepare_enable(host->clk_ipg);
a7d403cf 1240 if (mmc)
d96be879 1241 ret = mmc_resume_host(mmc);
d96be879
SH		 1242
1243 return ret;
1244}
a7d403cf
EB		 1245
1246static const struct dev_pm_ops mxcmci_pm_ops = {
1247 .suspend = mxcmci_suspend,
1248 .resume = mxcmci_resume,
1249};
1250#endif
d96be879
SH		 1251
1252static struct platform_driver mxcmci_driver = {
1253 .probe = mxcmci_probe,
1254 .remove = mxcmci_remove,
7f917a8d 1255 .id_table = mxcmci_devtype,
d96be879
SH		 1256 .driver = {
1257 .name = DRIVER_NAME,
1258 .owner = THIS_MODULE,
a7d403cf
EB		 1259#ifdef CONFIG_PM
1260 .pm = &mxcmci_pm_ops,
1261#endif
7ff747c4 1262 .of_match_table = mxcmci_of_match,
d96be879
SH		 1263 }
1264};
1265
d1f81a64 1266module_platform_driver(mxcmci_driver);
d96be879
SH		 1267
1268MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1269MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1270MODULE_LICENSE("GPL");
6eb30adf 1271MODULE_ALIAS("platform:mxc-mmc");
Linux kernel - Deliverables
This page took 0.324204 seconds and 5 git commands to generate.