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ARM: MXC: mxcmmc: misc cleanups
[deliverable/linux.git] / drivers / mmc / host / mxcmmc.c
CommitLineData
d96be879
SH		 1/*
2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
3 *
4 * This is a driver for the SDHC controller found in Freescale MX2/MX3
5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
6 * Unlike the hardware found on MX1, this hardware just works and does
3ad2f3fb 7 * not need all the quirks found in imxmmc.c, hence the separate driver.
d96be879
SH		 8 *
9 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
10 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
11 *
12 * derived from pxamci.c by Russell King
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 *
18 */
19
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/ioport.h>
23#include <linux/platform_device.h>
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/blkdev.h>
27#include <linux/dma-mapping.h>
28#include <linux/mmc/host.h>
29#include <linux/mmc/card.h>
30#include <linux/delay.h>
31#include <linux/clk.h>
32#include <linux/io.h>
33#include <linux/gpio.h>
34
35#include <asm/dma.h>
36#include <asm/irq.h>
37#include <asm/sizes.h>
38#include <mach/mmc.h>
39
40#ifdef CONFIG_ARCH_MX2
41#include <mach/dma-mx1-mx2.h>
42#define HAS_DMA
43#endif
44
9563b1db 45#define DRIVER_NAME "mxc-mmc"
d96be879
SH		 46
47#define MMC_REG_STR_STP_CLK 0x00
48#define MMC_REG_STATUS 0x04
49#define MMC_REG_CLK_RATE 0x08
50#define MMC_REG_CMD_DAT_CONT 0x0C
51#define MMC_REG_RES_TO 0x10
52#define MMC_REG_READ_TO 0x14
53#define MMC_REG_BLK_LEN 0x18
54#define MMC_REG_NOB 0x1C
55#define MMC_REG_REV_NO 0x20
56#define MMC_REG_INT_CNTR 0x24
57#define MMC_REG_CMD 0x28
58#define MMC_REG_ARG 0x2C
59#define MMC_REG_RES_FIFO 0x34
60#define MMC_REG_BUFFER_ACCESS 0x38
61
62#define STR_STP_CLK_RESET (1 << 3)
63#define STR_STP_CLK_START_CLK (1 << 1)
64#define STR_STP_CLK_STOP_CLK (1 << 0)
65
66#define STATUS_CARD_INSERTION (1 << 31)
67#define STATUS_CARD_REMOVAL (1 << 30)
68#define STATUS_YBUF_EMPTY (1 << 29)
69#define STATUS_XBUF_EMPTY (1 << 28)
70#define STATUS_YBUF_FULL (1 << 27)
71#define STATUS_XBUF_FULL (1 << 26)
72#define STATUS_BUF_UND_RUN (1 << 25)
73#define STATUS_BUF_OVFL (1 << 24)
74#define STATUS_SDIO_INT_ACTIVE (1 << 14)
75#define STATUS_END_CMD_RESP (1 << 13)
76#define STATUS_WRITE_OP_DONE (1 << 12)
77#define STATUS_DATA_TRANS_DONE (1 << 11)
78#define STATUS_READ_OP_DONE (1 << 11)
79#define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
80#define STATUS_CARD_BUS_CLK_RUN (1 << 8)
81#define STATUS_BUF_READ_RDY (1 << 7)
82#define STATUS_BUF_WRITE_RDY (1 << 6)
83#define STATUS_RESP_CRC_ERR (1 << 5)
84#define STATUS_CRC_READ_ERR (1 << 3)
85#define STATUS_CRC_WRITE_ERR (1 << 2)
86#define STATUS_TIME_OUT_RESP (1 << 1)
87#define STATUS_TIME_OUT_READ (1 << 0)
88#define STATUS_ERR_MASK 0x2f
89
90#define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
91#define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
92#define CMD_DAT_CONT_START_READWAIT (1 << 10)
93#define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
94#define CMD_DAT_CONT_INIT (1 << 7)
95#define CMD_DAT_CONT_WRITE (1 << 4)
96#define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
97#define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
98#define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
99#define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
100
101#define INT_SDIO_INT_WKP_EN (1 << 18)
102#define INT_CARD_INSERTION_WKP_EN (1 << 17)
103#define INT_CARD_REMOVAL_WKP_EN (1 << 16)
104#define INT_CARD_INSERTION_EN (1 << 15)
105#define INT_CARD_REMOVAL_EN (1 << 14)
106#define INT_SDIO_IRQ_EN (1 << 13)
107#define INT_DAT0_EN (1 << 12)
108#define INT_BUF_READ_EN (1 << 4)
109#define INT_BUF_WRITE_EN (1 << 3)
110#define INT_END_CMD_RES_EN (1 << 2)
111#define INT_WRITE_OP_DONE_EN (1 << 1)
112#define INT_READ_OP_EN (1 << 0)
113
114struct mxcmci_host {
115 struct mmc_host *mmc;
116 struct resource *res;
117 void __iomem *base;
118 int irq;
119 int detect_irq;
120 int dma;
121 int do_dma;
122 unsigned int power_mode;
123 struct imxmmc_platform_data *pdata;
124
125 struct mmc_request *req;
126 struct mmc_command *cmd;
127 struct mmc_data *data;
128
129 unsigned int dma_nents;
130 unsigned int datasize;
131 unsigned int dma_dir;
132
133 u16 rev_no;
134 unsigned int cmdat;
135
136 struct clk *clk;
137
138 int clock;
139
140 struct work_struct datawork;
141};
142
18489fa2
MF		 143static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
144
d96be879
SH		 145static inline int mxcmci_use_dma(struct mxcmci_host *host)
146{
147 return host->do_dma;
148}
149
150static void mxcmci_softreset(struct mxcmci_host *host)
151{
152 int i;
153
4725f6f1
DM		 154 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n");
155
d96be879
SH		 156 /* reset sequence */
157 writew(STR_STP_CLK_RESET, host->base + MMC_REG_STR_STP_CLK);
158 writew(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
159 host->base + MMC_REG_STR_STP_CLK);
160
161 for (i = 0; i < 8; i++)
162 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
163
164 writew(0xff, host->base + MMC_REG_RES_TO);
165}
166
656217d2 167static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
d96be879
SH		 168{
169 unsigned int nob = data->blocks;
170 unsigned int blksz = data->blksz;
171 unsigned int datasize = nob * blksz;
172#ifdef HAS_DMA
173 struct scatterlist *sg;
174 int i;
656217d2 175 int ret;
d96be879
SH		 176#endif
177 if (data->flags & MMC_DATA_STREAM)
178 nob = 0xffff;
179
180 host->data = data;
181 data->bytes_xfered = 0;
182
183 writew(nob, host->base + MMC_REG_NOB);
184 writew(blksz, host->base + MMC_REG_BLK_LEN);
185 host->datasize = datasize;
186
187#ifdef HAS_DMA
188 for_each_sg(data->sg, sg, data->sg_len, i) {
189 if (sg->offset & 3 || sg->length & 3) {
190 host->do_dma = 0;
656217d2 191 return 0;
d96be879
SH		 192 }
193 }
194
195 if (data->flags & MMC_DATA_READ) {
196 host->dma_dir = DMA_FROM_DEVICE;
197 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
198 data->sg_len, host->dma_dir);
199
656217d2
MF		 200 ret = imx_dma_setup_sg(host->dma, data->sg, host->dma_nents,
201 datasize,
202 host->res->start + MMC_REG_BUFFER_ACCESS,
203 DMA_MODE_READ);
d96be879
SH		 204 } else {
205 host->dma_dir = DMA_TO_DEVICE;
206 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
207 data->sg_len, host->dma_dir);
208
656217d2
MF		 209 ret = imx_dma_setup_sg(host->dma, data->sg, host->dma_nents,
210 datasize,
211 host->res->start + MMC_REG_BUFFER_ACCESS,
212 DMA_MODE_WRITE);
d96be879
SH		 213 }
214
656217d2
MF		 215 if (ret) {
216 dev_err(mmc_dev(host->mmc), "failed to setup DMA : %d\n", ret);
217 return ret;
218 }
d96be879
SH		 219 wmb();
220
221 imx_dma_enable(host->dma);
222#endif /* HAS_DMA */
656217d2 223 return 0;
d96be879
SH		 224}
225
226static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
227 unsigned int cmdat)
228{
229 WARN_ON(host->cmd != NULL);
230 host->cmd = cmd;
231
232 switch (mmc_resp_type(cmd)) {
233 case MMC_RSP_R1: /* short CRC, OPCODE */
234 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
235 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
236 break;
237 case MMC_RSP_R2: /* long 136 bit + CRC */
238 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
239 break;
240 case MMC_RSP_R3: /* short */
241 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
242 break;
243 case MMC_RSP_NONE:
244 break;
245 default:
246 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n",
247 mmc_resp_type(cmd));
248 cmd->error = -EINVAL;
249 return -EINVAL;
250 }
251
252 if (mxcmci_use_dma(host))
253 writel(INT_READ_OP_EN | INT_WRITE_OP_DONE_EN |
254 INT_END_CMD_RES_EN,
255 host->base + MMC_REG_INT_CNTR);
256 else
257 writel(INT_END_CMD_RES_EN, host->base + MMC_REG_INT_CNTR);
258
259 writew(cmd->opcode, host->base + MMC_REG_CMD);
260 writel(cmd->arg, host->base + MMC_REG_ARG);
261 writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT);
262
263 return 0;
264}
265
266static void mxcmci_finish_request(struct mxcmci_host *host,
267 struct mmc_request *req)
268{
269 writel(0, host->base + MMC_REG_INT_CNTR);
270
271 host->req = NULL;
272 host->cmd = NULL;
273 host->data = NULL;
274
275 mmc_request_done(host->mmc, req);
276}
277
278static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
279{
280 struct mmc_data *data = host->data;
281 int data_error;
282
283#ifdef HAS_DMA
284 if (mxcmci_use_dma(host)) {
285 imx_dma_disable(host->dma);
286 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents,
287 host->dma_dir);
288 }
289#endif
290
291 if (stat & STATUS_ERR_MASK) {
292 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
293 stat);
294 if (stat & STATUS_CRC_READ_ERR) {
4725f6f1 295 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__);
d96be879
SH		 296 data->error = -EILSEQ;
297 } else if (stat & STATUS_CRC_WRITE_ERR) {
298 u32 err_code = (stat >> 9) & 0x3;
4725f6f1
DM		 299 if (err_code == 2) { /* No CRC response */
300 dev_err(mmc_dev(host->mmc),
301 "%s: No CRC -ETIMEDOUT\n", __func__);
d96be879 302 data->error = -ETIMEDOUT;
4725f6f1
DM		 303 } else {
304 dev_err(mmc_dev(host->mmc),
305 "%s: -EILSEQ\n", __func__);
d96be879 306 data->error = -EILSEQ;
4725f6f1 307 }
d96be879 308 } else if (stat & STATUS_TIME_OUT_READ) {
4725f6f1
DM		 309 dev_err(mmc_dev(host->mmc),
310 "%s: read -ETIMEDOUT\n", __func__);
d96be879
SH		 311 data->error = -ETIMEDOUT;
312 } else {
4725f6f1 313 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__);
d96be879
SH		 314 data->error = -EIO;
315 }
316 } else {
317 data->bytes_xfered = host->datasize;
318 }
319
320 data_error = data->error;
321
322 host->data = NULL;
323
324 return data_error;
325}
326
327static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
328{
329 struct mmc_command *cmd = host->cmd;
330 int i;
331 u32 a, b, c;
332
333 if (!cmd)
334 return;
335
336 if (stat & STATUS_TIME_OUT_RESP) {
337 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
338 cmd->error = -ETIMEDOUT;
339 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
340 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
341 cmd->error = -EILSEQ;
342 }
343
344 if (cmd->flags & MMC_RSP_PRESENT) {
345 if (cmd->flags & MMC_RSP_136) {
346 for (i = 0; i < 4; i++) {
347 a = readw(host->base + MMC_REG_RES_FIFO);
348 b = readw(host->base + MMC_REG_RES_FIFO);
349 cmd->resp[i] = a << 16 | b;
350 }
351 } else {
352 a = readw(host->base + MMC_REG_RES_FIFO);
353 b = readw(host->base + MMC_REG_RES_FIFO);
354 c = readw(host->base + MMC_REG_RES_FIFO);
355 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
356 }
357 }
358}
359
360static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
361{
362 u32 stat;
363 unsigned long timeout = jiffies + HZ;
364
365 do {
366 stat = readl(host->base + MMC_REG_STATUS);
367 if (stat & STATUS_ERR_MASK)
368 return stat;
18489fa2
MF		 369 if (time_after(jiffies, timeout)) {
370 mxcmci_softreset(host);
371 mxcmci_set_clk_rate(host, host->clock);
d96be879 372 return STATUS_TIME_OUT_READ;
18489fa2 373 }
d96be879
SH		 374 if (stat & mask)
375 return 0;
376 cpu_relax();
377 } while (1);
378}
379
380static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
381{
382 unsigned int stat;
383 u32 *buf = _buf;
384
385 while (bytes > 3) {
386 stat = mxcmci_poll_status(host,
387 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
388 if (stat)
389 return stat;
390 *buf++ = readl(host->base + MMC_REG_BUFFER_ACCESS);
391 bytes -= 4;
392 }
393
394 if (bytes) {
395 u8 *b = (u8 *)buf;
396 u32 tmp;
397
398 stat = mxcmci_poll_status(host,
399 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
400 if (stat)
401 return stat;
402 tmp = readl(host->base + MMC_REG_BUFFER_ACCESS);
403 memcpy(b, &tmp, bytes);
404 }
405
406 return 0;
407}
408
409static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes)
410{
411 unsigned int stat;
412 u32 *buf = _buf;
413
414 while (bytes > 3) {
415 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
416 if (stat)
417 return stat;
418 writel(*buf++, host->base + MMC_REG_BUFFER_ACCESS);
419 bytes -= 4;
420 }
421
422 if (bytes) {
423 u8 *b = (u8 *)buf;
424 u32 tmp;
425
426 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
427 if (stat)
428 return stat;
429
430 memcpy(&tmp, b, bytes);
431 writel(tmp, host->base + MMC_REG_BUFFER_ACCESS);
432 }
433
434 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
435 if (stat)
436 return stat;
437
438 return 0;
439}
440
441static int mxcmci_transfer_data(struct mxcmci_host *host)
442{
443 struct mmc_data *data = host->req->data;
444 struct scatterlist *sg;
445 int stat, i;
446
d96be879
SH		 447 host->data = data;
448 host->datasize = 0;
449
450 if (data->flags & MMC_DATA_READ) {
451 for_each_sg(data->sg, sg, data->sg_len, i) {
452 stat = mxcmci_pull(host, sg_virt(sg), sg->length);
453 if (stat)
454 return stat;
455 host->datasize += sg->length;
456 }
457 } else {
458 for_each_sg(data->sg, sg, data->sg_len, i) {
459 stat = mxcmci_push(host, sg_virt(sg), sg->length);
460 if (stat)
461 return stat;
462 host->datasize += sg->length;
463 }
464 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
465 if (stat)
466 return stat;
467 }
468 return 0;
469}
470
471static void mxcmci_datawork(struct work_struct *work)
472{
473 struct mxcmci_host *host = container_of(work, struct mxcmci_host,
474 datawork);
475 int datastat = mxcmci_transfer_data(host);
476 mxcmci_finish_data(host, datastat);
477
478 if (host->req->stop) {
479 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
480 mxcmci_finish_request(host, host->req);
481 return;
482 }
483 } else {
484 mxcmci_finish_request(host, host->req);
485 }
486}
487
488#ifdef HAS_DMA
489static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
490{
491 struct mmc_data *data = host->data;
492 int data_error;
493
494 if (!data)
495 return;
496
497 data_error = mxcmci_finish_data(host, stat);
498
499 mxcmci_read_response(host, stat);
500 host->cmd = NULL;
501
502 if (host->req->stop) {
503 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
504 mxcmci_finish_request(host, host->req);
505 return;
506 }
507 } else {
508 mxcmci_finish_request(host, host->req);
509 }
510}
511#endif /* HAS_DMA */
512
513static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
514{
515 mxcmci_read_response(host, stat);
516 host->cmd = NULL;
517
518 if (!host->data && host->req) {
519 mxcmci_finish_request(host, host->req);
520 return;
521 }
522
523 /* For the DMA case the DMA engine handles the data transfer
fd589a8f 524 * automatically. For non DMA we have to do it ourselves.
d96be879
SH		 525 * Don't do it in interrupt context though.
526 */
527 if (!mxcmci_use_dma(host) && host->data)
528 schedule_work(&host->datawork);
529
530}
531
532static irqreturn_t mxcmci_irq(int irq, void *devid)
533{
534 struct mxcmci_host *host = devid;
535 u32 stat;
536
537 stat = readl(host->base + MMC_REG_STATUS);
538 writel(stat, host->base + MMC_REG_STATUS);
539
540 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
541
542 if (stat & STATUS_END_CMD_RESP)
543 mxcmci_cmd_done(host, stat);
544#ifdef HAS_DMA
545 if (mxcmci_use_dma(host) &&
546 (stat & (STATUS_DATA_TRANS_DONE | STATUS_WRITE_OP_DONE)))
547 mxcmci_data_done(host, stat);
548#endif
549 return IRQ_HANDLED;
550}
551
552static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
553{
554 struct mxcmci_host *host = mmc_priv(mmc);
555 unsigned int cmdat = host->cmdat;
656217d2 556 int error;
d96be879
SH		 557
558 WARN_ON(host->req != NULL);
559
560 host->req = req;
561 host->cmdat &= ~CMD_DAT_CONT_INIT;
562#ifdef HAS_DMA
563 host->do_dma = 1;
564#endif
565 if (req->data) {
656217d2
MF		 566 error = mxcmci_setup_data(host, req->data);
567 if (error) {
568 req->cmd->error = error;
569 goto out;
570 }
571
d96be879
SH		 572
573 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
574
575 if (req->data->flags & MMC_DATA_WRITE)
576 cmdat |= CMD_DAT_CONT_WRITE;
577 }
578
656217d2
MF		 579 error = mxcmci_start_cmd(host, req->cmd, cmdat);
580out:
581 if (error)
d96be879
SH		 582 mxcmci_finish_request(host, req);
583}
584
585static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
586{
587 unsigned int divider;
588 int prescaler = 0;
589 unsigned int clk_in = clk_get_rate(host->clk);
590
591 while (prescaler <= 0x800) {
592 for (divider = 1; divider <= 0xF; divider++) {
593 int x;
594
595 x = (clk_in / (divider + 1));
596
597 if (prescaler)
598 x /= (prescaler * 2);
599
600 if (x <= clk_ios)
601 break;
602 }
603 if (divider < 0x10)
604 break;
605
606 if (prescaler == 0)
607 prescaler = 1;
608 else
609 prescaler <<= 1;
610 }
611
612 writew((prescaler << 4) | divider, host->base + MMC_REG_CLK_RATE);
613
614 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
615 prescaler, divider, clk_in, clk_ios);
616}
617
618static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
619{
620 struct mxcmci_host *host = mmc_priv(mmc);
621#ifdef HAS_DMA
622 unsigned int blen;
623 /*
624 * use burstlen of 64 in 4 bit mode (--> reg value 0)
625 * use burstlen of 16 in 1 bit mode (--> reg value 16)
626 */
627 if (ios->bus_width == MMC_BUS_WIDTH_4)
628 blen = 0;
629 else
630 blen = 16;
631
632 imx_dma_config_burstlen(host->dma, blen);
633#endif
634 if (ios->bus_width == MMC_BUS_WIDTH_4)
635 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
636 else
637 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
638
639 if (host->power_mode != ios->power_mode) {
640 if (host->pdata && host->pdata->setpower)
641 host->pdata->setpower(mmc_dev(mmc), ios->vdd);
642 host->power_mode = ios->power_mode;
643 if (ios->power_mode == MMC_POWER_ON)
644 host->cmdat |= CMD_DAT_CONT_INIT;
645 }
646
647 if (ios->clock) {
648 mxcmci_set_clk_rate(host, ios->clock);
649 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
650 } else {
651 writew(STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK);
652 }
653
654 host->clock = ios->clock;
655}
656
657static irqreturn_t mxcmci_detect_irq(int irq, void *data)
658{
659 struct mmc_host *mmc = data;
660
661 dev_dbg(mmc_dev(mmc), "%s\n", __func__);
662
663 mmc_detect_change(mmc, msecs_to_jiffies(250));
664 return IRQ_HANDLED;
665}
666
667static int mxcmci_get_ro(struct mmc_host *mmc)
668{
669 struct mxcmci_host *host = mmc_priv(mmc);
670
671 if (host->pdata && host->pdata->get_ro)
672 return !!host->pdata->get_ro(mmc_dev(mmc));
673 /*
674 * Board doesn't support read only detection; let the mmc core
675 * decide what to do.
676 */
677 return -ENOSYS;
678}
679
680
681static const struct mmc_host_ops mxcmci_ops = {
682 .request = mxcmci_request,
683 .set_ios = mxcmci_set_ios,
684 .get_ro = mxcmci_get_ro,
685};
686
687static int mxcmci_probe(struct platform_device *pdev)
688{
689 struct mmc_host *mmc;
690 struct mxcmci_host *host = NULL;
c0521baf 691 struct resource *iores, *r;
d96be879
SH		 692 int ret = 0, irq;
693
694 printk(KERN_INFO "i.MX SDHC driver\n");
695
c0521baf 696 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d96be879 697 irq = platform_get_irq(pdev, 0);
c0521baf 698 if (!iores || irq < 0)
d96be879
SH		 699 return -EINVAL;
700
c0521baf 701 r = request_mem_region(iores->start, resource_size(iores), pdev->name);
d96be879
SH		 702 if (!r)
703 return -EBUSY;
704
705 mmc = mmc_alloc_host(sizeof(struct mxcmci_host), &pdev->dev);
706 if (!mmc) {
707 ret = -ENOMEM;
708 goto out_release_mem;
709 }
710
711 mmc->ops = &mxcmci_ops;
712 mmc->caps = MMC_CAP_4_BIT_DATA;
713
714 /* MMC core transfer sizes tunable parameters */
715 mmc->max_hw_segs = 64;
716 mmc->max_phys_segs = 64;
717 mmc->max_blk_size = 2048;
718 mmc->max_blk_count = 65535;
719 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
d759c374 720 mmc->max_seg_size = mmc->max_req_size;
d96be879
SH		 721
722 host = mmc_priv(mmc);
723 host->base = ioremap(r->start, resource_size(r));
724 if (!host->base) {
725 ret = -ENOMEM;
726 goto out_free;
727 }
728
729 host->mmc = mmc;
730 host->pdata = pdev->dev.platform_data;
731
732 if (host->pdata && host->pdata->ocr_avail)
733 mmc->ocr_avail = host->pdata->ocr_avail;
734 else
735 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
736
737 host->res = r;
738 host->irq = irq;
739
06277b5c 740 host->clk = clk_get(&pdev->dev, NULL);
d96be879
SH		 741 if (IS_ERR(host->clk)) {
742 ret = PTR_ERR(host->clk);
743 goto out_iounmap;
744 }
745 clk_enable(host->clk);
746
747 mxcmci_softreset(host);
748
749 host->rev_no = readw(host->base + MMC_REG_REV_NO);
750 if (host->rev_no != 0x400) {
751 ret = -ENODEV;
752 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
753 host->rev_no);
754 goto out_clk_put;
755 }
756
c499b067 757 mmc->f_min = clk_get_rate(host->clk) >> 16;
d96be879
SH		 758 mmc->f_max = clk_get_rate(host->clk) >> 1;
759
760 /* recommended in data sheet */
761 writew(0x2db4, host->base + MMC_REG_READ_TO);
762
763 writel(0, host->base + MMC_REG_INT_CNTR);
764
765#ifdef HAS_DMA
766 host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW);
767 if (host->dma < 0) {
768 dev_err(mmc_dev(host->mmc), "imx_dma_request_by_prio failed\n");
769 ret = -EBUSY;
770 goto out_clk_put;
771 }
772
773 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
774 if (!r) {
775 ret = -EINVAL;
776 goto out_free_dma;
777 }
778
779 ret = imx_dma_config_channel(host->dma,
780 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_FIFO,
781 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
782 r->start, 0);
783 if (ret) {
784 dev_err(mmc_dev(host->mmc), "failed to config DMA channel\n");
785 goto out_free_dma;
786 }
787#endif
788 INIT_WORK(&host->datawork, mxcmci_datawork);
789
790 ret = request_irq(host->irq, mxcmci_irq, 0, DRIVER_NAME, host);
791 if (ret)
792 goto out_free_dma;
793
794 platform_set_drvdata(pdev, mmc);
795
796 if (host->pdata && host->pdata->init) {
797 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq,
798 host->mmc);
799 if (ret)
800 goto out_free_irq;
801 }
802
803 mmc_add_host(mmc);
804
805 return 0;
806
807out_free_irq:
808 free_irq(host->irq, host);
809out_free_dma:
810#ifdef HAS_DMA
811 imx_dma_free(host->dma);
812#endif
813out_clk_put:
814 clk_disable(host->clk);
815 clk_put(host->clk);
816out_iounmap:
817 iounmap(host->base);
818out_free:
819 mmc_free_host(mmc);
820out_release_mem:
c0521baf 821 release_mem_region(iores->start, resource_size(iores));
d96be879
SH		 822 return ret;
823}
824
825static int mxcmci_remove(struct platform_device *pdev)
826{
827 struct mmc_host *mmc = platform_get_drvdata(pdev);
828 struct mxcmci_host *host = mmc_priv(mmc);
829
830 platform_set_drvdata(pdev, NULL);
831
832 mmc_remove_host(mmc);
833
834 if (host->pdata && host->pdata->exit)
835 host->pdata->exit(&pdev->dev, mmc);
836
837 free_irq(host->irq, host);
838 iounmap(host->base);
839#ifdef HAS_DMA
840 imx_dma_free(host->dma);
841#endif
842 clk_disable(host->clk);
843 clk_put(host->clk);
844
845 release_mem_region(host->res->start, resource_size(host->res));
846 release_resource(host->res);
847
848 mmc_free_host(mmc);
849
850 return 0;
851}
852
853#ifdef CONFIG_PM
854static int mxcmci_suspend(struct platform_device *dev, pm_message_t state)
855{
856 struct mmc_host *mmc = platform_get_drvdata(dev);
857 int ret = 0;
858
859 if (mmc)
860 ret = mmc_suspend_host(mmc, state);
861
862 return ret;
863}
864
865static int mxcmci_resume(struct platform_device *dev)
866{
867 struct mmc_host *mmc = platform_get_drvdata(dev);
868 struct mxcmci_host *host;
869 int ret = 0;
870
871 if (mmc) {
872 host = mmc_priv(mmc);
873 ret = mmc_resume_host(mmc);
874 }
875
876 return ret;
877}
878#else
879#define mxcmci_suspend NULL
880#define mxcmci_resume NULL
881#endif /* CONFIG_PM */
882
883static struct platform_driver mxcmci_driver = {
884 .probe = mxcmci_probe,
885 .remove = mxcmci_remove,
886 .suspend = mxcmci_suspend,
887 .resume = mxcmci_resume,
888 .driver = {
889 .name = DRIVER_NAME,
890 .owner = THIS_MODULE,
891 }
892};
893
894static int __init mxcmci_init(void)
895{
896 return platform_driver_register(&mxcmci_driver);
897}
898
899static void __exit mxcmci_exit(void)
900{
901 platform_driver_unregister(&mxcmci_driver);
902}
903
904module_init(mxcmci_init);
905module_exit(mxcmci_exit);
906
907MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
908MODULE_AUTHOR("Sascha Hauer, Pengutronix");
909MODULE_LICENSE("GPL");
910MODULE_ALIAS("platform:imx-mmc");
Linux kernel - Deliverables
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