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mmc: mxcmmc: remove cpu_is_xxx by using platform_device_id
[deliverable/linux.git] / drivers / mmc / host / mxcmmc.c
CommitLineData
d96be879
SH		 1/*
2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
3 *
4 * This is a driver for the SDHC controller found in Freescale MX2/MX3
5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
6 * Unlike the hardware found on MX1, this hardware just works and does
3ad2f3fb 7 * not need all the quirks found in imxmmc.c, hence the separate driver.
d96be879
SH		 8 *
9 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
10 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
11 *
12 * derived from pxamci.c by Russell King
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 *
18 */
19
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/ioport.h>
23#include <linux/platform_device.h>
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/blkdev.h>
27#include <linux/dma-mapping.h>
28#include <linux/mmc/host.h>
29#include <linux/mmc/card.h>
30#include <linux/delay.h>
31#include <linux/clk.h>
32#include <linux/io.h>
33#include <linux/gpio.h>
74b66954 34#include <linux/regulator/consumer.h>
f53fbde4 35#include <linux/dmaengine.h>
258aea76 36#include <linux/types.h>
d96be879
SH		 37
38#include <asm/dma.h>
39#include <asm/irq.h>
40#include <asm/sizes.h>
82906b13 41#include <linux/platform_data/mmc-mxcmmc.h>
d96be879 42
82906b13 43#include <linux/platform_data/dma-imx.h>
d96be879 44
9563b1db 45#define DRIVER_NAME "mxc-mmc"
f6ad0a48 46#define MXCMCI_TIMEOUT_MS 10000
d96be879
SH		 47
48#define MMC_REG_STR_STP_CLK 0x00
49#define MMC_REG_STATUS 0x04
50#define MMC_REG_CLK_RATE 0x08
51#define MMC_REG_CMD_DAT_CONT 0x0C
52#define MMC_REG_RES_TO 0x10
53#define MMC_REG_READ_TO 0x14
54#define MMC_REG_BLK_LEN 0x18
55#define MMC_REG_NOB 0x1C
56#define MMC_REG_REV_NO 0x20
57#define MMC_REG_INT_CNTR 0x24
58#define MMC_REG_CMD 0x28
59#define MMC_REG_ARG 0x2C
60#define MMC_REG_RES_FIFO 0x34
61#define MMC_REG_BUFFER_ACCESS 0x38
62
63#define STR_STP_CLK_RESET (1 << 3)
64#define STR_STP_CLK_START_CLK (1 << 1)
65#define STR_STP_CLK_STOP_CLK (1 << 0)
66
67#define STATUS_CARD_INSERTION (1 << 31)
68#define STATUS_CARD_REMOVAL (1 << 30)
69#define STATUS_YBUF_EMPTY (1 << 29)
70#define STATUS_XBUF_EMPTY (1 << 28)
71#define STATUS_YBUF_FULL (1 << 27)
72#define STATUS_XBUF_FULL (1 << 26)
73#define STATUS_BUF_UND_RUN (1 << 25)
74#define STATUS_BUF_OVFL (1 << 24)
75#define STATUS_SDIO_INT_ACTIVE (1 << 14)
76#define STATUS_END_CMD_RESP (1 << 13)
77#define STATUS_WRITE_OP_DONE (1 << 12)
78#define STATUS_DATA_TRANS_DONE (1 << 11)
79#define STATUS_READ_OP_DONE (1 << 11)
80#define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
81#define STATUS_CARD_BUS_CLK_RUN (1 << 8)
82#define STATUS_BUF_READ_RDY (1 << 7)
83#define STATUS_BUF_WRITE_RDY (1 << 6)
84#define STATUS_RESP_CRC_ERR (1 << 5)
85#define STATUS_CRC_READ_ERR (1 << 3)
86#define STATUS_CRC_WRITE_ERR (1 << 2)
87#define STATUS_TIME_OUT_RESP (1 << 1)
88#define STATUS_TIME_OUT_READ (1 << 0)
89#define STATUS_ERR_MASK 0x2f
90
91#define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
92#define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
93#define CMD_DAT_CONT_START_READWAIT (1 << 10)
94#define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
95#define CMD_DAT_CONT_INIT (1 << 7)
96#define CMD_DAT_CONT_WRITE (1 << 4)
97#define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
98#define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
99#define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
100#define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
101
102#define INT_SDIO_INT_WKP_EN (1 << 18)
103#define INT_CARD_INSERTION_WKP_EN (1 << 17)
104#define INT_CARD_REMOVAL_WKP_EN (1 << 16)
105#define INT_CARD_INSERTION_EN (1 << 15)
106#define INT_CARD_REMOVAL_EN (1 << 14)
107#define INT_SDIO_IRQ_EN (1 << 13)
108#define INT_DAT0_EN (1 << 12)
109#define INT_BUF_READ_EN (1 << 4)
110#define INT_BUF_WRITE_EN (1 << 3)
111#define INT_END_CMD_RES_EN (1 << 2)
112#define INT_WRITE_OP_DONE_EN (1 << 1)
113#define INT_READ_OP_EN (1 << 0)
114
7f917a8d
SG		 115enum mxcmci_type {
116 IMX21_MMC,
117 IMX31_MMC,
118};
119
d96be879
SH		 120struct mxcmci_host {
121 struct mmc_host *mmc;
122 struct resource *res;
123 void __iomem *base;
124 int irq;
125 int detect_irq;
f53fbde4
SH		 126 struct dma_chan *dma;
127 struct dma_async_tx_descriptor *desc;
d96be879 128 int do_dma;
16b3bf8c 129 int default_irq_mask;
f441b993 130 int use_sdio;
d96be879
SH		 131 unsigned int power_mode;
132 struct imxmmc_platform_data *pdata;
133
134 struct mmc_request *req;
135 struct mmc_command *cmd;
136 struct mmc_data *data;
137
d96be879
SH		 138 unsigned int datasize;
139 unsigned int dma_dir;
140
141 u16 rev_no;
142 unsigned int cmdat;
143
529aa29e
SH		 144 struct clk *clk_ipg;
145 struct clk *clk_per;
d96be879
SH		 146
147 int clock;
148
149 struct work_struct datawork;
f441b993 150 spinlock_t lock;
74b66954
AP		 151
152 struct regulator *vcc;
f53fbde4
SH		 153
154 int burstlen;
155 int dmareq;
156 struct dma_slave_config dma_slave_config;
157 struct imx_dma_data dma_data;
f6ad0a48
JM		 158
159 struct timer_list watchdog;
7f917a8d
SG		 160 enum mxcmci_type devtype;
161};
162
163static struct platform_device_id mxcmci_devtype[] = {
164 {
165 .name = "imx21-mmc",
166 .driver_data = IMX21_MMC,
167 }, {
168 .name = "imx31-mmc",
169 .driver_data = IMX31_MMC,
170 }, {
171 /* sentinel */
172 }
d96be879 173};
7f917a8d
SG		 174MODULE_DEVICE_TABLE(platform, mxcmci_devtype);
175
176static inline int is_imx31_mmc(struct mxcmci_host *host)
177{
178 return host->devtype == IMX31_MMC;
179}
d96be879 180
18489fa2
MF		 181static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
182
74b66954
AP		 183static inline void mxcmci_init_ocr(struct mxcmci_host *host)
184{
74b66954
AP		 185 host->vcc = regulator_get(mmc_dev(host->mmc), "vmmc");
186
187 if (IS_ERR(host->vcc)) {
188 host->vcc = NULL;
189 } else {
190 host->mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vcc);
191 if (host->pdata && host->pdata->ocr_avail)
192 dev_warn(mmc_dev(host->mmc),
193 "pdata->ocr_avail will not be used\n");
194 }
d078d242 195
74b66954
AP		 196 if (host->vcc == NULL) {
197 /* fall-back to platform data */
198 if (host->pdata && host->pdata->ocr_avail)
199 host->mmc->ocr_avail = host->pdata->ocr_avail;
200 else
201 host->mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
202 }
203}
204
d078d242
AP		 205static inline void mxcmci_set_power(struct mxcmci_host *host,
206 unsigned char power_mode,
207 unsigned int vdd)
74b66954 208{
d078d242
AP		 209 if (host->vcc) {
210 if (power_mode == MMC_POWER_UP)
211 mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
212 else if (power_mode == MMC_POWER_OFF)
213 mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
214 }
215
74b66954
AP		 216 if (host->pdata && host->pdata->setpower)
217 host->pdata->setpower(mmc_dev(host->mmc), vdd);
218}
219
d96be879
SH		 220static inline int mxcmci_use_dma(struct mxcmci_host *host)
221{
222 return host->do_dma;
223}
224
225static void mxcmci_softreset(struct mxcmci_host *host)
226{
227 int i;
228
4725f6f1
DM		 229 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n");
230
d96be879
SH		 231 /* reset sequence */
232 writew(STR_STP_CLK_RESET, host->base + MMC_REG_STR_STP_CLK);
233 writew(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
234 host->base + MMC_REG_STR_STP_CLK);
235
236 for (i = 0; i < 8; i++)
237 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
238
239 writew(0xff, host->base + MMC_REG_RES_TO);
240}
f53fbde4 241static int mxcmci_setup_dma(struct mmc_host *mmc);
d96be879 242
656217d2 243static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
d96be879
SH		 244{
245 unsigned int nob = data->blocks;
246 unsigned int blksz = data->blksz;
247 unsigned int datasize = nob * blksz;
d96be879 248 struct scatterlist *sg;
05f5799c 249 enum dma_transfer_direction slave_dirn;
f53fbde4
SH		 250 int i, nents;
251
d96be879
SH		 252 if (data->flags & MMC_DATA_STREAM)
253 nob = 0xffff;
254
255 host->data = data;
256 data->bytes_xfered = 0;
257
258 writew(nob, host->base + MMC_REG_NOB);
259 writew(blksz, host->base + MMC_REG_BLK_LEN);
260 host->datasize = datasize;
261
f53fbde4
SH		 262 if (!mxcmci_use_dma(host))
263 return 0;
264
d96be879
SH		 265 for_each_sg(data->sg, sg, data->sg_len, i) {
266 if (sg->offset & 3 || sg->length & 3) {
267 host->do_dma = 0;
656217d2 268 return 0;
d96be879
SH		 269 }
270 }
271
05f5799c 272 if (data->flags & MMC_DATA_READ) {
d96be879 273 host->dma_dir = DMA_FROM_DEVICE;
05f5799c
VK		 274 slave_dirn = DMA_DEV_TO_MEM;
275 } else {
d96be879 276 host->dma_dir = DMA_TO_DEVICE;
05f5799c
VK		 277 slave_dirn = DMA_MEM_TO_DEV;
278 }
d96be879 279
f53fbde4
SH		 280 nents = dma_map_sg(host->dma->device->dev, data->sg,
281 data->sg_len, host->dma_dir);
282 if (nents != data->sg_len)
283 return -EINVAL;
284
16052827 285 host->desc = dmaengine_prep_slave_sg(host->dma,
05f5799c 286 data->sg, data->sg_len, slave_dirn,
f53fbde4 287 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
d96be879 288
f53fbde4
SH		 289 if (!host->desc) {
290 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
291 host->dma_dir);
292 host->do_dma = 0;
293 return 0; /* Fall back to PIO */
656217d2 294 }
d96be879
SH		 295 wmb();
296
f53fbde4 297 dmaengine_submit(host->desc);
439aa0ef 298 dma_async_issue_pending(host->dma);
f53fbde4 299
f6ad0a48
JM		 300 mod_timer(&host->watchdog, jiffies + msecs_to_jiffies(MXCMCI_TIMEOUT_MS));
301
656217d2 302 return 0;
d96be879
SH		 303}
304
f6ad0a48
JM		 305static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat);
306static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat);
307
308static void mxcmci_dma_callback(void *data)
309{
310 struct mxcmci_host *host = data;
311 u32 stat;
312
313 del_timer(&host->watchdog);
314
315 stat = readl(host->base + MMC_REG_STATUS);
316 writel(stat & ~STATUS_DATA_TRANS_DONE, host->base + MMC_REG_STATUS);
317
318 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
319
320 if (stat & STATUS_READ_OP_DONE)
321 writel(STATUS_READ_OP_DONE, host->base + MMC_REG_STATUS);
322
323 mxcmci_data_done(host, stat);
324}
325
d96be879
SH		 326static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
327 unsigned int cmdat)
328{
16b3bf8c 329 u32 int_cntr = host->default_irq_mask;
f441b993
DM		 330 unsigned long flags;
331
d96be879
SH		 332 WARN_ON(host->cmd != NULL);
333 host->cmd = cmd;
334
335 switch (mmc_resp_type(cmd)) {
336 case MMC_RSP_R1: /* short CRC, OPCODE */
337 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
338 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
339 break;
340 case MMC_RSP_R2: /* long 136 bit + CRC */
341 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
342 break;
343 case MMC_RSP_R3: /* short */
344 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
345 break;
346 case MMC_RSP_NONE:
347 break;
348 default:
349 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n",
350 mmc_resp_type(cmd));
351 cmd->error = -EINVAL;
352 return -EINVAL;
353 }
354
f441b993
DM		 355 int_cntr = INT_END_CMD_RES_EN;
356
f6ad0a48
JM		 357 if (mxcmci_use_dma(host)) {
358 if (host->dma_dir == DMA_FROM_DEVICE) {
359 host->desc->callback = mxcmci_dma_callback;
360 host->desc->callback_param = host;
361 } else {
362 int_cntr |= INT_WRITE_OP_DONE_EN;
363 }
364 }
f441b993
DM		 365
366 spin_lock_irqsave(&host->lock, flags);
367 if (host->use_sdio)
368 int_cntr |= INT_SDIO_IRQ_EN;
369 writel(int_cntr, host->base + MMC_REG_INT_CNTR);
370 spin_unlock_irqrestore(&host->lock, flags);
d96be879
SH		 371
372 writew(cmd->opcode, host->base + MMC_REG_CMD);
373 writel(cmd->arg, host->base + MMC_REG_ARG);
374 writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT);
375
376 return 0;
377}
378
379static void mxcmci_finish_request(struct mxcmci_host *host,
380 struct mmc_request *req)
381{
16b3bf8c 382 u32 int_cntr = host->default_irq_mask;
f441b993
DM		 383 unsigned long flags;
384
385 spin_lock_irqsave(&host->lock, flags);
386 if (host->use_sdio)
387 int_cntr |= INT_SDIO_IRQ_EN;
388 writel(int_cntr, host->base + MMC_REG_INT_CNTR);
389 spin_unlock_irqrestore(&host->lock, flags);
d96be879
SH		 390
391 host->req = NULL;
392 host->cmd = NULL;
393 host->data = NULL;
394
395 mmc_request_done(host->mmc, req);
396}
397
398static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
399{
400 struct mmc_data *data = host->data;
401 int data_error;
402
f6ad0a48 403 if (mxcmci_use_dma(host))
f53fbde4 404 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
d96be879 405 host->dma_dir);
d96be879
SH		 406
407 if (stat & STATUS_ERR_MASK) {
408 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
409 stat);
410 if (stat & STATUS_CRC_READ_ERR) {
4725f6f1 411 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__);
d96be879
SH		 412 data->error = -EILSEQ;
413 } else if (stat & STATUS_CRC_WRITE_ERR) {
414 u32 err_code = (stat >> 9) & 0x3;
4725f6f1
DM		 415 if (err_code == 2) { /* No CRC response */
416 dev_err(mmc_dev(host->mmc),
417 "%s: No CRC -ETIMEDOUT\n", __func__);
d96be879 418 data->error = -ETIMEDOUT;
4725f6f1
DM		 419 } else {
420 dev_err(mmc_dev(host->mmc),
421 "%s: -EILSEQ\n", __func__);
d96be879 422 data->error = -EILSEQ;
4725f6f1 423 }
d96be879 424 } else if (stat & STATUS_TIME_OUT_READ) {
4725f6f1
DM		 425 dev_err(mmc_dev(host->mmc),
426 "%s: read -ETIMEDOUT\n", __func__);
d96be879
SH		 427 data->error = -ETIMEDOUT;
428 } else {
4725f6f1 429 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__);
d96be879
SH		 430 data->error = -EIO;
431 }
432 } else {
433 data->bytes_xfered = host->datasize;
434 }
435
436 data_error = data->error;
437
438 host->data = NULL;
439
440 return data_error;
441}
442
443static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
444{
445 struct mmc_command *cmd = host->cmd;
446 int i;
447 u32 a, b, c;
448
449 if (!cmd)
450 return;
451
452 if (stat & STATUS_TIME_OUT_RESP) {
453 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
454 cmd->error = -ETIMEDOUT;
455 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
456 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
457 cmd->error = -EILSEQ;
458 }
459
460 if (cmd->flags & MMC_RSP_PRESENT) {
461 if (cmd->flags & MMC_RSP_136) {
462 for (i = 0; i < 4; i++) {
463 a = readw(host->base + MMC_REG_RES_FIFO);
464 b = readw(host->base + MMC_REG_RES_FIFO);
465 cmd->resp[i] = a << 16 | b;
466 }
467 } else {
468 a = readw(host->base + MMC_REG_RES_FIFO);
469 b = readw(host->base + MMC_REG_RES_FIFO);
470 c = readw(host->base + MMC_REG_RES_FIFO);
471 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
472 }
473 }
474}
475
476static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
477{
478 u32 stat;
479 unsigned long timeout = jiffies + HZ;
480
481 do {
482 stat = readl(host->base + MMC_REG_STATUS);
483 if (stat & STATUS_ERR_MASK)
484 return stat;
18489fa2
MF		 485 if (time_after(jiffies, timeout)) {
486 mxcmci_softreset(host);
487 mxcmci_set_clk_rate(host, host->clock);
d96be879 488 return STATUS_TIME_OUT_READ;
18489fa2 489 }
d96be879
SH		 490 if (stat & mask)
491 return 0;
492 cpu_relax();
493 } while (1);
494}
495
496static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
497{
498 unsigned int stat;
499 u32 *buf = _buf;
500
501 while (bytes > 3) {
502 stat = mxcmci_poll_status(host,
503 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
504 if (stat)
505 return stat;
506 *buf++ = readl(host->base + MMC_REG_BUFFER_ACCESS);
507 bytes -= 4;
508 }
509
510 if (bytes) {
511 u8 *b = (u8 *)buf;
512 u32 tmp;
513
514 stat = mxcmci_poll_status(host,
515 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
516 if (stat)
517 return stat;
518 tmp = readl(host->base + MMC_REG_BUFFER_ACCESS);
519 memcpy(b, &tmp, bytes);
520 }
521
522 return 0;
523}
524
525static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes)
526{
527 unsigned int stat;
528 u32 *buf = _buf;
529
530 while (bytes > 3) {
531 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
532 if (stat)
533 return stat;
534 writel(*buf++, host->base + MMC_REG_BUFFER_ACCESS);
535 bytes -= 4;
536 }
537
538 if (bytes) {
539 u8 *b = (u8 *)buf;
540 u32 tmp;
541
542 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
543 if (stat)
544 return stat;
545
546 memcpy(&tmp, b, bytes);
547 writel(tmp, host->base + MMC_REG_BUFFER_ACCESS);
548 }
549
550 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
551 if (stat)
552 return stat;
553
554 return 0;
555}
556
557static int mxcmci_transfer_data(struct mxcmci_host *host)
558{
559 struct mmc_data *data = host->req->data;
560 struct scatterlist *sg;
561 int stat, i;
562
d96be879
SH		 563 host->data = data;
564 host->datasize = 0;
565
566 if (data->flags & MMC_DATA_READ) {
567 for_each_sg(data->sg, sg, data->sg_len, i) {
568 stat = mxcmci_pull(host, sg_virt(sg), sg->length);
569 if (stat)
570 return stat;
571 host->datasize += sg->length;
572 }
573 } else {
574 for_each_sg(data->sg, sg, data->sg_len, i) {
575 stat = mxcmci_push(host, sg_virt(sg), sg->length);
576 if (stat)
577 return stat;
578 host->datasize += sg->length;
579 }
580 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
581 if (stat)
582 return stat;
583 }
584 return 0;
585}
586
587static void mxcmci_datawork(struct work_struct *work)
588{
589 struct mxcmci_host *host = container_of(work, struct mxcmci_host,
590 datawork);
591 int datastat = mxcmci_transfer_data(host);
4a31f2ef
DM		 592
593 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
594 host->base + MMC_REG_STATUS);
d96be879
SH		 595 mxcmci_finish_data(host, datastat);
596
597 if (host->req->stop) {
598 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
599 mxcmci_finish_request(host, host->req);
600 return;
601 }
602 } else {
603 mxcmci_finish_request(host, host->req);
604 }
605}
606
d96be879
SH		 607static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
608{
609 struct mmc_data *data = host->data;
610 int data_error;
611
612 if (!data)
613 return;
614
615 data_error = mxcmci_finish_data(host, stat);
616
617 mxcmci_read_response(host, stat);
618 host->cmd = NULL;
619
620 if (host->req->stop) {
621 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
622 mxcmci_finish_request(host, host->req);
623 return;
624 }
625 } else {
626 mxcmci_finish_request(host, host->req);
627 }
628}
d96be879
SH		 629
630static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
631{
632 mxcmci_read_response(host, stat);
633 host->cmd = NULL;
634
635 if (!host->data && host->req) {
636 mxcmci_finish_request(host, host->req);
637 return;
638 }
639
640 /* For the DMA case the DMA engine handles the data transfer
fd589a8f 641 * automatically. For non DMA we have to do it ourselves.
d96be879
SH		 642 * Don't do it in interrupt context though.
643 */
644 if (!mxcmci_use_dma(host) && host->data)
645 schedule_work(&host->datawork);
646
647}
648
649static irqreturn_t mxcmci_irq(int irq, void *devid)
650{
651 struct mxcmci_host *host = devid;
f441b993
DM		 652 unsigned long flags;
653 bool sdio_irq;
d96be879
SH		 654 u32 stat;
655
656 stat = readl(host->base + MMC_REG_STATUS);
4a31f2ef
DM		 657 writel(stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE |
658 STATUS_WRITE_OP_DONE), host->base + MMC_REG_STATUS);
d96be879
SH		 659
660 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
661
f441b993
DM		 662 spin_lock_irqsave(&host->lock, flags);
663 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio;
664 spin_unlock_irqrestore(&host->lock, flags);
665
4a31f2ef
DM		 666 if (mxcmci_use_dma(host) &&
667 (stat & (STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE)))
668 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
669 host->base + MMC_REG_STATUS);
4a31f2ef 670
f441b993
DM		 671 if (sdio_irq) {
672 writel(STATUS_SDIO_INT_ACTIVE, host->base + MMC_REG_STATUS);
673 mmc_signal_sdio_irq(host->mmc);
674 }
675
d96be879
SH		 676 if (stat & STATUS_END_CMD_RESP)
677 mxcmci_cmd_done(host, stat);
f441b993 678
d96be879 679 if (mxcmci_use_dma(host) &&
f6ad0a48
JM		 680 (stat & (STATUS_DATA_TRANS_DONE | STATUS_WRITE_OP_DONE))) {
681 del_timer(&host->watchdog);
d96be879 682 mxcmci_data_done(host, stat);
f6ad0a48 683 }
f53fbde4 684
16b3bf8c
EB		 685 if (host->default_irq_mask &&
686 (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL)))
687 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
f53fbde4 688
d96be879
SH		 689 return IRQ_HANDLED;
690}
691
692static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
693{
694 struct mxcmci_host *host = mmc_priv(mmc);
695 unsigned int cmdat = host->cmdat;
656217d2 696 int error;
d96be879
SH		 697
698 WARN_ON(host->req != NULL);
699
700 host->req = req;
701 host->cmdat &= ~CMD_DAT_CONT_INIT;
f53fbde4
SH		 702
703 if (host->dma)
704 host->do_dma = 1;
705
d96be879 706 if (req->data) {
656217d2
MF		 707 error = mxcmci_setup_data(host, req->data);
708 if (error) {
709 req->cmd->error = error;
710 goto out;
711 }
712
d96be879
SH		 713
714 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
715
716 if (req->data->flags & MMC_DATA_WRITE)
717 cmdat |= CMD_DAT_CONT_WRITE;
718 }
719
656217d2 720 error = mxcmci_start_cmd(host, req->cmd, cmdat);
f53fbde4 721
656217d2
MF		 722out:
723 if (error)
d96be879
SH		 724 mxcmci_finish_request(host, req);
725}
726
727static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
728{
729 unsigned int divider;
730 int prescaler = 0;
529aa29e 731 unsigned int clk_in = clk_get_rate(host->clk_per);
d96be879
SH		 732
733 while (prescaler <= 0x800) {
734 for (divider = 1; divider <= 0xF; divider++) {
735 int x;
736
737 x = (clk_in / (divider + 1));
738
739 if (prescaler)
740 x /= (prescaler * 2);
741
742 if (x <= clk_ios)
743 break;
744 }
745 if (divider < 0x10)
746 break;
747
748 if (prescaler == 0)
749 prescaler = 1;
750 else
751 prescaler <<= 1;
752 }
753
754 writew((prescaler << 4) | divider, host->base + MMC_REG_CLK_RATE);
755
756 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
757 prescaler, divider, clk_in, clk_ios);
758}
759
f53fbde4
SH		 760static int mxcmci_setup_dma(struct mmc_host *mmc)
761{
762 struct mxcmci_host *host = mmc_priv(mmc);
763 struct dma_slave_config *config = &host->dma_slave_config;
764
765 config->dst_addr = host->res->start + MMC_REG_BUFFER_ACCESS;
766 config->src_addr = host->res->start + MMC_REG_BUFFER_ACCESS;
767 config->dst_addr_width = 4;
768 config->src_addr_width = 4;
769 config->dst_maxburst = host->burstlen;
770 config->src_maxburst = host->burstlen;
258aea76 771 config->device_fc = false;
f53fbde4
SH		 772
773 return dmaengine_slave_config(host->dma, config);
774}
775
d96be879
SH		 776static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
777{
778 struct mxcmci_host *host = mmc_priv(mmc);
f53fbde4
SH		 779 int burstlen, ret;
780
d96be879 781 /*
6584cb88
SH		 782 * use burstlen of 64 (16 words) in 4 bit mode (--> reg value 0)
783 * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16)
d96be879
SH		 784 */
785 if (ios->bus_width == MMC_BUS_WIDTH_4)
f53fbde4 786 burstlen = 16;
6584cb88
SH		 787 else
788 burstlen = 4;
f53fbde4
SH		 789
790 if (mxcmci_use_dma(host) && burstlen != host->burstlen) {
791 host->burstlen = burstlen;
792 ret = mxcmci_setup_dma(mmc);
793 if (ret) {
794 dev_err(mmc_dev(host->mmc),
795 "failed to config DMA channel. Falling back to PIO\n");
796 dma_release_channel(host->dma);
797 host->do_dma = 0;
e58f516f 798 host->dma = NULL;
f53fbde4
SH		 799 }
800 }
d96be879 801
d96be879
SH		 802 if (ios->bus_width == MMC_BUS_WIDTH_4)
803 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
804 else
805 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
806
807 if (host->power_mode != ios->power_mode) {
d078d242 808 mxcmci_set_power(host, ios->power_mode, ios->vdd);
d96be879 809 host->power_mode = ios->power_mode;
74b66954 810
d96be879
SH		 811 if (ios->power_mode == MMC_POWER_ON)
812 host->cmdat |= CMD_DAT_CONT_INIT;
813 }
814
815 if (ios->clock) {
816 mxcmci_set_clk_rate(host, ios->clock);
817 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
818 } else {
819 writew(STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK);
820 }
821
822 host->clock = ios->clock;
823}
824
825static irqreturn_t mxcmci_detect_irq(int irq, void *data)
826{
827 struct mmc_host *mmc = data;
828
829 dev_dbg(mmc_dev(mmc), "%s\n", __func__);
830
831 mmc_detect_change(mmc, msecs_to_jiffies(250));
832 return IRQ_HANDLED;
833}
834
835static int mxcmci_get_ro(struct mmc_host *mmc)
836{
837 struct mxcmci_host *host = mmc_priv(mmc);
838
839 if (host->pdata && host->pdata->get_ro)
840 return !!host->pdata->get_ro(mmc_dev(mmc));
841 /*
842 * Board doesn't support read only detection; let the mmc core
843 * decide what to do.
844 */
845 return -ENOSYS;
846}
847
f441b993
DM		 848static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
849{
850 struct mxcmci_host *host = mmc_priv(mmc);
851 unsigned long flags;
852 u32 int_cntr;
853
854 spin_lock_irqsave(&host->lock, flags);
855 host->use_sdio = enable;
856 int_cntr = readl(host->base + MMC_REG_INT_CNTR);
857
858 if (enable)
859 int_cntr |= INT_SDIO_IRQ_EN;
860 else
861 int_cntr &= ~INT_SDIO_IRQ_EN;
862
863 writel(int_cntr, host->base + MMC_REG_INT_CNTR);
864 spin_unlock_irqrestore(&host->lock, flags);
865}
d96be879 866
3fcb027d
DM		 867static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card)
868{
7f917a8d
SG		 869 struct mxcmci_host *mxcmci = mmc_priv(host);
870
3fcb027d
DM		 871 /*
872 * MX3 SoCs have a silicon bug which corrupts CRC calculation of
873 * multi-block transfers when connected SDIO peripheral doesn't
874 * drive the BUSY line as required by the specs.
875 * One way to prevent this is to only allow 1-bit transfers.
876 */
877
7f917a8d 878 if (is_imx31_mmc(mxcmci) && card->type == MMC_TYPE_SDIO)
3fcb027d
DM		 879 host->caps &= ~MMC_CAP_4_BIT_DATA;
880 else
881 host->caps |= MMC_CAP_4_BIT_DATA;
882}
883
f53fbde4
SH		 884static bool filter(struct dma_chan *chan, void *param)
885{
886 struct mxcmci_host *host = param;
887
888 if (!imx_dma_is_general_purpose(chan))
889 return false;
890
891 chan->private = &host->dma_data;
892
893 return true;
894}
895
f6ad0a48
JM		 896static void mxcmci_watchdog(unsigned long data)
897{
898 struct mmc_host *mmc = (struct mmc_host *)data;
899 struct mxcmci_host *host = mmc_priv(mmc);
900 struct mmc_request *req = host->req;
901 unsigned int stat = readl(host->base + MMC_REG_STATUS);
902
903 if (host->dma_dir == DMA_FROM_DEVICE) {
904 dmaengine_terminate_all(host->dma);
905 dev_err(mmc_dev(host->mmc),
906 "%s: read time out (status = 0x%08x)\n",
907 __func__, stat);
908 } else {
909 dev_err(mmc_dev(host->mmc),
910 "%s: write time out (status = 0x%08x)\n",
911 __func__, stat);
912 mxcmci_softreset(host);
913 }
914
915 /* Mark transfer as erroneus and inform the upper layers */
916
917 host->data->error = -ETIMEDOUT;
918 host->req = NULL;
919 host->cmd = NULL;
920 host->data = NULL;
921 mmc_request_done(host->mmc, req);
922}
923
d96be879 924static const struct mmc_host_ops mxcmci_ops = {
f441b993
DM		 925 .request = mxcmci_request,
926 .set_ios = mxcmci_set_ios,
927 .get_ro = mxcmci_get_ro,
928 .enable_sdio_irq = mxcmci_enable_sdio_irq,
3fcb027d 929 .init_card = mxcmci_init_card,
d96be879
SH		 930};
931
932static int mxcmci_probe(struct platform_device *pdev)
933{
934 struct mmc_host *mmc;
935 struct mxcmci_host *host = NULL;
c0521baf 936 struct resource *iores, *r;
d96be879 937 int ret = 0, irq;
f53fbde4 938 dma_cap_mask_t mask;
d96be879 939
a3c76eb9 940 pr_info("i.MX SDHC driver\n");
d96be879 941
c0521baf 942 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d96be879 943 irq = platform_get_irq(pdev, 0);
c0521baf 944 if (!iores || irq < 0)
d96be879
SH		 945 return -EINVAL;
946
c0521baf 947 r = request_mem_region(iores->start, resource_size(iores), pdev->name);
d96be879
SH		 948 if (!r)
949 return -EBUSY;
950
951 mmc = mmc_alloc_host(sizeof(struct mxcmci_host), &pdev->dev);
952 if (!mmc) {
953 ret = -ENOMEM;
954 goto out_release_mem;
955 }
956
957 mmc->ops = &mxcmci_ops;
f441b993 958 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
d96be879
SH		 959
960 /* MMC core transfer sizes tunable parameters */
a36274e0 961 mmc->max_segs = 64;
d96be879
SH		 962 mmc->max_blk_size = 2048;
963 mmc->max_blk_count = 65535;
964 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
d759c374 965 mmc->max_seg_size = mmc->max_req_size;
d96be879
SH		 966
967 host = mmc_priv(mmc);
968 host->base = ioremap(r->start, resource_size(r));
969 if (!host->base) {
970 ret = -ENOMEM;
971 goto out_free;
972 }
973
974 host->mmc = mmc;
975 host->pdata = pdev->dev.platform_data;
7f917a8d 976 host->devtype = pdev->id_entry->driver_data;
f441b993 977 spin_lock_init(&host->lock);
d96be879 978
74b66954 979 mxcmci_init_ocr(host);
d96be879 980
16b3bf8c
EB		 981 if (host->pdata && host->pdata->dat3_card_detect)
982 host->default_irq_mask =
983 INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN;
984 else
985 host->default_irq_mask = 0;
986
d96be879
SH		 987 host->res = r;
988 host->irq = irq;
989
529aa29e
SH		 990 host->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
991 if (IS_ERR(host->clk_ipg)) {
992 ret = PTR_ERR(host->clk_ipg);
d96be879
SH		 993 goto out_iounmap;
994 }
529aa29e
SH		 995
996 host->clk_per = devm_clk_get(&pdev->dev, "per");
997 if (IS_ERR(host->clk_per)) {
998 ret = PTR_ERR(host->clk_per);
999 goto out_iounmap;
1000 }
1001
1002 clk_prepare_enable(host->clk_per);
1003 clk_prepare_enable(host->clk_ipg);
d96be879
SH		 1004
1005 mxcmci_softreset(host);
1006
1007 host->rev_no = readw(host->base + MMC_REG_REV_NO);
1008 if (host->rev_no != 0x400) {
1009 ret = -ENODEV;
1010 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
1011 host->rev_no);
1012 goto out_clk_put;
1013 }
1014
529aa29e
SH		 1015 mmc->f_min = clk_get_rate(host->clk_per) >> 16;
1016 mmc->f_max = clk_get_rate(host->clk_per) >> 1;
d96be879
SH		 1017
1018 /* recommended in data sheet */
1019 writew(0x2db4, host->base + MMC_REG_READ_TO);
1020
16b3bf8c 1021 writel(host->default_irq_mask, host->base + MMC_REG_INT_CNTR);
d96be879 1022
d96be879 1023 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
f53fbde4
SH		 1024 if (r) {
1025 host->dmareq = r->start;
1026 host->dma_data.peripheral_type = IMX_DMATYPE_SDHC;
1027 host->dma_data.priority = DMA_PRIO_LOW;
1028 host->dma_data.dma_request = host->dmareq;
1029 dma_cap_zero(mask);
1030 dma_cap_set(DMA_SLAVE, mask);
1031 host->dma = dma_request_channel(mask, filter, host);
1032 if (host->dma)
1033 mmc->max_seg_size = dma_get_max_seg_size(
1034 host->dma->device->dev);
1035 }
1036
1037 if (!host->dma)
1038 dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n");
d96be879 1039
d96be879
SH		 1040 INIT_WORK(&host->datawork, mxcmci_datawork);
1041
1042 ret = request_irq(host->irq, mxcmci_irq, 0, DRIVER_NAME, host);
1043 if (ret)
1044 goto out_free_dma;
1045
1046 platform_set_drvdata(pdev, mmc);
1047
1048 if (host->pdata && host->pdata->init) {
1049 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq,
1050 host->mmc);
1051 if (ret)
1052 goto out_free_irq;
1053 }
1054
1055 mmc_add_host(mmc);
1056
f6ad0a48
JM		 1057 init_timer(&host->watchdog);
1058 host->watchdog.function = &mxcmci_watchdog;
1059 host->watchdog.data = (unsigned long)mmc;
1060
d96be879
SH		 1061 return 0;
1062
1063out_free_irq:
1064 free_irq(host->irq, host);
1065out_free_dma:
f53fbde4
SH		 1066 if (host->dma)
1067 dma_release_channel(host->dma);
d96be879 1068out_clk_put:
529aa29e
SH		 1069 clk_disable_unprepare(host->clk_per);
1070 clk_disable_unprepare(host->clk_ipg);
d96be879
SH		 1071out_iounmap:
1072 iounmap(host->base);
1073out_free:
1074 mmc_free_host(mmc);
1075out_release_mem:
c0521baf 1076 release_mem_region(iores->start, resource_size(iores));
d96be879
SH		 1077 return ret;
1078}
1079
1080static int mxcmci_remove(struct platform_device *pdev)
1081{
1082 struct mmc_host *mmc = platform_get_drvdata(pdev);
1083 struct mxcmci_host *host = mmc_priv(mmc);
1084
1085 platform_set_drvdata(pdev, NULL);
1086
1087 mmc_remove_host(mmc);
1088
74b66954
AP		 1089 if (host->vcc)
1090 regulator_put(host->vcc);
1091
d96be879
SH		 1092 if (host->pdata && host->pdata->exit)
1093 host->pdata->exit(&pdev->dev, mmc);
1094
1095 free_irq(host->irq, host);
1096 iounmap(host->base);
f53fbde4
SH		 1097
1098 if (host->dma)
1099 dma_release_channel(host->dma);
1100
529aa29e
SH		 1101 clk_disable_unprepare(host->clk_per);
1102 clk_disable_unprepare(host->clk_ipg);
d96be879
SH		 1103
1104 release_mem_region(host->res->start, resource_size(host->res));
d96be879
SH		 1105
1106 mmc_free_host(mmc);
1107
1108 return 0;
1109}
1110
1111#ifdef CONFIG_PM
a7d403cf 1112static int mxcmci_suspend(struct device *dev)
d96be879 1113{
a7d403cf
EB		 1114 struct mmc_host *mmc = dev_get_drvdata(dev);
1115 struct mxcmci_host *host = mmc_priv(mmc);
d96be879
SH		 1116 int ret = 0;
1117
1118 if (mmc)
1a13f8fa 1119 ret = mmc_suspend_host(mmc);
529aa29e
SH		 1120 clk_disable_unprepare(host->clk_per);
1121 clk_disable_unprepare(host->clk_ipg);
d96be879
SH		 1122
1123 return ret;
1124}
1125
a7d403cf 1126static int mxcmci_resume(struct device *dev)
d96be879 1127{
a7d403cf
EB		 1128 struct mmc_host *mmc = dev_get_drvdata(dev);
1129 struct mxcmci_host *host = mmc_priv(mmc);
d96be879
SH		 1130 int ret = 0;
1131
529aa29e
SH		 1132 clk_prepare_enable(host->clk_per);
1133 clk_prepare_enable(host->clk_ipg);
a7d403cf 1134 if (mmc)
d96be879 1135 ret = mmc_resume_host(mmc);
d96be879
SH		 1136
1137 return ret;
1138}
a7d403cf
EB		 1139
1140static const struct dev_pm_ops mxcmci_pm_ops = {
1141 .suspend = mxcmci_suspend,
1142 .resume = mxcmci_resume,
1143};
1144#endif
d96be879
SH		 1145
1146static struct platform_driver mxcmci_driver = {
1147 .probe = mxcmci_probe,
1148 .remove = mxcmci_remove,
7f917a8d 1149 .id_table = mxcmci_devtype,
d96be879
SH		 1150 .driver = {
1151 .name = DRIVER_NAME,
1152 .owner = THIS_MODULE,
a7d403cf
EB		 1153#ifdef CONFIG_PM
1154 .pm = &mxcmci_pm_ops,
1155#endif
d96be879
SH		 1156 }
1157};
1158
d1f81a64 1159module_platform_driver(mxcmci_driver);
d96be879
SH		 1160
1161MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1162MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1163MODULE_LICENSE("GPL");
1164MODULE_ALIAS("platform:imx-mmc");
Linux kernel - Deliverables
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