projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
media/bt8xx: Remove old powerpc cruft
[deliverable/linux.git] / drivers / mmc / host / mxcmmc.c
CommitLineData
d96be879
SH		 1/*
2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
3 *
4 * This is a driver for the SDHC controller found in Freescale MX2/MX3
5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
6 * Unlike the hardware found on MX1, this hardware just works and does
3ad2f3fb 7 * not need all the quirks found in imxmmc.c, hence the separate driver.
d96be879
SH		 8 *
9 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
10 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
11 *
12 * derived from pxamci.c by Russell King
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 *
18 */
19
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/ioport.h>
23#include <linux/platform_device.h>
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/blkdev.h>
27#include <linux/dma-mapping.h>
28#include <linux/mmc/host.h>
29#include <linux/mmc/card.h>
30#include <linux/delay.h>
31#include <linux/clk.h>
32#include <linux/io.h>
33#include <linux/gpio.h>
74b66954 34#include <linux/regulator/consumer.h>
f53fbde4 35#include <linux/dmaengine.h>
258aea76 36#include <linux/types.h>
7ff747c4
MP		 37#include <linux/of.h>
38#include <linux/of_device.h>
39#include <linux/of_dma.h>
40#include <linux/of_gpio.h>
bcf53524 41#include <linux/mmc/slot-gpio.h>
d96be879
SH		 42
43#include <asm/dma.h>
44#include <asm/irq.h>
82906b13 45#include <linux/platform_data/mmc-mxcmmc.h>
d96be879 46
82906b13 47#include <linux/platform_data/dma-imx.h>
d96be879 48
9563b1db 49#define DRIVER_NAME "mxc-mmc"
f6ad0a48 50#define MXCMCI_TIMEOUT_MS 10000
d96be879
SH		 51
52#define MMC_REG_STR_STP_CLK 0x00
53#define MMC_REG_STATUS 0x04
54#define MMC_REG_CLK_RATE 0x08
55#define MMC_REG_CMD_DAT_CONT 0x0C
56#define MMC_REG_RES_TO 0x10
57#define MMC_REG_READ_TO 0x14
58#define MMC_REG_BLK_LEN 0x18
59#define MMC_REG_NOB 0x1C
60#define MMC_REG_REV_NO 0x20
61#define MMC_REG_INT_CNTR 0x24
62#define MMC_REG_CMD 0x28
63#define MMC_REG_ARG 0x2C
64#define MMC_REG_RES_FIFO 0x34
65#define MMC_REG_BUFFER_ACCESS 0x38
66
67#define STR_STP_CLK_RESET (1 << 3)
68#define STR_STP_CLK_START_CLK (1 << 1)
69#define STR_STP_CLK_STOP_CLK (1 << 0)
70
71#define STATUS_CARD_INSERTION (1 << 31)
72#define STATUS_CARD_REMOVAL (1 << 30)
73#define STATUS_YBUF_EMPTY (1 << 29)
74#define STATUS_XBUF_EMPTY (1 << 28)
75#define STATUS_YBUF_FULL (1 << 27)
76#define STATUS_XBUF_FULL (1 << 26)
77#define STATUS_BUF_UND_RUN (1 << 25)
78#define STATUS_BUF_OVFL (1 << 24)
79#define STATUS_SDIO_INT_ACTIVE (1 << 14)
80#define STATUS_END_CMD_RESP (1 << 13)
81#define STATUS_WRITE_OP_DONE (1 << 12)
82#define STATUS_DATA_TRANS_DONE (1 << 11)
83#define STATUS_READ_OP_DONE (1 << 11)
84#define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
85#define STATUS_CARD_BUS_CLK_RUN (1 << 8)
86#define STATUS_BUF_READ_RDY (1 << 7)
87#define STATUS_BUF_WRITE_RDY (1 << 6)
88#define STATUS_RESP_CRC_ERR (1 << 5)
89#define STATUS_CRC_READ_ERR (1 << 3)
90#define STATUS_CRC_WRITE_ERR (1 << 2)
91#define STATUS_TIME_OUT_RESP (1 << 1)
92#define STATUS_TIME_OUT_READ (1 << 0)
93#define STATUS_ERR_MASK 0x2f
94
95#define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
96#define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
97#define CMD_DAT_CONT_START_READWAIT (1 << 10)
98#define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
99#define CMD_DAT_CONT_INIT (1 << 7)
100#define CMD_DAT_CONT_WRITE (1 << 4)
101#define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
102#define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
103#define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
104#define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
105
106#define INT_SDIO_INT_WKP_EN (1 << 18)
107#define INT_CARD_INSERTION_WKP_EN (1 << 17)
108#define INT_CARD_REMOVAL_WKP_EN (1 << 16)
109#define INT_CARD_INSERTION_EN (1 << 15)
110#define INT_CARD_REMOVAL_EN (1 << 14)
111#define INT_SDIO_IRQ_EN (1 << 13)
112#define INT_DAT0_EN (1 << 12)
113#define INT_BUF_READ_EN (1 << 4)
114#define INT_BUF_WRITE_EN (1 << 3)
115#define INT_END_CMD_RES_EN (1 << 2)
116#define INT_WRITE_OP_DONE_EN (1 << 1)
117#define INT_READ_OP_EN (1 << 0)
118
7f917a8d
SG		 119enum mxcmci_type {
120 IMX21_MMC,
121 IMX31_MMC,
c7ceab02 122 MPC512X_MMC,
7f917a8d
SG		 123};
124
d96be879
SH		 125struct mxcmci_host {
126 struct mmc_host *mmc;
d96be879 127 void __iomem *base;
01e4f958 128 dma_addr_t phys_base;
d96be879 129 int detect_irq;
f53fbde4
SH		 130 struct dma_chan *dma;
131 struct dma_async_tx_descriptor *desc;
d96be879 132 int do_dma;
16b3bf8c 133 int default_irq_mask;
f441b993 134 int use_sdio;
d96be879
SH		 135 unsigned int power_mode;
136 struct imxmmc_platform_data *pdata;
137
138 struct mmc_request *req;
139 struct mmc_command *cmd;
140 struct mmc_data *data;
141
d96be879
SH		 142 unsigned int datasize;
143 unsigned int dma_dir;
144
145 u16 rev_no;
146 unsigned int cmdat;
147
529aa29e
SH		 148 struct clk *clk_ipg;
149 struct clk *clk_per;
d96be879
SH		 150
151 int clock;
152
153 struct work_struct datawork;
f441b993 154 spinlock_t lock;
74b66954 155
f53fbde4
SH		 156 int burstlen;
157 int dmareq;
158 struct dma_slave_config dma_slave_config;
159 struct imx_dma_data dma_data;
f6ad0a48
JM		 160
161 struct timer_list watchdog;
7f917a8d
SG		 162 enum mxcmci_type devtype;
163};
164
42477053 165static const struct platform_device_id mxcmci_devtype[] = {
7f917a8d
SG		 166 {
167 .name = "imx21-mmc",
168 .driver_data = IMX21_MMC,
169 }, {
170 .name = "imx31-mmc",
171 .driver_data = IMX31_MMC,
c7ceab02
AG		 172 }, {
173 .name = "mpc512x-sdhc",
174 .driver_data = MPC512X_MMC,
7f917a8d
SG		 175 }, {
176 /* sentinel */
177 }
d96be879 178};
7f917a8d
SG		 179MODULE_DEVICE_TABLE(platform, mxcmci_devtype);
180
7ff747c4
MP		 181static const struct of_device_id mxcmci_of_match[] = {
182 {
183 .compatible = "fsl,imx21-mmc",
184 .data = &mxcmci_devtype[IMX21_MMC],
185 }, {
186 .compatible = "fsl,imx31-mmc",
187 .data = &mxcmci_devtype[IMX31_MMC],
c7ceab02
AG		 188 }, {
189 .compatible = "fsl,mpc5121-sdhc",
190 .data = &mxcmci_devtype[MPC512X_MMC],
7ff747c4
MP		 191 }, {
192 /* sentinel */
193 }
194};
195MODULE_DEVICE_TABLE(of, mxcmci_of_match);
196
7f917a8d
SG		 197static inline int is_imx31_mmc(struct mxcmci_host *host)
198{
199 return host->devtype == IMX31_MMC;
200}
d96be879 201
c7ceab02
AG		 202static inline int is_mpc512x_mmc(struct mxcmci_host *host)
203{
204 return host->devtype == MPC512X_MMC;
205}
206
207static inline u32 mxcmci_readl(struct mxcmci_host *host, int reg)
208{
209 if (IS_ENABLED(CONFIG_PPC_MPC512x))
210 return ioread32be(host->base + reg);
211 else
212 return readl(host->base + reg);
213}
214
215static inline void mxcmci_writel(struct mxcmci_host *host, u32 val, int reg)
216{
217 if (IS_ENABLED(CONFIG_PPC_MPC512x))
218 iowrite32be(val, host->base + reg);
219 else
220 writel(val, host->base + reg);
221}
222
223static inline u16 mxcmci_readw(struct mxcmci_host *host, int reg)
224{
225 if (IS_ENABLED(CONFIG_PPC_MPC512x))
226 return ioread32be(host->base + reg);
227 else
228 return readw(host->base + reg);
229}
230
231static inline void mxcmci_writew(struct mxcmci_host *host, u16 val, int reg)
232{
233 if (IS_ENABLED(CONFIG_PPC_MPC512x))
234 iowrite32be(val, host->base + reg);
235 else
236 writew(val, host->base + reg);
237}
238
18489fa2
MF		 239static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
240
bc3c1771 241static void mxcmci_set_power(struct mxcmci_host *host, unsigned int vdd)
74b66954 242{
bc3c1771
AS		 243 if (!IS_ERR(host->mmc->supply.vmmc)) {
244 if (host->power_mode == MMC_POWER_UP)
245 mmc_regulator_set_ocr(host->mmc,
246 host->mmc->supply.vmmc, vdd);
247 else if (host->power_mode == MMC_POWER_OFF)
248 mmc_regulator_set_ocr(host->mmc,
249 host->mmc->supply.vmmc, 0);
d078d242
AP		 250 }
251
74b66954
AP		 252 if (host->pdata && host->pdata->setpower)
253 host->pdata->setpower(mmc_dev(host->mmc), vdd);
254}
255
d96be879
SH		 256static inline int mxcmci_use_dma(struct mxcmci_host *host)
257{
258 return host->do_dma;
259}
260
261static void mxcmci_softreset(struct mxcmci_host *host)
262{
263 int i;
264
4725f6f1
DM		 265 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n");
266
d96be879 267 /* reset sequence */
c7ceab02
AG		 268 mxcmci_writew(host, STR_STP_CLK_RESET, MMC_REG_STR_STP_CLK);
269 mxcmci_writew(host, STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
270 MMC_REG_STR_STP_CLK);
d96be879
SH		 271
272 for (i = 0; i < 8; i++)
c7ceab02 273 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
d96be879 274
c7ceab02 275 mxcmci_writew(host, 0xff, MMC_REG_RES_TO);
d96be879
SH		 276}
277
e48fc15a
AG		 278#if IS_ENABLED(CONFIG_PPC_MPC512x)
279static inline void buffer_swap32(u32 *buf, int len)
280{
281 int i;
282
283 for (i = 0; i < ((len + 3) / 4); i++) {
284 st_le32(buf, *buf);
285 buf++;
286 }
287}
288
289static void mxcmci_swap_buffers(struct mmc_data *data)
290{
291 struct scatterlist *sg;
292 int i;
293
294 for_each_sg(data->sg, sg, data->sg_len, i)
295 buffer_swap32(sg_virt(sg), sg->length);
296}
297#else
298static inline void mxcmci_swap_buffers(struct mmc_data *data) {}
299#endif
300
656217d2 301static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
d96be879
SH		 302{
303 unsigned int nob = data->blocks;
304 unsigned int blksz = data->blksz;
305 unsigned int datasize = nob * blksz;
d96be879 306 struct scatterlist *sg;
05f5799c 307 enum dma_transfer_direction slave_dirn;
f53fbde4
SH		 308 int i, nents;
309
d96be879
SH		 310 if (data->flags & MMC_DATA_STREAM)
311 nob = 0xffff;
312
313 host->data = data;
314 data->bytes_xfered = 0;
315
c7ceab02
AG		 316 mxcmci_writew(host, nob, MMC_REG_NOB);
317 mxcmci_writew(host, blksz, MMC_REG_BLK_LEN);
d96be879
SH		 318 host->datasize = datasize;
319
f53fbde4
SH		 320 if (!mxcmci_use_dma(host))
321 return 0;
322
d96be879 323 for_each_sg(data->sg, sg, data->sg_len, i) {
2cb53552 324 if (sg->offset & 3 || sg->length & 3 || sg->length < 512) {
d96be879 325 host->do_dma = 0;
656217d2 326 return 0;
d96be879
SH		 327 }
328 }
329
05f5799c 330 if (data->flags & MMC_DATA_READ) {
d96be879 331 host->dma_dir = DMA_FROM_DEVICE;
05f5799c
VK		 332 slave_dirn = DMA_DEV_TO_MEM;
333 } else {
d96be879 334 host->dma_dir = DMA_TO_DEVICE;
05f5799c 335 slave_dirn = DMA_MEM_TO_DEV;
e48fc15a
AG		 336
337 mxcmci_swap_buffers(data);
05f5799c 338 }
d96be879 339
f53fbde4
SH		 340 nents = dma_map_sg(host->dma->device->dev, data->sg,
341 data->sg_len, host->dma_dir);
342 if (nents != data->sg_len)
343 return -EINVAL;
344
16052827 345 host->desc = dmaengine_prep_slave_sg(host->dma,
05f5799c 346 data->sg, data->sg_len, slave_dirn,
f53fbde4 347 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
d96be879 348
f53fbde4
SH		 349 if (!host->desc) {
350 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
351 host->dma_dir);
352 host->do_dma = 0;
353 return 0; /* Fall back to PIO */
656217d2 354 }
d96be879
SH		 355 wmb();
356
f53fbde4 357 dmaengine_submit(host->desc);
439aa0ef 358 dma_async_issue_pending(host->dma);
f53fbde4 359
f6ad0a48
JM		 360 mod_timer(&host->watchdog, jiffies + msecs_to_jiffies(MXCMCI_TIMEOUT_MS));
361
656217d2 362 return 0;
d96be879
SH		 363}
364
f6ad0a48
JM		 365static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat);
366static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat);
367
368static void mxcmci_dma_callback(void *data)
369{
370 struct mxcmci_host *host = data;
371 u32 stat;
372
373 del_timer(&host->watchdog);
374
c7ceab02 375 stat = mxcmci_readl(host, MMC_REG_STATUS);
f6ad0a48
JM		 376
377 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
378
f6ad0a48
JM		 379 mxcmci_data_done(host, stat);
380}
381
d96be879
SH		 382static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
383 unsigned int cmdat)
384{
16b3bf8c 385 u32 int_cntr = host->default_irq_mask;
f441b993
DM		 386 unsigned long flags;
387
d96be879
SH		 388 WARN_ON(host->cmd != NULL);
389 host->cmd = cmd;
390
391 switch (mmc_resp_type(cmd)) {
392 case MMC_RSP_R1: /* short CRC, OPCODE */
393 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
394 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
395 break;
396 case MMC_RSP_R2: /* long 136 bit + CRC */
397 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
398 break;
399 case MMC_RSP_R3: /* short */
400 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
401 break;
402 case MMC_RSP_NONE:
403 break;
404 default:
405 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n",
406 mmc_resp_type(cmd));
407 cmd->error = -EINVAL;
408 return -EINVAL;
409 }
410
f441b993
DM		 411 int_cntr = INT_END_CMD_RES_EN;
412
f6ad0a48
JM		 413 if (mxcmci_use_dma(host)) {
414 if (host->dma_dir == DMA_FROM_DEVICE) {
415 host->desc->callback = mxcmci_dma_callback;
416 host->desc->callback_param = host;
417 } else {
418 int_cntr |= INT_WRITE_OP_DONE_EN;
419 }
420 }
f441b993
DM		 421
422 spin_lock_irqsave(&host->lock, flags);
423 if (host->use_sdio)
424 int_cntr |= INT_SDIO_IRQ_EN;
c7ceab02 425 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
f441b993 426 spin_unlock_irqrestore(&host->lock, flags);
d96be879 427
c7ceab02
AG		 428 mxcmci_writew(host, cmd->opcode, MMC_REG_CMD);
429 mxcmci_writel(host, cmd->arg, MMC_REG_ARG);
430 mxcmci_writew(host, cmdat, MMC_REG_CMD_DAT_CONT);
d96be879
SH		 431
432 return 0;
433}
434
435static void mxcmci_finish_request(struct mxcmci_host *host,
436 struct mmc_request *req)
437{
16b3bf8c 438 u32 int_cntr = host->default_irq_mask;
f441b993
DM		 439 unsigned long flags;
440
441 spin_lock_irqsave(&host->lock, flags);
442 if (host->use_sdio)
443 int_cntr |= INT_SDIO_IRQ_EN;
c7ceab02 444 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
f441b993 445 spin_unlock_irqrestore(&host->lock, flags);
d96be879
SH		 446
447 host->req = NULL;
448 host->cmd = NULL;
449 host->data = NULL;
450
451 mmc_request_done(host->mmc, req);
452}
453
454static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
455{
456 struct mmc_data *data = host->data;
457 int data_error;
458
e48fc15a 459 if (mxcmci_use_dma(host)) {
f53fbde4 460 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
d96be879 461 host->dma_dir);
e48fc15a
AG		 462 mxcmci_swap_buffers(data);
463 }
d96be879
SH		 464
465 if (stat & STATUS_ERR_MASK) {
466 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
467 stat);
468 if (stat & STATUS_CRC_READ_ERR) {
4725f6f1 469 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__);
d96be879
SH		 470 data->error = -EILSEQ;
471 } else if (stat & STATUS_CRC_WRITE_ERR) {
472 u32 err_code = (stat >> 9) & 0x3;
4725f6f1
DM		 473 if (err_code == 2) { /* No CRC response */
474 dev_err(mmc_dev(host->mmc),
475 "%s: No CRC -ETIMEDOUT\n", __func__);
d96be879 476 data->error = -ETIMEDOUT;
4725f6f1
DM		 477 } else {
478 dev_err(mmc_dev(host->mmc),
479 "%s: -EILSEQ\n", __func__);
d96be879 480 data->error = -EILSEQ;
4725f6f1 481 }
d96be879 482 } else if (stat & STATUS_TIME_OUT_READ) {
4725f6f1
DM		 483 dev_err(mmc_dev(host->mmc),
484 "%s: read -ETIMEDOUT\n", __func__);
d96be879
SH		 485 data->error = -ETIMEDOUT;
486 } else {
4725f6f1 487 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__);
d96be879
SH		 488 data->error = -EIO;
489 }
490 } else {
491 data->bytes_xfered = host->datasize;
492 }
493
494 data_error = data->error;
495
496 host->data = NULL;
497
498 return data_error;
499}
500
501static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
502{
503 struct mmc_command *cmd = host->cmd;
504 int i;
505 u32 a, b, c;
506
507 if (!cmd)
508 return;
509
510 if (stat & STATUS_TIME_OUT_RESP) {
511 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
512 cmd->error = -ETIMEDOUT;
513 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
514 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
515 cmd->error = -EILSEQ;
516 }
517
518 if (cmd->flags & MMC_RSP_PRESENT) {
519 if (cmd->flags & MMC_RSP_136) {
520 for (i = 0; i < 4; i++) {
c7ceab02
AG		 521 a = mxcmci_readw(host, MMC_REG_RES_FIFO);
522 b = mxcmci_readw(host, MMC_REG_RES_FIFO);
d96be879
SH		 523 cmd->resp[i] = a << 16 | b;
524 }
525 } else {
c7ceab02
AG		 526 a = mxcmci_readw(host, MMC_REG_RES_FIFO);
527 b = mxcmci_readw(host, MMC_REG_RES_FIFO);
528 c = mxcmci_readw(host, MMC_REG_RES_FIFO);
d96be879
SH		 529 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
530 }
531 }
532}
533
534static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
535{
536 u32 stat;
537 unsigned long timeout = jiffies + HZ;
538
539 do {
c7ceab02 540 stat = mxcmci_readl(host, MMC_REG_STATUS);
d96be879
SH		 541 if (stat & STATUS_ERR_MASK)
542 return stat;
18489fa2
MF		 543 if (time_after(jiffies, timeout)) {
544 mxcmci_softreset(host);
545 mxcmci_set_clk_rate(host, host->clock);
d96be879 546 return STATUS_TIME_OUT_READ;
18489fa2 547 }
d96be879
SH		 548 if (stat & mask)
549 return 0;
550 cpu_relax();
551 } while (1);
552}
553
554static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
555{
556 unsigned int stat;
557 u32 *buf = _buf;
558
559 while (bytes > 3) {
560 stat = mxcmci_poll_status(host,
561 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
562 if (stat)
563 return stat;
c7ceab02 564 *buf++ = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
d96be879
SH		 565 bytes -= 4;
566 }
567
568 if (bytes) {
569 u8 *b = (u8 *)buf;
570 u32 tmp;
571
572 stat = mxcmci_poll_status(host,
573 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
574 if (stat)
575 return stat;
c7ceab02 576 tmp = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
d96be879
SH		 577 memcpy(b, &tmp, bytes);
578 }
579
580 return 0;
581}
582
583static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes)
584{
585 unsigned int stat;
586 u32 *buf = _buf;
587
588 while (bytes > 3) {
589 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
590 if (stat)
591 return stat;
c7ceab02 592 mxcmci_writel(host, cpu_to_le32(*buf++), MMC_REG_BUFFER_ACCESS);
d96be879
SH		 593 bytes -= 4;
594 }
595
596 if (bytes) {
597 u8 *b = (u8 *)buf;
598 u32 tmp;
599
600 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
601 if (stat)
602 return stat;
603
604 memcpy(&tmp, b, bytes);
c7ceab02 605 mxcmci_writel(host, cpu_to_le32(tmp), MMC_REG_BUFFER_ACCESS);
d96be879
SH		 606 }
607
608 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
609 if (stat)
610 return stat;
611
612 return 0;
613}
614
615static int mxcmci_transfer_data(struct mxcmci_host *host)
616{
617 struct mmc_data *data = host->req->data;
618 struct scatterlist *sg;
619 int stat, i;
620
d96be879
SH		 621 host->data = data;
622 host->datasize = 0;
623
624 if (data->flags & MMC_DATA_READ) {
625 for_each_sg(data->sg, sg, data->sg_len, i) {
626 stat = mxcmci_pull(host, sg_virt(sg), sg->length);
627 if (stat)
628 return stat;
629 host->datasize += sg->length;
630 }
631 } else {
632 for_each_sg(data->sg, sg, data->sg_len, i) {
633 stat = mxcmci_push(host, sg_virt(sg), sg->length);
634 if (stat)
635 return stat;
636 host->datasize += sg->length;
637 }
638 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
639 if (stat)
640 return stat;
641 }
642 return 0;
643}
644
645static void mxcmci_datawork(struct work_struct *work)
646{
647 struct mxcmci_host *host = container_of(work, struct mxcmci_host,
648 datawork);
649 int datastat = mxcmci_transfer_data(host);
4a31f2ef 650
c7ceab02
AG		 651 mxcmci_writel(host, STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
652 MMC_REG_STATUS);
d96be879
SH		 653 mxcmci_finish_data(host, datastat);
654
655 if (host->req->stop) {
656 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
657 mxcmci_finish_request(host, host->req);
658 return;
659 }
660 } else {
661 mxcmci_finish_request(host, host->req);
662 }
663}
664
d96be879
SH		 665static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
666{
70aa6109 667 struct mmc_request *req;
d96be879 668 int data_error;
70aa6109
AG		 669 unsigned long flags;
670
671 spin_lock_irqsave(&host->lock, flags);
d96be879 672
70aa6109
AG		 673 if (!host->data) {
674 spin_unlock_irqrestore(&host->lock, flags);
d96be879 675 return;
70aa6109
AG		 676 }
677
678 if (!host->req) {
679 spin_unlock_irqrestore(&host->lock, flags);
680 return;
681 }
682
683 req = host->req;
684 if (!req->stop)
685 host->req = NULL; /* we will handle finish req below */
d96be879
SH		 686
687 data_error = mxcmci_finish_data(host, stat);
688
70aa6109
AG		 689 spin_unlock_irqrestore(&host->lock, flags);
690
d96be879
SH		 691 mxcmci_read_response(host, stat);
692 host->cmd = NULL;
693
70aa6109
AG		 694 if (req->stop) {
695 if (mxcmci_start_cmd(host, req->stop, 0)) {
696 mxcmci_finish_request(host, req);
d96be879
SH		 697 return;
698 }
699 } else {
70aa6109 700 mxcmci_finish_request(host, req);
d96be879
SH		 701 }
702}
d96be879
SH		 703
704static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
705{
706 mxcmci_read_response(host, stat);
707 host->cmd = NULL;
708
709 if (!host->data && host->req) {
710 mxcmci_finish_request(host, host->req);
711 return;
712 }
713
714 /* For the DMA case the DMA engine handles the data transfer
fd589a8f 715 * automatically. For non DMA we have to do it ourselves.
d96be879
SH		 716 * Don't do it in interrupt context though.
717 */
718 if (!mxcmci_use_dma(host) && host->data)
719 schedule_work(&host->datawork);
720
721}
722
723static irqreturn_t mxcmci_irq(int irq, void *devid)
724{
725 struct mxcmci_host *host = devid;
f441b993
DM		 726 unsigned long flags;
727 bool sdio_irq;
d96be879
SH		 728 u32 stat;
729
c7ceab02
AG		 730 stat = mxcmci_readl(host, MMC_REG_STATUS);
731 mxcmci_writel(host,
732 stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE |
733 STATUS_WRITE_OP_DONE),
734 MMC_REG_STATUS);
d96be879
SH		 735
736 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
737
f441b993
DM		 738 spin_lock_irqsave(&host->lock, flags);
739 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio;
740 spin_unlock_irqrestore(&host->lock, flags);
741
adfa5703
MF		 742 if (mxcmci_use_dma(host) && (stat & (STATUS_WRITE_OP_DONE)))
743 mxcmci_writel(host, STATUS_WRITE_OP_DONE, MMC_REG_STATUS);
4a31f2ef 744
f441b993 745 if (sdio_irq) {
c7ceab02 746 mxcmci_writel(host, STATUS_SDIO_INT_ACTIVE, MMC_REG_STATUS);
f441b993
DM		 747 mmc_signal_sdio_irq(host->mmc);
748 }
749
d96be879
SH		 750 if (stat & STATUS_END_CMD_RESP)
751 mxcmci_cmd_done(host, stat);
f441b993 752
adfa5703 753 if (mxcmci_use_dma(host) && (stat & STATUS_WRITE_OP_DONE)) {
f6ad0a48 754 del_timer(&host->watchdog);
d96be879 755 mxcmci_data_done(host, stat);
f6ad0a48 756 }
f53fbde4 757
16b3bf8c
EB		 758 if (host->default_irq_mask &&
759 (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL)))
760 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
f53fbde4 761
d96be879
SH		 762 return IRQ_HANDLED;
763}
764
765static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
766{
767 struct mxcmci_host *host = mmc_priv(mmc);
768 unsigned int cmdat = host->cmdat;
656217d2 769 int error;
d96be879
SH		 770
771 WARN_ON(host->req != NULL);
772
773 host->req = req;
774 host->cmdat &= ~CMD_DAT_CONT_INIT;
f53fbde4
SH		 775
776 if (host->dma)
777 host->do_dma = 1;
778
d96be879 779 if (req->data) {
656217d2
MF		 780 error = mxcmci_setup_data(host, req->data);
781 if (error) {
782 req->cmd->error = error;
783 goto out;
784 }
785
d96be879
SH		 786
787 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
788
789 if (req->data->flags & MMC_DATA_WRITE)
790 cmdat |= CMD_DAT_CONT_WRITE;
791 }
792
656217d2 793 error = mxcmci_start_cmd(host, req->cmd, cmdat);
f53fbde4 794
656217d2
MF		 795out:
796 if (error)
d96be879
SH		 797 mxcmci_finish_request(host, req);
798}
799
800static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
801{
802 unsigned int divider;
803 int prescaler = 0;
529aa29e 804 unsigned int clk_in = clk_get_rate(host->clk_per);
d96be879
SH		 805
806 while (prescaler <= 0x800) {
807 for (divider = 1; divider <= 0xF; divider++) {
808 int x;
809
810 x = (clk_in / (divider + 1));
811
812 if (prescaler)
813 x /= (prescaler * 2);
814
815 if (x <= clk_ios)
816 break;
817 }
818 if (divider < 0x10)
819 break;
820
821 if (prescaler == 0)
822 prescaler = 1;
823 else
824 prescaler <<= 1;
825 }
826
c7ceab02 827 mxcmci_writew(host, (prescaler << 4) | divider, MMC_REG_CLK_RATE);
d96be879
SH		 828
829 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
830 prescaler, divider, clk_in, clk_ios);
831}
832
f53fbde4
SH		 833static int mxcmci_setup_dma(struct mmc_host *mmc)
834{
835 struct mxcmci_host *host = mmc_priv(mmc);
836 struct dma_slave_config *config = &host->dma_slave_config;
837
01e4f958
AS		 838 config->dst_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
839 config->src_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
f53fbde4
SH		 840 config->dst_addr_width = 4;
841 config->src_addr_width = 4;
842 config->dst_maxburst = host->burstlen;
843 config->src_maxburst = host->burstlen;
258aea76 844 config->device_fc = false;
f53fbde4
SH		 845
846 return dmaengine_slave_config(host->dma, config);
847}
848
d96be879
SH		 849static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
850{
851 struct mxcmci_host *host = mmc_priv(mmc);
f53fbde4
SH		 852 int burstlen, ret;
853
d96be879 854 /*
6584cb88
SH		 855 * use burstlen of 64 (16 words) in 4 bit mode (--> reg value 0)
856 * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16)
d96be879
SH		 857 */
858 if (ios->bus_width == MMC_BUS_WIDTH_4)
f53fbde4 859 burstlen = 16;
6584cb88
SH		 860 else
861 burstlen = 4;
f53fbde4
SH		 862
863 if (mxcmci_use_dma(host) && burstlen != host->burstlen) {
864 host->burstlen = burstlen;
865 ret = mxcmci_setup_dma(mmc);
866 if (ret) {
867 dev_err(mmc_dev(host->mmc),
868 "failed to config DMA channel. Falling back to PIO\n");
869 dma_release_channel(host->dma);
870 host->do_dma = 0;
e58f516f 871 host->dma = NULL;
f53fbde4
SH		 872 }
873 }
d96be879 874
d96be879
SH		 875 if (ios->bus_width == MMC_BUS_WIDTH_4)
876 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
877 else
878 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
879
880 if (host->power_mode != ios->power_mode) {
d96be879 881 host->power_mode = ios->power_mode;
bc3c1771 882 mxcmci_set_power(host, ios->vdd);
74b66954 883
d96be879
SH		 884 if (ios->power_mode == MMC_POWER_ON)
885 host->cmdat |= CMD_DAT_CONT_INIT;
886 }
887
888 if (ios->clock) {
889 mxcmci_set_clk_rate(host, ios->clock);
c7ceab02 890 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
d96be879 891 } else {
c7ceab02 892 mxcmci_writew(host, STR_STP_CLK_STOP_CLK, MMC_REG_STR_STP_CLK);
d96be879
SH		 893 }
894
895 host->clock = ios->clock;
896}
897
898static irqreturn_t mxcmci_detect_irq(int irq, void *data)
899{
900 struct mmc_host *mmc = data;
901
902 dev_dbg(mmc_dev(mmc), "%s\n", __func__);
903
904 mmc_detect_change(mmc, msecs_to_jiffies(250));
905 return IRQ_HANDLED;
906}
907
908static int mxcmci_get_ro(struct mmc_host *mmc)
909{
910 struct mxcmci_host *host = mmc_priv(mmc);
911
912 if (host->pdata && host->pdata->get_ro)
913 return !!host->pdata->get_ro(mmc_dev(mmc));
914 /*
bcf53524
AG		 915 * If board doesn't support read only detection (no mmc_gpio
916 * context or gpio is invalid), then let the mmc core decide
917 * what to do.
d96be879 918 */
bcf53524 919 return mmc_gpio_get_ro(mmc);
d96be879
SH		 920}
921
f441b993
DM		 922static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
923{
924 struct mxcmci_host *host = mmc_priv(mmc);
925 unsigned long flags;
926 u32 int_cntr;
927
928 spin_lock_irqsave(&host->lock, flags);
929 host->use_sdio = enable;
c7ceab02 930 int_cntr = mxcmci_readl(host, MMC_REG_INT_CNTR);
f441b993
DM		 931
932 if (enable)
933 int_cntr |= INT_SDIO_IRQ_EN;
934 else
935 int_cntr &= ~INT_SDIO_IRQ_EN;
936
c7ceab02 937 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
f441b993
DM		 938 spin_unlock_irqrestore(&host->lock, flags);
939}
d96be879 940
3fcb027d
DM		 941static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card)
942{
7f917a8d
SG		 943 struct mxcmci_host *mxcmci = mmc_priv(host);
944
3fcb027d
DM		 945 /*
946 * MX3 SoCs have a silicon bug which corrupts CRC calculation of
947 * multi-block transfers when connected SDIO peripheral doesn't
948 * drive the BUSY line as required by the specs.
949 * One way to prevent this is to only allow 1-bit transfers.
950 */
951
7f917a8d 952 if (is_imx31_mmc(mxcmci) && card->type == MMC_TYPE_SDIO)
3fcb027d
DM		 953 host->caps &= ~MMC_CAP_4_BIT_DATA;
954 else
955 host->caps |= MMC_CAP_4_BIT_DATA;
956}
957
f53fbde4
SH		 958static bool filter(struct dma_chan *chan, void *param)
959{
960 struct mxcmci_host *host = param;
961
962 if (!imx_dma_is_general_purpose(chan))
963 return false;
964
965 chan->private = &host->dma_data;
966
967 return true;
968}
969
f6ad0a48
JM		 970static void mxcmci_watchdog(unsigned long data)
971{
972 struct mmc_host *mmc = (struct mmc_host *)data;
973 struct mxcmci_host *host = mmc_priv(mmc);
974 struct mmc_request *req = host->req;
c7ceab02 975 unsigned int stat = mxcmci_readl(host, MMC_REG_STATUS);
f6ad0a48
JM		 976
977 if (host->dma_dir == DMA_FROM_DEVICE) {
978 dmaengine_terminate_all(host->dma);
979 dev_err(mmc_dev(host->mmc),
980 "%s: read time out (status = 0x%08x)\n",
981 __func__, stat);
982 } else {
983 dev_err(mmc_dev(host->mmc),
984 "%s: write time out (status = 0x%08x)\n",
985 __func__, stat);
986 mxcmci_softreset(host);
987 }
988
989 /* Mark transfer as erroneus and inform the upper layers */
990
70aa6109
AG		 991 if (host->data)
992 host->data->error = -ETIMEDOUT;
f6ad0a48
JM		 993 host->req = NULL;
994 host->cmd = NULL;
995 host->data = NULL;
996 mmc_request_done(host->mmc, req);
997}
998
d96be879 999static const struct mmc_host_ops mxcmci_ops = {
f441b993
DM		 1000 .request = mxcmci_request,
1001 .set_ios = mxcmci_set_ios,
1002 .get_ro = mxcmci_get_ro,
1003 .enable_sdio_irq = mxcmci_enable_sdio_irq,
3fcb027d 1004 .init_card = mxcmci_init_card,
d96be879
SH		 1005};
1006
1007static int mxcmci_probe(struct platform_device *pdev)
1008{
1009 struct mmc_host *mmc;
01e4f958
AS		 1010 struct mxcmci_host *host;
1011 struct resource *res;
d96be879 1012 int ret = 0, irq;
7ff747c4 1013 bool dat3_card_detect = false;
f53fbde4 1014 dma_cap_mask_t mask;
7ff747c4
MP		 1015 const struct of_device_id *of_id;
1016 struct imxmmc_platform_data *pdata = pdev->dev.platform_data;
d96be879 1017
c7ceab02 1018 pr_info("i.MX/MPC512x SDHC driver\n");
d96be879 1019
7ff747c4
MP		 1020 of_id = of_match_device(mxcmci_of_match, &pdev->dev);
1021
01e4f958 1022 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d96be879 1023 irq = platform_get_irq(pdev, 0);
01e4f958 1024 if (irq < 0)
d96be879
SH		 1025 return -EINVAL;
1026
01e4f958
AS		 1027 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1028 if (!mmc)
1029 return -ENOMEM;
d96be879 1030
01e4f958
AS		 1031 host = mmc_priv(mmc);
1032
1033 host->base = devm_ioremap_resource(&pdev->dev, res);
1034 if (IS_ERR(host->base)) {
1035 ret = PTR_ERR(host->base);
1036 goto out_free;
d96be879
SH		 1037 }
1038
01e4f958
AS		 1039 host->phys_base = res->start;
1040
b8857696
SB		 1041 ret = mmc_of_parse(mmc);
1042 if (ret)
1043 goto out_free;
d96be879 1044 mmc->ops = &mxcmci_ops;
7ff747c4
MP		 1045
1046 /* For devicetree parsing, the bus width is read from devicetree */
1047 if (pdata)
1048 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1049 else
1050 mmc->caps |= MMC_CAP_SDIO_IRQ;
d96be879
SH		 1051
1052 /* MMC core transfer sizes tunable parameters */
d96be879
SH		 1053 mmc->max_blk_size = 2048;
1054 mmc->max_blk_count = 65535;
1055 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
d759c374 1056 mmc->max_seg_size = mmc->max_req_size;
d96be879 1057
7ff747c4
MP		 1058 if (of_id) {
1059 const struct platform_device_id *id_entry = of_id->data;
1060 host->devtype = id_entry->driver_data;
1061 } else {
1062 host->devtype = pdev->id_entry->driver_data;
1063 }
e48fc15a
AG		 1064
1065 /* adjust max_segs after devtype detection */
1066 if (!is_mpc512x_mmc(host))
1067 mmc->max_segs = 64;
1068
d96be879 1069 host->mmc = mmc;
7ff747c4 1070 host->pdata = pdata;
f441b993 1071 spin_lock_init(&host->lock);
d96be879 1072
7ff747c4
MP		 1073 if (pdata)
1074 dat3_card_detect = pdata->dat3_card_detect;
1075 else if (!(mmc->caps & MMC_CAP_NONREMOVABLE)
1076 && !of_property_read_bool(pdev->dev.of_node, "cd-gpios"))
1077 dat3_card_detect = true;
1078
bc3c1771 1079 ret = mmc_regulator_get_supply(mmc);
18a09806
MF		 1080 if (ret == -EPROBE_DEFER)
1081 goto out_free;
1082
1083 if (!mmc->ocr_avail) {
1084 if (pdata && pdata->ocr_avail)
1085 mmc->ocr_avail = pdata->ocr_avail;
bc3c1771 1086 else
18a09806 1087 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
bc3c1771 1088 }
d96be879 1089
7ff747c4 1090 if (dat3_card_detect)
16b3bf8c
EB		 1091 host->default_irq_mask =
1092 INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN;
1093 else
1094 host->default_irq_mask = 0;
1095
529aa29e
SH		 1096 host->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1097 if (IS_ERR(host->clk_ipg)) {
1098 ret = PTR_ERR(host->clk_ipg);
01e4f958 1099 goto out_free;
d96be879 1100 }
529aa29e
SH		 1101
1102 host->clk_per = devm_clk_get(&pdev->dev, "per");
1103 if (IS_ERR(host->clk_per)) {
1104 ret = PTR_ERR(host->clk_per);
01e4f958 1105 goto out_free;
529aa29e
SH		 1106 }
1107
1108 clk_prepare_enable(host->clk_per);
1109 clk_prepare_enable(host->clk_ipg);
d96be879
SH		 1110
1111 mxcmci_softreset(host);
1112
c7ceab02 1113 host->rev_no = mxcmci_readw(host, MMC_REG_REV_NO);
d96be879
SH		 1114 if (host->rev_no != 0x400) {
1115 ret = -ENODEV;
1116 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
1117 host->rev_no);
1118 goto out_clk_put;
1119 }
1120
529aa29e
SH		 1121 mmc->f_min = clk_get_rate(host->clk_per) >> 16;
1122 mmc->f_max = clk_get_rate(host->clk_per) >> 1;
d96be879
SH		 1123
1124 /* recommended in data sheet */
c7ceab02 1125 mxcmci_writew(host, 0x2db4, MMC_REG_READ_TO);
d96be879 1126
c7ceab02 1127 mxcmci_writel(host, host->default_irq_mask, MMC_REG_INT_CNTR);
d96be879 1128
7ff747c4
MP		 1129 if (!host->pdata) {
1130 host->dma = dma_request_slave_channel(&pdev->dev, "rx-tx");
1131 } else {
01e4f958
AS		 1132 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1133 if (res) {
1134 host->dmareq = res->start;
7ff747c4
MP		 1135 host->dma_data.peripheral_type = IMX_DMATYPE_SDHC;
1136 host->dma_data.priority = DMA_PRIO_LOW;
1137 host->dma_data.dma_request = host->dmareq;
1138 dma_cap_zero(mask);
1139 dma_cap_set(DMA_SLAVE, mask);
1140 host->dma = dma_request_channel(mask, filter, host);
1141 }
f53fbde4 1142 }
7ff747c4
MP		 1143 if (host->dma)
1144 mmc->max_seg_size = dma_get_max_seg_size(
1145 host->dma->device->dev);
1146 else
f53fbde4 1147 dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n");
d96be879 1148
d96be879
SH		 1149 INIT_WORK(&host->datawork, mxcmci_datawork);
1150
01e4f958
AS		 1151 ret = devm_request_irq(&pdev->dev, irq, mxcmci_irq, 0,
1152 dev_name(&pdev->dev), host);
d96be879
SH		 1153 if (ret)
1154 goto out_free_dma;
1155
1156 platform_set_drvdata(pdev, mmc);
1157
1158 if (host->pdata && host->pdata->init) {
1159 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq,
1160 host->mmc);
1161 if (ret)
01e4f958 1162 goto out_free_dma;
d96be879
SH		 1163 }
1164
f6ad0a48
JM		 1165 init_timer(&host->watchdog);
1166 host->watchdog.function = &mxcmci_watchdog;
1167 host->watchdog.data = (unsigned long)mmc;
1168
abd4190f
AS		 1169 mmc_add_host(mmc);
1170
d96be879
SH		 1171 return 0;
1172
d96be879 1173out_free_dma:
f53fbde4
SH		 1174 if (host->dma)
1175 dma_release_channel(host->dma);
01e4f958 1176
d96be879 1177out_clk_put:
529aa29e
SH		 1178 clk_disable_unprepare(host->clk_per);
1179 clk_disable_unprepare(host->clk_ipg);
01e4f958 1180
d96be879
SH		 1181out_free:
1182 mmc_free_host(mmc);
01e4f958 1183
d96be879
SH		 1184 return ret;
1185}
1186
1187static int mxcmci_remove(struct platform_device *pdev)
1188{
1189 struct mmc_host *mmc = platform_get_drvdata(pdev);
1190 struct mxcmci_host *host = mmc_priv(mmc);
1191
d96be879
SH		 1192 mmc_remove_host(mmc);
1193
1194 if (host->pdata && host->pdata->exit)
1195 host->pdata->exit(&pdev->dev, mmc);
1196
f53fbde4
SH		 1197 if (host->dma)
1198 dma_release_channel(host->dma);
1199
529aa29e
SH		 1200 clk_disable_unprepare(host->clk_per);
1201 clk_disable_unprepare(host->clk_ipg);
d96be879 1202
d96be879
SH		 1203 mmc_free_host(mmc);
1204
1205 return 0;
1206}
1207
384a81d5 1208static int __maybe_unused mxcmci_suspend(struct device *dev)
d96be879 1209{
a7d403cf
EB		 1210 struct mmc_host *mmc = dev_get_drvdata(dev);
1211 struct mxcmci_host *host = mmc_priv(mmc);
d96be879 1212
529aa29e
SH		 1213 clk_disable_unprepare(host->clk_per);
1214 clk_disable_unprepare(host->clk_ipg);
bd190f90 1215 return 0;
d96be879
SH		 1216}
1217
384a81d5 1218static int __maybe_unused mxcmci_resume(struct device *dev)
d96be879 1219{
a7d403cf
EB		 1220 struct mmc_host *mmc = dev_get_drvdata(dev);
1221 struct mxcmci_host *host = mmc_priv(mmc);
d96be879 1222
529aa29e
SH		 1223 clk_prepare_enable(host->clk_per);
1224 clk_prepare_enable(host->clk_ipg);
bd190f90 1225 return 0;
d96be879 1226}
a7d403cf 1227
384a81d5 1228static SIMPLE_DEV_PM_OPS(mxcmci_pm_ops, mxcmci_suspend, mxcmci_resume);
d96be879
SH		 1229
1230static struct platform_driver mxcmci_driver = {
1231 .probe = mxcmci_probe,
1232 .remove = mxcmci_remove,
7f917a8d 1233 .id_table = mxcmci_devtype,
d96be879
SH		 1234 .driver = {
1235 .name = DRIVER_NAME,
a7d403cf 1236 .pm = &mxcmci_pm_ops,
7ff747c4 1237 .of_match_table = mxcmci_of_match,
d96be879
SH		 1238 }
1239};
1240
d1f81a64 1241module_platform_driver(mxcmci_driver);
d96be879
SH		 1242
1243MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1244MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1245MODULE_LICENSE("GPL");
6eb30adf 1246MODULE_ALIAS("platform:mxc-mmc");
Linux kernel - Deliverables
This page took 0.450908 seconds and 5 git commands to generate.