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mmc: mxs-mmc: copy wp_gpio in struct mxs_mmc_host
[deliverable/linux.git] / drivers / mmc / host / mxs-mmc.c
CommitLineData
e4243f13
SG		 1/*
2 * Portions copyright (C) 2003 Russell King, PXA MMCI Driver
3 * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
4 *
5 * Copyright 2008 Embedded Alley Solutions, Inc.
6 * Copyright 2009-2011 Freescale Semiconductor, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 */
22
23#include <linux/kernel.h>
24#include <linux/init.h>
25#include <linux/ioport.h>
26#include <linux/platform_device.h>
27#include <linux/delay.h>
28#include <linux/interrupt.h>
29#include <linux/dma-mapping.h>
30#include <linux/dmaengine.h>
31#include <linux/highmem.h>
32#include <linux/clk.h>
33#include <linux/err.h>
34#include <linux/completion.h>
35#include <linux/mmc/host.h>
36#include <linux/mmc/mmc.h>
37#include <linux/mmc/sdio.h>
38#include <linux/gpio.h>
39#include <linux/regulator/consumer.h>
88b47679 40#include <linux/module.h>
39468604 41#include <linux/fsl/mxs-dma.h>
9c92cf24 42#include <linux/pinctrl/consumer.h>
70e60206 43#include <linux/stmp_device.h>
81f38ee8 44#include <linux/mmc/mxs-mmc.h>
e4243f13
SG		 45
46#define DRIVER_NAME "mxs-mmc"
47
48/* card detect polling timeout */
49#define MXS_MMC_DETECT_TIMEOUT (HZ/2)
50
ef9b4d39 51#define ssp_is_old(host) ((host)->devid == IMX23_MMC)
e4243f13
SG		 52
53/* SSP registers */
54#define HW_SSP_CTRL0 0x000
55#define BM_SSP_CTRL0_RUN (1 << 29)
56#define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28)
57#define BM_SSP_CTRL0_IGNORE_CRC (1 << 26)
58#define BM_SSP_CTRL0_READ (1 << 25)
59#define BM_SSP_CTRL0_DATA_XFER (1 << 24)
60#define BP_SSP_CTRL0_BUS_WIDTH (22)
61#define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22)
62#define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21)
63#define BM_SSP_CTRL0_LONG_RESP (1 << 19)
64#define BM_SSP_CTRL0_GET_RESP (1 << 17)
65#define BM_SSP_CTRL0_ENABLE (1 << 16)
66#define BP_SSP_CTRL0_XFER_COUNT (0)
67#define BM_SSP_CTRL0_XFER_COUNT (0xffff)
68#define HW_SSP_CMD0 0x010
69#define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25)
70#define BM_SSP_CMD0_SLOW_CLKING_EN (1 << 22)
71#define BM_SSP_CMD0_CONT_CLKING_EN (1 << 21)
72#define BM_SSP_CMD0_APPEND_8CYC (1 << 20)
73#define BP_SSP_CMD0_BLOCK_SIZE (16)
74#define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16)
75#define BP_SSP_CMD0_BLOCK_COUNT (8)
76#define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8)
77#define BP_SSP_CMD0_CMD (0)
78#define BM_SSP_CMD0_CMD (0xff)
79#define HW_SSP_CMD1 0x020
80#define HW_SSP_XFER_SIZE 0x030
81#define HW_SSP_BLOCK_SIZE 0x040
82#define BP_SSP_BLOCK_SIZE_BLOCK_COUNT (4)
83#define BM_SSP_BLOCK_SIZE_BLOCK_COUNT (0xffffff << 4)
84#define BP_SSP_BLOCK_SIZE_BLOCK_SIZE (0)
85#define BM_SSP_BLOCK_SIZE_BLOCK_SIZE (0xf)
e0bf141d 86#define HW_SSP_TIMING(h) (ssp_is_old(h) ? 0x050 : 0x070)
e4243f13
SG		 87#define BP_SSP_TIMING_TIMEOUT (16)
88#define BM_SSP_TIMING_TIMEOUT (0xffff << 16)
89#define BP_SSP_TIMING_CLOCK_DIVIDE (8)
90#define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8)
91#define BP_SSP_TIMING_CLOCK_RATE (0)
92#define BM_SSP_TIMING_CLOCK_RATE (0xff)
e0bf141d 93#define HW_SSP_CTRL1(h) (ssp_is_old(h) ? 0x060 : 0x080)
e4243f13
SG		 94#define BM_SSP_CTRL1_SDIO_IRQ (1 << 31)
95#define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30)
96#define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29)
97#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28)
98#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27)
99#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26)
100#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25)
101#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24)
102#define BM_SSP_CTRL1_DATA_CRC_IRQ (1 << 23)
103#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22)
104#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21)
105#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN (1 << 20)
106#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17)
107#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16)
108#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15)
109#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14)
110#define BM_SSP_CTRL1_DMA_ENABLE (1 << 13)
111#define BM_SSP_CTRL1_POLARITY (1 << 9)
112#define BP_SSP_CTRL1_WORD_LENGTH (4)
113#define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4)
114#define BP_SSP_CTRL1_SSP_MODE (0)
115#define BM_SSP_CTRL1_SSP_MODE (0xf)
e0bf141d
SG		 116#define HW_SSP_SDRESP0(h) (ssp_is_old(h) ? 0x080 : 0x0a0)
117#define HW_SSP_SDRESP1(h) (ssp_is_old(h) ? 0x090 : 0x0b0)
118#define HW_SSP_SDRESP2(h) (ssp_is_old(h) ? 0x0a0 : 0x0c0)
119#define HW_SSP_SDRESP3(h) (ssp_is_old(h) ? 0x0b0 : 0x0d0)
120#define HW_SSP_STATUS(h) (ssp_is_old(h) ? 0x0c0 : 0x100)
e4243f13
SG		 121#define BM_SSP_STATUS_CARD_DETECT (1 << 28)
122#define BM_SSP_STATUS_SDIO_IRQ (1 << 17)
e4243f13
SG		 123
124#define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field)
125
126#define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \
127 BM_SSP_CTRL1_RESP_ERR_IRQ | \
128 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \
129 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \
130 BM_SSP_CTRL1_DATA_CRC_IRQ | \
131 BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \
132 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \
133 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)
134
135#define SSP_PIO_NUM 3
136
ef9b4d39
SG		 137enum mxs_mmc_id {
138 IMX23_MMC,
139 IMX28_MMC,
140};
141
e4243f13
SG		 142struct mxs_mmc_host {
143 struct mmc_host *mmc;
144 struct mmc_request *mrq;
145 struct mmc_command *cmd;
146 struct mmc_data *data;
147
148 void __iomem *base;
b60188c8 149 int dma_channel;
e4243f13
SG		 150 struct clk *clk;
151 unsigned int clk_rate;
152
153 struct dma_chan *dmach;
154 struct mxs_dma_data dma_data;
155 unsigned int dma_dir;
05f5799c 156 enum dma_transfer_direction slave_dirn;
e4243f13
SG		 157 u32 ssp_pio_words[SSP_PIO_NUM];
158
ef9b4d39 159 enum mxs_mmc_id devid;
e4243f13
SG		 160 unsigned char bus_width;
161 spinlock_t lock;
162 int sdio_irq_en;
31b0ff5e 163 int wp_gpio;
e4243f13
SG		 164};
165
166static int mxs_mmc_get_ro(struct mmc_host *mmc)
167{
168 struct mxs_mmc_host *host = mmc_priv(mmc);
e4243f13 169
31b0ff5e 170 if (!gpio_is_valid(host->wp_gpio))
e4243f13
SG		 171 return -EINVAL;
172
31b0ff5e 173 return gpio_get_value(host->wp_gpio);
e4243f13
SG		 174}
175
176static int mxs_mmc_get_cd(struct mmc_host *mmc)
177{
178 struct mxs_mmc_host *host = mmc_priv(mmc);
179
e0bf141d 180 return !(readl(host->base + HW_SSP_STATUS(host)) &
e4243f13
SG		 181 BM_SSP_STATUS_CARD_DETECT);
182}
183
184static void mxs_mmc_reset(struct mxs_mmc_host *host)
185{
186 u32 ctrl0, ctrl1;
187
70e60206 188 stmp_reset_block(host->base);
e4243f13
SG		 189
190 ctrl0 = BM_SSP_CTRL0_IGNORE_CRC;
191 ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) |
192 BF_SSP(0x7, CTRL1_WORD_LENGTH) |
193 BM_SSP_CTRL1_DMA_ENABLE |
194 BM_SSP_CTRL1_POLARITY |
195 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
196 BM_SSP_CTRL1_DATA_CRC_IRQ_EN |
197 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
198 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
199 BM_SSP_CTRL1_RESP_ERR_IRQ_EN;
200
201 writel(BF_SSP(0xffff, TIMING_TIMEOUT) |
202 BF_SSP(2, TIMING_CLOCK_DIVIDE) |
203 BF_SSP(0, TIMING_CLOCK_RATE),
e0bf141d 204 host->base + HW_SSP_TIMING(host));
e4243f13
SG		 205
206 if (host->sdio_irq_en) {
207 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
208 ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN;
209 }
210
211 writel(ctrl0, host->base + HW_SSP_CTRL0);
e0bf141d 212 writel(ctrl1, host->base + HW_SSP_CTRL1(host));
e4243f13
SG		 213}
214
215static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
216 struct mmc_command *cmd);
217
218static void mxs_mmc_request_done(struct mxs_mmc_host *host)
219{
220 struct mmc_command *cmd = host->cmd;
221 struct mmc_data *data = host->data;
222 struct mmc_request *mrq = host->mrq;
223
224 if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) {
225 if (mmc_resp_type(cmd) & MMC_RSP_136) {
e0bf141d
SG		 226 cmd->resp[3] = readl(host->base + HW_SSP_SDRESP0(host));
227 cmd->resp[2] = readl(host->base + HW_SSP_SDRESP1(host));
228 cmd->resp[1] = readl(host->base + HW_SSP_SDRESP2(host));
229 cmd->resp[0] = readl(host->base + HW_SSP_SDRESP3(host));
e4243f13 230 } else {
e0bf141d 231 cmd->resp[0] = readl(host->base + HW_SSP_SDRESP0(host));
e4243f13
SG		 232 }
233 }
234
235 if (data) {
236 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
237 data->sg_len, host->dma_dir);
238 /*
239 * If there was an error on any block, we mark all
240 * data blocks as being in error.
241 */
242 if (!data->error)
243 data->bytes_xfered = data->blocks * data->blksz;
244 else
245 data->bytes_xfered = 0;
246
247 host->data = NULL;
248 if (mrq->stop) {
249 mxs_mmc_start_cmd(host, mrq->stop);
250 return;
251 }
252 }
253
254 host->mrq = NULL;
255 mmc_request_done(host->mmc, mrq);
256}
257
258static void mxs_mmc_dma_irq_callback(void *param)
259{
260 struct mxs_mmc_host *host = param;
261
262 mxs_mmc_request_done(host);
263}
264
265static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id)
266{
267 struct mxs_mmc_host *host = dev_id;
268 struct mmc_command *cmd = host->cmd;
269 struct mmc_data *data = host->data;
270 u32 stat;
271
272 spin_lock(&host->lock);
273
e0bf141d 274 stat = readl(host->base + HW_SSP_CTRL1(host));
e4243f13 275 writel(stat & MXS_MMC_IRQ_BITS,
e0bf141d 276 host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_CLR);
e4243f13
SG		 277
278 if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN))
279 mmc_signal_sdio_irq(host->mmc);
280
281 spin_unlock(&host->lock);
282
283 if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ)
284 cmd->error = -ETIMEDOUT;
285 else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ)
286 cmd->error = -EIO;
287
288 if (data) {
289 if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ |
290 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ))
291 data->error = -ETIMEDOUT;
292 else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ)
293 data->error = -EILSEQ;
294 else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ |
295 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ))
296 data->error = -EIO;
297 }
298
299 return IRQ_HANDLED;
300}
301
302static struct dma_async_tx_descriptor *mxs_mmc_prep_dma(
921de864 303 struct mxs_mmc_host *host, unsigned long flags)
e4243f13
SG		 304{
305 struct dma_async_tx_descriptor *desc;
306 struct mmc_data *data = host->data;
307 struct scatterlist * sgl;
308 unsigned int sg_len;
309
310 if (data) {
311 /* data */
312 dma_map_sg(mmc_dev(host->mmc), data->sg,
313 data->sg_len, host->dma_dir);
314 sgl = data->sg;
315 sg_len = data->sg_len;
316 } else {
317 /* pio */
318 sgl = (struct scatterlist *) host->ssp_pio_words;
319 sg_len = SSP_PIO_NUM;
320 }
321
16052827 322 desc = dmaengine_prep_slave_sg(host->dmach,
921de864 323 sgl, sg_len, host->slave_dirn, flags);
e4243f13
SG		 324 if (desc) {
325 desc->callback = mxs_mmc_dma_irq_callback;
326 desc->callback_param = host;
327 } else {
328 if (data)
329 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
330 data->sg_len, host->dma_dir);
331 }
332
333 return desc;
334}
335
336static void mxs_mmc_bc(struct mxs_mmc_host *host)
337{
338 struct mmc_command *cmd = host->cmd;
339 struct dma_async_tx_descriptor *desc;
340 u32 ctrl0, cmd0, cmd1;
341
342 ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC;
343 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC;
344 cmd1 = cmd->arg;
345
346 if (host->sdio_irq_en) {
347 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
348 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
349 }
350
351 host->ssp_pio_words[0] = ctrl0;
352 host->ssp_pio_words[1] = cmd0;
353 host->ssp_pio_words[2] = cmd1;
354 host->dma_dir = DMA_NONE;
a4e3e86d 355 host->slave_dirn = DMA_TRANS_NONE;
921de864 356 desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK);
e4243f13
SG		 357 if (!desc)
358 goto out;
359
360 dmaengine_submit(desc);
d04525ed 361 dma_async_issue_pending(host->dmach);
e4243f13
SG		 362 return;
363
364out:
365 dev_warn(mmc_dev(host->mmc),
366 "%s: failed to prep dma\n", __func__);
367}
368
369static void mxs_mmc_ac(struct mxs_mmc_host *host)
370{
371 struct mmc_command *cmd = host->cmd;
372 struct dma_async_tx_descriptor *desc;
373 u32 ignore_crc, get_resp, long_resp;
374 u32 ctrl0, cmd0, cmd1;
375
376 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
377 0 : BM_SSP_CTRL0_IGNORE_CRC;
378 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
379 BM_SSP_CTRL0_GET_RESP : 0;
380 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
381 BM_SSP_CTRL0_LONG_RESP : 0;
382
383 ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp;
384 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
385 cmd1 = cmd->arg;
386
387 if (host->sdio_irq_en) {
388 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
389 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
390 }
391
392 host->ssp_pio_words[0] = ctrl0;
393 host->ssp_pio_words[1] = cmd0;
394 host->ssp_pio_words[2] = cmd1;
395 host->dma_dir = DMA_NONE;
a4e3e86d 396 host->slave_dirn = DMA_TRANS_NONE;
921de864 397 desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK);
e4243f13
SG		 398 if (!desc)
399 goto out;
400
401 dmaengine_submit(desc);
d04525ed 402 dma_async_issue_pending(host->dmach);
e4243f13
SG		 403 return;
404
405out:
406 dev_warn(mmc_dev(host->mmc),
407 "%s: failed to prep dma\n", __func__);
408}
409
410static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns)
411{
412 const unsigned int ssp_timeout_mul = 4096;
413 /*
414 * Calculate ticks in ms since ns are large numbers
415 * and might overflow
416 */
417 const unsigned int clock_per_ms = clock_rate / 1000;
418 const unsigned int ms = ns / 1000;
419 const unsigned int ticks = ms * clock_per_ms;
420 const unsigned int ssp_ticks = ticks / ssp_timeout_mul;
421
422 WARN_ON(ssp_ticks == 0);
423 return ssp_ticks;
424}
425
426static void mxs_mmc_adtc(struct mxs_mmc_host *host)
427{
428 struct mmc_command *cmd = host->cmd;
429 struct mmc_data *data = cmd->data;
430 struct dma_async_tx_descriptor *desc;
431 struct scatterlist *sgl = data->sg, *sg;
432 unsigned int sg_len = data->sg_len;
433 int i;
434
435 unsigned short dma_data_dir, timeout;
05f5799c 436 enum dma_transfer_direction slave_dirn;
e4243f13
SG		 437 unsigned int data_size = 0, log2_blksz;
438 unsigned int blocks = data->blocks;
439
440 u32 ignore_crc, get_resp, long_resp, read;
441 u32 ctrl0, cmd0, cmd1, val;
442
443 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
444 0 : BM_SSP_CTRL0_IGNORE_CRC;
445 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
446 BM_SSP_CTRL0_GET_RESP : 0;
447 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
448 BM_SSP_CTRL0_LONG_RESP : 0;
449
450 if (data->flags & MMC_DATA_WRITE) {
451 dma_data_dir = DMA_TO_DEVICE;
05f5799c 452 slave_dirn = DMA_MEM_TO_DEV;
e4243f13
SG		 453 read = 0;
454 } else {
455 dma_data_dir = DMA_FROM_DEVICE;
05f5799c 456 slave_dirn = DMA_DEV_TO_MEM;
e4243f13
SG		 457 read = BM_SSP_CTRL0_READ;
458 }
459
460 ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) |
461 ignore_crc | get_resp | long_resp |
462 BM_SSP_CTRL0_DATA_XFER | read |
463 BM_SSP_CTRL0_WAIT_FOR_IRQ |
464 BM_SSP_CTRL0_ENABLE;
465
466 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
467
468 /* get logarithm to base 2 of block size for setting register */
469 log2_blksz = ilog2(data->blksz);
470
471 /*
472 * take special care of the case that data size from data->sg
473 * is not equal to blocks x blksz
474 */
475 for_each_sg(sgl, sg, sg_len, i)
476 data_size += sg->length;
477
478 if (data_size != data->blocks * data->blksz)
479 blocks = 1;
480
481 /* xfer count, block size and count need to be set differently */
e0bf141d 482 if (ssp_is_old(host)) {
e4243f13
SG		 483 ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT);
484 cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) |
485 BF_SSP(blocks - 1, CMD0_BLOCK_COUNT);
486 } else {
487 writel(data_size, host->base + HW_SSP_XFER_SIZE);
488 writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) |
489 BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT),
490 host->base + HW_SSP_BLOCK_SIZE);
491 }
492
493 if ((cmd->opcode == MMC_STOP_TRANSMISSION) ||
494 (cmd->opcode == SD_IO_RW_EXTENDED))
495 cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
496
497 cmd1 = cmd->arg;
498
499 if (host->sdio_irq_en) {
500 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
501 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
502 }
503
504 /* set the timeout count */
505 timeout = mxs_ns_to_ssp_ticks(host->clk_rate, data->timeout_ns);
e0bf141d 506 val = readl(host->base + HW_SSP_TIMING(host));
e4243f13
SG		 507 val &= ~(BM_SSP_TIMING_TIMEOUT);
508 val |= BF_SSP(timeout, TIMING_TIMEOUT);
e0bf141d 509 writel(val, host->base + HW_SSP_TIMING(host));
e4243f13
SG		 510
511 /* pio */
512 host->ssp_pio_words[0] = ctrl0;
513 host->ssp_pio_words[1] = cmd0;
514 host->ssp_pio_words[2] = cmd1;
515 host->dma_dir = DMA_NONE;
a4e3e86d 516 host->slave_dirn = DMA_TRANS_NONE;
e4243f13
SG		 517 desc = mxs_mmc_prep_dma(host, 0);
518 if (!desc)
519 goto out;
520
521 /* append data sg */
522 WARN_ON(host->data != NULL);
523 host->data = data;
524 host->dma_dir = dma_data_dir;
05f5799c 525 host->slave_dirn = slave_dirn;
921de864 526 desc = mxs_mmc_prep_dma(host, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
e4243f13
SG		 527 if (!desc)
528 goto out;
529
530 dmaengine_submit(desc);
d04525ed 531 dma_async_issue_pending(host->dmach);
e4243f13
SG		 532 return;
533out:
534 dev_warn(mmc_dev(host->mmc),
535 "%s: failed to prep dma\n", __func__);
536}
537
538static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
539 struct mmc_command *cmd)
540{
541 host->cmd = cmd;
542
543 switch (mmc_cmd_type(cmd)) {
544 case MMC_CMD_BC:
545 mxs_mmc_bc(host);
546 break;
547 case MMC_CMD_BCR:
548 mxs_mmc_ac(host);
549 break;
550 case MMC_CMD_AC:
551 mxs_mmc_ac(host);
552 break;
553 case MMC_CMD_ADTC:
554 mxs_mmc_adtc(host);
555 break;
556 default:
557 dev_warn(mmc_dev(host->mmc),
558 "%s: unknown MMC command\n", __func__);
559 break;
560 }
561}
562
563static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
564{
565 struct mxs_mmc_host *host = mmc_priv(mmc);
566
567 WARN_ON(host->mrq != NULL);
568 host->mrq = mrq;
569 mxs_mmc_start_cmd(host, mrq->cmd);
570}
571
572static void mxs_mmc_set_clk_rate(struct mxs_mmc_host *host, unsigned int rate)
573{
d982dcdc
KB		 574 unsigned int ssp_clk, ssp_sck;
575 u32 clock_divide, clock_rate;
e4243f13
SG		 576 u32 val;
577
d982dcdc 578 ssp_clk = clk_get_rate(host->clk);
e4243f13 579
d982dcdc
KB		 580 for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) {
581 clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide);
582 clock_rate = (clock_rate > 0) ? clock_rate - 1 : 0;
583 if (clock_rate <= 255)
e4243f13
SG		 584 break;
585 }
586
d982dcdc 587 if (clock_divide > 254) {
e4243f13
SG		 588 dev_err(mmc_dev(host->mmc),
589 "%s: cannot set clock to %d\n", __func__, rate);
590 return;
591 }
592
d982dcdc 593 ssp_sck = ssp_clk / clock_divide / (1 + clock_rate);
e4243f13 594
e0bf141d 595 val = readl(host->base + HW_SSP_TIMING(host));
e4243f13 596 val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE);
d982dcdc
KB		 597 val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE);
598 val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE);
e0bf141d 599 writel(val, host->base + HW_SSP_TIMING(host));
e4243f13 600
d982dcdc 601 host->clk_rate = ssp_sck;
e4243f13
SG		 602
603 dev_dbg(mmc_dev(host->mmc),
d982dcdc
KB		 604 "%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n",
605 __func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate);
e4243f13
SG		 606}
607
608static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
609{
610 struct mxs_mmc_host *host = mmc_priv(mmc);
611
612 if (ios->bus_width == MMC_BUS_WIDTH_8)
613 host->bus_width = 2;
614 else if (ios->bus_width == MMC_BUS_WIDTH_4)
615 host->bus_width = 1;
616 else
617 host->bus_width = 0;
618
619 if (ios->clock)
620 mxs_mmc_set_clk_rate(host, ios->clock);
621}
622
623static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
624{
625 struct mxs_mmc_host *host = mmc_priv(mmc);
626 unsigned long flags;
627
628 spin_lock_irqsave(&host->lock, flags);
629
630 host->sdio_irq_en = enable;
631
632 if (enable) {
633 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
70e60206 634 host->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
e4243f13 635 writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
e0bf141d 636 host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_SET);
e4243f13 637
e0bf141d
SG		 638 if (readl(host->base + HW_SSP_STATUS(host)) &
639 BM_SSP_STATUS_SDIO_IRQ)
e4243f13
SG		 640 mmc_signal_sdio_irq(host->mmc);
641
642 } else {
643 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
70e60206 644 host->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
e4243f13 645 writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
e0bf141d 646 host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_CLR);
e4243f13
SG		 647 }
648
649 spin_unlock_irqrestore(&host->lock, flags);
650}
651
652static const struct mmc_host_ops mxs_mmc_ops = {
653 .request = mxs_mmc_request,
654 .get_ro = mxs_mmc_get_ro,
655 .get_cd = mxs_mmc_get_cd,
656 .set_ios = mxs_mmc_set_ios,
657 .enable_sdio_irq = mxs_mmc_enable_sdio_irq,
658};
659
660static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param)
661{
662 struct mxs_mmc_host *host = param;
663
664 if (!mxs_dma_is_apbh(chan))
665 return false;
666
b60188c8 667 if (chan->chan_id != host->dma_channel)
e4243f13
SG		 668 return false;
669
670 chan->private = &host->dma_data;
671
672 return true;
673}
674
ef9b4d39
SG		 675static struct platform_device_id mxs_mmc_ids[] = {
676 {
677 .name = "imx23-mmc",
678 .driver_data = IMX23_MMC,
679 }, {
680 .name = "imx28-mmc",
681 .driver_data = IMX28_MMC,
682 }, {
683 /* sentinel */
684 }
685};
686MODULE_DEVICE_TABLE(platform, mxs_mmc_ids);
687
e4243f13
SG		 688static int mxs_mmc_probe(struct platform_device *pdev)
689{
690 struct mxs_mmc_host *host;
691 struct mmc_host *mmc;
df06bfc7 692 struct resource *iores, *dmares;
e4243f13 693 struct mxs_mmc_platform_data *pdata;
9c92cf24 694 struct pinctrl *pinctrl;
e4243f13
SG		 695 int ret = 0, irq_err, irq_dma;
696 dma_cap_mask_t mask;
697
698 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
699 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
700 irq_err = platform_get_irq(pdev, 0);
701 irq_dma = platform_get_irq(pdev, 1);
702 if (!iores || !dmares || irq_err < 0 || irq_dma < 0)
703 return -EINVAL;
704
e4243f13 705 mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev);
df06bfc7
SG		 706 if (!mmc)
707 return -ENOMEM;
e4243f13
SG		 708
709 host = mmc_priv(mmc);
df06bfc7 710 host->base = devm_request_and_ioremap(&pdev->dev, iores);
e4243f13 711 if (!host->base) {
df06bfc7 712 ret = -EADDRNOTAVAIL;
e4243f13
SG		 713 goto out_mmc_free;
714 }
715
ef9b4d39 716 host->devid = pdev->id_entry->driver_data;
e4243f13 717 host->mmc = mmc;
b60188c8 718 host->dma_channel = dmares->start;
e4243f13
SG		 719 host->sdio_irq_en = 0;
720
9c92cf24
SG		 721 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
722 if (IS_ERR(pinctrl)) {
723 ret = PTR_ERR(pinctrl);
724 goto out_iounmap;
725 }
726
e4243f13
SG		 727 host->clk = clk_get(&pdev->dev, NULL);
728 if (IS_ERR(host->clk)) {
729 ret = PTR_ERR(host->clk);
df06bfc7 730 goto out_mmc_free;
e4243f13 731 }
efdfc52c 732 clk_prepare_enable(host->clk);
e4243f13
SG		 733
734 mxs_mmc_reset(host);
735
736 dma_cap_zero(mask);
737 dma_cap_set(DMA_SLAVE, mask);
738 host->dma_data.chan_irq = irq_dma;
739 host->dmach = dma_request_channel(mask, mxs_mmc_dma_filter, host);
740 if (!host->dmach) {
741 dev_err(mmc_dev(host->mmc),
742 "%s: failed to request dma\n", __func__);
743 goto out_clk_put;
744 }
745
746 /* set mmc core parameters */
747 mmc->ops = &mxs_mmc_ops;
748 mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
749 MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL;
750
751 pdata = mmc_dev(host->mmc)->platform_data;
752 if (pdata) {
753 if (pdata->flags & SLOTF_8_BIT_CAPABLE)
754 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
755 if (pdata->flags & SLOTF_4_BIT_CAPABLE)
756 mmc->caps |= MMC_CAP_4_BIT_DATA;
31b0ff5e 757 host->wp_gpio = pdata->wp_gpio;
e4243f13
SG		 758 }
759
760 mmc->f_min = 400000;
761 mmc->f_max = 288000000;
762 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
763
764 mmc->max_segs = 52;
765 mmc->max_blk_size = 1 << 0xf;
e0bf141d
SG		 766 mmc->max_blk_count = (ssp_is_old(host)) ? 0xff : 0xffffff;
767 mmc->max_req_size = (ssp_is_old(host)) ? 0xffff : 0xffffffff;
e4243f13
SG		 768 mmc->max_seg_size = dma_get_max_seg_size(host->dmach->device->dev);
769
770 platform_set_drvdata(pdev, mmc);
771
df06bfc7
SG		 772 ret = devm_request_irq(&pdev->dev, irq_err, mxs_mmc_irq_handler, 0,
773 DRIVER_NAME, host);
e4243f13
SG		 774 if (ret)
775 goto out_free_dma;
776
777 spin_lock_init(&host->lock);
778
779 ret = mmc_add_host(mmc);
780 if (ret)
df06bfc7 781 goto out_free_dma;
e4243f13
SG		 782
783 dev_info(mmc_dev(host->mmc), "initialized\n");
784
785 return 0;
786
e4243f13
SG		 787out_free_dma:
788 if (host->dmach)
789 dma_release_channel(host->dmach);
790out_clk_put:
efdfc52c 791 clk_disable_unprepare(host->clk);
e4243f13 792 clk_put(host->clk);
e4243f13
SG		 793out_mmc_free:
794 mmc_free_host(mmc);
e4243f13
SG		 795 return ret;
796}
797
798static int mxs_mmc_remove(struct platform_device *pdev)
799{
800 struct mmc_host *mmc = platform_get_drvdata(pdev);
801 struct mxs_mmc_host *host = mmc_priv(mmc);
e4243f13
SG		 802
803 mmc_remove_host(mmc);
804
e4243f13
SG		 805 platform_set_drvdata(pdev, NULL);
806
807 if (host->dmach)
808 dma_release_channel(host->dmach);
809
efdfc52c 810 clk_disable_unprepare(host->clk);
e4243f13
SG		 811 clk_put(host->clk);
812
e4243f13
SG		 813 mmc_free_host(mmc);
814
e4243f13
SG		 815 return 0;
816}
817
818#ifdef CONFIG_PM
819static int mxs_mmc_suspend(struct device *dev)
820{
821 struct mmc_host *mmc = dev_get_drvdata(dev);
822 struct mxs_mmc_host *host = mmc_priv(mmc);
823 int ret = 0;
824
825 ret = mmc_suspend_host(mmc);
826
efdfc52c 827 clk_disable_unprepare(host->clk);
e4243f13
SG		 828
829 return ret;
830}
831
832static int mxs_mmc_resume(struct device *dev)
833{
834 struct mmc_host *mmc = dev_get_drvdata(dev);
835 struct mxs_mmc_host *host = mmc_priv(mmc);
836 int ret = 0;
837
efdfc52c 838 clk_prepare_enable(host->clk);
e4243f13
SG		 839
840 ret = mmc_resume_host(mmc);
841
842 return ret;
843}
844
845static const struct dev_pm_ops mxs_mmc_pm_ops = {
846 .suspend = mxs_mmc_suspend,
847 .resume = mxs_mmc_resume,
848};
849#endif
850
851static struct platform_driver mxs_mmc_driver = {
852 .probe = mxs_mmc_probe,
853 .remove = mxs_mmc_remove,
ef9b4d39 854 .id_table = mxs_mmc_ids,
e4243f13
SG		 855 .driver = {
856 .name = DRIVER_NAME,
857 .owner = THIS_MODULE,
858#ifdef CONFIG_PM
859 .pm = &mxs_mmc_pm_ops,
860#endif
861 },
862};
863
d1f81a64 864module_platform_driver(mxs_mmc_driver);
e4243f13
SG		 865
866MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral");
867MODULE_AUTHOR("Freescale Semiconductor");
868MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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