projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'chrome-platform' of git://git.kernel.org/pub/scm/linux/kernel/git/olof...
[deliverable/linux.git] / drivers / mmc / host / omap.c
CommitLineData
730c9b7e 1/*
70f10482 2 * linux/drivers/mmc/host/omap.c
730c9b7e
CA		 3 *
4 * Copyright (C) 2004 Nokia Corporation
d36b6910 5 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
730c9b7e
CA		 6 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
7 * Other hacks (DMA, SD, etc) by David Brownell
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
730c9b7e
CA		 14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/ioport.h>
18#include <linux/platform_device.h>
19#include <linux/interrupt.h>
3451c067 20#include <linux/dmaengine.h>
730c9b7e
CA		 21#include <linux/dma-mapping.h>
22#include <linux/delay.h>
23#include <linux/spinlock.h>
24#include <linux/timer.h>
9cb238c0 25#include <linux/of.h>
730c9b7e 26#include <linux/mmc/host.h>
730c9b7e 27#include <linux/mmc/card.h>
b13d1f0f 28#include <linux/mmc/mmc.h>
730c9b7e 29#include <linux/clk.h>
45711f1a 30#include <linux/scatterlist.h>
5a0e3ad6 31#include <linux/slab.h>
68f39e74 32#include <linux/platform_data/mmc-omap.h>
730c9b7e 33
730c9b7e 34
0551f4df 35#define OMAP_MMC_REG_CMD 0x00
0e950fa6
MB		 36#define OMAP_MMC_REG_ARGL 0x01
37#define OMAP_MMC_REG_ARGH 0x02
38#define OMAP_MMC_REG_CON 0x03
39#define OMAP_MMC_REG_STAT 0x04
40#define OMAP_MMC_REG_IE 0x05
41#define OMAP_MMC_REG_CTO 0x06
42#define OMAP_MMC_REG_DTO 0x07
43#define OMAP_MMC_REG_DATA 0x08
44#define OMAP_MMC_REG_BLEN 0x09
45#define OMAP_MMC_REG_NBLK 0x0a
46#define OMAP_MMC_REG_BUF 0x0b
47#define OMAP_MMC_REG_SDIO 0x0d
48#define OMAP_MMC_REG_REV 0x0f
49#define OMAP_MMC_REG_RSP0 0x10
50#define OMAP_MMC_REG_RSP1 0x11
51#define OMAP_MMC_REG_RSP2 0x12
52#define OMAP_MMC_REG_RSP3 0x13
53#define OMAP_MMC_REG_RSP4 0x14
54#define OMAP_MMC_REG_RSP5 0x15
55#define OMAP_MMC_REG_RSP6 0x16
56#define OMAP_MMC_REG_RSP7 0x17
57#define OMAP_MMC_REG_IOSR 0x18
58#define OMAP_MMC_REG_SYSC 0x19
59#define OMAP_MMC_REG_SYSS 0x1a
0551f4df
JY		 60
61#define OMAP_MMC_STAT_CARD_ERR (1 << 14)
62#define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
63#define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
64#define OMAP_MMC_STAT_A_EMPTY (1 << 11)
65#define OMAP_MMC_STAT_A_FULL (1 << 10)
66#define OMAP_MMC_STAT_CMD_CRC (1 << 8)
67#define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
68#define OMAP_MMC_STAT_DATA_CRC (1 << 6)
69#define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
70#define OMAP_MMC_STAT_END_BUSY (1 << 4)
71#define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
72#define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
73#define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
74
53db20d1
TL		 75#define mmc_omap7xx() (host->features & MMC_OMAP7XX)
76#define mmc_omap15xx() (host->features & MMC_OMAP15XX)
77#define mmc_omap16xx() (host->features & MMC_OMAP16XX)
78#define MMC_OMAP1_MASK (MMC_OMAP7XX | MMC_OMAP15XX | MMC_OMAP16XX)
79#define mmc_omap1() (host->features & MMC_OMAP1_MASK)
80#define mmc_omap2() (!mmc_omap1())
81
0e950fa6
MB		 82#define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift)
83#define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))
84#define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
0551f4df
JY		 85
86/*
87 * Command types
88 */
89#define OMAP_MMC_CMDTYPE_BC 0
90#define OMAP_MMC_CMDTYPE_BCR 1
91#define OMAP_MMC_CMDTYPE_AC 2
92#define OMAP_MMC_CMDTYPE_ADTC 3
93
730c9b7e 94#define DRIVER_NAME "mmci-omap"
730c9b7e
CA		 95
96/* Specifies how often in millisecs to poll for card status changes
97 * when the cover switch is open */
7584d276 98#define OMAP_MMC_COVER_POLL_DELAY 500
730c9b7e 99
abfbe5f7
JY		 100struct mmc_omap_host;
101
102struct mmc_omap_slot {
103 int id;
104 unsigned int vdd;
105 u16 saved_con;
106 u16 bus_mode;
107 unsigned int fclk_freq;
abfbe5f7 108
7584d276
JL		 109 struct tasklet_struct cover_tasklet;
110 struct timer_list cover_timer;
5a0f3f1f
JY		 111 unsigned cover_open;
112
abfbe5f7
JY		 113 struct mmc_request *mrq;
114 struct mmc_omap_host *host;
115 struct mmc_host *mmc;
116 struct omap_mmc_slot_data *pdata;
117};
118
730c9b7e
CA		 119struct mmc_omap_host {
120 int initialized;
730c9b7e
CA		 121 struct mmc_request * mrq;
122 struct mmc_command * cmd;
123 struct mmc_data * data;
124 struct mmc_host * mmc;
125 struct device * dev;
126 unsigned char id; /* 16xx chips have 2 MMC blocks */
127 struct clk * iclk;
128 struct clk * fclk;
3451c067
RK		 129 struct dma_chan *dma_rx;
130 u32 dma_rx_burst;
131 struct dma_chan *dma_tx;
132 u32 dma_tx_burst;
89783b1e
JY		 133 void __iomem *virt_base;
134 unsigned int phys_base;
730c9b7e
CA		 135 int irq;
136 unsigned char bus_mode;
0e950fa6 137 unsigned int reg_shift;
730c9b7e 138
0fb4723d
JL		 139 struct work_struct cmd_abort_work;
140 unsigned abort:1;
141 struct timer_list cmd_abort_timer;
eb1860bc 142
0f602ec7
JL		 143 struct work_struct slot_release_work;
144 struct mmc_omap_slot *next_slot;
145 struct work_struct send_stop_work;
146 struct mmc_data *stop_data;
147
730c9b7e
CA		 148 unsigned int sg_len;
149 int sg_idx;
150 u16 * buffer;
151 u32 buffer_bytes_left;
152 u32 total_bytes_left;
153
53db20d1 154 unsigned features;
730c9b7e 155 unsigned brs_received:1, dma_done:1;
730c9b7e 156 unsigned dma_in_use:1;
3451c067 157 spinlock_t dma_lock;
730c9b7e 158
abfbe5f7
JY		 159 struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS];
160 struct mmc_omap_slot *current_slot;
161 spinlock_t slot_lock;
162 wait_queue_head_t slot_wq;
163 int nr_slots;
164
0807a9b5
JL		 165 struct timer_list clk_timer;
166 spinlock_t clk_lock; /* for changing enabled state */
167 unsigned int fclk_enabled:1;
b01a4f1c 168 struct workqueue_struct *mmc_omap_wq;
0807a9b5 169
abfbe5f7 170 struct omap_mmc_platform_data *pdata;
730c9b7e
CA		 171};
172
0d9ee5b2 173
7c8ad982 174static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
0807a9b5
JL		 175{
176 unsigned long tick_ns;
177
178 if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
03a16853 179 tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);
0807a9b5
JL		 180 ndelay(8 * tick_ns);
181 }
182}
183
7c8ad982 184static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
0807a9b5
JL		 185{
186 unsigned long flags;
187
188 spin_lock_irqsave(&host->clk_lock, flags);
189 if (host->fclk_enabled != enable) {
190 host->fclk_enabled = enable;
191 if (enable)
192 clk_enable(host->fclk);
193 else
194 clk_disable(host->fclk);
195 }
196 spin_unlock_irqrestore(&host->clk_lock, flags);
197}
198
abfbe5f7
JY		 199static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
200{
201 struct mmc_omap_host *host = slot->host;
202 unsigned long flags;
203
204 if (claimed)
205 goto no_claim;
206 spin_lock_irqsave(&host->slot_lock, flags);
207 while (host->mmc != NULL) {
208 spin_unlock_irqrestore(&host->slot_lock, flags);
209 wait_event(host->slot_wq, host->mmc == NULL);
210 spin_lock_irqsave(&host->slot_lock, flags);
211 }
212 host->mmc = slot->mmc;
213 spin_unlock_irqrestore(&host->slot_lock, flags);
214no_claim:
0807a9b5
JL		 215 del_timer(&host->clk_timer);
216 if (host->current_slot != slot || !claimed)
217 mmc_omap_fclk_offdelay(host->current_slot);
218
abfbe5f7 219 if (host->current_slot != slot) {
0807a9b5 220 OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
abfbe5f7
JY		 221 if (host->pdata->switch_slot != NULL)
222 host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
223 host->current_slot = slot;
224 }
225
0807a9b5
JL		 226 if (claimed) {
227 mmc_omap_fclk_enable(host, 1);
228
229 /* Doing the dummy read here seems to work around some bug
230 * at least in OMAP24xx silicon where the command would not
231 * start after writing the CMD register. Sigh. */
232 OMAP_MMC_READ(host, CON);
abfbe5f7 233
0807a9b5
JL		 234 OMAP_MMC_WRITE(host, CON, slot->saved_con);
235 } else
236 mmc_omap_fclk_enable(host, 0);
abfbe5f7
JY		 237}
238
239static void mmc_omap_start_request(struct mmc_omap_host *host,
240 struct mmc_request *req);
241
0f602ec7
JL		 242static void mmc_omap_slot_release_work(struct work_struct *work)
243{
244 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
245 slot_release_work);
246 struct mmc_omap_slot *next_slot = host->next_slot;
247 struct mmc_request *rq;
248
249 host->next_slot = NULL;
250 mmc_omap_select_slot(next_slot, 1);
251
252 rq = next_slot->mrq;
253 next_slot->mrq = NULL;
254 mmc_omap_start_request(host, rq);
255}
256
0807a9b5 257static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
abfbe5f7
JY		 258{
259 struct mmc_omap_host *host = slot->host;
260 unsigned long flags;
261 int i;
262
263 BUG_ON(slot == NULL || host->mmc == NULL);
0807a9b5
JL		 264
265 if (clk_enabled)
266 /* Keeps clock running for at least 8 cycles on valid freq */
267 mod_timer(&host->clk_timer, jiffies + HZ/10);
268 else {
269 del_timer(&host->clk_timer);
270 mmc_omap_fclk_offdelay(slot);
271 mmc_omap_fclk_enable(host, 0);
272 }
abfbe5f7
JY		 273
274 spin_lock_irqsave(&host->slot_lock, flags);
275 /* Check for any pending requests */
276 for (i = 0; i < host->nr_slots; i++) {
277 struct mmc_omap_slot *new_slot;
abfbe5f7
JY		 278
279 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
280 continue;
281
0f602ec7 282 BUG_ON(host->next_slot != NULL);
abfbe5f7
JY		 283 new_slot = host->slots[i];
284 /* The current slot should not have a request in queue */
285 BUG_ON(new_slot == host->current_slot);
286
0f602ec7 287 host->next_slot = new_slot;
abfbe5f7
JY		 288 host->mmc = new_slot->mmc;
289 spin_unlock_irqrestore(&host->slot_lock, flags);
b01a4f1c 290 queue_work(host->mmc_omap_wq, &host->slot_release_work);
abfbe5f7
JY		 291 return;
292 }
293
294 host->mmc = NULL;
295 wake_up(&host->slot_wq);
296 spin_unlock_irqrestore(&host->slot_lock, flags);
297}
298
5a0f3f1f
JY		 299static inline
300int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
301{
8348f002
KP		 302 if (slot->pdata->get_cover_state)
303 return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
304 slot->id);
305 return 0;
5a0f3f1f
JY		 306}
307
308static ssize_t
309mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
310 char *buf)
311{
312 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
313 struct mmc_omap_slot *slot = mmc_priv(mmc);
314
315 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
316 "closed");
317}
318
319static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
320
abfbe5f7
JY		 321static ssize_t
322mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
323 char *buf)
324{
325 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
326 struct mmc_omap_slot *slot = mmc_priv(mmc);
327
328 return sprintf(buf, "%s\n", slot->pdata->name);
329}
330
331static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
332
730c9b7e
CA		 333static void
334mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
335{
336 u32 cmdreg;
337 u32 resptype;
338 u32 cmdtype;
b13d1f0f 339 u16 irq_mask;
730c9b7e
CA		 340
341 host->cmd = cmd;
342
343 resptype = 0;
344 cmdtype = 0;
345
346 /* Our hardware needs to know exact type */
1b3b2631
CEA		 347 switch (mmc_resp_type(cmd)) {
348 case MMC_RSP_NONE:
349 break;
350 case MMC_RSP_R1:
351 case MMC_RSP_R1B:
6f949909 352 /* resp 1, 1b, 6, 7 */
730c9b7e
CA		 353 resptype = 1;
354 break;
1b3b2631 355 case MMC_RSP_R2:
730c9b7e
CA		 356 resptype = 2;
357 break;
1b3b2631 358 case MMC_RSP_R3:
730c9b7e
CA		 359 resptype = 3;
360 break;
361 default:
1b3b2631 362 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
730c9b7e
CA		 363 break;
364 }
365
366 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
367 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
368 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
369 cmdtype = OMAP_MMC_CMDTYPE_BC;
370 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
371 cmdtype = OMAP_MMC_CMDTYPE_BCR;
372 } else {
373 cmdtype = OMAP_MMC_CMDTYPE_AC;
374 }
375
376 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
377
abfbe5f7 378 if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
730c9b7e
CA		 379 cmdreg |= 1 << 6;
380
381 if (cmd->flags & MMC_RSP_BUSY)
382 cmdreg |= 1 << 11;
383
384 if (host->data && !(host->data->flags & MMC_DATA_WRITE))
385 cmdreg |= 1 << 15;
386
0fb4723d 387 mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
eb1860bc 388
3342ee8b
JY		 389 OMAP_MMC_WRITE(host, CTO, 200);
390 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
391 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
b13d1f0f
JN		 392 irq_mask = OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
393 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
394 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
395 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
396 OMAP_MMC_STAT_END_OF_DATA;
397 if (cmd->opcode == MMC_ERASE)
398 irq_mask &= ~OMAP_MMC_STAT_DATA_TOUT;
399 OMAP_MMC_WRITE(host, IE, irq_mask);
3342ee8b 400 OMAP_MMC_WRITE(host, CMD, cmdreg);
730c9b7e
CA		 401}
402
a914ded2
JY		 403static void
404mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
405 int abort)
406{
407 enum dma_data_direction dma_data_dir;
3451c067
RK		 408 struct device *dev = mmc_dev(host->mmc);
409 struct dma_chan *c;
a914ded2 410
3451c067 411 if (data->flags & MMC_DATA_WRITE) {
a914ded2 412 dma_data_dir = DMA_TO_DEVICE;
3451c067
RK		 413 c = host->dma_tx;
414 } else {
a914ded2 415 dma_data_dir = DMA_FROM_DEVICE;
3451c067
RK		 416 c = host->dma_rx;
417 }
418 if (c) {
419 if (data->error) {
420 dmaengine_terminate_all(c);
421 /* Claim nothing transferred on error... */
422 data->bytes_xfered = 0;
423 }
424 dev = c->device->dev;
425 }
426 dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir);
a914ded2
JY		 427}
428
0f602ec7
JL		 429static void mmc_omap_send_stop_work(struct work_struct *work)
430{
431 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
432 send_stop_work);
433 struct mmc_omap_slot *slot = host->current_slot;
434 struct mmc_data *data = host->stop_data;
435 unsigned long tick_ns;
436
03a16853 437 tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);
0f602ec7
JL		 438 ndelay(8*tick_ns);
439
440 mmc_omap_start_command(host, data->stop);
441}
442
730c9b7e
CA		 443static void
444mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
445{
a914ded2
JY		 446 if (host->dma_in_use)
447 mmc_omap_release_dma(host, data, data->error);
448
730c9b7e
CA		 449 host->data = NULL;
450 host->sg_len = 0;
730c9b7e
CA		 451
452 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
453 * dozens of requests until the card finishes writing data.
454 * It'd be cheaper to just wait till an EOFB interrupt arrives...
455 */
456
457 if (!data->stop) {
a914ded2
JY		 458 struct mmc_host *mmc;
459
730c9b7e 460 host->mrq = NULL;
a914ded2 461 mmc = host->mmc;
0807a9b5 462 mmc_omap_release_slot(host->current_slot, 1);
a914ded2 463 mmc_request_done(mmc, data->mrq);
730c9b7e
CA		 464 return;
465 }
466
0f602ec7 467 host->stop_data = data;
b01a4f1c 468 queue_work(host->mmc_omap_wq, &host->send_stop_work);
730c9b7e
CA		 469}
470
eb1860bc 471static void
0fb4723d 472mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
eb1860bc
JL		 473{
474 struct mmc_omap_slot *slot = host->current_slot;
475 unsigned int restarts, passes, timeout;
476 u16 stat = 0;
477
478 /* Sending abort takes 80 clocks. Have some extra and round up */
03a16853 479 timeout = DIV_ROUND_UP(120 * USEC_PER_SEC, slot->fclk_freq);
eb1860bc 480 restarts = 0;
0fb4723d 481 while (restarts < maxloops) {
eb1860bc
JL		 482 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
483 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
484
485 passes = 0;
486 while (passes < timeout) {
487 stat = OMAP_MMC_READ(host, STAT);
488 if (stat & OMAP_MMC_STAT_END_OF_CMD)
489 goto out;
490 udelay(1);
491 passes++;
492 }
493
494 restarts++;
495 }
496out:
497 OMAP_MMC_WRITE(host, STAT, stat);
498}
499
a914ded2
JY		 500static void
501mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
502{
a914ded2
JY		 503 if (host->dma_in_use)
504 mmc_omap_release_dma(host, data, 1);
505
506 host->data = NULL;
507 host->sg_len = 0;
508
0fb4723d 509 mmc_omap_send_abort(host, 10000);
a914ded2
JY		 510}
511
730c9b7e
CA		 512static void
513mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
514{
515 unsigned long flags;
516 int done;
517
518 if (!host->dma_in_use) {
519 mmc_omap_xfer_done(host, data);
520 return;
521 }
522 done = 0;
523 spin_lock_irqsave(&host->dma_lock, flags);
524 if (host->dma_done)
525 done = 1;
526 else
527 host->brs_received = 1;
528 spin_unlock_irqrestore(&host->dma_lock, flags);
529 if (done)
530 mmc_omap_xfer_done(host, data);
531}
532
730c9b7e
CA		 533static void
534mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
535{
536 unsigned long flags;
537 int done;
538
539 done = 0;
540 spin_lock_irqsave(&host->dma_lock, flags);
541 if (host->brs_received)
542 done = 1;
543 else
544 host->dma_done = 1;
545 spin_unlock_irqrestore(&host->dma_lock, flags);
546 if (done)
547 mmc_omap_xfer_done(host, data);
548}
549
550static void
551mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
552{
553 host->cmd = NULL;
554
0fb4723d 555 del_timer(&host->cmd_abort_timer);
eb1860bc 556
730c9b7e
CA		 557 if (cmd->flags & MMC_RSP_PRESENT) {
558 if (cmd->flags & MMC_RSP_136) {
559 /* response type 2 */
560 cmd->resp[3] =
3342ee8b
JY		 561 OMAP_MMC_READ(host, RSP0) |
562 (OMAP_MMC_READ(host, RSP1) << 16);
730c9b7e 563 cmd->resp[2] =
3342ee8b
JY		 564 OMAP_MMC_READ(host, RSP2) |
565 (OMAP_MMC_READ(host, RSP3) << 16);
730c9b7e 566 cmd->resp[1] =
3342ee8b
JY		 567 OMAP_MMC_READ(host, RSP4) |
568 (OMAP_MMC_READ(host, RSP5) << 16);
730c9b7e 569 cmd->resp[0] =
3342ee8b
JY		 570 OMAP_MMC_READ(host, RSP6) |
571 (OMAP_MMC_READ(host, RSP7) << 16);
730c9b7e
CA		 572 } else {
573 /* response types 1, 1b, 3, 4, 5, 6 */
574 cmd->resp[0] =
3342ee8b
JY		 575 OMAP_MMC_READ(host, RSP6) |
576 (OMAP_MMC_READ(host, RSP7) << 16);
730c9b7e
CA		 577 }
578 }
579
17b0429d 580 if (host->data == NULL || cmd->error) {
a914ded2
JY		 581 struct mmc_host *mmc;
582
583 if (host->data != NULL)
584 mmc_omap_abort_xfer(host, host->data);
730c9b7e 585 host->mrq = NULL;
a914ded2 586 mmc = host->mmc;
0807a9b5 587 mmc_omap_release_slot(host->current_slot, 1);
a914ded2 588 mmc_request_done(mmc, cmd->mrq);
730c9b7e
CA		 589 }
590}
591
eb1860bc
JL		 592/*
593 * Abort stuck command. Can occur when card is removed while it is being
594 * read.
595 */
596static void mmc_omap_abort_command(struct work_struct *work)
597{
598 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
0fb4723d
JL		 599 cmd_abort_work);
600 BUG_ON(!host->cmd);
eb1860bc
JL		 601
602 dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
603 host->cmd->opcode);
604
0fb4723d
JL		 605 if (host->cmd->error == 0)
606 host->cmd->error = -ETIMEDOUT;
eb1860bc 607
0fb4723d
JL		 608 if (host->data == NULL) {
609 struct mmc_command *cmd;
610 struct mmc_host *mmc;
611
612 cmd = host->cmd;
613 host->cmd = NULL;
614 mmc_omap_send_abort(host, 10000);
615
616 host->mrq = NULL;
617 mmc = host->mmc;
0807a9b5 618 mmc_omap_release_slot(host->current_slot, 1);
0fb4723d
JL		 619 mmc_request_done(mmc, cmd->mrq);
620 } else
621 mmc_omap_cmd_done(host, host->cmd);
eb1860bc 622
0fb4723d
JL		 623 host->abort = 0;
624 enable_irq(host->irq);
eb1860bc
JL		 625}
626
627static void
628mmc_omap_cmd_timer(unsigned long data)
629{
630 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
0fb4723d 631 unsigned long flags;
eb1860bc 632
0fb4723d
JL		 633 spin_lock_irqsave(&host->slot_lock, flags);
634 if (host->cmd != NULL && !host->abort) {
635 OMAP_MMC_WRITE(host, IE, 0);
636 disable_irq(host->irq);
637 host->abort = 1;
b01a4f1c 638 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
0fb4723d
JL		 639 }
640 spin_unlock_irqrestore(&host->slot_lock, flags);
eb1860bc
JL		 641}
642
730c9b7e
CA		 643/* PIO only */
644static void
645mmc_omap_sg_to_buf(struct mmc_omap_host *host)
646{
647 struct scatterlist *sg;
648
649 sg = host->data->sg + host->sg_idx;
650 host->buffer_bytes_left = sg->length;
45711f1a 651 host->buffer = sg_virt(sg);
730c9b7e
CA		 652 if (host->buffer_bytes_left > host->total_bytes_left)
653 host->buffer_bytes_left = host->total_bytes_left;
654}
655
0807a9b5
JL		 656static void
657mmc_omap_clk_timer(unsigned long data)
658{
659 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
660
661 mmc_omap_fclk_enable(host, 0);
662}
663
730c9b7e
CA		 664/* PIO only */
665static void
666mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
667{
75b53aee 668 int n, nwords;
730c9b7e
CA		 669
670 if (host->buffer_bytes_left == 0) {
671 host->sg_idx++;
672 BUG_ON(host->sg_idx == host->sg_len);
673 mmc_omap_sg_to_buf(host);
674 }
675 n = 64;
676 if (n > host->buffer_bytes_left)
677 n = host->buffer_bytes_left;
75b53aee 678
03a16853
AL		 679 /* Round up to handle odd number of bytes to transfer */
680 nwords = DIV_ROUND_UP(n, 2);
75b53aee 681
730c9b7e
CA		 682 host->buffer_bytes_left -= n;
683 host->total_bytes_left -= n;
684 host->data->bytes_xfered += n;
685
686 if (write) {
75b53aee
PW		 687 __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA),
688 host->buffer, nwords);
730c9b7e 689 } else {
75b53aee
PW		 690 __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA),
691 host->buffer, nwords);
730c9b7e 692 }
75b53aee
PW		 693
694 host->buffer += nwords;
730c9b7e
CA		 695}
696
75d569d3
V		 697#ifdef CONFIG_MMC_DEBUG
698static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
730c9b7e
CA		 699{
700 static const char *mmc_omap_status_bits[] = {
701 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
702 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
703 };
75d569d3
V		 704 int i;
705 char res[64], *buf = res;
706
707 buf += sprintf(buf, "MMC IRQ 0x%x:", status);
730c9b7e
CA		 708
709 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
75d569d3
V		 710 if (status & (1 << i))
711 buf += sprintf(buf, " %s", mmc_omap_status_bits[i]);
712 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
713}
714#else
715static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
716{
730c9b7e 717}
75d569d3
V		 718#endif
719
730c9b7e 720
7d12e780 721static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
730c9b7e
CA		 722{
723 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
724 u16 status;
725 int end_command;
726 int end_transfer;
2a50b888 727 int transfer_error, cmd_error;
730c9b7e
CA		 728
729 if (host->cmd == NULL && host->data == NULL) {
3342ee8b 730 status = OMAP_MMC_READ(host, STAT);
2a50b888
JY		 731 dev_info(mmc_dev(host->slots[0]->mmc),
732 "Spurious IRQ 0x%04x\n", status);
730c9b7e 733 if (status != 0) {
3342ee8b
JY		 734 OMAP_MMC_WRITE(host, STAT, status);
735 OMAP_MMC_WRITE(host, IE, 0);
730c9b7e
CA		 736 }
737 return IRQ_HANDLED;
738 }
739
740 end_command = 0;
741 end_transfer = 0;
742 transfer_error = 0;
2a50b888 743 cmd_error = 0;
730c9b7e 744
3342ee8b 745 while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
2a50b888
JY		 746 int cmd;
747
3342ee8b 748 OMAP_MMC_WRITE(host, STAT, status);
2a50b888
JY		 749 if (host->cmd != NULL)
750 cmd = host->cmd->opcode;
751 else
752 cmd = -1;
730c9b7e 753 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
2a50b888 754 status, cmd);
75d569d3
V		 755 mmc_omap_report_irq(host, status);
756
730c9b7e
CA		 757 if (host->total_bytes_left) {
758 if ((status & OMAP_MMC_STAT_A_FULL) ||
759 (status & OMAP_MMC_STAT_END_OF_DATA))
760 mmc_omap_xfer_data(host, 0);
761 if (status & OMAP_MMC_STAT_A_EMPTY)
762 mmc_omap_xfer_data(host, 1);
763 }
764
2a50b888 765 if (status & OMAP_MMC_STAT_END_OF_DATA)
730c9b7e 766 end_transfer = 1;
730c9b7e
CA		 767
768 if (status & OMAP_MMC_STAT_DATA_TOUT) {
2a50b888
JY		 769 dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
770 cmd);
730c9b7e 771 if (host->data) {
17b0429d 772 host->data->error = -ETIMEDOUT;
730c9b7e
CA		 773 transfer_error = 1;
774 }
775 }
776
777 if (status & OMAP_MMC_STAT_DATA_CRC) {
778 if (host->data) {
17b0429d 779 host->data->error = -EILSEQ;
730c9b7e
CA		 780 dev_dbg(mmc_dev(host->mmc),
781 "data CRC error, bytes left %d\n",
782 host->total_bytes_left);
783 transfer_error = 1;
784 } else {
785 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
786 }
787 }
788
789 if (status & OMAP_MMC_STAT_CMD_TOUT) {
790 /* Timeouts are routine with some commands */
791 if (host->cmd) {
abfbe5f7
JY		 792 struct mmc_omap_slot *slot =
793 host->current_slot;
2a50b888
JY		 794 if (slot == NULL ||
795 !mmc_omap_cover_is_open(slot))
5a0f3f1f 796 dev_err(mmc_dev(host->mmc),
2a50b888
JY		 797 "command timeout (CMD%d)\n",
798 cmd);
17b0429d 799 host->cmd->error = -ETIMEDOUT;
730c9b7e 800 end_command = 1;
2a50b888 801 cmd_error = 1;
730c9b7e
CA		 802 }
803 }
804
805 if (status & OMAP_MMC_STAT_CMD_CRC) {
806 if (host->cmd) {
807 dev_err(mmc_dev(host->mmc),
808 "command CRC error (CMD%d, arg 0x%08x)\n",
2a50b888 809 cmd, host->cmd->arg);
17b0429d 810 host->cmd->error = -EILSEQ;
730c9b7e 811 end_command = 1;
2a50b888 812 cmd_error = 1;
730c9b7e
CA		 813 } else
814 dev_err(mmc_dev(host->mmc),
815 "command CRC error without cmd?\n");
816 }
817
818 if (status & OMAP_MMC_STAT_CARD_ERR) {
0107a4b3
RM		 819 dev_dbg(mmc_dev(host->mmc),
820 "ignoring card status error (CMD%d)\n",
2a50b888 821 cmd);
0107a4b3 822 end_command = 1;
730c9b7e
CA		 823 }
824
825 /*
826 * NOTE: On 1610 the END_OF_CMD may come too early when
2a50b888 827 * starting a write
730c9b7e
CA		 828 */
829 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
830 (!(status & OMAP_MMC_STAT_A_EMPTY))) {
831 end_command = 1;
832 }
833 }
834
0fb4723d
JL		 835 if (cmd_error && host->data) {
836 del_timer(&host->cmd_abort_timer);
837 host->abort = 1;
838 OMAP_MMC_WRITE(host, IE, 0);
e749c6f2 839 disable_irq_nosync(host->irq);
b01a4f1c 840 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
0fb4723d
JL		 841 return IRQ_HANDLED;
842 }
843
f6947514 844 if (end_command && host->cmd)
730c9b7e 845 mmc_omap_cmd_done(host, host->cmd);
2a50b888
JY		 846 if (host->data != NULL) {
847 if (transfer_error)
848 mmc_omap_xfer_done(host, host->data);
849 else if (end_transfer)
850 mmc_omap_end_of_data(host, host->data);
730c9b7e 851 }
730c9b7e
CA		 852
853 return IRQ_HANDLED;
854}
855
7584d276 856void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
5a0f3f1f 857{
7584d276 858 int cover_open;
5a0f3f1f 859 struct mmc_omap_host *host = dev_get_drvdata(dev);
7584d276 860 struct mmc_omap_slot *slot = host->slots[num];
5a0f3f1f 861
7584d276 862 BUG_ON(num >= host->nr_slots);
5a0f3f1f
JY		 863
864 /* Other subsystems can call in here before we're initialised. */
7584d276 865 if (host->nr_slots == 0 || !host->slots[num])
5a0f3f1f
JY		 866 return;
867
7584d276
JL		 868 cover_open = mmc_omap_cover_is_open(slot);
869 if (cover_open != slot->cover_open) {
870 slot->cover_open = cover_open;
871 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
872 }
873
874 tasklet_hi_schedule(&slot->cover_tasklet);
5a0f3f1f
JY		 875}
876
7584d276 877static void mmc_omap_cover_timer(unsigned long arg)
5a0f3f1f
JY		 878{
879 struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
7584d276 880 tasklet_schedule(&slot->cover_tasklet);
5a0f3f1f
JY		 881}
882
7584d276 883static void mmc_omap_cover_handler(unsigned long param)
5a0f3f1f 884{
7584d276
JL		 885 struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
886 int cover_open = mmc_omap_cover_is_open(slot);
5a0f3f1f 887
7584d276
JL		 888 mmc_detect_change(slot->mmc, 0);
889 if (!cover_open)
890 return;
891
892 /*
893 * If no card is inserted, we postpone polling until
894 * the cover has been closed.
895 */
896 if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card))
897 return;
898
899 mod_timer(&slot->cover_timer,
900 jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
5a0f3f1f
JY		 901}
902
3451c067
RK		 903static void mmc_omap_dma_callback(void *priv)
904{
905 struct mmc_omap_host *host = priv;
906 struct mmc_data *data = host->data;
907
908 /* If we got to the end of DMA, assume everything went well */
909 data->bytes_xfered += data->blocks * data->blksz;
910
911 mmc_omap_dma_done(host, data);
912}
913
730c9b7e
CA		 914static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
915{
916 u16 reg;
917
3342ee8b 918 reg = OMAP_MMC_READ(host, SDIO);
730c9b7e 919 reg &= ~(1 << 5);
3342ee8b 920 OMAP_MMC_WRITE(host, SDIO, reg);
730c9b7e 921 /* Set maximum timeout */
3342ee8b 922 OMAP_MMC_WRITE(host, CTO, 0xff);
730c9b7e
CA		 923}
924
925static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
926{
b8f9f0e9 927 unsigned int timeout, cycle_ns;
730c9b7e
CA		 928 u16 reg;
929
b8f9f0e9
JY		 930 cycle_ns = 1000000000 / host->current_slot->fclk_freq;
931 timeout = req->data->timeout_ns / cycle_ns;
932 timeout += req->data->timeout_clks;
730c9b7e
CA		 933
934 /* Check if we need to use timeout multiplier register */
3342ee8b 935 reg = OMAP_MMC_READ(host, SDIO);
730c9b7e
CA		 936 if (timeout > 0xffff) {
937 reg |= (1 << 5);
938 timeout /= 1024;
939 } else
940 reg &= ~(1 << 5);
3342ee8b
JY		 941 OMAP_MMC_WRITE(host, SDIO, reg);
942 OMAP_MMC_WRITE(host, DTO, timeout);
730c9b7e
CA		 943}
944
945static void
946mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
947{
948 struct mmc_data *data = req->data;
a6c668fb 949 int i, use_dma = 1, block_size;
8292adc6 950 struct scatterlist *sg;
730c9b7e
CA		 951 unsigned sg_len;
952
953 host->data = data;
954 if (data == NULL) {
3342ee8b
JY		 955 OMAP_MMC_WRITE(host, BLEN, 0);
956 OMAP_MMC_WRITE(host, NBLK, 0);
957 OMAP_MMC_WRITE(host, BUF, 0);
730c9b7e
CA		 958 host->dma_in_use = 0;
959 set_cmd_timeout(host, req);
960 return;
961 }
962
a3fd4a1b 963 block_size = data->blksz;
730c9b7e 964
3342ee8b
JY		 965 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
966 OMAP_MMC_WRITE(host, BLEN, block_size - 1);
730c9b7e
CA		 967 set_data_timeout(host, req);
968
969 /* cope with calling layer confusion; it issues "single
970 * block" writes using multi-block scatterlists.
971 */
972 sg_len = (data->blocks == 1) ? 1 : data->sg_len;
973
974 /* Only do DMA for entire blocks */
8292adc6
FF		 975 for_each_sg(data->sg, sg, sg_len, i) {
976 if ((sg->length % block_size) != 0) {
a6c668fb
JN		 977 use_dma = 0;
978 break;
730c9b7e
CA		 979 }
980 }
981
982 host->sg_idx = 0;
3451c067
RK		 983 if (use_dma) {
984 enum dma_data_direction dma_data_dir;
985 struct dma_async_tx_descriptor *tx;
986 struct dma_chan *c;
987 u32 burst, *bp;
988 u16 buf;
989
990 /*
991 * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx
992 * and 24xx. Use 16 or 32 word frames when the
993 * blocksize is at least that large. Blocksize is
994 * usually 512 bytes; but not for some SD reads.
995 */
53db20d1 996 burst = mmc_omap15xx() ? 32 : 64;
3451c067
RK		 997 if (burst > data->blksz)
998 burst = data->blksz;
999
1000 burst >>= 1;
1001
1002 if (data->flags & MMC_DATA_WRITE) {
1003 c = host->dma_tx;
1004 bp = &host->dma_tx_burst;
1005 buf = 0x0f80 | (burst - 1) << 0;
1006 dma_data_dir = DMA_TO_DEVICE;
1007 } else {
1008 c = host->dma_rx;
1009 bp = &host->dma_rx_burst;
1010 buf = 0x800f | (burst - 1) << 8;
1011 dma_data_dir = DMA_FROM_DEVICE;
1012 }
1013
1014 if (!c)
1015 goto use_pio;
1016
1017 /* Only reconfigure if we have a different burst size */
1018 if (*bp != burst) {
1019 struct dma_slave_config cfg;
1020
1021 cfg.src_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1022 cfg.dst_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1023 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1024 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1025 cfg.src_maxburst = burst;
1026 cfg.dst_maxburst = burst;
1027
1028 if (dmaengine_slave_config(c, &cfg))
1029 goto use_pio;
1030
1031 *bp = burst;
1032 }
1033
1034 host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len,
1035 dma_data_dir);
1036 if (host->sg_len == 0)
1037 goto use_pio;
1038
1039 tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len,
1040 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1041 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1042 if (!tx)
1043 goto use_pio;
1044
1045 OMAP_MMC_WRITE(host, BUF, buf);
1046
1047 tx->callback = mmc_omap_dma_callback;
1048 tx->callback_param = host;
1049 dmaengine_submit(tx);
1050 host->brs_received = 0;
1051 host->dma_done = 0;
1052 host->dma_in_use = 1;
1053 return;
1054 }
1055 use_pio:
730c9b7e
CA		 1056
1057 /* Revert to PIO? */
4e078fbd
RK		 1058 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1059 host->total_bytes_left = data->blocks * block_size;
1060 host->sg_len = sg_len;
1061 mmc_omap_sg_to_buf(host);
1062 host->dma_in_use = 0;
730c9b7e
CA		 1063}
1064
abfbe5f7
JY		 1065static void mmc_omap_start_request(struct mmc_omap_host *host,
1066 struct mmc_request *req)
730c9b7e 1067{
abfbe5f7 1068 BUG_ON(host->mrq != NULL);
730c9b7e
CA		 1069
1070 host->mrq = req;
1071
1072 /* only touch fifo AFTER the controller readies it */
1073 mmc_omap_prepare_data(host, req);
1074 mmc_omap_start_command(host, req->cmd);
3451c067
RK		 1075 if (host->dma_in_use) {
1076 struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ?
1077 host->dma_tx : host->dma_rx;
1078
4e078fbd 1079 dma_async_issue_pending(c);
3451c067 1080 }
abfbe5f7
JY		 1081}
1082
1083static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1084{
1085 struct mmc_omap_slot *slot = mmc_priv(mmc);
1086 struct mmc_omap_host *host = slot->host;
1087 unsigned long flags;
1088
1089 spin_lock_irqsave(&host->slot_lock, flags);
1090 if (host->mmc != NULL) {
1091 BUG_ON(slot->mrq != NULL);
1092 slot->mrq = req;
1093 spin_unlock_irqrestore(&host->slot_lock, flags);
1094 return;
1095 } else
1096 host->mmc = mmc;
1097 spin_unlock_irqrestore(&host->slot_lock, flags);
1098 mmc_omap_select_slot(slot, 1);
1099 mmc_omap_start_request(host, req);
730c9b7e
CA		 1100}
1101
65b5b6e5
JY		 1102static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1103 int vdd)
730c9b7e 1104{
65b5b6e5 1105 struct mmc_omap_host *host;
730c9b7e 1106
65b5b6e5
JY		 1107 host = slot->host;
1108
1109 if (slot->pdata->set_power != NULL)
1110 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1111 vdd);
53db20d1 1112 if (mmc_omap2()) {
65b5b6e5
JY		 1113 u16 w;
1114
1115 if (power_on) {
1116 w = OMAP_MMC_READ(host, CON);
1117 OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1118 } else {
1119 w = OMAP_MMC_READ(host, CON);
1120 OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1121 }
730c9b7e
CA		 1122 }
1123}
1124
d3af5abe 1125static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
730c9b7e 1126{
abfbe5f7
JY		 1127 struct mmc_omap_slot *slot = mmc_priv(mmc);
1128 struct mmc_omap_host *host = slot->host;
d3af5abe 1129 int func_clk_rate = clk_get_rate(host->fclk);
730c9b7e 1130 int dsor;
730c9b7e
CA		 1131
1132 if (ios->clock == 0)
d3af5abe 1133 return 0;
730c9b7e 1134
d3af5abe
TL		 1135 dsor = func_clk_rate / ios->clock;
1136 if (dsor < 1)
1137 dsor = 1;
730c9b7e 1138
d3af5abe 1139 if (func_clk_rate / dsor > ios->clock)
730c9b7e
CA		 1140 dsor++;
1141
d3af5abe
TL		 1142 if (dsor > 250)
1143 dsor = 250;
d3af5abe 1144
abfbe5f7
JY		 1145 slot->fclk_freq = func_clk_rate / dsor;
1146
d3af5abe
TL		 1147 if (ios->bus_width == MMC_BUS_WIDTH_4)
1148 dsor |= 1 << 15;
1149
1150 return dsor;
1151}
1152
1153static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1154{
abfbe5f7
JY		 1155 struct mmc_omap_slot *slot = mmc_priv(mmc);
1156 struct mmc_omap_host *host = slot->host;
1157 int i, dsor;
0807a9b5 1158 int clk_enabled;
65b5b6e5
JY		 1159
1160 mmc_omap_select_slot(slot, 0);
1161
0807a9b5
JL		 1162 dsor = mmc_omap_calc_divisor(mmc, ios);
1163
65b5b6e5
JY		 1164 if (ios->vdd != slot->vdd)
1165 slot->vdd = ios->vdd;
730c9b7e 1166
0807a9b5 1167 clk_enabled = 0;
730c9b7e
CA		 1168 switch (ios->power_mode) {
1169 case MMC_POWER_OFF:
65b5b6e5 1170 mmc_omap_set_power(slot, 0, ios->vdd);
730c9b7e
CA		 1171 break;
1172 case MMC_POWER_UP:
46a6730e 1173 /* Cannot touch dsor yet, just power up MMC */
65b5b6e5
JY		 1174 mmc_omap_set_power(slot, 1, ios->vdd);
1175 goto exit;
46a6730e 1176 case MMC_POWER_ON:
0807a9b5
JL		 1177 mmc_omap_fclk_enable(host, 1);
1178 clk_enabled = 1;
c5cb431d 1179 dsor |= 1 << 11;
730c9b7e
CA		 1180 break;
1181 }
1182
65b5b6e5
JY		 1183 if (slot->bus_mode != ios->bus_mode) {
1184 if (slot->pdata->set_bus_mode != NULL)
1185 slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1186 ios->bus_mode);
1187 slot->bus_mode = ios->bus_mode;
1188 }
730c9b7e
CA		 1189
1190 /* On insanely high arm_per frequencies something sometimes
1191 * goes somehow out of sync, and the POW bit is not being set,
1192 * which results in the while loop below getting stuck.
1193 * Writing to the CON register twice seems to do the trick. */
1194 for (i = 0; i < 2; i++)
3342ee8b 1195 OMAP_MMC_WRITE(host, CON, dsor);
65b5b6e5 1196 slot->saved_con = dsor;
46a6730e 1197 if (ios->power_mode == MMC_POWER_ON) {
9d7c6eee
JL		 1198 /* worst case at 400kHz, 80 cycles makes 200 microsecs */
1199 int usecs = 250;
1200
730c9b7e 1201 /* Send clock cycles, poll completion */
3342ee8b
JY		 1202 OMAP_MMC_WRITE(host, IE, 0);
1203 OMAP_MMC_WRITE(host, STAT, 0xffff);
c5cb431d 1204 OMAP_MMC_WRITE(host, CMD, 1 << 7);
9d7c6eee
JL		 1205 while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
1206 udelay(1);
1207 usecs--;
1208 }
3342ee8b 1209 OMAP_MMC_WRITE(host, STAT, 1);
730c9b7e 1210 }
65b5b6e5
JY		 1211
1212exit:
0807a9b5 1213 mmc_omap_release_slot(slot, clk_enabled);
730c9b7e
CA		 1214}
1215
ab7aefd0 1216static const struct mmc_host_ops mmc_omap_ops = {
730c9b7e
CA		 1217 .request = mmc_omap_request,
1218 .set_ios = mmc_omap_set_ios,
730c9b7e
CA		 1219};
1220
c3be1efd 1221static int mmc_omap_new_slot(struct mmc_omap_host *host, int id)
730c9b7e 1222{
abfbe5f7 1223 struct mmc_omap_slot *slot = NULL;
730c9b7e 1224 struct mmc_host *mmc;
abfbe5f7
JY		 1225 int r;
1226
1227 mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1228 if (mmc == NULL)
1229 return -ENOMEM;
1230
1231 slot = mmc_priv(mmc);
1232 slot->host = host;
1233 slot->mmc = mmc;
1234 slot->id = id;
1235 slot->pdata = &host->pdata->slots[id];
1236
1237 host->slots[id] = slot;
1238
23af6039 1239 mmc->caps = 0;
90c62bf0 1240 if (host->pdata->slots[id].wires >= 4)
b13d1f0f 1241 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_ERASE;
abfbe5f7
JY		 1242
1243 mmc->ops = &mmc_omap_ops;
1244 mmc->f_min = 400000;
1245
53db20d1 1246 if (mmc_omap2())
abfbe5f7
JY		 1247 mmc->f_max = 48000000;
1248 else
1249 mmc->f_max = 24000000;
1250 if (host->pdata->max_freq)
1251 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1252 mmc->ocr_avail = slot->pdata->ocr_mask;
1253
1254 /* Use scatterlist DMA to reduce per-transfer costs.
1255 * NOTE max_seg_size assumption that small blocks aren't
1256 * normally used (except e.g. for reading SD registers).
1257 */
a36274e0 1258 mmc->max_segs = 32;
abfbe5f7
JY		 1259 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
1260 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
1261 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1262 mmc->max_seg_size = mmc->max_req_size;
1263
0e5c93e0
JN		 1264 if (slot->pdata->get_cover_state != NULL) {
1265 setup_timer(&slot->cover_timer, mmc_omap_cover_timer,
1266 (unsigned long)slot);
1267 tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
1268 (unsigned long)slot);
1269 }
1270
abfbe5f7
JY		 1271 r = mmc_add_host(mmc);
1272 if (r < 0)
1273 goto err_remove_host;
1274
1275 if (slot->pdata->name != NULL) {
1276 r = device_create_file(&mmc->class_dev,
1277 &dev_attr_slot_name);
1278 if (r < 0)
1279 goto err_remove_host;
1280 }
1281
5a0f3f1f
JY		 1282 if (slot->pdata->get_cover_state != NULL) {
1283 r = device_create_file(&mmc->class_dev,
1284 &dev_attr_cover_switch);
1285 if (r < 0)
1286 goto err_remove_slot_name;
7584d276 1287 tasklet_schedule(&slot->cover_tasklet);
5a0f3f1f
JY		 1288 }
1289
abfbe5f7
JY		 1290 return 0;
1291
5a0f3f1f
JY		 1292err_remove_slot_name:
1293 if (slot->pdata->name != NULL)
1294 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
abfbe5f7
JY		 1295err_remove_host:
1296 mmc_remove_host(mmc);
1297 mmc_free_host(mmc);
1298 return r;
1299}
1300
1301static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1302{
1303 struct mmc_host *mmc = slot->mmc;
1304
1305 if (slot->pdata->name != NULL)
1306 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
5a0f3f1f
JY		 1307 if (slot->pdata->get_cover_state != NULL)
1308 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1309
7584d276
JL		 1310 tasklet_kill(&slot->cover_tasklet);
1311 del_timer_sync(&slot->cover_timer);
b01a4f1c 1312 flush_workqueue(slot->host->mmc_omap_wq);
abfbe5f7
JY		 1313
1314 mmc_remove_host(mmc);
1315 mmc_free_host(mmc);
1316}
1317
c3be1efd 1318static int mmc_omap_probe(struct platform_device *pdev)
abfbe5f7
JY		 1319{
1320 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
730c9b7e 1321 struct mmc_omap_host *host = NULL;
81ca7034 1322 struct resource *res;
abfbe5f7 1323 int i, ret = 0;
ce9c1a83 1324 int irq;
81ca7034 1325
abfbe5f7 1326 if (pdata == NULL) {
81ca7034
JY		 1327 dev_err(&pdev->dev, "platform data missing\n");
1328 return -ENXIO;
1329 }
abfbe5f7
JY		 1330 if (pdata->nr_slots == 0) {
1331 dev_err(&pdev->dev, "no slots\n");
9cb238c0 1332 return -EPROBE_DEFER;
abfbe5f7 1333 }
81ca7034 1334
64ac16ec
JN		 1335 host = devm_kzalloc(&pdev->dev, sizeof(struct mmc_omap_host),
1336 GFP_KERNEL);
1337 if (host == NULL)
1338 return -ENOMEM;
1339
ce9c1a83 1340 irq = platform_get_irq(pdev, 0);
64ac16ec 1341 if (irq < 0)
ce9c1a83 1342 return -ENXIO;
730c9b7e 1343
64ac16ec
JN		 1344 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1345 host->virt_base = devm_ioremap_resource(&pdev->dev, res);
1346 if (IS_ERR(host->virt_base))
1347 return PTR_ERR(host->virt_base);
730c9b7e 1348
0f602ec7
JL		 1349 INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
1350 INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
1351
0fb4723d
JL		 1352 INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
1353 setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer,
1354 (unsigned long) host);
eb1860bc 1355
0807a9b5
JL		 1356 spin_lock_init(&host->clk_lock);
1357 setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host);
1358
730c9b7e 1359 spin_lock_init(&host->dma_lock);
abfbe5f7
JY		 1360 spin_lock_init(&host->slot_lock);
1361 init_waitqueue_head(&host->slot_wq);
1362
abfbe5f7 1363 host->pdata = pdata;
53db20d1 1364 host->features = host->pdata->slots[0].features;
abfbe5f7
JY		 1365 host->dev = &pdev->dev;
1366 platform_set_drvdata(pdev, host);
1367
730c9b7e 1368 host->id = pdev->id;
ce9c1a83 1369 host->irq = irq;
2ca5dc6f 1370 host->phys_base = res->start;
d4a36645 1371 host->iclk = clk_get(&pdev->dev, "ick");
64ac16ec
JN		 1372 if (IS_ERR(host->iclk))
1373 return PTR_ERR(host->iclk);
d4a36645 1374 clk_enable(host->iclk);
730c9b7e 1375
5c9e02b1 1376 host->fclk = clk_get(&pdev->dev, "fck");
730c9b7e
CA		 1377 if (IS_ERR(host->fclk)) {
1378 ret = PTR_ERR(host->fclk);
81ca7034 1379 goto err_free_iclk;
730c9b7e
CA		 1380 }
1381
3451c067
RK		 1382 host->dma_tx_burst = -1;
1383 host->dma_rx_burst = -1;
1384
d15b08fb
PU		 1385 host->dma_tx = dma_request_chan(&pdev->dev, "tx");
1386 if (IS_ERR(host->dma_tx)) {
1387 ret = PTR_ERR(host->dma_tx);
1388 if (ret == -EPROBE_DEFER) {
1389 clk_put(host->fclk);
1390 goto err_free_iclk;
1391 }
1392
1393 host->dma_tx = NULL;
1394 dev_warn(host->dev, "TX DMA channel request failed\n");
1395 }
1396
1397 host->dma_rx = dma_request_chan(&pdev->dev, "rx");
1398 if (IS_ERR(host->dma_rx)) {
1399 ret = PTR_ERR(host->dma_rx);
1400 if (ret == -EPROBE_DEFER) {
1401 if (host->dma_tx)
1402 dma_release_channel(host->dma_tx);
1403 clk_put(host->fclk);
1404 goto err_free_iclk;
1405 }
1406
1407 host->dma_rx = NULL;
1408 dev_warn(host->dev, "RX DMA channel request failed\n");
1409 }
3451c067 1410
abfbe5f7
JY		 1411 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1412 if (ret)
3451c067 1413 goto err_free_dma;
42431acb 1414
abfbe5f7
JY		 1415 if (pdata->init != NULL) {
1416 ret = pdata->init(&pdev->dev);
1417 if (ret < 0)
1418 goto err_free_irq;
1419 }
730c9b7e 1420
abfbe5f7 1421 host->nr_slots = pdata->nr_slots;
53db20d1 1422 host->reg_shift = (mmc_omap7xx() ? 1 : 2);
3caf4140
TL		 1423
1424 host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0);
38276a91
JL		 1425 if (!host->mmc_omap_wq) {
1426 ret = -ENOMEM;
3caf4140 1427 goto err_plat_cleanup;
38276a91 1428 }
3caf4140 1429
abfbe5f7
JY		 1430 for (i = 0; i < pdata->nr_slots; i++) {
1431 ret = mmc_omap_new_slot(host, i);
1432 if (ret < 0) {
1433 while (--i >= 0)
1434 mmc_omap_remove_slot(host->slots[i]);
730c9b7e 1435
3caf4140 1436 goto err_destroy_wq;
730c9b7e 1437 }
730c9b7e
CA		 1438 }
1439
730c9b7e
CA		 1440 return 0;
1441
3caf4140
TL		 1442err_destroy_wq:
1443 destroy_workqueue(host->mmc_omap_wq);
abfbe5f7
JY		 1444err_plat_cleanup:
1445 if (pdata->cleanup)
1446 pdata->cleanup(&pdev->dev);
1447err_free_irq:
1448 free_irq(host->irq, host);
3451c067
RK		 1449err_free_dma:
1450 if (host->dma_tx)
1451 dma_release_channel(host->dma_tx);
1452 if (host->dma_rx)
1453 dma_release_channel(host->dma_rx);
81ca7034
JY		 1454 clk_put(host->fclk);
1455err_free_iclk:
e799acb2
LM		 1456 clk_disable(host->iclk);
1457 clk_put(host->iclk);
730c9b7e
CA		 1458 return ret;
1459}
1460
6e0ee714 1461static int mmc_omap_remove(struct platform_device *pdev)
730c9b7e
CA		 1462{
1463 struct mmc_omap_host *host = platform_get_drvdata(pdev);
abfbe5f7 1464 int i;
730c9b7e 1465
81ca7034
JY		 1466 BUG_ON(host == NULL);
1467
abfbe5f7
JY		 1468 for (i = 0; i < host->nr_slots; i++)
1469 mmc_omap_remove_slot(host->slots[i]);
1470
1471 if (host->pdata->cleanup)
1472 host->pdata->cleanup(&pdev->dev);
81ca7034 1473
d4a36645 1474 mmc_omap_fclk_enable(host, 0);
49c1d9da 1475 free_irq(host->irq, host);
d4a36645
RK		 1476 clk_put(host->fclk);
1477 clk_disable(host->iclk);
1478 clk_put(host->iclk);
730c9b7e 1479
3451c067
RK		 1480 if (host->dma_tx)
1481 dma_release_channel(host->dma_tx);
1482 if (host->dma_rx)
1483 dma_release_channel(host->dma_rx);
1484
b01a4f1c 1485 destroy_workqueue(host->mmc_omap_wq);
81ca7034 1486
730c9b7e
CA		 1487 return 0;
1488}
1489
9cb238c0
TL		 1490#if IS_BUILTIN(CONFIG_OF)
1491static const struct of_device_id mmc_omap_match[] = {
1492 { .compatible = "ti,omap2420-mmc", },
1493 { },
1494};
b73f34c2 1495MODULE_DEVICE_TABLE(of, mmc_omap_match);
9cb238c0
TL		 1496#endif
1497
730c9b7e 1498static struct platform_driver mmc_omap_driver = {
b6e0703b 1499 .probe = mmc_omap_probe,
0433c143 1500 .remove = mmc_omap_remove,
730c9b7e
CA		 1501 .driver = {
1502 .name = DRIVER_NAME,
9cb238c0 1503 .of_match_table = of_match_ptr(mmc_omap_match),
730c9b7e
CA		 1504 },
1505};
1506
680f1b5b 1507module_platform_driver(mmc_omap_driver);
730c9b7e
CA		 1508MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1509MODULE_LICENSE("GPL");
bc65c724 1510MODULE_ALIAS("platform:" DRIVER_NAME);
d36b6910 1511MODULE_AUTHOR("Juha Yrjölä");
Linux kernel - Deliverables
This page took 0.82034 seconds and 5 git commands to generate.