Commit | Line | Data |
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730c9b7e | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/omap.c |
730c9b7e CA |
3 | * |
4 | * Copyright (C) 2004 Nokia Corporation | |
d36b6910 | 5 | * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com> |
730c9b7e CA |
6 | * Misc hacks here and there by Tony Lindgren <tony@atomide.com> |
7 | * Other hacks (DMA, SD, etc) by David Brownell | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
730c9b7e CA |
14 | #include <linux/module.h> |
15 | #include <linux/moduleparam.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/ioport.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/dma-mapping.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/timer.h> | |
24 | #include <linux/mmc/host.h> | |
730c9b7e CA |
25 | #include <linux/mmc/card.h> |
26 | #include <linux/clk.h> | |
45711f1a | 27 | #include <linux/scatterlist.h> |
6d16bfb5 | 28 | #include <linux/i2c/tps65010.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
730c9b7e CA |
30 | |
31 | #include <asm/io.h> | |
32 | #include <asm/irq.h> | |
730c9b7e | 33 | |
ce491cf8 TL |
34 | #include <plat/board.h> |
35 | #include <plat/mmc.h> | |
1bc857f7 | 36 | #include <asm/gpio.h> |
ce491cf8 TL |
37 | #include <plat/dma.h> |
38 | #include <plat/mux.h> | |
39 | #include <plat/fpga.h> | |
730c9b7e | 40 | |
0551f4df | 41 | #define OMAP_MMC_REG_CMD 0x00 |
0e950fa6 MB |
42 | #define OMAP_MMC_REG_ARGL 0x01 |
43 | #define OMAP_MMC_REG_ARGH 0x02 | |
44 | #define OMAP_MMC_REG_CON 0x03 | |
45 | #define OMAP_MMC_REG_STAT 0x04 | |
46 | #define OMAP_MMC_REG_IE 0x05 | |
47 | #define OMAP_MMC_REG_CTO 0x06 | |
48 | #define OMAP_MMC_REG_DTO 0x07 | |
49 | #define OMAP_MMC_REG_DATA 0x08 | |
50 | #define OMAP_MMC_REG_BLEN 0x09 | |
51 | #define OMAP_MMC_REG_NBLK 0x0a | |
52 | #define OMAP_MMC_REG_BUF 0x0b | |
53 | #define OMAP_MMC_REG_SDIO 0x0d | |
54 | #define OMAP_MMC_REG_REV 0x0f | |
55 | #define OMAP_MMC_REG_RSP0 0x10 | |
56 | #define OMAP_MMC_REG_RSP1 0x11 | |
57 | #define OMAP_MMC_REG_RSP2 0x12 | |
58 | #define OMAP_MMC_REG_RSP3 0x13 | |
59 | #define OMAP_MMC_REG_RSP4 0x14 | |
60 | #define OMAP_MMC_REG_RSP5 0x15 | |
61 | #define OMAP_MMC_REG_RSP6 0x16 | |
62 | #define OMAP_MMC_REG_RSP7 0x17 | |
63 | #define OMAP_MMC_REG_IOSR 0x18 | |
64 | #define OMAP_MMC_REG_SYSC 0x19 | |
65 | #define OMAP_MMC_REG_SYSS 0x1a | |
0551f4df JY |
66 | |
67 | #define OMAP_MMC_STAT_CARD_ERR (1 << 14) | |
68 | #define OMAP_MMC_STAT_CARD_IRQ (1 << 13) | |
69 | #define OMAP_MMC_STAT_OCR_BUSY (1 << 12) | |
70 | #define OMAP_MMC_STAT_A_EMPTY (1 << 11) | |
71 | #define OMAP_MMC_STAT_A_FULL (1 << 10) | |
72 | #define OMAP_MMC_STAT_CMD_CRC (1 << 8) | |
73 | #define OMAP_MMC_STAT_CMD_TOUT (1 << 7) | |
74 | #define OMAP_MMC_STAT_DATA_CRC (1 << 6) | |
75 | #define OMAP_MMC_STAT_DATA_TOUT (1 << 5) | |
76 | #define OMAP_MMC_STAT_END_BUSY (1 << 4) | |
77 | #define OMAP_MMC_STAT_END_OF_DATA (1 << 3) | |
78 | #define OMAP_MMC_STAT_CARD_BUSY (1 << 2) | |
79 | #define OMAP_MMC_STAT_END_OF_CMD (1 << 0) | |
80 | ||
0e950fa6 MB |
81 | #define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift) |
82 | #define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg)) | |
83 | #define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg)) | |
0551f4df JY |
84 | |
85 | /* | |
86 | * Command types | |
87 | */ | |
88 | #define OMAP_MMC_CMDTYPE_BC 0 | |
89 | #define OMAP_MMC_CMDTYPE_BCR 1 | |
90 | #define OMAP_MMC_CMDTYPE_AC 2 | |
91 | #define OMAP_MMC_CMDTYPE_ADTC 3 | |
92 | ||
730c9b7e CA |
93 | |
94 | #define DRIVER_NAME "mmci-omap" | |
730c9b7e CA |
95 | |
96 | /* Specifies how often in millisecs to poll for card status changes | |
97 | * when the cover switch is open */ | |
7584d276 | 98 | #define OMAP_MMC_COVER_POLL_DELAY 500 |
730c9b7e | 99 | |
abfbe5f7 JY |
100 | struct mmc_omap_host; |
101 | ||
102 | struct mmc_omap_slot { | |
103 | int id; | |
104 | unsigned int vdd; | |
105 | u16 saved_con; | |
106 | u16 bus_mode; | |
107 | unsigned int fclk_freq; | |
108 | unsigned powered:1; | |
109 | ||
7584d276 JL |
110 | struct tasklet_struct cover_tasklet; |
111 | struct timer_list cover_timer; | |
5a0f3f1f JY |
112 | unsigned cover_open; |
113 | ||
abfbe5f7 JY |
114 | struct mmc_request *mrq; |
115 | struct mmc_omap_host *host; | |
116 | struct mmc_host *mmc; | |
117 | struct omap_mmc_slot_data *pdata; | |
118 | }; | |
119 | ||
730c9b7e CA |
120 | struct mmc_omap_host { |
121 | int initialized; | |
122 | int suspended; | |
123 | struct mmc_request * mrq; | |
124 | struct mmc_command * cmd; | |
125 | struct mmc_data * data; | |
126 | struct mmc_host * mmc; | |
127 | struct device * dev; | |
128 | unsigned char id; /* 16xx chips have 2 MMC blocks */ | |
129 | struct clk * iclk; | |
130 | struct clk * fclk; | |
89783b1e JY |
131 | struct resource *mem_res; |
132 | void __iomem *virt_base; | |
133 | unsigned int phys_base; | |
730c9b7e CA |
134 | int irq; |
135 | unsigned char bus_mode; | |
136 | unsigned char hw_bus_mode; | |
0e950fa6 | 137 | unsigned int reg_shift; |
730c9b7e | 138 | |
0fb4723d JL |
139 | struct work_struct cmd_abort_work; |
140 | unsigned abort:1; | |
141 | struct timer_list cmd_abort_timer; | |
eb1860bc | 142 | |
0f602ec7 JL |
143 | struct work_struct slot_release_work; |
144 | struct mmc_omap_slot *next_slot; | |
145 | struct work_struct send_stop_work; | |
146 | struct mmc_data *stop_data; | |
147 | ||
730c9b7e CA |
148 | unsigned int sg_len; |
149 | int sg_idx; | |
150 | u16 * buffer; | |
151 | u32 buffer_bytes_left; | |
152 | u32 total_bytes_left; | |
153 | ||
154 | unsigned use_dma:1; | |
155 | unsigned brs_received:1, dma_done:1; | |
156 | unsigned dma_is_read:1; | |
157 | unsigned dma_in_use:1; | |
158 | int dma_ch; | |
159 | spinlock_t dma_lock; | |
160 | struct timer_list dma_timer; | |
161 | unsigned dma_len; | |
162 | ||
abfbe5f7 JY |
163 | struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS]; |
164 | struct mmc_omap_slot *current_slot; | |
165 | spinlock_t slot_lock; | |
166 | wait_queue_head_t slot_wq; | |
167 | int nr_slots; | |
168 | ||
0807a9b5 JL |
169 | struct timer_list clk_timer; |
170 | spinlock_t clk_lock; /* for changing enabled state */ | |
171 | unsigned int fclk_enabled:1; | |
b01a4f1c | 172 | struct workqueue_struct *mmc_omap_wq; |
0807a9b5 | 173 | |
abfbe5f7 | 174 | struct omap_mmc_platform_data *pdata; |
730c9b7e CA |
175 | }; |
176 | ||
0d9ee5b2 | 177 | |
7c8ad982 | 178 | static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot) |
0807a9b5 JL |
179 | { |
180 | unsigned long tick_ns; | |
181 | ||
182 | if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) { | |
183 | tick_ns = (1000000000 + slot->fclk_freq - 1) / slot->fclk_freq; | |
184 | ndelay(8 * tick_ns); | |
185 | } | |
186 | } | |
187 | ||
7c8ad982 | 188 | static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable) |
0807a9b5 JL |
189 | { |
190 | unsigned long flags; | |
191 | ||
192 | spin_lock_irqsave(&host->clk_lock, flags); | |
193 | if (host->fclk_enabled != enable) { | |
194 | host->fclk_enabled = enable; | |
195 | if (enable) | |
196 | clk_enable(host->fclk); | |
197 | else | |
198 | clk_disable(host->fclk); | |
199 | } | |
200 | spin_unlock_irqrestore(&host->clk_lock, flags); | |
201 | } | |
202 | ||
abfbe5f7 JY |
203 | static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed) |
204 | { | |
205 | struct mmc_omap_host *host = slot->host; | |
206 | unsigned long flags; | |
207 | ||
208 | if (claimed) | |
209 | goto no_claim; | |
210 | spin_lock_irqsave(&host->slot_lock, flags); | |
211 | while (host->mmc != NULL) { | |
212 | spin_unlock_irqrestore(&host->slot_lock, flags); | |
213 | wait_event(host->slot_wq, host->mmc == NULL); | |
214 | spin_lock_irqsave(&host->slot_lock, flags); | |
215 | } | |
216 | host->mmc = slot->mmc; | |
217 | spin_unlock_irqrestore(&host->slot_lock, flags); | |
218 | no_claim: | |
0807a9b5 JL |
219 | del_timer(&host->clk_timer); |
220 | if (host->current_slot != slot || !claimed) | |
221 | mmc_omap_fclk_offdelay(host->current_slot); | |
222 | ||
abfbe5f7 | 223 | if (host->current_slot != slot) { |
0807a9b5 | 224 | OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00); |
abfbe5f7 JY |
225 | if (host->pdata->switch_slot != NULL) |
226 | host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id); | |
227 | host->current_slot = slot; | |
228 | } | |
229 | ||
0807a9b5 JL |
230 | if (claimed) { |
231 | mmc_omap_fclk_enable(host, 1); | |
232 | ||
233 | /* Doing the dummy read here seems to work around some bug | |
234 | * at least in OMAP24xx silicon where the command would not | |
235 | * start after writing the CMD register. Sigh. */ | |
236 | OMAP_MMC_READ(host, CON); | |
abfbe5f7 | 237 | |
0807a9b5 JL |
238 | OMAP_MMC_WRITE(host, CON, slot->saved_con); |
239 | } else | |
240 | mmc_omap_fclk_enable(host, 0); | |
abfbe5f7 JY |
241 | } |
242 | ||
243 | static void mmc_omap_start_request(struct mmc_omap_host *host, | |
244 | struct mmc_request *req); | |
245 | ||
0f602ec7 JL |
246 | static void mmc_omap_slot_release_work(struct work_struct *work) |
247 | { | |
248 | struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, | |
249 | slot_release_work); | |
250 | struct mmc_omap_slot *next_slot = host->next_slot; | |
251 | struct mmc_request *rq; | |
252 | ||
253 | host->next_slot = NULL; | |
254 | mmc_omap_select_slot(next_slot, 1); | |
255 | ||
256 | rq = next_slot->mrq; | |
257 | next_slot->mrq = NULL; | |
258 | mmc_omap_start_request(host, rq); | |
259 | } | |
260 | ||
0807a9b5 | 261 | static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled) |
abfbe5f7 JY |
262 | { |
263 | struct mmc_omap_host *host = slot->host; | |
264 | unsigned long flags; | |
265 | int i; | |
266 | ||
267 | BUG_ON(slot == NULL || host->mmc == NULL); | |
0807a9b5 JL |
268 | |
269 | if (clk_enabled) | |
270 | /* Keeps clock running for at least 8 cycles on valid freq */ | |
271 | mod_timer(&host->clk_timer, jiffies + HZ/10); | |
272 | else { | |
273 | del_timer(&host->clk_timer); | |
274 | mmc_omap_fclk_offdelay(slot); | |
275 | mmc_omap_fclk_enable(host, 0); | |
276 | } | |
abfbe5f7 JY |
277 | |
278 | spin_lock_irqsave(&host->slot_lock, flags); | |
279 | /* Check for any pending requests */ | |
280 | for (i = 0; i < host->nr_slots; i++) { | |
281 | struct mmc_omap_slot *new_slot; | |
abfbe5f7 JY |
282 | |
283 | if (host->slots[i] == NULL || host->slots[i]->mrq == NULL) | |
284 | continue; | |
285 | ||
0f602ec7 | 286 | BUG_ON(host->next_slot != NULL); |
abfbe5f7 JY |
287 | new_slot = host->slots[i]; |
288 | /* The current slot should not have a request in queue */ | |
289 | BUG_ON(new_slot == host->current_slot); | |
290 | ||
0f602ec7 | 291 | host->next_slot = new_slot; |
abfbe5f7 JY |
292 | host->mmc = new_slot->mmc; |
293 | spin_unlock_irqrestore(&host->slot_lock, flags); | |
b01a4f1c | 294 | queue_work(host->mmc_omap_wq, &host->slot_release_work); |
abfbe5f7 JY |
295 | return; |
296 | } | |
297 | ||
298 | host->mmc = NULL; | |
299 | wake_up(&host->slot_wq); | |
300 | spin_unlock_irqrestore(&host->slot_lock, flags); | |
301 | } | |
302 | ||
5a0f3f1f JY |
303 | static inline |
304 | int mmc_omap_cover_is_open(struct mmc_omap_slot *slot) | |
305 | { | |
8348f002 KP |
306 | if (slot->pdata->get_cover_state) |
307 | return slot->pdata->get_cover_state(mmc_dev(slot->mmc), | |
308 | slot->id); | |
309 | return 0; | |
5a0f3f1f JY |
310 | } |
311 | ||
312 | static ssize_t | |
313 | mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr, | |
314 | char *buf) | |
315 | { | |
316 | struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); | |
317 | struct mmc_omap_slot *slot = mmc_priv(mmc); | |
318 | ||
319 | return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" : | |
320 | "closed"); | |
321 | } | |
322 | ||
323 | static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL); | |
324 | ||
abfbe5f7 JY |
325 | static ssize_t |
326 | mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr, | |
327 | char *buf) | |
328 | { | |
329 | struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); | |
330 | struct mmc_omap_slot *slot = mmc_priv(mmc); | |
331 | ||
332 | return sprintf(buf, "%s\n", slot->pdata->name); | |
333 | } | |
334 | ||
335 | static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL); | |
336 | ||
730c9b7e CA |
337 | static void |
338 | mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd) | |
339 | { | |
340 | u32 cmdreg; | |
341 | u32 resptype; | |
342 | u32 cmdtype; | |
343 | ||
344 | host->cmd = cmd; | |
345 | ||
346 | resptype = 0; | |
347 | cmdtype = 0; | |
348 | ||
349 | /* Our hardware needs to know exact type */ | |
1b3b2631 CEA |
350 | switch (mmc_resp_type(cmd)) { |
351 | case MMC_RSP_NONE: | |
352 | break; | |
353 | case MMC_RSP_R1: | |
354 | case MMC_RSP_R1B: | |
6f949909 | 355 | /* resp 1, 1b, 6, 7 */ |
730c9b7e CA |
356 | resptype = 1; |
357 | break; | |
1b3b2631 | 358 | case MMC_RSP_R2: |
730c9b7e CA |
359 | resptype = 2; |
360 | break; | |
1b3b2631 | 361 | case MMC_RSP_R3: |
730c9b7e CA |
362 | resptype = 3; |
363 | break; | |
364 | default: | |
1b3b2631 | 365 | dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd)); |
730c9b7e CA |
366 | break; |
367 | } | |
368 | ||
369 | if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) { | |
370 | cmdtype = OMAP_MMC_CMDTYPE_ADTC; | |
371 | } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) { | |
372 | cmdtype = OMAP_MMC_CMDTYPE_BC; | |
373 | } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) { | |
374 | cmdtype = OMAP_MMC_CMDTYPE_BCR; | |
375 | } else { | |
376 | cmdtype = OMAP_MMC_CMDTYPE_AC; | |
377 | } | |
378 | ||
379 | cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12); | |
380 | ||
abfbe5f7 | 381 | if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN) |
730c9b7e CA |
382 | cmdreg |= 1 << 6; |
383 | ||
384 | if (cmd->flags & MMC_RSP_BUSY) | |
385 | cmdreg |= 1 << 11; | |
386 | ||
387 | if (host->data && !(host->data->flags & MMC_DATA_WRITE)) | |
388 | cmdreg |= 1 << 15; | |
389 | ||
0fb4723d | 390 | mod_timer(&host->cmd_abort_timer, jiffies + HZ/2); |
eb1860bc | 391 | |
3342ee8b JY |
392 | OMAP_MMC_WRITE(host, CTO, 200); |
393 | OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff); | |
394 | OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16); | |
395 | OMAP_MMC_WRITE(host, IE, | |
730c9b7e CA |
396 | OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL | |
397 | OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT | | |
398 | OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT | | |
399 | OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR | | |
400 | OMAP_MMC_STAT_END_OF_DATA); | |
3342ee8b | 401 | OMAP_MMC_WRITE(host, CMD, cmdreg); |
730c9b7e CA |
402 | } |
403 | ||
a914ded2 JY |
404 | static void |
405 | mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data, | |
406 | int abort) | |
407 | { | |
408 | enum dma_data_direction dma_data_dir; | |
409 | ||
410 | BUG_ON(host->dma_ch < 0); | |
411 | if (data->error) | |
412 | omap_stop_dma(host->dma_ch); | |
413 | /* Release DMA channel lazily */ | |
414 | mod_timer(&host->dma_timer, jiffies + HZ); | |
415 | if (data->flags & MMC_DATA_WRITE) | |
416 | dma_data_dir = DMA_TO_DEVICE; | |
417 | else | |
418 | dma_data_dir = DMA_FROM_DEVICE; | |
419 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len, | |
420 | dma_data_dir); | |
421 | } | |
422 | ||
0f602ec7 JL |
423 | static void mmc_omap_send_stop_work(struct work_struct *work) |
424 | { | |
425 | struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, | |
426 | send_stop_work); | |
427 | struct mmc_omap_slot *slot = host->current_slot; | |
428 | struct mmc_data *data = host->stop_data; | |
429 | unsigned long tick_ns; | |
430 | ||
431 | tick_ns = (1000000000 + slot->fclk_freq - 1)/slot->fclk_freq; | |
432 | ndelay(8*tick_ns); | |
433 | ||
434 | mmc_omap_start_command(host, data->stop); | |
435 | } | |
436 | ||
730c9b7e CA |
437 | static void |
438 | mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data) | |
439 | { | |
a914ded2 JY |
440 | if (host->dma_in_use) |
441 | mmc_omap_release_dma(host, data, data->error); | |
442 | ||
730c9b7e CA |
443 | host->data = NULL; |
444 | host->sg_len = 0; | |
730c9b7e CA |
445 | |
446 | /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing | |
447 | * dozens of requests until the card finishes writing data. | |
448 | * It'd be cheaper to just wait till an EOFB interrupt arrives... | |
449 | */ | |
450 | ||
451 | if (!data->stop) { | |
a914ded2 JY |
452 | struct mmc_host *mmc; |
453 | ||
730c9b7e | 454 | host->mrq = NULL; |
a914ded2 | 455 | mmc = host->mmc; |
0807a9b5 | 456 | mmc_omap_release_slot(host->current_slot, 1); |
a914ded2 | 457 | mmc_request_done(mmc, data->mrq); |
730c9b7e CA |
458 | return; |
459 | } | |
460 | ||
0f602ec7 | 461 | host->stop_data = data; |
b01a4f1c | 462 | queue_work(host->mmc_omap_wq, &host->send_stop_work); |
730c9b7e CA |
463 | } |
464 | ||
eb1860bc | 465 | static void |
0fb4723d | 466 | mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops) |
eb1860bc JL |
467 | { |
468 | struct mmc_omap_slot *slot = host->current_slot; | |
469 | unsigned int restarts, passes, timeout; | |
470 | u16 stat = 0; | |
471 | ||
472 | /* Sending abort takes 80 clocks. Have some extra and round up */ | |
473 | timeout = (120*1000000 + slot->fclk_freq - 1)/slot->fclk_freq; | |
474 | restarts = 0; | |
0fb4723d | 475 | while (restarts < maxloops) { |
eb1860bc JL |
476 | OMAP_MMC_WRITE(host, STAT, 0xFFFF); |
477 | OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7)); | |
478 | ||
479 | passes = 0; | |
480 | while (passes < timeout) { | |
481 | stat = OMAP_MMC_READ(host, STAT); | |
482 | if (stat & OMAP_MMC_STAT_END_OF_CMD) | |
483 | goto out; | |
484 | udelay(1); | |
485 | passes++; | |
486 | } | |
487 | ||
488 | restarts++; | |
489 | } | |
490 | out: | |
491 | OMAP_MMC_WRITE(host, STAT, stat); | |
492 | } | |
493 | ||
a914ded2 JY |
494 | static void |
495 | mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data) | |
496 | { | |
a914ded2 JY |
497 | if (host->dma_in_use) |
498 | mmc_omap_release_dma(host, data, 1); | |
499 | ||
500 | host->data = NULL; | |
501 | host->sg_len = 0; | |
502 | ||
0fb4723d | 503 | mmc_omap_send_abort(host, 10000); |
a914ded2 JY |
504 | } |
505 | ||
730c9b7e CA |
506 | static void |
507 | mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data) | |
508 | { | |
509 | unsigned long flags; | |
510 | int done; | |
511 | ||
512 | if (!host->dma_in_use) { | |
513 | mmc_omap_xfer_done(host, data); | |
514 | return; | |
515 | } | |
516 | done = 0; | |
517 | spin_lock_irqsave(&host->dma_lock, flags); | |
518 | if (host->dma_done) | |
519 | done = 1; | |
520 | else | |
521 | host->brs_received = 1; | |
522 | spin_unlock_irqrestore(&host->dma_lock, flags); | |
523 | if (done) | |
524 | mmc_omap_xfer_done(host, data); | |
525 | } | |
526 | ||
527 | static void | |
528 | mmc_omap_dma_timer(unsigned long data) | |
529 | { | |
530 | struct mmc_omap_host *host = (struct mmc_omap_host *) data; | |
531 | ||
532 | BUG_ON(host->dma_ch < 0); | |
533 | omap_free_dma(host->dma_ch); | |
534 | host->dma_ch = -1; | |
535 | } | |
536 | ||
537 | static void | |
538 | mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data) | |
539 | { | |
540 | unsigned long flags; | |
541 | int done; | |
542 | ||
543 | done = 0; | |
544 | spin_lock_irqsave(&host->dma_lock, flags); | |
545 | if (host->brs_received) | |
546 | done = 1; | |
547 | else | |
548 | host->dma_done = 1; | |
549 | spin_unlock_irqrestore(&host->dma_lock, flags); | |
550 | if (done) | |
551 | mmc_omap_xfer_done(host, data); | |
552 | } | |
553 | ||
554 | static void | |
555 | mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd) | |
556 | { | |
557 | host->cmd = NULL; | |
558 | ||
0fb4723d | 559 | del_timer(&host->cmd_abort_timer); |
eb1860bc | 560 | |
730c9b7e CA |
561 | if (cmd->flags & MMC_RSP_PRESENT) { |
562 | if (cmd->flags & MMC_RSP_136) { | |
563 | /* response type 2 */ | |
564 | cmd->resp[3] = | |
3342ee8b JY |
565 | OMAP_MMC_READ(host, RSP0) | |
566 | (OMAP_MMC_READ(host, RSP1) << 16); | |
730c9b7e | 567 | cmd->resp[2] = |
3342ee8b JY |
568 | OMAP_MMC_READ(host, RSP2) | |
569 | (OMAP_MMC_READ(host, RSP3) << 16); | |
730c9b7e | 570 | cmd->resp[1] = |
3342ee8b JY |
571 | OMAP_MMC_READ(host, RSP4) | |
572 | (OMAP_MMC_READ(host, RSP5) << 16); | |
730c9b7e | 573 | cmd->resp[0] = |
3342ee8b JY |
574 | OMAP_MMC_READ(host, RSP6) | |
575 | (OMAP_MMC_READ(host, RSP7) << 16); | |
730c9b7e CA |
576 | } else { |
577 | /* response types 1, 1b, 3, 4, 5, 6 */ | |
578 | cmd->resp[0] = | |
3342ee8b JY |
579 | OMAP_MMC_READ(host, RSP6) | |
580 | (OMAP_MMC_READ(host, RSP7) << 16); | |
730c9b7e CA |
581 | } |
582 | } | |
583 | ||
17b0429d | 584 | if (host->data == NULL || cmd->error) { |
a914ded2 JY |
585 | struct mmc_host *mmc; |
586 | ||
587 | if (host->data != NULL) | |
588 | mmc_omap_abort_xfer(host, host->data); | |
730c9b7e | 589 | host->mrq = NULL; |
a914ded2 | 590 | mmc = host->mmc; |
0807a9b5 | 591 | mmc_omap_release_slot(host->current_slot, 1); |
a914ded2 | 592 | mmc_request_done(mmc, cmd->mrq); |
730c9b7e CA |
593 | } |
594 | } | |
595 | ||
eb1860bc JL |
596 | /* |
597 | * Abort stuck command. Can occur when card is removed while it is being | |
598 | * read. | |
599 | */ | |
600 | static void mmc_omap_abort_command(struct work_struct *work) | |
601 | { | |
602 | struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, | |
0fb4723d JL |
603 | cmd_abort_work); |
604 | BUG_ON(!host->cmd); | |
eb1860bc JL |
605 | |
606 | dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n", | |
607 | host->cmd->opcode); | |
608 | ||
0fb4723d JL |
609 | if (host->cmd->error == 0) |
610 | host->cmd->error = -ETIMEDOUT; | |
eb1860bc | 611 | |
0fb4723d JL |
612 | if (host->data == NULL) { |
613 | struct mmc_command *cmd; | |
614 | struct mmc_host *mmc; | |
615 | ||
616 | cmd = host->cmd; | |
617 | host->cmd = NULL; | |
618 | mmc_omap_send_abort(host, 10000); | |
619 | ||
620 | host->mrq = NULL; | |
621 | mmc = host->mmc; | |
0807a9b5 | 622 | mmc_omap_release_slot(host->current_slot, 1); |
0fb4723d JL |
623 | mmc_request_done(mmc, cmd->mrq); |
624 | } else | |
625 | mmc_omap_cmd_done(host, host->cmd); | |
eb1860bc | 626 | |
0fb4723d JL |
627 | host->abort = 0; |
628 | enable_irq(host->irq); | |
eb1860bc JL |
629 | } |
630 | ||
631 | static void | |
632 | mmc_omap_cmd_timer(unsigned long data) | |
633 | { | |
634 | struct mmc_omap_host *host = (struct mmc_omap_host *) data; | |
0fb4723d | 635 | unsigned long flags; |
eb1860bc | 636 | |
0fb4723d JL |
637 | spin_lock_irqsave(&host->slot_lock, flags); |
638 | if (host->cmd != NULL && !host->abort) { | |
639 | OMAP_MMC_WRITE(host, IE, 0); | |
640 | disable_irq(host->irq); | |
641 | host->abort = 1; | |
b01a4f1c | 642 | queue_work(host->mmc_omap_wq, &host->cmd_abort_work); |
0fb4723d JL |
643 | } |
644 | spin_unlock_irqrestore(&host->slot_lock, flags); | |
eb1860bc JL |
645 | } |
646 | ||
730c9b7e CA |
647 | /* PIO only */ |
648 | static void | |
649 | mmc_omap_sg_to_buf(struct mmc_omap_host *host) | |
650 | { | |
651 | struct scatterlist *sg; | |
652 | ||
653 | sg = host->data->sg + host->sg_idx; | |
654 | host->buffer_bytes_left = sg->length; | |
45711f1a | 655 | host->buffer = sg_virt(sg); |
730c9b7e CA |
656 | if (host->buffer_bytes_left > host->total_bytes_left) |
657 | host->buffer_bytes_left = host->total_bytes_left; | |
658 | } | |
659 | ||
0807a9b5 JL |
660 | static void |
661 | mmc_omap_clk_timer(unsigned long data) | |
662 | { | |
663 | struct mmc_omap_host *host = (struct mmc_omap_host *) data; | |
664 | ||
665 | mmc_omap_fclk_enable(host, 0); | |
666 | } | |
667 | ||
730c9b7e CA |
668 | /* PIO only */ |
669 | static void | |
670 | mmc_omap_xfer_data(struct mmc_omap_host *host, int write) | |
671 | { | |
672 | int n; | |
730c9b7e CA |
673 | |
674 | if (host->buffer_bytes_left == 0) { | |
675 | host->sg_idx++; | |
676 | BUG_ON(host->sg_idx == host->sg_len); | |
677 | mmc_omap_sg_to_buf(host); | |
678 | } | |
679 | n = 64; | |
680 | if (n > host->buffer_bytes_left) | |
681 | n = host->buffer_bytes_left; | |
682 | host->buffer_bytes_left -= n; | |
683 | host->total_bytes_left -= n; | |
684 | host->data->bytes_xfered += n; | |
685 | ||
686 | if (write) { | |
0e950fa6 | 687 | __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA), host->buffer, n); |
730c9b7e | 688 | } else { |
0e950fa6 | 689 | __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA), host->buffer, n); |
730c9b7e CA |
690 | } |
691 | } | |
692 | ||
693 | static inline void mmc_omap_report_irq(u16 status) | |
694 | { | |
695 | static const char *mmc_omap_status_bits[] = { | |
696 | "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO", | |
697 | "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR" | |
698 | }; | |
699 | int i, c = 0; | |
700 | ||
701 | for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++) | |
702 | if (status & (1 << i)) { | |
703 | if (c) | |
704 | printk(" "); | |
705 | printk("%s", mmc_omap_status_bits[i]); | |
706 | c++; | |
707 | } | |
708 | } | |
709 | ||
7d12e780 | 710 | static irqreturn_t mmc_omap_irq(int irq, void *dev_id) |
730c9b7e CA |
711 | { |
712 | struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id; | |
713 | u16 status; | |
714 | int end_command; | |
715 | int end_transfer; | |
2a50b888 | 716 | int transfer_error, cmd_error; |
730c9b7e CA |
717 | |
718 | if (host->cmd == NULL && host->data == NULL) { | |
3342ee8b | 719 | status = OMAP_MMC_READ(host, STAT); |
2a50b888 JY |
720 | dev_info(mmc_dev(host->slots[0]->mmc), |
721 | "Spurious IRQ 0x%04x\n", status); | |
730c9b7e | 722 | if (status != 0) { |
3342ee8b JY |
723 | OMAP_MMC_WRITE(host, STAT, status); |
724 | OMAP_MMC_WRITE(host, IE, 0); | |
730c9b7e CA |
725 | } |
726 | return IRQ_HANDLED; | |
727 | } | |
728 | ||
729 | end_command = 0; | |
730 | end_transfer = 0; | |
731 | transfer_error = 0; | |
2a50b888 | 732 | cmd_error = 0; |
730c9b7e | 733 | |
3342ee8b | 734 | while ((status = OMAP_MMC_READ(host, STAT)) != 0) { |
2a50b888 JY |
735 | int cmd; |
736 | ||
3342ee8b | 737 | OMAP_MMC_WRITE(host, STAT, status); |
2a50b888 JY |
738 | if (host->cmd != NULL) |
739 | cmd = host->cmd->opcode; | |
740 | else | |
741 | cmd = -1; | |
730c9b7e CA |
742 | #ifdef CONFIG_MMC_DEBUG |
743 | dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ", | |
2a50b888 | 744 | status, cmd); |
730c9b7e CA |
745 | mmc_omap_report_irq(status); |
746 | printk("\n"); | |
747 | #endif | |
748 | if (host->total_bytes_left) { | |
749 | if ((status & OMAP_MMC_STAT_A_FULL) || | |
750 | (status & OMAP_MMC_STAT_END_OF_DATA)) | |
751 | mmc_omap_xfer_data(host, 0); | |
752 | if (status & OMAP_MMC_STAT_A_EMPTY) | |
753 | mmc_omap_xfer_data(host, 1); | |
754 | } | |
755 | ||
2a50b888 | 756 | if (status & OMAP_MMC_STAT_END_OF_DATA) |
730c9b7e | 757 | end_transfer = 1; |
730c9b7e CA |
758 | |
759 | if (status & OMAP_MMC_STAT_DATA_TOUT) { | |
2a50b888 JY |
760 | dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n", |
761 | cmd); | |
730c9b7e | 762 | if (host->data) { |
17b0429d | 763 | host->data->error = -ETIMEDOUT; |
730c9b7e CA |
764 | transfer_error = 1; |
765 | } | |
766 | } | |
767 | ||
768 | if (status & OMAP_MMC_STAT_DATA_CRC) { | |
769 | if (host->data) { | |
17b0429d | 770 | host->data->error = -EILSEQ; |
730c9b7e CA |
771 | dev_dbg(mmc_dev(host->mmc), |
772 | "data CRC error, bytes left %d\n", | |
773 | host->total_bytes_left); | |
774 | transfer_error = 1; | |
775 | } else { | |
776 | dev_dbg(mmc_dev(host->mmc), "data CRC error\n"); | |
777 | } | |
778 | } | |
779 | ||
780 | if (status & OMAP_MMC_STAT_CMD_TOUT) { | |
781 | /* Timeouts are routine with some commands */ | |
782 | if (host->cmd) { | |
abfbe5f7 JY |
783 | struct mmc_omap_slot *slot = |
784 | host->current_slot; | |
2a50b888 JY |
785 | if (slot == NULL || |
786 | !mmc_omap_cover_is_open(slot)) | |
5a0f3f1f | 787 | dev_err(mmc_dev(host->mmc), |
2a50b888 JY |
788 | "command timeout (CMD%d)\n", |
789 | cmd); | |
17b0429d | 790 | host->cmd->error = -ETIMEDOUT; |
730c9b7e | 791 | end_command = 1; |
2a50b888 | 792 | cmd_error = 1; |
730c9b7e CA |
793 | } |
794 | } | |
795 | ||
796 | if (status & OMAP_MMC_STAT_CMD_CRC) { | |
797 | if (host->cmd) { | |
798 | dev_err(mmc_dev(host->mmc), | |
799 | "command CRC error (CMD%d, arg 0x%08x)\n", | |
2a50b888 | 800 | cmd, host->cmd->arg); |
17b0429d | 801 | host->cmd->error = -EILSEQ; |
730c9b7e | 802 | end_command = 1; |
2a50b888 | 803 | cmd_error = 1; |
730c9b7e CA |
804 | } else |
805 | dev_err(mmc_dev(host->mmc), | |
806 | "command CRC error without cmd?\n"); | |
807 | } | |
808 | ||
809 | if (status & OMAP_MMC_STAT_CARD_ERR) { | |
0107a4b3 RM |
810 | dev_dbg(mmc_dev(host->mmc), |
811 | "ignoring card status error (CMD%d)\n", | |
2a50b888 | 812 | cmd); |
0107a4b3 | 813 | end_command = 1; |
730c9b7e CA |
814 | } |
815 | ||
816 | /* | |
817 | * NOTE: On 1610 the END_OF_CMD may come too early when | |
2a50b888 | 818 | * starting a write |
730c9b7e CA |
819 | */ |
820 | if ((status & OMAP_MMC_STAT_END_OF_CMD) && | |
821 | (!(status & OMAP_MMC_STAT_A_EMPTY))) { | |
822 | end_command = 1; | |
823 | } | |
824 | } | |
825 | ||
0fb4723d JL |
826 | if (cmd_error && host->data) { |
827 | del_timer(&host->cmd_abort_timer); | |
828 | host->abort = 1; | |
829 | OMAP_MMC_WRITE(host, IE, 0); | |
e749c6f2 | 830 | disable_irq_nosync(host->irq); |
b01a4f1c | 831 | queue_work(host->mmc_omap_wq, &host->cmd_abort_work); |
0fb4723d JL |
832 | return IRQ_HANDLED; |
833 | } | |
834 | ||
f6947514 | 835 | if (end_command && host->cmd) |
730c9b7e | 836 | mmc_omap_cmd_done(host, host->cmd); |
2a50b888 JY |
837 | if (host->data != NULL) { |
838 | if (transfer_error) | |
839 | mmc_omap_xfer_done(host, host->data); | |
840 | else if (end_transfer) | |
841 | mmc_omap_end_of_data(host, host->data); | |
730c9b7e | 842 | } |
730c9b7e CA |
843 | |
844 | return IRQ_HANDLED; | |
845 | } | |
846 | ||
7584d276 | 847 | void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed) |
5a0f3f1f | 848 | { |
7584d276 | 849 | int cover_open; |
5a0f3f1f | 850 | struct mmc_omap_host *host = dev_get_drvdata(dev); |
7584d276 | 851 | struct mmc_omap_slot *slot = host->slots[num]; |
5a0f3f1f | 852 | |
7584d276 | 853 | BUG_ON(num >= host->nr_slots); |
5a0f3f1f JY |
854 | |
855 | /* Other subsystems can call in here before we're initialised. */ | |
7584d276 | 856 | if (host->nr_slots == 0 || !host->slots[num]) |
5a0f3f1f JY |
857 | return; |
858 | ||
7584d276 JL |
859 | cover_open = mmc_omap_cover_is_open(slot); |
860 | if (cover_open != slot->cover_open) { | |
861 | slot->cover_open = cover_open; | |
862 | sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch"); | |
863 | } | |
864 | ||
865 | tasklet_hi_schedule(&slot->cover_tasklet); | |
5a0f3f1f JY |
866 | } |
867 | ||
7584d276 | 868 | static void mmc_omap_cover_timer(unsigned long arg) |
5a0f3f1f JY |
869 | { |
870 | struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg; | |
7584d276 | 871 | tasklet_schedule(&slot->cover_tasklet); |
5a0f3f1f JY |
872 | } |
873 | ||
7584d276 | 874 | static void mmc_omap_cover_handler(unsigned long param) |
5a0f3f1f | 875 | { |
7584d276 JL |
876 | struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param; |
877 | int cover_open = mmc_omap_cover_is_open(slot); | |
5a0f3f1f | 878 | |
7584d276 JL |
879 | mmc_detect_change(slot->mmc, 0); |
880 | if (!cover_open) | |
881 | return; | |
882 | ||
883 | /* | |
884 | * If no card is inserted, we postpone polling until | |
885 | * the cover has been closed. | |
886 | */ | |
887 | if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card)) | |
888 | return; | |
889 | ||
890 | mod_timer(&slot->cover_timer, | |
891 | jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY)); | |
5a0f3f1f JY |
892 | } |
893 | ||
730c9b7e CA |
894 | /* Prepare to transfer the next segment of a scatterlist */ |
895 | static void | |
896 | mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data) | |
897 | { | |
898 | int dma_ch = host->dma_ch; | |
899 | unsigned long data_addr; | |
900 | u16 buf, frame; | |
901 | u32 count; | |
902 | struct scatterlist *sg = &data->sg[host->sg_idx]; | |
903 | int src_port = 0; | |
904 | int dst_port = 0; | |
905 | int sync_dev = 0; | |
906 | ||
0e950fa6 | 907 | data_addr = host->phys_base + OMAP_MMC_REG(host, DATA); |
a3fd4a1b | 908 | frame = data->blksz; |
730c9b7e CA |
909 | count = sg_dma_len(sg); |
910 | ||
a3fd4a1b | 911 | if ((data->blocks == 1) && (count > data->blksz)) |
730c9b7e CA |
912 | count = frame; |
913 | ||
914 | host->dma_len = count; | |
915 | ||
916 | /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx. | |
917 | * Use 16 or 32 word frames when the blocksize is at least that large. | |
918 | * Blocksize is usually 512 bytes; but not for some SD reads. | |
919 | */ | |
920 | if (cpu_is_omap15xx() && frame > 32) | |
921 | frame = 32; | |
922 | else if (frame > 64) | |
923 | frame = 64; | |
924 | count /= frame; | |
925 | frame >>= 1; | |
926 | ||
927 | if (!(data->flags & MMC_DATA_WRITE)) { | |
928 | buf = 0x800f | ((frame - 1) << 8); | |
929 | ||
930 | if (cpu_class_is_omap1()) { | |
931 | src_port = OMAP_DMA_PORT_TIPB; | |
932 | dst_port = OMAP_DMA_PORT_EMIFF; | |
933 | } | |
934 | if (cpu_is_omap24xx()) | |
935 | sync_dev = OMAP24XX_DMA_MMC1_RX; | |
936 | ||
937 | omap_set_dma_src_params(dma_ch, src_port, | |
938 | OMAP_DMA_AMODE_CONSTANT, | |
939 | data_addr, 0, 0); | |
940 | omap_set_dma_dest_params(dma_ch, dst_port, | |
941 | OMAP_DMA_AMODE_POST_INC, | |
942 | sg_dma_address(sg), 0, 0); | |
943 | omap_set_dma_dest_data_pack(dma_ch, 1); | |
944 | omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4); | |
945 | } else { | |
946 | buf = 0x0f80 | ((frame - 1) << 0); | |
947 | ||
948 | if (cpu_class_is_omap1()) { | |
949 | src_port = OMAP_DMA_PORT_EMIFF; | |
950 | dst_port = OMAP_DMA_PORT_TIPB; | |
951 | } | |
952 | if (cpu_is_omap24xx()) | |
953 | sync_dev = OMAP24XX_DMA_MMC1_TX; | |
954 | ||
955 | omap_set_dma_dest_params(dma_ch, dst_port, | |
956 | OMAP_DMA_AMODE_CONSTANT, | |
957 | data_addr, 0, 0); | |
958 | omap_set_dma_src_params(dma_ch, src_port, | |
959 | OMAP_DMA_AMODE_POST_INC, | |
960 | sg_dma_address(sg), 0, 0); | |
961 | omap_set_dma_src_data_pack(dma_ch, 1); | |
962 | omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4); | |
963 | } | |
964 | ||
965 | /* Max limit for DMA frame count is 0xffff */ | |
d99c5909 | 966 | BUG_ON(count > 0xffff); |
730c9b7e | 967 | |
3342ee8b | 968 | OMAP_MMC_WRITE(host, BUF, buf); |
730c9b7e CA |
969 | omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16, |
970 | frame, count, OMAP_DMA_SYNC_FRAME, | |
971 | sync_dev, 0); | |
972 | } | |
973 | ||
974 | /* A scatterlist segment completed */ | |
975 | static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data) | |
976 | { | |
977 | struct mmc_omap_host *host = (struct mmc_omap_host *) data; | |
978 | struct mmc_data *mmcdat = host->data; | |
979 | ||
980 | if (unlikely(host->dma_ch < 0)) { | |
ce9c1a83 TL |
981 | dev_err(mmc_dev(host->mmc), |
982 | "DMA callback while DMA not enabled\n"); | |
730c9b7e CA |
983 | return; |
984 | } | |
985 | /* FIXME: We really should do something to _handle_ the errors */ | |
7ff879db | 986 | if (ch_status & OMAP1_DMA_TOUT_IRQ) { |
730c9b7e CA |
987 | dev_err(mmc_dev(host->mmc),"DMA timeout\n"); |
988 | return; | |
989 | } | |
990 | if (ch_status & OMAP_DMA_DROP_IRQ) { | |
991 | dev_err(mmc_dev(host->mmc), "DMA sync error\n"); | |
992 | return; | |
993 | } | |
994 | if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) { | |
995 | return; | |
996 | } | |
997 | mmcdat->bytes_xfered += host->dma_len; | |
998 | host->sg_idx++; | |
999 | if (host->sg_idx < host->sg_len) { | |
1000 | mmc_omap_prepare_dma(host, host->data); | |
1001 | omap_start_dma(host->dma_ch); | |
1002 | } else | |
1003 | mmc_omap_dma_done(host, host->data); | |
1004 | } | |
1005 | ||
1006 | static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data) | |
1007 | { | |
df48dd02 | 1008 | const char *dma_dev_name; |
730c9b7e CA |
1009 | int sync_dev, dma_ch, is_read, r; |
1010 | ||
1011 | is_read = !(data->flags & MMC_DATA_WRITE); | |
1012 | del_timer_sync(&host->dma_timer); | |
1013 | if (host->dma_ch >= 0) { | |
1014 | if (is_read == host->dma_is_read) | |
1015 | return 0; | |
1016 | omap_free_dma(host->dma_ch); | |
1017 | host->dma_ch = -1; | |
1018 | } | |
1019 | ||
1020 | if (is_read) { | |
d8874665 | 1021 | if (host->id == 0) { |
730c9b7e | 1022 | sync_dev = OMAP_DMA_MMC_RX; |
df48dd02 | 1023 | dma_dev_name = "MMC1 read"; |
730c9b7e CA |
1024 | } else { |
1025 | sync_dev = OMAP_DMA_MMC2_RX; | |
df48dd02 | 1026 | dma_dev_name = "MMC2 read"; |
730c9b7e CA |
1027 | } |
1028 | } else { | |
d8874665 | 1029 | if (host->id == 0) { |
730c9b7e | 1030 | sync_dev = OMAP_DMA_MMC_TX; |
df48dd02 | 1031 | dma_dev_name = "MMC1 write"; |
730c9b7e CA |
1032 | } else { |
1033 | sync_dev = OMAP_DMA_MMC2_TX; | |
df48dd02 | 1034 | dma_dev_name = "MMC2 write"; |
730c9b7e CA |
1035 | } |
1036 | } | |
df48dd02 | 1037 | r = omap_request_dma(sync_dev, dma_dev_name, mmc_omap_dma_cb, |
730c9b7e CA |
1038 | host, &dma_ch); |
1039 | if (r != 0) { | |
1040 | dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r); | |
1041 | return r; | |
1042 | } | |
1043 | host->dma_ch = dma_ch; | |
1044 | host->dma_is_read = is_read; | |
1045 | ||
1046 | return 0; | |
1047 | } | |
1048 | ||
1049 | static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req) | |
1050 | { | |
1051 | u16 reg; | |
1052 | ||
3342ee8b | 1053 | reg = OMAP_MMC_READ(host, SDIO); |
730c9b7e | 1054 | reg &= ~(1 << 5); |
3342ee8b | 1055 | OMAP_MMC_WRITE(host, SDIO, reg); |
730c9b7e | 1056 | /* Set maximum timeout */ |
3342ee8b | 1057 | OMAP_MMC_WRITE(host, CTO, 0xff); |
730c9b7e CA |
1058 | } |
1059 | ||
1060 | static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req) | |
1061 | { | |
b8f9f0e9 | 1062 | unsigned int timeout, cycle_ns; |
730c9b7e CA |
1063 | u16 reg; |
1064 | ||
b8f9f0e9 JY |
1065 | cycle_ns = 1000000000 / host->current_slot->fclk_freq; |
1066 | timeout = req->data->timeout_ns / cycle_ns; | |
1067 | timeout += req->data->timeout_clks; | |
730c9b7e CA |
1068 | |
1069 | /* Check if we need to use timeout multiplier register */ | |
3342ee8b | 1070 | reg = OMAP_MMC_READ(host, SDIO); |
730c9b7e CA |
1071 | if (timeout > 0xffff) { |
1072 | reg |= (1 << 5); | |
1073 | timeout /= 1024; | |
1074 | } else | |
1075 | reg &= ~(1 << 5); | |
3342ee8b JY |
1076 | OMAP_MMC_WRITE(host, SDIO, reg); |
1077 | OMAP_MMC_WRITE(host, DTO, timeout); | |
730c9b7e CA |
1078 | } |
1079 | ||
1080 | static void | |
1081 | mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req) | |
1082 | { | |
1083 | struct mmc_data *data = req->data; | |
1084 | int i, use_dma, block_size; | |
1085 | unsigned sg_len; | |
1086 | ||
1087 | host->data = data; | |
1088 | if (data == NULL) { | |
3342ee8b JY |
1089 | OMAP_MMC_WRITE(host, BLEN, 0); |
1090 | OMAP_MMC_WRITE(host, NBLK, 0); | |
1091 | OMAP_MMC_WRITE(host, BUF, 0); | |
730c9b7e CA |
1092 | host->dma_in_use = 0; |
1093 | set_cmd_timeout(host, req); | |
1094 | return; | |
1095 | } | |
1096 | ||
a3fd4a1b | 1097 | block_size = data->blksz; |
730c9b7e | 1098 | |
3342ee8b JY |
1099 | OMAP_MMC_WRITE(host, NBLK, data->blocks - 1); |
1100 | OMAP_MMC_WRITE(host, BLEN, block_size - 1); | |
730c9b7e CA |
1101 | set_data_timeout(host, req); |
1102 | ||
1103 | /* cope with calling layer confusion; it issues "single | |
1104 | * block" writes using multi-block scatterlists. | |
1105 | */ | |
1106 | sg_len = (data->blocks == 1) ? 1 : data->sg_len; | |
1107 | ||
1108 | /* Only do DMA for entire blocks */ | |
1109 | use_dma = host->use_dma; | |
1110 | if (use_dma) { | |
1111 | for (i = 0; i < sg_len; i++) { | |
1112 | if ((data->sg[i].length % block_size) != 0) { | |
1113 | use_dma = 0; | |
1114 | break; | |
1115 | } | |
1116 | } | |
1117 | } | |
1118 | ||
1119 | host->sg_idx = 0; | |
1120 | if (use_dma) { | |
1121 | if (mmc_omap_get_dma_channel(host, data) == 0) { | |
1122 | enum dma_data_direction dma_data_dir; | |
1123 | ||
1124 | if (data->flags & MMC_DATA_WRITE) | |
1125 | dma_data_dir = DMA_TO_DEVICE; | |
1126 | else | |
1127 | dma_data_dir = DMA_FROM_DEVICE; | |
1128 | ||
1129 | host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, | |
1130 | sg_len, dma_data_dir); | |
1131 | host->total_bytes_left = 0; | |
1132 | mmc_omap_prepare_dma(host, req->data); | |
1133 | host->brs_received = 0; | |
1134 | host->dma_done = 0; | |
1135 | host->dma_in_use = 1; | |
1136 | } else | |
1137 | use_dma = 0; | |
1138 | } | |
1139 | ||
1140 | /* Revert to PIO? */ | |
1141 | if (!use_dma) { | |
3342ee8b | 1142 | OMAP_MMC_WRITE(host, BUF, 0x1f1f); |
730c9b7e CA |
1143 | host->total_bytes_left = data->blocks * block_size; |
1144 | host->sg_len = sg_len; | |
1145 | mmc_omap_sg_to_buf(host); | |
1146 | host->dma_in_use = 0; | |
1147 | } | |
1148 | } | |
1149 | ||
abfbe5f7 JY |
1150 | static void mmc_omap_start_request(struct mmc_omap_host *host, |
1151 | struct mmc_request *req) | |
730c9b7e | 1152 | { |
abfbe5f7 | 1153 | BUG_ON(host->mrq != NULL); |
730c9b7e CA |
1154 | |
1155 | host->mrq = req; | |
1156 | ||
1157 | /* only touch fifo AFTER the controller readies it */ | |
1158 | mmc_omap_prepare_data(host, req); | |
1159 | mmc_omap_start_command(host, req->cmd); | |
1160 | if (host->dma_in_use) | |
1161 | omap_start_dma(host->dma_ch); | |
abfbe5f7 JY |
1162 | } |
1163 | ||
1164 | static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req) | |
1165 | { | |
1166 | struct mmc_omap_slot *slot = mmc_priv(mmc); | |
1167 | struct mmc_omap_host *host = slot->host; | |
1168 | unsigned long flags; | |
1169 | ||
1170 | spin_lock_irqsave(&host->slot_lock, flags); | |
1171 | if (host->mmc != NULL) { | |
1172 | BUG_ON(slot->mrq != NULL); | |
1173 | slot->mrq = req; | |
1174 | spin_unlock_irqrestore(&host->slot_lock, flags); | |
1175 | return; | |
1176 | } else | |
1177 | host->mmc = mmc; | |
1178 | spin_unlock_irqrestore(&host->slot_lock, flags); | |
1179 | mmc_omap_select_slot(slot, 1); | |
1180 | mmc_omap_start_request(host, req); | |
730c9b7e CA |
1181 | } |
1182 | ||
65b5b6e5 JY |
1183 | static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on, |
1184 | int vdd) | |
730c9b7e | 1185 | { |
65b5b6e5 | 1186 | struct mmc_omap_host *host; |
730c9b7e | 1187 | |
65b5b6e5 JY |
1188 | host = slot->host; |
1189 | ||
1190 | if (slot->pdata->set_power != NULL) | |
1191 | slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on, | |
1192 | vdd); | |
1193 | ||
1194 | if (cpu_is_omap24xx()) { | |
1195 | u16 w; | |
1196 | ||
1197 | if (power_on) { | |
1198 | w = OMAP_MMC_READ(host, CON); | |
1199 | OMAP_MMC_WRITE(host, CON, w | (1 << 11)); | |
1200 | } else { | |
1201 | w = OMAP_MMC_READ(host, CON); | |
1202 | OMAP_MMC_WRITE(host, CON, w & ~(1 << 11)); | |
1203 | } | |
730c9b7e CA |
1204 | } |
1205 | } | |
1206 | ||
d3af5abe | 1207 | static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios) |
730c9b7e | 1208 | { |
abfbe5f7 JY |
1209 | struct mmc_omap_slot *slot = mmc_priv(mmc); |
1210 | struct mmc_omap_host *host = slot->host; | |
d3af5abe | 1211 | int func_clk_rate = clk_get_rate(host->fclk); |
730c9b7e | 1212 | int dsor; |
730c9b7e CA |
1213 | |
1214 | if (ios->clock == 0) | |
d3af5abe | 1215 | return 0; |
730c9b7e | 1216 | |
d3af5abe TL |
1217 | dsor = func_clk_rate / ios->clock; |
1218 | if (dsor < 1) | |
1219 | dsor = 1; | |
730c9b7e | 1220 | |
d3af5abe | 1221 | if (func_clk_rate / dsor > ios->clock) |
730c9b7e CA |
1222 | dsor++; |
1223 | ||
d3af5abe TL |
1224 | if (dsor > 250) |
1225 | dsor = 250; | |
d3af5abe | 1226 | |
abfbe5f7 JY |
1227 | slot->fclk_freq = func_clk_rate / dsor; |
1228 | ||
d3af5abe TL |
1229 | if (ios->bus_width == MMC_BUS_WIDTH_4) |
1230 | dsor |= 1 << 15; | |
1231 | ||
1232 | return dsor; | |
1233 | } | |
1234 | ||
1235 | static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
1236 | { | |
abfbe5f7 JY |
1237 | struct mmc_omap_slot *slot = mmc_priv(mmc); |
1238 | struct mmc_omap_host *host = slot->host; | |
1239 | int i, dsor; | |
0807a9b5 | 1240 | int clk_enabled; |
65b5b6e5 JY |
1241 | |
1242 | mmc_omap_select_slot(slot, 0); | |
1243 | ||
0807a9b5 JL |
1244 | dsor = mmc_omap_calc_divisor(mmc, ios); |
1245 | ||
65b5b6e5 JY |
1246 | if (ios->vdd != slot->vdd) |
1247 | slot->vdd = ios->vdd; | |
730c9b7e | 1248 | |
0807a9b5 | 1249 | clk_enabled = 0; |
730c9b7e CA |
1250 | switch (ios->power_mode) { |
1251 | case MMC_POWER_OFF: | |
65b5b6e5 | 1252 | mmc_omap_set_power(slot, 0, ios->vdd); |
730c9b7e CA |
1253 | break; |
1254 | case MMC_POWER_UP: | |
46a6730e | 1255 | /* Cannot touch dsor yet, just power up MMC */ |
65b5b6e5 JY |
1256 | mmc_omap_set_power(slot, 1, ios->vdd); |
1257 | goto exit; | |
46a6730e | 1258 | case MMC_POWER_ON: |
0807a9b5 JL |
1259 | mmc_omap_fclk_enable(host, 1); |
1260 | clk_enabled = 1; | |
c5cb431d | 1261 | dsor |= 1 << 11; |
730c9b7e CA |
1262 | break; |
1263 | } | |
1264 | ||
65b5b6e5 JY |
1265 | if (slot->bus_mode != ios->bus_mode) { |
1266 | if (slot->pdata->set_bus_mode != NULL) | |
1267 | slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id, | |
1268 | ios->bus_mode); | |
1269 | slot->bus_mode = ios->bus_mode; | |
1270 | } | |
730c9b7e CA |
1271 | |
1272 | /* On insanely high arm_per frequencies something sometimes | |
1273 | * goes somehow out of sync, and the POW bit is not being set, | |
1274 | * which results in the while loop below getting stuck. | |
1275 | * Writing to the CON register twice seems to do the trick. */ | |
1276 | for (i = 0; i < 2; i++) | |
3342ee8b | 1277 | OMAP_MMC_WRITE(host, CON, dsor); |
65b5b6e5 | 1278 | slot->saved_con = dsor; |
46a6730e | 1279 | if (ios->power_mode == MMC_POWER_ON) { |
9d7c6eee JL |
1280 | /* worst case at 400kHz, 80 cycles makes 200 microsecs */ |
1281 | int usecs = 250; | |
1282 | ||
730c9b7e | 1283 | /* Send clock cycles, poll completion */ |
3342ee8b JY |
1284 | OMAP_MMC_WRITE(host, IE, 0); |
1285 | OMAP_MMC_WRITE(host, STAT, 0xffff); | |
c5cb431d | 1286 | OMAP_MMC_WRITE(host, CMD, 1 << 7); |
9d7c6eee JL |
1287 | while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) { |
1288 | udelay(1); | |
1289 | usecs--; | |
1290 | } | |
3342ee8b | 1291 | OMAP_MMC_WRITE(host, STAT, 1); |
730c9b7e | 1292 | } |
65b5b6e5 JY |
1293 | |
1294 | exit: | |
0807a9b5 | 1295 | mmc_omap_release_slot(slot, clk_enabled); |
730c9b7e CA |
1296 | } |
1297 | ||
ab7aefd0 | 1298 | static const struct mmc_host_ops mmc_omap_ops = { |
730c9b7e CA |
1299 | .request = mmc_omap_request, |
1300 | .set_ios = mmc_omap_set_ios, | |
730c9b7e CA |
1301 | }; |
1302 | ||
4f837791 | 1303 | static int __devinit mmc_omap_new_slot(struct mmc_omap_host *host, int id) |
730c9b7e | 1304 | { |
abfbe5f7 | 1305 | struct mmc_omap_slot *slot = NULL; |
730c9b7e | 1306 | struct mmc_host *mmc; |
abfbe5f7 JY |
1307 | int r; |
1308 | ||
1309 | mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev); | |
1310 | if (mmc == NULL) | |
1311 | return -ENOMEM; | |
1312 | ||
1313 | slot = mmc_priv(mmc); | |
1314 | slot->host = host; | |
1315 | slot->mmc = mmc; | |
1316 | slot->id = id; | |
1317 | slot->pdata = &host->pdata->slots[id]; | |
1318 | ||
1319 | host->slots[id] = slot; | |
1320 | ||
23af6039 | 1321 | mmc->caps = 0; |
90c62bf0 | 1322 | if (host->pdata->slots[id].wires >= 4) |
abfbe5f7 JY |
1323 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
1324 | ||
1325 | mmc->ops = &mmc_omap_ops; | |
1326 | mmc->f_min = 400000; | |
1327 | ||
1328 | if (cpu_class_is_omap2()) | |
1329 | mmc->f_max = 48000000; | |
1330 | else | |
1331 | mmc->f_max = 24000000; | |
1332 | if (host->pdata->max_freq) | |
1333 | mmc->f_max = min(host->pdata->max_freq, mmc->f_max); | |
1334 | mmc->ocr_avail = slot->pdata->ocr_mask; | |
1335 | ||
1336 | /* Use scatterlist DMA to reduce per-transfer costs. | |
1337 | * NOTE max_seg_size assumption that small blocks aren't | |
1338 | * normally used (except e.g. for reading SD registers). | |
1339 | */ | |
a36274e0 | 1340 | mmc->max_segs = 32; |
abfbe5f7 JY |
1341 | mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */ |
1342 | mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */ | |
1343 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; | |
1344 | mmc->max_seg_size = mmc->max_req_size; | |
1345 | ||
1346 | r = mmc_add_host(mmc); | |
1347 | if (r < 0) | |
1348 | goto err_remove_host; | |
1349 | ||
1350 | if (slot->pdata->name != NULL) { | |
1351 | r = device_create_file(&mmc->class_dev, | |
1352 | &dev_attr_slot_name); | |
1353 | if (r < 0) | |
1354 | goto err_remove_host; | |
1355 | } | |
1356 | ||
5a0f3f1f JY |
1357 | if (slot->pdata->get_cover_state != NULL) { |
1358 | r = device_create_file(&mmc->class_dev, | |
1359 | &dev_attr_cover_switch); | |
1360 | if (r < 0) | |
1361 | goto err_remove_slot_name; | |
1362 | ||
7584d276 JL |
1363 | setup_timer(&slot->cover_timer, mmc_omap_cover_timer, |
1364 | (unsigned long)slot); | |
1365 | tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler, | |
1366 | (unsigned long)slot); | |
1367 | tasklet_schedule(&slot->cover_tasklet); | |
5a0f3f1f JY |
1368 | } |
1369 | ||
abfbe5f7 JY |
1370 | return 0; |
1371 | ||
5a0f3f1f JY |
1372 | err_remove_slot_name: |
1373 | if (slot->pdata->name != NULL) | |
1374 | device_remove_file(&mmc->class_dev, &dev_attr_slot_name); | |
abfbe5f7 JY |
1375 | err_remove_host: |
1376 | mmc_remove_host(mmc); | |
1377 | mmc_free_host(mmc); | |
1378 | return r; | |
1379 | } | |
1380 | ||
1381 | static void mmc_omap_remove_slot(struct mmc_omap_slot *slot) | |
1382 | { | |
1383 | struct mmc_host *mmc = slot->mmc; | |
1384 | ||
1385 | if (slot->pdata->name != NULL) | |
1386 | device_remove_file(&mmc->class_dev, &dev_attr_slot_name); | |
5a0f3f1f JY |
1387 | if (slot->pdata->get_cover_state != NULL) |
1388 | device_remove_file(&mmc->class_dev, &dev_attr_cover_switch); | |
1389 | ||
7584d276 JL |
1390 | tasklet_kill(&slot->cover_tasklet); |
1391 | del_timer_sync(&slot->cover_timer); | |
b01a4f1c | 1392 | flush_workqueue(slot->host->mmc_omap_wq); |
abfbe5f7 JY |
1393 | |
1394 | mmc_remove_host(mmc); | |
1395 | mmc_free_host(mmc); | |
1396 | } | |
1397 | ||
b6e0703b | 1398 | static int __devinit mmc_omap_probe(struct platform_device *pdev) |
abfbe5f7 JY |
1399 | { |
1400 | struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; | |
730c9b7e | 1401 | struct mmc_omap_host *host = NULL; |
81ca7034 | 1402 | struct resource *res; |
abfbe5f7 | 1403 | int i, ret = 0; |
ce9c1a83 | 1404 | int irq; |
81ca7034 | 1405 | |
abfbe5f7 | 1406 | if (pdata == NULL) { |
81ca7034 JY |
1407 | dev_err(&pdev->dev, "platform data missing\n"); |
1408 | return -ENXIO; | |
1409 | } | |
abfbe5f7 JY |
1410 | if (pdata->nr_slots == 0) { |
1411 | dev_err(&pdev->dev, "no slots\n"); | |
1412 | return -ENXIO; | |
1413 | } | |
81ca7034 JY |
1414 | |
1415 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
ce9c1a83 | 1416 | irq = platform_get_irq(pdev, 0); |
81ca7034 | 1417 | if (res == NULL || irq < 0) |
ce9c1a83 | 1418 | return -ENXIO; |
730c9b7e | 1419 | |
2092014d | 1420 | res = request_mem_region(res->start, resource_size(res), |
abfbe5f7 | 1421 | pdev->name); |
81ca7034 | 1422 | if (res == NULL) |
730c9b7e | 1423 | return -EBUSY; |
730c9b7e | 1424 | |
abfbe5f7 JY |
1425 | host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL); |
1426 | if (host == NULL) { | |
730c9b7e | 1427 | ret = -ENOMEM; |
81ca7034 | 1428 | goto err_free_mem_region; |
730c9b7e CA |
1429 | } |
1430 | ||
0f602ec7 JL |
1431 | INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work); |
1432 | INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work); | |
1433 | ||
0fb4723d JL |
1434 | INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command); |
1435 | setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer, | |
1436 | (unsigned long) host); | |
eb1860bc | 1437 | |
0807a9b5 JL |
1438 | spin_lock_init(&host->clk_lock); |
1439 | setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host); | |
1440 | ||
730c9b7e | 1441 | spin_lock_init(&host->dma_lock); |
01e77e13 | 1442 | setup_timer(&host->dma_timer, mmc_omap_dma_timer, (unsigned long) host); |
abfbe5f7 JY |
1443 | spin_lock_init(&host->slot_lock); |
1444 | init_waitqueue_head(&host->slot_wq); | |
1445 | ||
abfbe5f7 JY |
1446 | host->pdata = pdata; |
1447 | host->dev = &pdev->dev; | |
1448 | platform_set_drvdata(pdev, host); | |
1449 | ||
730c9b7e | 1450 | host->id = pdev->id; |
81ca7034 | 1451 | host->mem_res = res; |
ce9c1a83 | 1452 | host->irq = irq; |
730c9b7e | 1453 | |
abfbe5f7 | 1454 | host->use_dma = 1; |
d8874665 | 1455 | host->dev->dma_mask = &pdata->dma_mask; |
abfbe5f7 JY |
1456 | host->dma_ch = -1; |
1457 | ||
1458 | host->irq = irq; | |
1459 | host->phys_base = host->mem_res->start; | |
2092014d | 1460 | host->virt_base = ioremap(res->start, resource_size(res)); |
55c381e4 RK |
1461 | if (!host->virt_base) |
1462 | goto err_ioremap; | |
abfbe5f7 | 1463 | |
d4a36645 | 1464 | host->iclk = clk_get(&pdev->dev, "ick"); |
e799acb2 LM |
1465 | if (IS_ERR(host->iclk)) { |
1466 | ret = PTR_ERR(host->iclk); | |
d4a36645 | 1467 | goto err_free_mmc_host; |
e799acb2 | 1468 | } |
d4a36645 | 1469 | clk_enable(host->iclk); |
730c9b7e | 1470 | |
5c9e02b1 | 1471 | host->fclk = clk_get(&pdev->dev, "fck"); |
730c9b7e CA |
1472 | if (IS_ERR(host->fclk)) { |
1473 | ret = PTR_ERR(host->fclk); | |
81ca7034 | 1474 | goto err_free_iclk; |
730c9b7e CA |
1475 | } |
1476 | ||
abfbe5f7 JY |
1477 | ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host); |
1478 | if (ret) | |
1479 | goto err_free_fclk; | |
42431acb | 1480 | |
abfbe5f7 JY |
1481 | if (pdata->init != NULL) { |
1482 | ret = pdata->init(&pdev->dev); | |
1483 | if (ret < 0) | |
1484 | goto err_free_irq; | |
1485 | } | |
730c9b7e | 1486 | |
abfbe5f7 | 1487 | host->nr_slots = pdata->nr_slots; |
ebbe6f88 | 1488 | host->reg_shift = (cpu_is_omap7xx() ? 1 : 2); |
3caf4140 TL |
1489 | |
1490 | host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0); | |
1491 | if (!host->mmc_omap_wq) | |
1492 | goto err_plat_cleanup; | |
1493 | ||
abfbe5f7 JY |
1494 | for (i = 0; i < pdata->nr_slots; i++) { |
1495 | ret = mmc_omap_new_slot(host, i); | |
1496 | if (ret < 0) { | |
1497 | while (--i >= 0) | |
1498 | mmc_omap_remove_slot(host->slots[i]); | |
730c9b7e | 1499 | |
3caf4140 | 1500 | goto err_destroy_wq; |
730c9b7e | 1501 | } |
730c9b7e CA |
1502 | } |
1503 | ||
730c9b7e CA |
1504 | return 0; |
1505 | ||
3caf4140 TL |
1506 | err_destroy_wq: |
1507 | destroy_workqueue(host->mmc_omap_wq); | |
abfbe5f7 JY |
1508 | err_plat_cleanup: |
1509 | if (pdata->cleanup) | |
1510 | pdata->cleanup(&pdev->dev); | |
1511 | err_free_irq: | |
1512 | free_irq(host->irq, host); | |
81ca7034 JY |
1513 | err_free_fclk: |
1514 | clk_put(host->fclk); | |
1515 | err_free_iclk: | |
e799acb2 LM |
1516 | clk_disable(host->iclk); |
1517 | clk_put(host->iclk); | |
81ca7034 | 1518 | err_free_mmc_host: |
55c381e4 RK |
1519 | iounmap(host->virt_base); |
1520 | err_ioremap: | |
abfbe5f7 | 1521 | kfree(host); |
81ca7034 | 1522 | err_free_mem_region: |
2092014d | 1523 | release_mem_region(res->start, resource_size(res)); |
730c9b7e CA |
1524 | return ret; |
1525 | } | |
1526 | ||
b6e0703b | 1527 | static int __devexit mmc_omap_remove(struct platform_device *pdev) |
730c9b7e CA |
1528 | { |
1529 | struct mmc_omap_host *host = platform_get_drvdata(pdev); | |
abfbe5f7 | 1530 | int i; |
730c9b7e CA |
1531 | |
1532 | platform_set_drvdata(pdev, NULL); | |
1533 | ||
81ca7034 JY |
1534 | BUG_ON(host == NULL); |
1535 | ||
abfbe5f7 JY |
1536 | for (i = 0; i < host->nr_slots; i++) |
1537 | mmc_omap_remove_slot(host->slots[i]); | |
1538 | ||
1539 | if (host->pdata->cleanup) | |
1540 | host->pdata->cleanup(&pdev->dev); | |
81ca7034 | 1541 | |
d4a36645 | 1542 | mmc_omap_fclk_enable(host, 0); |
49c1d9da | 1543 | free_irq(host->irq, host); |
d4a36645 RK |
1544 | clk_put(host->fclk); |
1545 | clk_disable(host->iclk); | |
1546 | clk_put(host->iclk); | |
730c9b7e | 1547 | |
55c381e4 | 1548 | iounmap(host->virt_base); |
730c9b7e | 1549 | release_mem_region(pdev->resource[0].start, |
81ca7034 | 1550 | pdev->resource[0].end - pdev->resource[0].start + 1); |
b01a4f1c | 1551 | destroy_workqueue(host->mmc_omap_wq); |
81ca7034 | 1552 | |
abfbe5f7 | 1553 | kfree(host); |
730c9b7e CA |
1554 | |
1555 | return 0; | |
1556 | } | |
1557 | ||
1558 | #ifdef CONFIG_PM | |
1559 | static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg) | |
1560 | { | |
abfbe5f7 | 1561 | int i, ret = 0; |
730c9b7e CA |
1562 | struct mmc_omap_host *host = platform_get_drvdata(pdev); |
1563 | ||
abfbe5f7 | 1564 | if (host == NULL || host->suspended) |
730c9b7e CA |
1565 | return 0; |
1566 | ||
abfbe5f7 JY |
1567 | for (i = 0; i < host->nr_slots; i++) { |
1568 | struct mmc_omap_slot *slot; | |
1569 | ||
1570 | slot = host->slots[i]; | |
1a13f8fa | 1571 | ret = mmc_suspend_host(slot->mmc); |
abfbe5f7 JY |
1572 | if (ret < 0) { |
1573 | while (--i >= 0) { | |
1574 | slot = host->slots[i]; | |
1575 | mmc_resume_host(slot->mmc); | |
1576 | } | |
1577 | return ret; | |
1578 | } | |
730c9b7e | 1579 | } |
abfbe5f7 JY |
1580 | host->suspended = 1; |
1581 | return 0; | |
730c9b7e CA |
1582 | } |
1583 | ||
1584 | static int mmc_omap_resume(struct platform_device *pdev) | |
1585 | { | |
abfbe5f7 | 1586 | int i, ret = 0; |
730c9b7e CA |
1587 | struct mmc_omap_host *host = platform_get_drvdata(pdev); |
1588 | ||
abfbe5f7 | 1589 | if (host == NULL || !host->suspended) |
730c9b7e CA |
1590 | return 0; |
1591 | ||
abfbe5f7 JY |
1592 | for (i = 0; i < host->nr_slots; i++) { |
1593 | struct mmc_omap_slot *slot; | |
1594 | slot = host->slots[i]; | |
1595 | ret = mmc_resume_host(slot->mmc); | |
1596 | if (ret < 0) | |
1597 | return ret; | |
730c9b7e | 1598 | |
abfbe5f7 JY |
1599 | host->suspended = 0; |
1600 | } | |
1601 | return 0; | |
730c9b7e CA |
1602 | } |
1603 | #else | |
1604 | #define mmc_omap_suspend NULL | |
1605 | #define mmc_omap_resume NULL | |
1606 | #endif | |
1607 | ||
1608 | static struct platform_driver mmc_omap_driver = { | |
b6e0703b V |
1609 | .probe = mmc_omap_probe, |
1610 | .remove = __devexit_p(mmc_omap_remove), | |
730c9b7e CA |
1611 | .suspend = mmc_omap_suspend, |
1612 | .resume = mmc_omap_resume, | |
1613 | .driver = { | |
1614 | .name = DRIVER_NAME, | |
bc65c724 | 1615 | .owner = THIS_MODULE, |
730c9b7e CA |
1616 | }, |
1617 | }; | |
1618 | ||
680f1b5b | 1619 | module_platform_driver(mmc_omap_driver); |
730c9b7e CA |
1620 | MODULE_DESCRIPTION("OMAP Multimedia Card driver"); |
1621 | MODULE_LICENSE("GPL"); | |
bc65c724 | 1622 | MODULE_ALIAS("platform:" DRIVER_NAME); |
d36b6910 | 1623 | MODULE_AUTHOR("Juha Yrjölä"); |