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Merge tag 'omap-devel-am33xx-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / drivers / mmc / host / omap.c
CommitLineData
730c9b7e 1/*
70f10482 2 * linux/drivers/mmc/host/omap.c
730c9b7e
CA		 3 *
4 * Copyright (C) 2004 Nokia Corporation
d36b6910 5 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
730c9b7e
CA		 6 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
7 * Other hacks (DMA, SD, etc) by David Brownell
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
730c9b7e
CA		 14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/ioport.h>
18#include <linux/platform_device.h>
19#include <linux/interrupt.h>
3451c067 20#include <linux/dmaengine.h>
730c9b7e
CA		 21#include <linux/dma-mapping.h>
22#include <linux/delay.h>
23#include <linux/spinlock.h>
24#include <linux/timer.h>
3451c067 25#include <linux/omap-dma.h>
730c9b7e 26#include <linux/mmc/host.h>
730c9b7e
CA		 27#include <linux/mmc/card.h>
28#include <linux/clk.h>
45711f1a 29#include <linux/scatterlist.h>
6d16bfb5 30#include <linux/i2c/tps65010.h>
5a0e3ad6 31#include <linux/slab.h>
730c9b7e
CA		 32
33#include <asm/io.h>
34#include <asm/irq.h>
730c9b7e 35
ce491cf8 36#include <plat/mmc.h>
1bc857f7 37#include <asm/gpio.h>
ce491cf8
TL		 38#include <plat/dma.h>
39#include <plat/mux.h>
40#include <plat/fpga.h>
730c9b7e 41
0551f4df 42#define OMAP_MMC_REG_CMD 0x00
0e950fa6
MB		 43#define OMAP_MMC_REG_ARGL 0x01
44#define OMAP_MMC_REG_ARGH 0x02
45#define OMAP_MMC_REG_CON 0x03
46#define OMAP_MMC_REG_STAT 0x04
47#define OMAP_MMC_REG_IE 0x05
48#define OMAP_MMC_REG_CTO 0x06
49#define OMAP_MMC_REG_DTO 0x07
50#define OMAP_MMC_REG_DATA 0x08
51#define OMAP_MMC_REG_BLEN 0x09
52#define OMAP_MMC_REG_NBLK 0x0a
53#define OMAP_MMC_REG_BUF 0x0b
54#define OMAP_MMC_REG_SDIO 0x0d
55#define OMAP_MMC_REG_REV 0x0f
56#define OMAP_MMC_REG_RSP0 0x10
57#define OMAP_MMC_REG_RSP1 0x11
58#define OMAP_MMC_REG_RSP2 0x12
59#define OMAP_MMC_REG_RSP3 0x13
60#define OMAP_MMC_REG_RSP4 0x14
61#define OMAP_MMC_REG_RSP5 0x15
62#define OMAP_MMC_REG_RSP6 0x16
63#define OMAP_MMC_REG_RSP7 0x17
64#define OMAP_MMC_REG_IOSR 0x18
65#define OMAP_MMC_REG_SYSC 0x19
66#define OMAP_MMC_REG_SYSS 0x1a
0551f4df
JY		 67
68#define OMAP_MMC_STAT_CARD_ERR (1 << 14)
69#define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
70#define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
71#define OMAP_MMC_STAT_A_EMPTY (1 << 11)
72#define OMAP_MMC_STAT_A_FULL (1 << 10)
73#define OMAP_MMC_STAT_CMD_CRC (1 << 8)
74#define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
75#define OMAP_MMC_STAT_DATA_CRC (1 << 6)
76#define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
77#define OMAP_MMC_STAT_END_BUSY (1 << 4)
78#define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
79#define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
80#define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
81
0e950fa6
MB		 82#define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift)
83#define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))
84#define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
0551f4df
JY		 85
86/*
87 * Command types
88 */
89#define OMAP_MMC_CMDTYPE_BC 0
90#define OMAP_MMC_CMDTYPE_BCR 1
91#define OMAP_MMC_CMDTYPE_AC 2
92#define OMAP_MMC_CMDTYPE_ADTC 3
93
730c9b7e
CA		 94
95#define DRIVER_NAME "mmci-omap"
730c9b7e
CA		 96
97/* Specifies how often in millisecs to poll for card status changes
98 * when the cover switch is open */
7584d276 99#define OMAP_MMC_COVER_POLL_DELAY 500
730c9b7e 100
abfbe5f7
JY		 101struct mmc_omap_host;
102
103struct mmc_omap_slot {
104 int id;
105 unsigned int vdd;
106 u16 saved_con;
107 u16 bus_mode;
108 unsigned int fclk_freq;
109 unsigned powered:1;
110
7584d276
JL		 111 struct tasklet_struct cover_tasklet;
112 struct timer_list cover_timer;
5a0f3f1f
JY		 113 unsigned cover_open;
114
abfbe5f7
JY		 115 struct mmc_request *mrq;
116 struct mmc_omap_host *host;
117 struct mmc_host *mmc;
118 struct omap_mmc_slot_data *pdata;
119};
120
730c9b7e
CA		 121struct mmc_omap_host {
122 int initialized;
123 int suspended;
124 struct mmc_request * mrq;
125 struct mmc_command * cmd;
126 struct mmc_data * data;
127 struct mmc_host * mmc;
128 struct device * dev;
129 unsigned char id; /* 16xx chips have 2 MMC blocks */
130 struct clk * iclk;
131 struct clk * fclk;
3451c067
RK		 132 struct dma_chan *dma_rx;
133 u32 dma_rx_burst;
134 struct dma_chan *dma_tx;
135 u32 dma_tx_burst;
89783b1e
JY		 136 struct resource *mem_res;
137 void __iomem *virt_base;
138 unsigned int phys_base;
730c9b7e
CA		 139 int irq;
140 unsigned char bus_mode;
141 unsigned char hw_bus_mode;
0e950fa6 142 unsigned int reg_shift;
730c9b7e 143
0fb4723d
JL		 144 struct work_struct cmd_abort_work;
145 unsigned abort:1;
146 struct timer_list cmd_abort_timer;
eb1860bc 147
0f602ec7
JL		 148 struct work_struct slot_release_work;
149 struct mmc_omap_slot *next_slot;
150 struct work_struct send_stop_work;
151 struct mmc_data *stop_data;
152
730c9b7e
CA		 153 unsigned int sg_len;
154 int sg_idx;
155 u16 * buffer;
156 u32 buffer_bytes_left;
157 u32 total_bytes_left;
158
159 unsigned use_dma:1;
160 unsigned brs_received:1, dma_done:1;
730c9b7e 161 unsigned dma_in_use:1;
3451c067 162 spinlock_t dma_lock;
730c9b7e 163
abfbe5f7
JY		 164 struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS];
165 struct mmc_omap_slot *current_slot;
166 spinlock_t slot_lock;
167 wait_queue_head_t slot_wq;
168 int nr_slots;
169
0807a9b5
JL		 170 struct timer_list clk_timer;
171 spinlock_t clk_lock; /* for changing enabled state */
172 unsigned int fclk_enabled:1;
b01a4f1c 173 struct workqueue_struct *mmc_omap_wq;
0807a9b5 174
abfbe5f7 175 struct omap_mmc_platform_data *pdata;
730c9b7e
CA		 176};
177
0d9ee5b2 178
7c8ad982 179static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
0807a9b5
JL		 180{
181 unsigned long tick_ns;
182
183 if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
184 tick_ns = (1000000000 + slot->fclk_freq - 1) / slot->fclk_freq;
185 ndelay(8 * tick_ns);
186 }
187}
188
7c8ad982 189static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
0807a9b5
JL		 190{
191 unsigned long flags;
192
193 spin_lock_irqsave(&host->clk_lock, flags);
194 if (host->fclk_enabled != enable) {
195 host->fclk_enabled = enable;
196 if (enable)
197 clk_enable(host->fclk);
198 else
199 clk_disable(host->fclk);
200 }
201 spin_unlock_irqrestore(&host->clk_lock, flags);
202}
203
abfbe5f7
JY		 204static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
205{
206 struct mmc_omap_host *host = slot->host;
207 unsigned long flags;
208
209 if (claimed)
210 goto no_claim;
211 spin_lock_irqsave(&host->slot_lock, flags);
212 while (host->mmc != NULL) {
213 spin_unlock_irqrestore(&host->slot_lock, flags);
214 wait_event(host->slot_wq, host->mmc == NULL);
215 spin_lock_irqsave(&host->slot_lock, flags);
216 }
217 host->mmc = slot->mmc;
218 spin_unlock_irqrestore(&host->slot_lock, flags);
219no_claim:
0807a9b5
JL		 220 del_timer(&host->clk_timer);
221 if (host->current_slot != slot || !claimed)
222 mmc_omap_fclk_offdelay(host->current_slot);
223
abfbe5f7 224 if (host->current_slot != slot) {
0807a9b5 225 OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
abfbe5f7
JY		 226 if (host->pdata->switch_slot != NULL)
227 host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
228 host->current_slot = slot;
229 }
230
0807a9b5
JL		 231 if (claimed) {
232 mmc_omap_fclk_enable(host, 1);
233
234 /* Doing the dummy read here seems to work around some bug
235 * at least in OMAP24xx silicon where the command would not
236 * start after writing the CMD register. Sigh. */
237 OMAP_MMC_READ(host, CON);
abfbe5f7 238
0807a9b5
JL		 239 OMAP_MMC_WRITE(host, CON, slot->saved_con);
240 } else
241 mmc_omap_fclk_enable(host, 0);
abfbe5f7
JY		 242}
243
244static void mmc_omap_start_request(struct mmc_omap_host *host,
245 struct mmc_request *req);
246
0f602ec7
JL		 247static void mmc_omap_slot_release_work(struct work_struct *work)
248{
249 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
250 slot_release_work);
251 struct mmc_omap_slot *next_slot = host->next_slot;
252 struct mmc_request *rq;
253
254 host->next_slot = NULL;
255 mmc_omap_select_slot(next_slot, 1);
256
257 rq = next_slot->mrq;
258 next_slot->mrq = NULL;
259 mmc_omap_start_request(host, rq);
260}
261
0807a9b5 262static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
abfbe5f7
JY		 263{
264 struct mmc_omap_host *host = slot->host;
265 unsigned long flags;
266 int i;
267
268 BUG_ON(slot == NULL || host->mmc == NULL);
0807a9b5
JL		 269
270 if (clk_enabled)
271 /* Keeps clock running for at least 8 cycles on valid freq */
272 mod_timer(&host->clk_timer, jiffies + HZ/10);
273 else {
274 del_timer(&host->clk_timer);
275 mmc_omap_fclk_offdelay(slot);
276 mmc_omap_fclk_enable(host, 0);
277 }
abfbe5f7
JY		 278
279 spin_lock_irqsave(&host->slot_lock, flags);
280 /* Check for any pending requests */
281 for (i = 0; i < host->nr_slots; i++) {
282 struct mmc_omap_slot *new_slot;
abfbe5f7
JY		 283
284 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
285 continue;
286
0f602ec7 287 BUG_ON(host->next_slot != NULL);
abfbe5f7
JY		 288 new_slot = host->slots[i];
289 /* The current slot should not have a request in queue */
290 BUG_ON(new_slot == host->current_slot);
291
0f602ec7 292 host->next_slot = new_slot;
abfbe5f7
JY		 293 host->mmc = new_slot->mmc;
294 spin_unlock_irqrestore(&host->slot_lock, flags);
b01a4f1c 295 queue_work(host->mmc_omap_wq, &host->slot_release_work);
abfbe5f7
JY		 296 return;
297 }
298
299 host->mmc = NULL;
300 wake_up(&host->slot_wq);
301 spin_unlock_irqrestore(&host->slot_lock, flags);
302}
303
5a0f3f1f
JY		 304static inline
305int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
306{
8348f002
KP		 307 if (slot->pdata->get_cover_state)
308 return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
309 slot->id);
310 return 0;
5a0f3f1f
JY		 311}
312
313static ssize_t
314mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
315 char *buf)
316{
317 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
318 struct mmc_omap_slot *slot = mmc_priv(mmc);
319
320 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
321 "closed");
322}
323
324static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
325
abfbe5f7
JY		 326static ssize_t
327mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
328 char *buf)
329{
330 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
331 struct mmc_omap_slot *slot = mmc_priv(mmc);
332
333 return sprintf(buf, "%s\n", slot->pdata->name);
334}
335
336static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
337
730c9b7e
CA		 338static void
339mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
340{
341 u32 cmdreg;
342 u32 resptype;
343 u32 cmdtype;
344
345 host->cmd = cmd;
346
347 resptype = 0;
348 cmdtype = 0;
349
350 /* Our hardware needs to know exact type */
1b3b2631
CEA		 351 switch (mmc_resp_type(cmd)) {
352 case MMC_RSP_NONE:
353 break;
354 case MMC_RSP_R1:
355 case MMC_RSP_R1B:
6f949909 356 /* resp 1, 1b, 6, 7 */
730c9b7e
CA		 357 resptype = 1;
358 break;
1b3b2631 359 case MMC_RSP_R2:
730c9b7e
CA		 360 resptype = 2;
361 break;
1b3b2631 362 case MMC_RSP_R3:
730c9b7e
CA		 363 resptype = 3;
364 break;
365 default:
1b3b2631 366 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
730c9b7e
CA		 367 break;
368 }
369
370 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
371 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
372 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
373 cmdtype = OMAP_MMC_CMDTYPE_BC;
374 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
375 cmdtype = OMAP_MMC_CMDTYPE_BCR;
376 } else {
377 cmdtype = OMAP_MMC_CMDTYPE_AC;
378 }
379
380 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
381
abfbe5f7 382 if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
730c9b7e
CA		 383 cmdreg |= 1 << 6;
384
385 if (cmd->flags & MMC_RSP_BUSY)
386 cmdreg |= 1 << 11;
387
388 if (host->data && !(host->data->flags & MMC_DATA_WRITE))
389 cmdreg |= 1 << 15;
390
0fb4723d 391 mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
eb1860bc 392
3342ee8b
JY		 393 OMAP_MMC_WRITE(host, CTO, 200);
394 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
395 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
396 OMAP_MMC_WRITE(host, IE,
730c9b7e
CA		 397 OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
398 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
399 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
400 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
401 OMAP_MMC_STAT_END_OF_DATA);
3342ee8b 402 OMAP_MMC_WRITE(host, CMD, cmdreg);
730c9b7e
CA		 403}
404
a914ded2
JY		 405static void
406mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
407 int abort)
408{
409 enum dma_data_direction dma_data_dir;
3451c067
RK		 410 struct device *dev = mmc_dev(host->mmc);
411 struct dma_chan *c;
a914ded2 412
3451c067 413 if (data->flags & MMC_DATA_WRITE) {
a914ded2 414 dma_data_dir = DMA_TO_DEVICE;
3451c067
RK		 415 c = host->dma_tx;
416 } else {
a914ded2 417 dma_data_dir = DMA_FROM_DEVICE;
3451c067
RK		 418 c = host->dma_rx;
419 }
420 if (c) {
421 if (data->error) {
422 dmaengine_terminate_all(c);
423 /* Claim nothing transferred on error... */
424 data->bytes_xfered = 0;
425 }
426 dev = c->device->dev;
427 }
428 dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir);
a914ded2
JY		 429}
430
0f602ec7
JL		 431static void mmc_omap_send_stop_work(struct work_struct *work)
432{
433 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
434 send_stop_work);
435 struct mmc_omap_slot *slot = host->current_slot;
436 struct mmc_data *data = host->stop_data;
437 unsigned long tick_ns;
438
439 tick_ns = (1000000000 + slot->fclk_freq - 1)/slot->fclk_freq;
440 ndelay(8*tick_ns);
441
442 mmc_omap_start_command(host, data->stop);
443}
444
730c9b7e
CA		 445static void
446mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
447{
a914ded2
JY		 448 if (host->dma_in_use)
449 mmc_omap_release_dma(host, data, data->error);
450
730c9b7e
CA		 451 host->data = NULL;
452 host->sg_len = 0;
730c9b7e
CA		 453
454 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
455 * dozens of requests until the card finishes writing data.
456 * It'd be cheaper to just wait till an EOFB interrupt arrives...
457 */
458
459 if (!data->stop) {
a914ded2
JY		 460 struct mmc_host *mmc;
461
730c9b7e 462 host->mrq = NULL;
a914ded2 463 mmc = host->mmc;
0807a9b5 464 mmc_omap_release_slot(host->current_slot, 1);
a914ded2 465 mmc_request_done(mmc, data->mrq);
730c9b7e
CA		 466 return;
467 }
468
0f602ec7 469 host->stop_data = data;
b01a4f1c 470 queue_work(host->mmc_omap_wq, &host->send_stop_work);
730c9b7e
CA		 471}
472
eb1860bc 473static void
0fb4723d 474mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
eb1860bc
JL		 475{
476 struct mmc_omap_slot *slot = host->current_slot;
477 unsigned int restarts, passes, timeout;
478 u16 stat = 0;
479
480 /* Sending abort takes 80 clocks. Have some extra and round up */
481 timeout = (120*1000000 + slot->fclk_freq - 1)/slot->fclk_freq;
482 restarts = 0;
0fb4723d 483 while (restarts < maxloops) {
eb1860bc
JL		 484 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
485 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
486
487 passes = 0;
488 while (passes < timeout) {
489 stat = OMAP_MMC_READ(host, STAT);
490 if (stat & OMAP_MMC_STAT_END_OF_CMD)
491 goto out;
492 udelay(1);
493 passes++;
494 }
495
496 restarts++;
497 }
498out:
499 OMAP_MMC_WRITE(host, STAT, stat);
500}
501
a914ded2
JY		 502static void
503mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
504{
a914ded2
JY		 505 if (host->dma_in_use)
506 mmc_omap_release_dma(host, data, 1);
507
508 host->data = NULL;
509 host->sg_len = 0;
510
0fb4723d 511 mmc_omap_send_abort(host, 10000);
a914ded2
JY		 512}
513
730c9b7e
CA		 514static void
515mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
516{
517 unsigned long flags;
518 int done;
519
520 if (!host->dma_in_use) {
521 mmc_omap_xfer_done(host, data);
522 return;
523 }
524 done = 0;
525 spin_lock_irqsave(&host->dma_lock, flags);
526 if (host->dma_done)
527 done = 1;
528 else
529 host->brs_received = 1;
530 spin_unlock_irqrestore(&host->dma_lock, flags);
531 if (done)
532 mmc_omap_xfer_done(host, data);
533}
534
730c9b7e
CA		 535static void
536mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
537{
538 unsigned long flags;
539 int done;
540
541 done = 0;
542 spin_lock_irqsave(&host->dma_lock, flags);
543 if (host->brs_received)
544 done = 1;
545 else
546 host->dma_done = 1;
547 spin_unlock_irqrestore(&host->dma_lock, flags);
548 if (done)
549 mmc_omap_xfer_done(host, data);
550}
551
552static void
553mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
554{
555 host->cmd = NULL;
556
0fb4723d 557 del_timer(&host->cmd_abort_timer);
eb1860bc 558
730c9b7e
CA		 559 if (cmd->flags & MMC_RSP_PRESENT) {
560 if (cmd->flags & MMC_RSP_136) {
561 /* response type 2 */
562 cmd->resp[3] =
3342ee8b
JY		 563 OMAP_MMC_READ(host, RSP0) |
564 (OMAP_MMC_READ(host, RSP1) << 16);
730c9b7e 565 cmd->resp[2] =
3342ee8b
JY		 566 OMAP_MMC_READ(host, RSP2) |
567 (OMAP_MMC_READ(host, RSP3) << 16);
730c9b7e 568 cmd->resp[1] =
3342ee8b
JY		 569 OMAP_MMC_READ(host, RSP4) |
570 (OMAP_MMC_READ(host, RSP5) << 16);
730c9b7e 571 cmd->resp[0] =
3342ee8b
JY		 572 OMAP_MMC_READ(host, RSP6) |
573 (OMAP_MMC_READ(host, RSP7) << 16);
730c9b7e
CA		 574 } else {
575 /* response types 1, 1b, 3, 4, 5, 6 */
576 cmd->resp[0] =
3342ee8b
JY		 577 OMAP_MMC_READ(host, RSP6) |
578 (OMAP_MMC_READ(host, RSP7) << 16);
730c9b7e
CA		 579 }
580 }
581
17b0429d 582 if (host->data == NULL || cmd->error) {
a914ded2
JY		 583 struct mmc_host *mmc;
584
585 if (host->data != NULL)
586 mmc_omap_abort_xfer(host, host->data);
730c9b7e 587 host->mrq = NULL;
a914ded2 588 mmc = host->mmc;
0807a9b5 589 mmc_omap_release_slot(host->current_slot, 1);
a914ded2 590 mmc_request_done(mmc, cmd->mrq);
730c9b7e
CA		 591 }
592}
593
eb1860bc
JL		 594/*
595 * Abort stuck command. Can occur when card is removed while it is being
596 * read.
597 */
598static void mmc_omap_abort_command(struct work_struct *work)
599{
600 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
0fb4723d
JL		 601 cmd_abort_work);
602 BUG_ON(!host->cmd);
eb1860bc
JL		 603
604 dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
605 host->cmd->opcode);
606
0fb4723d
JL		 607 if (host->cmd->error == 0)
608 host->cmd->error = -ETIMEDOUT;
eb1860bc 609
0fb4723d
JL		 610 if (host->data == NULL) {
611 struct mmc_command *cmd;
612 struct mmc_host *mmc;
613
614 cmd = host->cmd;
615 host->cmd = NULL;
616 mmc_omap_send_abort(host, 10000);
617
618 host->mrq = NULL;
619 mmc = host->mmc;
0807a9b5 620 mmc_omap_release_slot(host->current_slot, 1);
0fb4723d
JL		 621 mmc_request_done(mmc, cmd->mrq);
622 } else
623 mmc_omap_cmd_done(host, host->cmd);
eb1860bc 624
0fb4723d
JL		 625 host->abort = 0;
626 enable_irq(host->irq);
eb1860bc
JL		 627}
628
629static void
630mmc_omap_cmd_timer(unsigned long data)
631{
632 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
0fb4723d 633 unsigned long flags;
eb1860bc 634
0fb4723d
JL		 635 spin_lock_irqsave(&host->slot_lock, flags);
636 if (host->cmd != NULL && !host->abort) {
637 OMAP_MMC_WRITE(host, IE, 0);
638 disable_irq(host->irq);
639 host->abort = 1;
b01a4f1c 640 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
0fb4723d
JL		 641 }
642 spin_unlock_irqrestore(&host->slot_lock, flags);
eb1860bc
JL		 643}
644
730c9b7e
CA		 645/* PIO only */
646static void
647mmc_omap_sg_to_buf(struct mmc_omap_host *host)
648{
649 struct scatterlist *sg;
650
651 sg = host->data->sg + host->sg_idx;
652 host->buffer_bytes_left = sg->length;
45711f1a 653 host->buffer = sg_virt(sg);
730c9b7e
CA		 654 if (host->buffer_bytes_left > host->total_bytes_left)
655 host->buffer_bytes_left = host->total_bytes_left;
656}
657
0807a9b5
JL		 658static void
659mmc_omap_clk_timer(unsigned long data)
660{
661 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
662
663 mmc_omap_fclk_enable(host, 0);
664}
665
730c9b7e
CA		 666/* PIO only */
667static void
668mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
669{
75b53aee 670 int n, nwords;
730c9b7e
CA		 671
672 if (host->buffer_bytes_left == 0) {
673 host->sg_idx++;
674 BUG_ON(host->sg_idx == host->sg_len);
675 mmc_omap_sg_to_buf(host);
676 }
677 n = 64;
678 if (n > host->buffer_bytes_left)
679 n = host->buffer_bytes_left;
75b53aee
PW		 680
681 nwords = n / 2;
682 nwords += n & 1; /* handle odd number of bytes to transfer */
683
730c9b7e
CA		 684 host->buffer_bytes_left -= n;
685 host->total_bytes_left -= n;
686 host->data->bytes_xfered += n;
687
688 if (write) {
75b53aee
PW		 689 __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA),
690 host->buffer, nwords);
730c9b7e 691 } else {
75b53aee
PW		 692 __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA),
693 host->buffer, nwords);
730c9b7e 694 }
75b53aee
PW		 695
696 host->buffer += nwords;
730c9b7e
CA		 697}
698
699static inline void mmc_omap_report_irq(u16 status)
700{
701 static const char *mmc_omap_status_bits[] = {
702 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
703 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
704 };
705 int i, c = 0;
706
707 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
708 if (status & (1 << i)) {
709 if (c)
710 printk(" ");
711 printk("%s", mmc_omap_status_bits[i]);
712 c++;
713 }
714}
715
7d12e780 716static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
730c9b7e
CA		 717{
718 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
719 u16 status;
720 int end_command;
721 int end_transfer;
2a50b888 722 int transfer_error, cmd_error;
730c9b7e
CA		 723
724 if (host->cmd == NULL && host->data == NULL) {
3342ee8b 725 status = OMAP_MMC_READ(host, STAT);
2a50b888
JY		 726 dev_info(mmc_dev(host->slots[0]->mmc),
727 "Spurious IRQ 0x%04x\n", status);
730c9b7e 728 if (status != 0) {
3342ee8b
JY		 729 OMAP_MMC_WRITE(host, STAT, status);
730 OMAP_MMC_WRITE(host, IE, 0);
730c9b7e
CA		 731 }
732 return IRQ_HANDLED;
733 }
734
735 end_command = 0;
736 end_transfer = 0;
737 transfer_error = 0;
2a50b888 738 cmd_error = 0;
730c9b7e 739
3342ee8b 740 while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
2a50b888
JY		 741 int cmd;
742
3342ee8b 743 OMAP_MMC_WRITE(host, STAT, status);
2a50b888
JY		 744 if (host->cmd != NULL)
745 cmd = host->cmd->opcode;
746 else
747 cmd = -1;
730c9b7e
CA		 748#ifdef CONFIG_MMC_DEBUG
749 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
2a50b888 750 status, cmd);
730c9b7e
CA		 751 mmc_omap_report_irq(status);
752 printk("\n");
753#endif
754 if (host->total_bytes_left) {
755 if ((status & OMAP_MMC_STAT_A_FULL) ||
756 (status & OMAP_MMC_STAT_END_OF_DATA))
757 mmc_omap_xfer_data(host, 0);
758 if (status & OMAP_MMC_STAT_A_EMPTY)
759 mmc_omap_xfer_data(host, 1);
760 }
761
2a50b888 762 if (status & OMAP_MMC_STAT_END_OF_DATA)
730c9b7e 763 end_transfer = 1;
730c9b7e
CA		 764
765 if (status & OMAP_MMC_STAT_DATA_TOUT) {
2a50b888
JY		 766 dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
767 cmd);
730c9b7e 768 if (host->data) {
17b0429d 769 host->data->error = -ETIMEDOUT;
730c9b7e
CA		 770 transfer_error = 1;
771 }
772 }
773
774 if (status & OMAP_MMC_STAT_DATA_CRC) {
775 if (host->data) {
17b0429d 776 host->data->error = -EILSEQ;
730c9b7e
CA		 777 dev_dbg(mmc_dev(host->mmc),
778 "data CRC error, bytes left %d\n",
779 host->total_bytes_left);
780 transfer_error = 1;
781 } else {
782 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
783 }
784 }
785
786 if (status & OMAP_MMC_STAT_CMD_TOUT) {
787 /* Timeouts are routine with some commands */
788 if (host->cmd) {
abfbe5f7
JY		 789 struct mmc_omap_slot *slot =
790 host->current_slot;
2a50b888
JY		 791 if (slot == NULL ||
792 !mmc_omap_cover_is_open(slot))
5a0f3f1f 793 dev_err(mmc_dev(host->mmc),
2a50b888
JY		 794 "command timeout (CMD%d)\n",
795 cmd);
17b0429d 796 host->cmd->error = -ETIMEDOUT;
730c9b7e 797 end_command = 1;
2a50b888 798 cmd_error = 1;
730c9b7e
CA		 799 }
800 }
801
802 if (status & OMAP_MMC_STAT_CMD_CRC) {
803 if (host->cmd) {
804 dev_err(mmc_dev(host->mmc),
805 "command CRC error (CMD%d, arg 0x%08x)\n",
2a50b888 806 cmd, host->cmd->arg);
17b0429d 807 host->cmd->error = -EILSEQ;
730c9b7e 808 end_command = 1;
2a50b888 809 cmd_error = 1;
730c9b7e
CA		 810 } else
811 dev_err(mmc_dev(host->mmc),
812 "command CRC error without cmd?\n");
813 }
814
815 if (status & OMAP_MMC_STAT_CARD_ERR) {
0107a4b3
RM		 816 dev_dbg(mmc_dev(host->mmc),
817 "ignoring card status error (CMD%d)\n",
2a50b888 818 cmd);
0107a4b3 819 end_command = 1;
730c9b7e
CA		 820 }
821
822 /*
823 * NOTE: On 1610 the END_OF_CMD may come too early when
2a50b888 824 * starting a write
730c9b7e
CA		 825 */
826 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
827 (!(status & OMAP_MMC_STAT_A_EMPTY))) {
828 end_command = 1;
829 }
830 }
831
0fb4723d
JL		 832 if (cmd_error && host->data) {
833 del_timer(&host->cmd_abort_timer);
834 host->abort = 1;
835 OMAP_MMC_WRITE(host, IE, 0);
e749c6f2 836 disable_irq_nosync(host->irq);
b01a4f1c 837 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
0fb4723d
JL		 838 return IRQ_HANDLED;
839 }
840
f6947514 841 if (end_command && host->cmd)
730c9b7e 842 mmc_omap_cmd_done(host, host->cmd);
2a50b888
JY		 843 if (host->data != NULL) {
844 if (transfer_error)
845 mmc_omap_xfer_done(host, host->data);
846 else if (end_transfer)
847 mmc_omap_end_of_data(host, host->data);
730c9b7e 848 }
730c9b7e
CA		 849
850 return IRQ_HANDLED;
851}
852
7584d276 853void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
5a0f3f1f 854{
7584d276 855 int cover_open;
5a0f3f1f 856 struct mmc_omap_host *host = dev_get_drvdata(dev);
7584d276 857 struct mmc_omap_slot *slot = host->slots[num];
5a0f3f1f 858
7584d276 859 BUG_ON(num >= host->nr_slots);
5a0f3f1f
JY		 860
861 /* Other subsystems can call in here before we're initialised. */
7584d276 862 if (host->nr_slots == 0 || !host->slots[num])
5a0f3f1f
JY		 863 return;
864
7584d276
JL		 865 cover_open = mmc_omap_cover_is_open(slot);
866 if (cover_open != slot->cover_open) {
867 slot->cover_open = cover_open;
868 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
869 }
870
871 tasklet_hi_schedule(&slot->cover_tasklet);
5a0f3f1f
JY		 872}
873
7584d276 874static void mmc_omap_cover_timer(unsigned long arg)
5a0f3f1f
JY		 875{
876 struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
7584d276 877 tasklet_schedule(&slot->cover_tasklet);
5a0f3f1f
JY		 878}
879
7584d276 880static void mmc_omap_cover_handler(unsigned long param)
5a0f3f1f 881{
7584d276
JL		 882 struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
883 int cover_open = mmc_omap_cover_is_open(slot);
5a0f3f1f 884
7584d276
JL		 885 mmc_detect_change(slot->mmc, 0);
886 if (!cover_open)
887 return;
888
889 /*
890 * If no card is inserted, we postpone polling until
891 * the cover has been closed.
892 */
893 if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card))
894 return;
895
896 mod_timer(&slot->cover_timer,
897 jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
5a0f3f1f
JY		 898}
899
3451c067
RK		 900static void mmc_omap_dma_callback(void *priv)
901{
902 struct mmc_omap_host *host = priv;
903 struct mmc_data *data = host->data;
904
905 /* If we got to the end of DMA, assume everything went well */
906 data->bytes_xfered += data->blocks * data->blksz;
907
908 mmc_omap_dma_done(host, data);
909}
910
730c9b7e
CA		 911static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
912{
913 u16 reg;
914
3342ee8b 915 reg = OMAP_MMC_READ(host, SDIO);
730c9b7e 916 reg &= ~(1 << 5);
3342ee8b 917 OMAP_MMC_WRITE(host, SDIO, reg);
730c9b7e 918 /* Set maximum timeout */
3342ee8b 919 OMAP_MMC_WRITE(host, CTO, 0xff);
730c9b7e
CA		 920}
921
922static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
923{
b8f9f0e9 924 unsigned int timeout, cycle_ns;
730c9b7e
CA		 925 u16 reg;
926
b8f9f0e9
JY		 927 cycle_ns = 1000000000 / host->current_slot->fclk_freq;
928 timeout = req->data->timeout_ns / cycle_ns;
929 timeout += req->data->timeout_clks;
730c9b7e
CA		 930
931 /* Check if we need to use timeout multiplier register */
3342ee8b 932 reg = OMAP_MMC_READ(host, SDIO);
730c9b7e
CA		 933 if (timeout > 0xffff) {
934 reg |= (1 << 5);
935 timeout /= 1024;
936 } else
937 reg &= ~(1 << 5);
3342ee8b
JY		 938 OMAP_MMC_WRITE(host, SDIO, reg);
939 OMAP_MMC_WRITE(host, DTO, timeout);
730c9b7e
CA		 940}
941
942static void
943mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
944{
945 struct mmc_data *data = req->data;
946 int i, use_dma, block_size;
947 unsigned sg_len;
948
949 host->data = data;
950 if (data == NULL) {
3342ee8b
JY		 951 OMAP_MMC_WRITE(host, BLEN, 0);
952 OMAP_MMC_WRITE(host, NBLK, 0);
953 OMAP_MMC_WRITE(host, BUF, 0);
730c9b7e
CA		 954 host->dma_in_use = 0;
955 set_cmd_timeout(host, req);
956 return;
957 }
958
a3fd4a1b 959 block_size = data->blksz;
730c9b7e 960
3342ee8b
JY		 961 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
962 OMAP_MMC_WRITE(host, BLEN, block_size - 1);
730c9b7e
CA		 963 set_data_timeout(host, req);
964
965 /* cope with calling layer confusion; it issues "single
966 * block" writes using multi-block scatterlists.
967 */
968 sg_len = (data->blocks == 1) ? 1 : data->sg_len;
969
970 /* Only do DMA for entire blocks */
971 use_dma = host->use_dma;
972 if (use_dma) {
973 for (i = 0; i < sg_len; i++) {
974 if ((data->sg[i].length % block_size) != 0) {
975 use_dma = 0;
976 break;
977 }
978 }
979 }
980
981 host->sg_idx = 0;
3451c067
RK		 982 if (use_dma) {
983 enum dma_data_direction dma_data_dir;
984 struct dma_async_tx_descriptor *tx;
985 struct dma_chan *c;
986 u32 burst, *bp;
987 u16 buf;
988
989 /*
990 * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx
991 * and 24xx. Use 16 or 32 word frames when the
992 * blocksize is at least that large. Blocksize is
993 * usually 512 bytes; but not for some SD reads.
994 */
995 burst = cpu_is_omap15xx() ? 32 : 64;
996 if (burst > data->blksz)
997 burst = data->blksz;
998
999 burst >>= 1;
1000
1001 if (data->flags & MMC_DATA_WRITE) {
1002 c = host->dma_tx;
1003 bp = &host->dma_tx_burst;
1004 buf = 0x0f80 | (burst - 1) << 0;
1005 dma_data_dir = DMA_TO_DEVICE;
1006 } else {
1007 c = host->dma_rx;
1008 bp = &host->dma_rx_burst;
1009 buf = 0x800f | (burst - 1) << 8;
1010 dma_data_dir = DMA_FROM_DEVICE;
1011 }
1012
1013 if (!c)
1014 goto use_pio;
1015
1016 /* Only reconfigure if we have a different burst size */
1017 if (*bp != burst) {
1018 struct dma_slave_config cfg;
1019
1020 cfg.src_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1021 cfg.dst_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1022 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1023 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1024 cfg.src_maxburst = burst;
1025 cfg.dst_maxburst = burst;
1026
1027 if (dmaengine_slave_config(c, &cfg))
1028 goto use_pio;
1029
1030 *bp = burst;
1031 }
1032
1033 host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len,
1034 dma_data_dir);
1035 if (host->sg_len == 0)
1036 goto use_pio;
1037
1038 tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len,
1039 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1040 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1041 if (!tx)
1042 goto use_pio;
1043
1044 OMAP_MMC_WRITE(host, BUF, buf);
1045
1046 tx->callback = mmc_omap_dma_callback;
1047 tx->callback_param = host;
1048 dmaengine_submit(tx);
1049 host->brs_received = 0;
1050 host->dma_done = 0;
1051 host->dma_in_use = 1;
1052 return;
1053 }
1054 use_pio:
730c9b7e
CA		 1055
1056 /* Revert to PIO? */
4e078fbd
RK		 1057 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1058 host->total_bytes_left = data->blocks * block_size;
1059 host->sg_len = sg_len;
1060 mmc_omap_sg_to_buf(host);
1061 host->dma_in_use = 0;
730c9b7e
CA		 1062}
1063
abfbe5f7
JY		 1064static void mmc_omap_start_request(struct mmc_omap_host *host,
1065 struct mmc_request *req)
730c9b7e 1066{
abfbe5f7 1067 BUG_ON(host->mrq != NULL);
730c9b7e
CA		 1068
1069 host->mrq = req;
1070
1071 /* only touch fifo AFTER the controller readies it */
1072 mmc_omap_prepare_data(host, req);
1073 mmc_omap_start_command(host, req->cmd);
3451c067
RK		 1074 if (host->dma_in_use) {
1075 struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ?
1076 host->dma_tx : host->dma_rx;
1077
4e078fbd 1078 dma_async_issue_pending(c);
3451c067 1079 }
abfbe5f7
JY		 1080}
1081
1082static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1083{
1084 struct mmc_omap_slot *slot = mmc_priv(mmc);
1085 struct mmc_omap_host *host = slot->host;
1086 unsigned long flags;
1087
1088 spin_lock_irqsave(&host->slot_lock, flags);
1089 if (host->mmc != NULL) {
1090 BUG_ON(slot->mrq != NULL);
1091 slot->mrq = req;
1092 spin_unlock_irqrestore(&host->slot_lock, flags);
1093 return;
1094 } else
1095 host->mmc = mmc;
1096 spin_unlock_irqrestore(&host->slot_lock, flags);
1097 mmc_omap_select_slot(slot, 1);
1098 mmc_omap_start_request(host, req);
730c9b7e
CA		 1099}
1100
65b5b6e5
JY		 1101static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1102 int vdd)
730c9b7e 1103{
65b5b6e5 1104 struct mmc_omap_host *host;
730c9b7e 1105
65b5b6e5
JY		 1106 host = slot->host;
1107
1108 if (slot->pdata->set_power != NULL)
1109 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1110 vdd);
1111
1112 if (cpu_is_omap24xx()) {
1113 u16 w;
1114
1115 if (power_on) {
1116 w = OMAP_MMC_READ(host, CON);
1117 OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1118 } else {
1119 w = OMAP_MMC_READ(host, CON);
1120 OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1121 }
730c9b7e
CA		 1122 }
1123}
1124
d3af5abe 1125static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
730c9b7e 1126{
abfbe5f7
JY		 1127 struct mmc_omap_slot *slot = mmc_priv(mmc);
1128 struct mmc_omap_host *host = slot->host;
d3af5abe 1129 int func_clk_rate = clk_get_rate(host->fclk);
730c9b7e 1130 int dsor;
730c9b7e
CA		 1131
1132 if (ios->clock == 0)
d3af5abe 1133 return 0;
730c9b7e 1134
d3af5abe
TL		 1135 dsor = func_clk_rate / ios->clock;
1136 if (dsor < 1)
1137 dsor = 1;
730c9b7e 1138
d3af5abe 1139 if (func_clk_rate / dsor > ios->clock)
730c9b7e
CA		 1140 dsor++;
1141
d3af5abe
TL		 1142 if (dsor > 250)
1143 dsor = 250;
d3af5abe 1144
abfbe5f7
JY		 1145 slot->fclk_freq = func_clk_rate / dsor;
1146
d3af5abe
TL		 1147 if (ios->bus_width == MMC_BUS_WIDTH_4)
1148 dsor |= 1 << 15;
1149
1150 return dsor;
1151}
1152
1153static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1154{
abfbe5f7
JY		 1155 struct mmc_omap_slot *slot = mmc_priv(mmc);
1156 struct mmc_omap_host *host = slot->host;
1157 int i, dsor;
0807a9b5 1158 int clk_enabled;
65b5b6e5
JY		 1159
1160 mmc_omap_select_slot(slot, 0);
1161
0807a9b5
JL		 1162 dsor = mmc_omap_calc_divisor(mmc, ios);
1163
65b5b6e5
JY		 1164 if (ios->vdd != slot->vdd)
1165 slot->vdd = ios->vdd;
730c9b7e 1166
0807a9b5 1167 clk_enabled = 0;
730c9b7e
CA		 1168 switch (ios->power_mode) {
1169 case MMC_POWER_OFF:
65b5b6e5 1170 mmc_omap_set_power(slot, 0, ios->vdd);
730c9b7e
CA		 1171 break;
1172 case MMC_POWER_UP:
46a6730e 1173 /* Cannot touch dsor yet, just power up MMC */
65b5b6e5
JY		 1174 mmc_omap_set_power(slot, 1, ios->vdd);
1175 goto exit;
46a6730e 1176 case MMC_POWER_ON:
0807a9b5
JL		 1177 mmc_omap_fclk_enable(host, 1);
1178 clk_enabled = 1;
c5cb431d 1179 dsor |= 1 << 11;
730c9b7e
CA		 1180 break;
1181 }
1182
65b5b6e5
JY		 1183 if (slot->bus_mode != ios->bus_mode) {
1184 if (slot->pdata->set_bus_mode != NULL)
1185 slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1186 ios->bus_mode);
1187 slot->bus_mode = ios->bus_mode;
1188 }
730c9b7e
CA		 1189
1190 /* On insanely high arm_per frequencies something sometimes
1191 * goes somehow out of sync, and the POW bit is not being set,
1192 * which results in the while loop below getting stuck.
1193 * Writing to the CON register twice seems to do the trick. */
1194 for (i = 0; i < 2; i++)
3342ee8b 1195 OMAP_MMC_WRITE(host, CON, dsor);
65b5b6e5 1196 slot->saved_con = dsor;
46a6730e 1197 if (ios->power_mode == MMC_POWER_ON) {
9d7c6eee
JL		 1198 /* worst case at 400kHz, 80 cycles makes 200 microsecs */
1199 int usecs = 250;
1200
730c9b7e 1201 /* Send clock cycles, poll completion */
3342ee8b
JY		 1202 OMAP_MMC_WRITE(host, IE, 0);
1203 OMAP_MMC_WRITE(host, STAT, 0xffff);
c5cb431d 1204 OMAP_MMC_WRITE(host, CMD, 1 << 7);
9d7c6eee
JL		 1205 while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
1206 udelay(1);
1207 usecs--;
1208 }
3342ee8b 1209 OMAP_MMC_WRITE(host, STAT, 1);
730c9b7e 1210 }
65b5b6e5
JY		 1211
1212exit:
0807a9b5 1213 mmc_omap_release_slot(slot, clk_enabled);
730c9b7e
CA		 1214}
1215
ab7aefd0 1216static const struct mmc_host_ops mmc_omap_ops = {
730c9b7e
CA		 1217 .request = mmc_omap_request,
1218 .set_ios = mmc_omap_set_ios,
730c9b7e
CA		 1219};
1220
4f837791 1221static int __devinit mmc_omap_new_slot(struct mmc_omap_host *host, int id)
730c9b7e 1222{
abfbe5f7 1223 struct mmc_omap_slot *slot = NULL;
730c9b7e 1224 struct mmc_host *mmc;
abfbe5f7
JY		 1225 int r;
1226
1227 mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1228 if (mmc == NULL)
1229 return -ENOMEM;
1230
1231 slot = mmc_priv(mmc);
1232 slot->host = host;
1233 slot->mmc = mmc;
1234 slot->id = id;
1235 slot->pdata = &host->pdata->slots[id];
1236
1237 host->slots[id] = slot;
1238
23af6039 1239 mmc->caps = 0;
90c62bf0 1240 if (host->pdata->slots[id].wires >= 4)
abfbe5f7
JY		 1241 mmc->caps |= MMC_CAP_4_BIT_DATA;
1242
1243 mmc->ops = &mmc_omap_ops;
1244 mmc->f_min = 400000;
1245
1246 if (cpu_class_is_omap2())
1247 mmc->f_max = 48000000;
1248 else
1249 mmc->f_max = 24000000;
1250 if (host->pdata->max_freq)
1251 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1252 mmc->ocr_avail = slot->pdata->ocr_mask;
1253
1254 /* Use scatterlist DMA to reduce per-transfer costs.
1255 * NOTE max_seg_size assumption that small blocks aren't
1256 * normally used (except e.g. for reading SD registers).
1257 */
a36274e0 1258 mmc->max_segs = 32;
abfbe5f7
JY		 1259 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
1260 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
1261 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1262 mmc->max_seg_size = mmc->max_req_size;
1263
1264 r = mmc_add_host(mmc);
1265 if (r < 0)
1266 goto err_remove_host;
1267
1268 if (slot->pdata->name != NULL) {
1269 r = device_create_file(&mmc->class_dev,
1270 &dev_attr_slot_name);
1271 if (r < 0)
1272 goto err_remove_host;
1273 }
1274
5a0f3f1f
JY		 1275 if (slot->pdata->get_cover_state != NULL) {
1276 r = device_create_file(&mmc->class_dev,
1277 &dev_attr_cover_switch);
1278 if (r < 0)
1279 goto err_remove_slot_name;
1280
7584d276
JL		 1281 setup_timer(&slot->cover_timer, mmc_omap_cover_timer,
1282 (unsigned long)slot);
1283 tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
1284 (unsigned long)slot);
1285 tasklet_schedule(&slot->cover_tasklet);
5a0f3f1f
JY		 1286 }
1287
abfbe5f7
JY		 1288 return 0;
1289
5a0f3f1f
JY		 1290err_remove_slot_name:
1291 if (slot->pdata->name != NULL)
1292 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
abfbe5f7
JY		 1293err_remove_host:
1294 mmc_remove_host(mmc);
1295 mmc_free_host(mmc);
1296 return r;
1297}
1298
1299static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1300{
1301 struct mmc_host *mmc = slot->mmc;
1302
1303 if (slot->pdata->name != NULL)
1304 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
5a0f3f1f
JY		 1305 if (slot->pdata->get_cover_state != NULL)
1306 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1307
7584d276
JL		 1308 tasklet_kill(&slot->cover_tasklet);
1309 del_timer_sync(&slot->cover_timer);
b01a4f1c 1310 flush_workqueue(slot->host->mmc_omap_wq);
abfbe5f7
JY		 1311
1312 mmc_remove_host(mmc);
1313 mmc_free_host(mmc);
1314}
1315
b6e0703b 1316static int __devinit mmc_omap_probe(struct platform_device *pdev)
abfbe5f7
JY		 1317{
1318 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
730c9b7e 1319 struct mmc_omap_host *host = NULL;
81ca7034 1320 struct resource *res;
3451c067
RK		 1321 dma_cap_mask_t mask;
1322 unsigned sig;
abfbe5f7 1323 int i, ret = 0;
ce9c1a83 1324 int irq;
81ca7034 1325
abfbe5f7 1326 if (pdata == NULL) {
81ca7034
JY		 1327 dev_err(&pdev->dev, "platform data missing\n");
1328 return -ENXIO;
1329 }
abfbe5f7
JY		 1330 if (pdata->nr_slots == 0) {
1331 dev_err(&pdev->dev, "no slots\n");
1332 return -ENXIO;
1333 }
81ca7034
JY		 1334
1335 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ce9c1a83 1336 irq = platform_get_irq(pdev, 0);
81ca7034 1337 if (res == NULL || irq < 0)
ce9c1a83 1338 return -ENXIO;
730c9b7e 1339
2092014d 1340 res = request_mem_region(res->start, resource_size(res),
abfbe5f7 1341 pdev->name);
81ca7034 1342 if (res == NULL)
730c9b7e 1343 return -EBUSY;
730c9b7e 1344
abfbe5f7
JY		 1345 host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1346 if (host == NULL) {
730c9b7e 1347 ret = -ENOMEM;
81ca7034 1348 goto err_free_mem_region;
730c9b7e
CA		 1349 }
1350
0f602ec7
JL		 1351 INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
1352 INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
1353
0fb4723d
JL		 1354 INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
1355 setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer,
1356 (unsigned long) host);
eb1860bc 1357
0807a9b5
JL		 1358 spin_lock_init(&host->clk_lock);
1359 setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host);
1360
730c9b7e 1361 spin_lock_init(&host->dma_lock);
abfbe5f7
JY		 1362 spin_lock_init(&host->slot_lock);
1363 init_waitqueue_head(&host->slot_wq);
1364
abfbe5f7
JY		 1365 host->pdata = pdata;
1366 host->dev = &pdev->dev;
1367 platform_set_drvdata(pdev, host);
1368
730c9b7e 1369 host->id = pdev->id;
81ca7034 1370 host->mem_res = res;
ce9c1a83 1371 host->irq = irq;
abfbe5f7 1372 host->use_dma = 1;
abfbe5f7
JY		 1373 host->irq = irq;
1374 host->phys_base = host->mem_res->start;
2092014d 1375 host->virt_base = ioremap(res->start, resource_size(res));
55c381e4
RK		 1376 if (!host->virt_base)
1377 goto err_ioremap;
abfbe5f7 1378
d4a36645 1379 host->iclk = clk_get(&pdev->dev, "ick");
e799acb2
LM		 1380 if (IS_ERR(host->iclk)) {
1381 ret = PTR_ERR(host->iclk);
d4a36645 1382 goto err_free_mmc_host;
e799acb2 1383 }
d4a36645 1384 clk_enable(host->iclk);
730c9b7e 1385
5c9e02b1 1386 host->fclk = clk_get(&pdev->dev, "fck");
730c9b7e
CA		 1387 if (IS_ERR(host->fclk)) {
1388 ret = PTR_ERR(host->fclk);
81ca7034 1389 goto err_free_iclk;
730c9b7e
CA		 1390 }
1391
3451c067
RK		 1392 dma_cap_zero(mask);
1393 dma_cap_set(DMA_SLAVE, mask);
1394
1395 host->dma_tx_burst = -1;
1396 host->dma_rx_burst = -1;
1397
1398 if (cpu_is_omap24xx())
1399 sig = host->id == 0 ? OMAP24XX_DMA_MMC1_TX : OMAP24XX_DMA_MMC2_TX;
1400 else
1401 sig = host->id == 0 ? OMAP_DMA_MMC_TX : OMAP_DMA_MMC2_TX;
1402 host->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1403#if 0
1404 if (!host->dma_tx) {
1405 dev_err(host->dev, "unable to obtain TX DMA engine channel %u\n",
1406 sig);
1407 goto err_dma;
1408 }
1409#else
1410 if (!host->dma_tx)
1411 dev_warn(host->dev, "unable to obtain TX DMA engine channel %u\n",
1412 sig);
1413#endif
1414 if (cpu_is_omap24xx())
1415 sig = host->id == 0 ? OMAP24XX_DMA_MMC1_RX : OMAP24XX_DMA_MMC2_RX;
1416 else
1417 sig = host->id == 0 ? OMAP_DMA_MMC_RX : OMAP_DMA_MMC2_RX;
1418 host->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1419#if 0
1420 if (!host->dma_rx) {
1421 dev_err(host->dev, "unable to obtain RX DMA engine channel %u\n",
1422 sig);
1423 goto err_dma;
1424 }
1425#else
1426 if (!host->dma_rx)
1427 dev_warn(host->dev, "unable to obtain RX DMA engine channel %u\n",
1428 sig);
1429#endif
1430
abfbe5f7
JY		 1431 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1432 if (ret)
3451c067 1433 goto err_free_dma;
42431acb 1434
abfbe5f7
JY		 1435 if (pdata->init != NULL) {
1436 ret = pdata->init(&pdev->dev);
1437 if (ret < 0)
1438 goto err_free_irq;
1439 }
730c9b7e 1440
abfbe5f7 1441 host->nr_slots = pdata->nr_slots;
ebbe6f88 1442 host->reg_shift = (cpu_is_omap7xx() ? 1 : 2);
3caf4140
TL		 1443
1444 host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0);
1445 if (!host->mmc_omap_wq)
1446 goto err_plat_cleanup;
1447
abfbe5f7
JY		 1448 for (i = 0; i < pdata->nr_slots; i++) {
1449 ret = mmc_omap_new_slot(host, i);
1450 if (ret < 0) {
1451 while (--i >= 0)
1452 mmc_omap_remove_slot(host->slots[i]);
730c9b7e 1453
3caf4140 1454 goto err_destroy_wq;
730c9b7e 1455 }
730c9b7e
CA		 1456 }
1457
730c9b7e
CA		 1458 return 0;
1459
3caf4140
TL		 1460err_destroy_wq:
1461 destroy_workqueue(host->mmc_omap_wq);
abfbe5f7
JY		 1462err_plat_cleanup:
1463 if (pdata->cleanup)
1464 pdata->cleanup(&pdev->dev);
1465err_free_irq:
1466 free_irq(host->irq, host);
3451c067
RK		 1467err_free_dma:
1468 if (host->dma_tx)
1469 dma_release_channel(host->dma_tx);
1470 if (host->dma_rx)
1471 dma_release_channel(host->dma_rx);
81ca7034
JY		 1472 clk_put(host->fclk);
1473err_free_iclk:
e799acb2
LM		 1474 clk_disable(host->iclk);
1475 clk_put(host->iclk);
81ca7034 1476err_free_mmc_host:
55c381e4
RK		 1477 iounmap(host->virt_base);
1478err_ioremap:
abfbe5f7 1479 kfree(host);
81ca7034 1480err_free_mem_region:
2092014d 1481 release_mem_region(res->start, resource_size(res));
730c9b7e
CA		 1482 return ret;
1483}
1484
b6e0703b 1485static int __devexit mmc_omap_remove(struct platform_device *pdev)
730c9b7e
CA		 1486{
1487 struct mmc_omap_host *host = platform_get_drvdata(pdev);
abfbe5f7 1488 int i;
730c9b7e
CA		 1489
1490 platform_set_drvdata(pdev, NULL);
1491
81ca7034
JY		 1492 BUG_ON(host == NULL);
1493
abfbe5f7
JY		 1494 for (i = 0; i < host->nr_slots; i++)
1495 mmc_omap_remove_slot(host->slots[i]);
1496
1497 if (host->pdata->cleanup)
1498 host->pdata->cleanup(&pdev->dev);
81ca7034 1499
d4a36645 1500 mmc_omap_fclk_enable(host, 0);
49c1d9da 1501 free_irq(host->irq, host);
d4a36645
RK		 1502 clk_put(host->fclk);
1503 clk_disable(host->iclk);
1504 clk_put(host->iclk);
730c9b7e 1505
3451c067
RK		 1506 if (host->dma_tx)
1507 dma_release_channel(host->dma_tx);
1508 if (host->dma_rx)
1509 dma_release_channel(host->dma_rx);
1510
55c381e4 1511 iounmap(host->virt_base);
730c9b7e 1512 release_mem_region(pdev->resource[0].start,
81ca7034 1513 pdev->resource[0].end - pdev->resource[0].start + 1);
b01a4f1c 1514 destroy_workqueue(host->mmc_omap_wq);
81ca7034 1515
abfbe5f7 1516 kfree(host);
730c9b7e
CA		 1517
1518 return 0;
1519}
1520
1521#ifdef CONFIG_PM
1522static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1523{
abfbe5f7 1524 int i, ret = 0;
730c9b7e
CA		 1525 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1526
abfbe5f7 1527 if (host == NULL || host->suspended)
730c9b7e
CA		 1528 return 0;
1529
abfbe5f7
JY		 1530 for (i = 0; i < host->nr_slots; i++) {
1531 struct mmc_omap_slot *slot;
1532
1533 slot = host->slots[i];
1a13f8fa 1534 ret = mmc_suspend_host(slot->mmc);
abfbe5f7
JY		 1535 if (ret < 0) {
1536 while (--i >= 0) {
1537 slot = host->slots[i];
1538 mmc_resume_host(slot->mmc);
1539 }
1540 return ret;
1541 }
730c9b7e 1542 }
abfbe5f7
JY		 1543 host->suspended = 1;
1544 return 0;
730c9b7e
CA		 1545}
1546
1547static int mmc_omap_resume(struct platform_device *pdev)
1548{
abfbe5f7 1549 int i, ret = 0;
730c9b7e
CA		 1550 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1551
abfbe5f7 1552 if (host == NULL || !host->suspended)
730c9b7e
CA		 1553 return 0;
1554
abfbe5f7
JY		 1555 for (i = 0; i < host->nr_slots; i++) {
1556 struct mmc_omap_slot *slot;
1557 slot = host->slots[i];
1558 ret = mmc_resume_host(slot->mmc);
1559 if (ret < 0)
1560 return ret;
730c9b7e 1561
abfbe5f7
JY		 1562 host->suspended = 0;
1563 }
1564 return 0;
730c9b7e
CA		 1565}
1566#else
1567#define mmc_omap_suspend NULL
1568#define mmc_omap_resume NULL
1569#endif
1570
1571static struct platform_driver mmc_omap_driver = {
b6e0703b
V		 1572 .probe = mmc_omap_probe,
1573 .remove = __devexit_p(mmc_omap_remove),
730c9b7e
CA		 1574 .suspend = mmc_omap_suspend,
1575 .resume = mmc_omap_resume,
1576 .driver = {
1577 .name = DRIVER_NAME,
bc65c724 1578 .owner = THIS_MODULE,
730c9b7e
CA		 1579 },
1580};
1581
680f1b5b 1582module_platform_driver(mmc_omap_driver);
730c9b7e
CA		 1583MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1584MODULE_LICENSE("GPL");
bc65c724 1585MODULE_ALIAS("platform:" DRIVER_NAME);
d36b6910 1586MODULE_AUTHOR("Juha Yrjölä");
Linux kernel - Deliverables
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