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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc
[deliverable/linux.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
d900f712
DK		 20#include <linux/debugfs.h>
21#include <linux/seq_file.h>
a45c6cb8
MC		 22#include <linux/interrupt.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
25#include <linux/platform_device.h>
26#include <linux/workqueue.h>
27#include <linux/timer.h>
28#include <linux/clk.h>
29#include <linux/mmc/host.h>
13189e78 30#include <linux/mmc/core.h>
93caf8e6 31#include <linux/mmc/mmc.h>
a45c6cb8
MC		 32#include <linux/io.h>
33#include <linux/semaphore.h>
db0fefc5
AH		 34#include <linux/gpio.h>
35#include <linux/regulator/consumer.h>
ce491cf8 36#include <plat/dma.h>
a45c6cb8 37#include <mach/hardware.h>
ce491cf8
TL		 38#include <plat/board.h>
39#include <plat/mmc.h>
40#include <plat/cpu.h>
a45c6cb8
MC		 41
42/* OMAP HSMMC Host Controller Registers */
43#define OMAP_HSMMC_SYSCONFIG 0x0010
11dd62a7 44#define OMAP_HSMMC_SYSSTATUS 0x0014
a45c6cb8
MC		 45#define OMAP_HSMMC_CON 0x002C
46#define OMAP_HSMMC_BLK 0x0104
47#define OMAP_HSMMC_ARG 0x0108
48#define OMAP_HSMMC_CMD 0x010C
49#define OMAP_HSMMC_RSP10 0x0110
50#define OMAP_HSMMC_RSP32 0x0114
51#define OMAP_HSMMC_RSP54 0x0118
52#define OMAP_HSMMC_RSP76 0x011C
53#define OMAP_HSMMC_DATA 0x0120
54#define OMAP_HSMMC_HCTL 0x0128
55#define OMAP_HSMMC_SYSCTL 0x012C
56#define OMAP_HSMMC_STAT 0x0130
57#define OMAP_HSMMC_IE 0x0134
58#define OMAP_HSMMC_ISE 0x0138
59#define OMAP_HSMMC_CAPA 0x0140
60
61#define VS18 (1 << 26)
62#define VS30 (1 << 25)
63#define SDVS18 (0x5 << 9)
64#define SDVS30 (0x6 << 9)
eb250826 65#define SDVS33 (0x7 << 9)
1b331e69 66#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 67#define SDVSCLR 0xFFFFF1FF
68#define SDVSDET 0x00000400
69#define AUTOIDLE 0x1
70#define SDBP (1 << 8)
71#define DTO 0xe
72#define ICE 0x1
73#define ICS 0x2
74#define CEN (1 << 2)
75#define CLKD_MASK 0x0000FFC0
76#define CLKD_SHIFT 6
77#define DTO_MASK 0x000F0000
78#define DTO_SHIFT 16
79#define INT_EN_MASK 0x307F0033
ccdfe3a6
AG		 80#define BWR_ENABLE (1 << 4)
81#define BRR_ENABLE (1 << 5)
93caf8e6 82#define DTO_ENABLE (1 << 20)
a45c6cb8
MC		 83#define INIT_STREAM (1 << 1)
84#define DP_SELECT (1 << 21)
85#define DDIR (1 << 4)
86#define DMA_EN 0x1
87#define MSBS (1 << 5)
88#define BCE (1 << 1)
89#define FOUR_BIT (1 << 1)
73153010 90#define DW8 (1 << 5)
a45c6cb8
MC		 91#define CC 0x1
92#define TC 0x02
93#define OD 0x1
94#define ERR (1 << 15)
95#define CMD_TIMEOUT (1 << 16)
96#define DATA_TIMEOUT (1 << 20)
97#define CMD_CRC (1 << 17)
98#define DATA_CRC (1 << 21)
99#define CARD_ERR (1 << 28)
100#define STAT_CLEAR 0xFFFFFFFF
101#define INIT_STREAM_CMD 0x00000000
102#define DUAL_VOLT_OCR_BIT 7
103#define SRC (1 << 25)
104#define SRD (1 << 26)
11dd62a7
DK		 105#define SOFTRESET (1 << 1)
106#define RESETDONE (1 << 0)
a45c6cb8
MC		 107
108/*
109 * FIXME: Most likely all the data using these _DEVID defines should come
110 * from the platform_data, or implemented in controller and slot specific
111 * functions.
112 */
113#define OMAP_MMC1_DEVID 0
114#define OMAP_MMC2_DEVID 1
f3e2f1dd 115#define OMAP_MMC3_DEVID 2
82cf818d 116#define OMAP_MMC4_DEVID 3
117#define OMAP_MMC5_DEVID 4
a45c6cb8 118
a45c6cb8
MC		 119#define MMC_TIMEOUT_MS 20
120#define OMAP_MMC_MASTER_CLOCK 96000000
121#define DRIVER_NAME "mmci-omap-hs"
122
dd498eff
DK		 123/* Timeouts for entering power saving states on inactivity, msec */
124#define OMAP_MMC_DISABLED_TIMEOUT 100
13189e78
JL		 125#define OMAP_MMC_SLEEP_TIMEOUT 1000
126#define OMAP_MMC_OFF_TIMEOUT 8000
dd498eff 127
a45c6cb8
MC		 128/*
129 * One controller can have multiple slots, like on some omap boards using
130 * omap.c controller driver. Luckily this is not currently done on any known
131 * omap_hsmmc.c device.
132 */
133#define mmc_slot(host) (host->pdata->slots[host->slot_id])
134
135/*
136 * MMC Host controller read/write API's
137 */
138#define OMAP_HSMMC_READ(base, reg) \
139 __raw_readl((base) + OMAP_HSMMC_##reg)
140
141#define OMAP_HSMMC_WRITE(base, reg, val) \
142 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
143
70a3341a 144struct omap_hsmmc_host {
a45c6cb8
MC		 145 struct device *dev;
146 struct mmc_host *mmc;
147 struct mmc_request *mrq;
148 struct mmc_command *cmd;
149 struct mmc_data *data;
150 struct clk *fclk;
151 struct clk *iclk;
152 struct clk *dbclk;
db0fefc5
AH		 153 /*
154 * vcc == configured supply
155 * vcc_aux == optional
156 * - MMC1, supply for DAT4..DAT7
157 * - MMC2/MMC2, external level shifter voltage supply, for
158 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
159 */
160 struct regulator *vcc;
161 struct regulator *vcc_aux;
a45c6cb8
MC		 162 struct work_struct mmc_carddetect_work;
163 void __iomem *base;
164 resource_size_t mapbase;
4dffd7a2 165 spinlock_t irq_lock; /* Prevent races with irq handler */
a45c6cb8
MC		 166 unsigned int id;
167 unsigned int dma_len;
0ccd76d4 168 unsigned int dma_sg_idx;
a45c6cb8 169 unsigned char bus_mode;
a3621465 170 unsigned char power_mode;
a45c6cb8
MC		 171 u32 *buffer;
172 u32 bytesleft;
173 int suspended;
174 int irq;
a45c6cb8 175 int use_dma, dma_ch;
f3e2f1dd 176 int dma_line_tx, dma_line_rx;
a45c6cb8 177 int slot_id;
2bec0893 178 int got_dbclk;
4a694dc9 179 int response_busy;
11dd62a7 180 int context_loss;
dd498eff 181 int dpm_state;
623821f7 182 int vdd;
b62f6228
AH		 183 int protect_card;
184 int reqs_blocked;
db0fefc5 185 int use_reg;
b417577d 186 int req_in_progress;
11dd62a7 187
a45c6cb8
MC		 188 struct omap_mmc_platform_data *pdata;
189};
190
db0fefc5
AH		 191static int omap_hsmmc_card_detect(struct device *dev, int slot)
192{
193 struct omap_mmc_platform_data *mmc = dev->platform_data;
194
195 /* NOTE: assumes card detect signal is active-low */
196 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
197}
198
199static int omap_hsmmc_get_wp(struct device *dev, int slot)
200{
201 struct omap_mmc_platform_data *mmc = dev->platform_data;
202
203 /* NOTE: assumes write protect signal is active-high */
204 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
205}
206
207static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
208{
209 struct omap_mmc_platform_data *mmc = dev->platform_data;
210
211 /* NOTE: assumes card detect signal is active-low */
212 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
213}
214
215#ifdef CONFIG_PM
216
217static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
218{
219 struct omap_mmc_platform_data *mmc = dev->platform_data;
220
221 disable_irq(mmc->slots[0].card_detect_irq);
222 return 0;
223}
224
225static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
226{
227 struct omap_mmc_platform_data *mmc = dev->platform_data;
228
229 enable_irq(mmc->slots[0].card_detect_irq);
230 return 0;
231}
232
233#else
234
235#define omap_hsmmc_suspend_cdirq NULL
236#define omap_hsmmc_resume_cdirq NULL
237
238#endif
239
b702b106
AH		 240#ifdef CONFIG_REGULATOR
241
db0fefc5
AH		 242static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
243 int vdd)
244{
245 struct omap_hsmmc_host *host =
246 platform_get_drvdata(to_platform_device(dev));
247 int ret;
248
249 if (mmc_slot(host).before_set_reg)
250 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
251
252 if (power_on)
99fc5131 253 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5 254 else
99fc5131 255 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
db0fefc5
AH		 256
257 if (mmc_slot(host).after_set_reg)
258 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
259
260 return ret;
261}
262
263static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on,
264 int vdd)
265{
266 struct omap_hsmmc_host *host =
267 platform_get_drvdata(to_platform_device(dev));
268 int ret = 0;
269
270 /*
271 * If we don't see a Vcc regulator, assume it's a fixed
272 * voltage always-on regulator.
273 */
274 if (!host->vcc)
275 return 0;
276
277 if (mmc_slot(host).before_set_reg)
278 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
279
280 /*
281 * Assume Vcc regulator is used only to power the card ... OMAP
282 * VDDS is used to power the pins, optionally with a transceiver to
283 * support cards using voltages other than VDDS (1.8V nominal). When a
284 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
285 *
286 * In some cases this regulator won't support enable/disable;
287 * e.g. it's a fixed rail for a WLAN chip.
288 *
289 * In other cases vcc_aux switches interface power. Example, for
290 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
291 * chips/cards need an interface voltage rail too.
292 */
293 if (power_on) {
99fc5131 294 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5
AH		 295 /* Enable interface voltage rail, if needed */
296 if (ret == 0 && host->vcc_aux) {
297 ret = regulator_enable(host->vcc_aux);
298 if (ret < 0)
99fc5131
LW		 299 ret = mmc_regulator_set_ocr(host->mmc,
300 host->vcc, 0);
db0fefc5
AH		 301 }
302 } else {
99fc5131 303 /* Shut down the rail */
6da20c89
AH		 304 if (host->vcc_aux)
305 ret = regulator_disable(host->vcc_aux);
99fc5131
LW		 306 if (!ret) {
307 /* Then proceed to shut down the local regulator */
308 ret = mmc_regulator_set_ocr(host->mmc,
309 host->vcc, 0);
310 }
db0fefc5
AH		 311 }
312
313 if (mmc_slot(host).after_set_reg)
314 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
315
316 return ret;
317}
318
319static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
320 int vdd, int cardsleep)
321{
322 struct omap_hsmmc_host *host =
323 platform_get_drvdata(to_platform_device(dev));
324 int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
325
326 return regulator_set_mode(host->vcc, mode);
327}
328
329static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep,
330 int vdd, int cardsleep)
331{
332 struct omap_hsmmc_host *host =
333 platform_get_drvdata(to_platform_device(dev));
334 int err, mode;
335
336 /*
337 * If we don't see a Vcc regulator, assume it's a fixed
338 * voltage always-on regulator.
339 */
340 if (!host->vcc)
341 return 0;
342
343 mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
344
345 if (!host->vcc_aux)
346 return regulator_set_mode(host->vcc, mode);
347
348 if (cardsleep) {
349 /* VCC can be turned off if card is asleep */
350 if (sleep)
99fc5131 351 err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
db0fefc5 352 else
99fc5131 353 err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5
AH		 354 } else
355 err = regulator_set_mode(host->vcc, mode);
356 if (err)
357 return err;
e0eb2424
AH		 358
359 if (!mmc_slot(host).vcc_aux_disable_is_sleep)
360 return regulator_set_mode(host->vcc_aux, mode);
361
362 if (sleep)
363 return regulator_disable(host->vcc_aux);
364 else
365 return regulator_enable(host->vcc_aux);
db0fefc5
AH		 366}
367
db0fefc5
AH		 368static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
369{
370 struct regulator *reg;
371 int ret = 0;
64be9782 372 int ocr_value = 0;
db0fefc5
AH		 373
374 switch (host->id) {
375 case OMAP_MMC1_DEVID:
376 /* On-chip level shifting via PBIAS0/PBIAS1 */
377 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
378 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
379 break;
380 case OMAP_MMC2_DEVID:
381 case OMAP_MMC3_DEVID:
382 /* Off-chip level shifting, or none */
383 mmc_slot(host).set_power = omap_hsmmc_23_set_power;
384 mmc_slot(host).set_sleep = omap_hsmmc_23_set_sleep;
385 break;
386 default:
387 pr_err("MMC%d configuration not supported!\n", host->id);
388 return -EINVAL;
389 }
390
391 reg = regulator_get(host->dev, "vmmc");
392 if (IS_ERR(reg)) {
393 dev_dbg(host->dev, "vmmc regulator missing\n");
394 /*
395 * HACK: until fixed.c regulator is usable,
396 * we don't require a main regulator
397 * for MMC2 or MMC3
398 */
399 if (host->id == OMAP_MMC1_DEVID) {
400 ret = PTR_ERR(reg);
401 goto err;
402 }
403 } else {
404 host->vcc = reg;
64be9782 405 ocr_value = mmc_regulator_get_ocrmask(reg);
406 if (!mmc_slot(host).ocr_mask) {
407 mmc_slot(host).ocr_mask = ocr_value;
408 } else {
409 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
410 pr_err("MMC%d ocrmask %x is not supported\n",
411 host->id, mmc_slot(host).ocr_mask);
412 mmc_slot(host).ocr_mask = 0;
413 return -EINVAL;
414 }
415 }
db0fefc5
AH		 416 mmc_slot(host).ocr_mask = mmc_regulator_get_ocrmask(reg);
417
418 /* Allow an aux regulator */
419 reg = regulator_get(host->dev, "vmmc_aux");
420 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
421
422 /*
423 * UGLY HACK: workaround regulator framework bugs.
424 * When the bootloader leaves a supply active, it's
425 * initialized with zero usecount ... and we can't
426 * disable it without first enabling it. Until the
427 * framework is fixed, we need a workaround like this
428 * (which is safe for MMC, but not in general).
429 */
430 if (regulator_is_enabled(host->vcc) > 0) {
431 regulator_enable(host->vcc);
432 regulator_disable(host->vcc);
433 }
434 if (host->vcc_aux) {
435 if (regulator_is_enabled(reg) > 0) {
436 regulator_enable(reg);
437 regulator_disable(reg);
438 }
439 }
440 }
441
442 return 0;
443
444err:
445 mmc_slot(host).set_power = NULL;
446 mmc_slot(host).set_sleep = NULL;
447 return ret;
448}
449
450static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
451{
452 regulator_put(host->vcc);
453 regulator_put(host->vcc_aux);
454 mmc_slot(host).set_power = NULL;
455 mmc_slot(host).set_sleep = NULL;
456}
457
b702b106
AH		 458static inline int omap_hsmmc_have_reg(void)
459{
460 return 1;
461}
462
463#else
464
465static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
466{
467 return -EINVAL;
468}
469
470static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
471{
472}
473
474static inline int omap_hsmmc_have_reg(void)
475{
476 return 0;
477}
478
479#endif
480
481static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
482{
483 int ret;
484
485 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
486 pdata->suspend = omap_hsmmc_suspend_cdirq;
487 pdata->resume = omap_hsmmc_resume_cdirq;
488 if (pdata->slots[0].cover)
489 pdata->slots[0].get_cover_state =
490 omap_hsmmc_get_cover_state;
491 else
492 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
493 pdata->slots[0].card_detect_irq =
494 gpio_to_irq(pdata->slots[0].switch_pin);
495 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
496 if (ret)
497 return ret;
498 ret = gpio_direction_input(pdata->slots[0].switch_pin);
499 if (ret)
500 goto err_free_sp;
501 } else
502 pdata->slots[0].switch_pin = -EINVAL;
503
504 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
505 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
506 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
507 if (ret)
508 goto err_free_cd;
509 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
510 if (ret)
511 goto err_free_wp;
512 } else
513 pdata->slots[0].gpio_wp = -EINVAL;
514
515 return 0;
516
517err_free_wp:
518 gpio_free(pdata->slots[0].gpio_wp);
519err_free_cd:
520 if (gpio_is_valid(pdata->slots[0].switch_pin))
521err_free_sp:
522 gpio_free(pdata->slots[0].switch_pin);
523 return ret;
524}
525
526static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
527{
528 if (gpio_is_valid(pdata->slots[0].gpio_wp))
529 gpio_free(pdata->slots[0].gpio_wp);
530 if (gpio_is_valid(pdata->slots[0].switch_pin))
531 gpio_free(pdata->slots[0].switch_pin);
532}
533
a45c6cb8
MC		 534/*
535 * Stop clock to the card
536 */
70a3341a 537static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
a45c6cb8
MC		 538{
539 OMAP_HSMMC_WRITE(host->base, SYSCTL,
540 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
541 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
542 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
543}
544
93caf8e6
AH		 545static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
546 struct mmc_command *cmd)
b417577d
AH		 547{
548 unsigned int irq_mask;
549
550 if (host->use_dma)
551 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
552 else
553 irq_mask = INT_EN_MASK;
554
93caf8e6
AH		 555 /* Disable timeout for erases */
556 if (cmd->opcode == MMC_ERASE)
557 irq_mask &= ~DTO_ENABLE;
558
b417577d
AH		 559 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
560 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
561 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
562}
563
564static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
565{
566 OMAP_HSMMC_WRITE(host->base, ISE, 0);
567 OMAP_HSMMC_WRITE(host->base, IE, 0);
568 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
569}
570
11dd62a7
DK		 571#ifdef CONFIG_PM
572
573/*
574 * Restore the MMC host context, if it was lost as result of a
575 * power state change.
576 */
70a3341a 577static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 578{
579 struct mmc_ios *ios = &host->mmc->ios;
580 struct omap_mmc_platform_data *pdata = host->pdata;
581 int context_loss = 0;
582 u32 hctl, capa, con;
583 u16 dsor = 0;
584 unsigned long timeout;
585
586 if (pdata->get_context_loss_count) {
587 context_loss = pdata->get_context_loss_count(host->dev);
588 if (context_loss < 0)
589 return 1;
590 }
591
592 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
593 context_loss == host->context_loss ? "not " : "");
594 if (host->context_loss == context_loss)
595 return 1;
596
597 /* Wait for hardware reset */
598 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
599 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
600 && time_before(jiffies, timeout))
601 ;
602
603 /* Do software reset */
604 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
605 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
606 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
607 && time_before(jiffies, timeout))
608 ;
609
610 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
611 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
612
613 if (host->id == OMAP_MMC1_DEVID) {
614 if (host->power_mode != MMC_POWER_OFF &&
615 (1 << ios->vdd) <= MMC_VDD_23_24)
616 hctl = SDVS18;
617 else
618 hctl = SDVS30;
619 capa = VS30 | VS18;
620 } else {
621 hctl = SDVS18;
622 capa = VS18;
623 }
624
625 OMAP_HSMMC_WRITE(host->base, HCTL,
626 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
627
628 OMAP_HSMMC_WRITE(host->base, CAPA,
629 OMAP_HSMMC_READ(host->base, CAPA) | capa);
630
631 OMAP_HSMMC_WRITE(host->base, HCTL,
632 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
633
634 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
635 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
636 && time_before(jiffies, timeout))
637 ;
638
b417577d 639 omap_hsmmc_disable_irq(host);
11dd62a7
DK		 640
641 /* Do not initialize card-specific things if the power is off */
642 if (host->power_mode == MMC_POWER_OFF)
643 goto out;
644
645 con = OMAP_HSMMC_READ(host->base, CON);
646 switch (ios->bus_width) {
647 case MMC_BUS_WIDTH_8:
648 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
649 break;
650 case MMC_BUS_WIDTH_4:
651 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
652 OMAP_HSMMC_WRITE(host->base, HCTL,
653 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
654 break;
655 case MMC_BUS_WIDTH_1:
656 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
657 OMAP_HSMMC_WRITE(host->base, HCTL,
658 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
659 break;
660 }
661
662 if (ios->clock) {
663 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
664 if (dsor < 1)
665 dsor = 1;
666
667 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
668 dsor++;
669
670 if (dsor > 250)
671 dsor = 250;
672 }
673
674 OMAP_HSMMC_WRITE(host->base, SYSCTL,
675 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
676 OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
677 OMAP_HSMMC_WRITE(host->base, SYSCTL,
678 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
679
680 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
681 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
682 && time_before(jiffies, timeout))
683 ;
684
685 OMAP_HSMMC_WRITE(host->base, SYSCTL,
686 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
687
688 con = OMAP_HSMMC_READ(host->base, CON);
689 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
690 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
691 else
692 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
693out:
694 host->context_loss = context_loss;
695
696 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
697 return 0;
698}
699
700/*
701 * Save the MMC host context (store the number of power state changes so far).
702 */
70a3341a 703static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 704{
705 struct omap_mmc_platform_data *pdata = host->pdata;
706 int context_loss;
707
708 if (pdata->get_context_loss_count) {
709 context_loss = pdata->get_context_loss_count(host->dev);
710 if (context_loss < 0)
711 return;
712 host->context_loss = context_loss;
713 }
714}
715
716#else
717
70a3341a 718static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 719{
720 return 0;
721}
722
70a3341a 723static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 724{
725}
726
727#endif
728
a45c6cb8
MC		 729/*
730 * Send init stream sequence to card
731 * before sending IDLE command
732 */
70a3341a 733static void send_init_stream(struct omap_hsmmc_host *host)
a45c6cb8
MC		 734{
735 int reg = 0;
736 unsigned long timeout;
737
b62f6228
AH		 738 if (host->protect_card)
739 return;
740
a45c6cb8 741 disable_irq(host->irq);
b417577d
AH		 742
743 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8
MC		 744 OMAP_HSMMC_WRITE(host->base, CON,
745 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
746 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
747
748 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
749 while ((reg != CC) && time_before(jiffies, timeout))
750 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
751
752 OMAP_HSMMC_WRITE(host->base, CON,
753 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
c653a6d4
AH		 754
755 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
756 OMAP_HSMMC_READ(host->base, STAT);
757
a45c6cb8
MC		 758 enable_irq(host->irq);
759}
760
761static inline
70a3341a 762int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
a45c6cb8
MC		 763{
764 int r = 1;
765
191d1f1d
DK		 766 if (mmc_slot(host).get_cover_state)
767 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
a45c6cb8
MC		 768 return r;
769}
770
771static ssize_t
70a3341a 772omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 773 char *buf)
774{
775 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 776 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 777
70a3341a
DK		 778 return sprintf(buf, "%s\n",
779 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
a45c6cb8
MC		 780}
781
70a3341a 782static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
a45c6cb8
MC		 783
784static ssize_t
70a3341a 785omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 786 char *buf)
787{
788 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 789 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 790
191d1f1d 791 return sprintf(buf, "%s\n", mmc_slot(host).name);
a45c6cb8
MC		 792}
793
70a3341a 794static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
a45c6cb8
MC		 795
796/*
797 * Configure the response type and send the cmd.
798 */
799static void
70a3341a 800omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
a45c6cb8
MC		 801 struct mmc_data *data)
802{
803 int cmdreg = 0, resptype = 0, cmdtype = 0;
804
805 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
806 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
807 host->cmd = cmd;
808
93caf8e6 809 omap_hsmmc_enable_irq(host, cmd);
a45c6cb8 810
4a694dc9 811 host->response_busy = 0;
a45c6cb8
MC		 812 if (cmd->flags & MMC_RSP_PRESENT) {
813 if (cmd->flags & MMC_RSP_136)
814 resptype = 1;
4a694dc9
AH		 815 else if (cmd->flags & MMC_RSP_BUSY) {
816 resptype = 3;
817 host->response_busy = 1;
818 } else
a45c6cb8
MC		 819 resptype = 2;
820 }
821
822 /*
823 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
824 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
825 * a val of 0x3, rest 0x0.
826 */
827 if (cmd == host->mrq->stop)
828 cmdtype = 0x3;
829
830 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
831
832 if (data) {
833 cmdreg |= DP_SELECT | MSBS | BCE;
834 if (data->flags & MMC_DATA_READ)
835 cmdreg |= DDIR;
836 else
837 cmdreg &= ~(DDIR);
838 }
839
840 if (host->use_dma)
841 cmdreg |= DMA_EN;
842
b417577d 843 host->req_in_progress = 1;
4dffd7a2 844
a45c6cb8
MC		 845 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
846 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
847}
848
0ccd76d4 849static int
70a3341a 850omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
0ccd76d4
JY		 851{
852 if (data->flags & MMC_DATA_WRITE)
853 return DMA_TO_DEVICE;
854 else
855 return DMA_FROM_DEVICE;
856}
857
b417577d
AH		 858static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
859{
860 int dma_ch;
861
862 spin_lock(&host->irq_lock);
863 host->req_in_progress = 0;
864 dma_ch = host->dma_ch;
865 spin_unlock(&host->irq_lock);
866
867 omap_hsmmc_disable_irq(host);
868 /* Do not complete the request if DMA is still in progress */
869 if (mrq->data && host->use_dma && dma_ch != -1)
870 return;
871 host->mrq = NULL;
872 mmc_request_done(host->mmc, mrq);
873}
874
a45c6cb8
MC		 875/*
876 * Notify the transfer complete to MMC core
877 */
878static void
70a3341a 879omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
a45c6cb8 880{
4a694dc9
AH		 881 if (!data) {
882 struct mmc_request *mrq = host->mrq;
883
23050103
AH		 884 /* TC before CC from CMD6 - don't know why, but it happens */
885 if (host->cmd && host->cmd->opcode == 6 &&
886 host->response_busy) {
887 host->response_busy = 0;
888 return;
889 }
890
b417577d 891 omap_hsmmc_request_done(host, mrq);
4a694dc9
AH		 892 return;
893 }
894
a45c6cb8
MC		 895 host->data = NULL;
896
a45c6cb8
MC		 897 if (!data->error)
898 data->bytes_xfered += data->blocks * (data->blksz);
899 else
900 data->bytes_xfered = 0;
901
902 if (!data->stop) {
b417577d 903 omap_hsmmc_request_done(host, data->mrq);
a45c6cb8
MC		 904 return;
905 }
70a3341a 906 omap_hsmmc_start_command(host, data->stop, NULL);
a45c6cb8
MC		 907}
908
909/*
910 * Notify the core about command completion
911 */
912static void
70a3341a 913omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
a45c6cb8
MC		 914{
915 host->cmd = NULL;
916
917 if (cmd->flags & MMC_RSP_PRESENT) {
918 if (cmd->flags & MMC_RSP_136) {
919 /* response type 2 */
920 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
921 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
922 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
923 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
924 } else {
925 /* response types 1, 1b, 3, 4, 5, 6 */
926 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
927 }
928 }
b417577d
AH		 929 if ((host->data == NULL && !host->response_busy) || cmd->error)
930 omap_hsmmc_request_done(host, cmd->mrq);
a45c6cb8
MC		 931}
932
933/*
934 * DMA clean up for command errors
935 */
70a3341a 936static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
a45c6cb8 937{
b417577d
AH		 938 int dma_ch;
939
82788ff5 940 host->data->error = errno;
a45c6cb8 941
b417577d
AH		 942 spin_lock(&host->irq_lock);
943 dma_ch = host->dma_ch;
944 host->dma_ch = -1;
945 spin_unlock(&host->irq_lock);
946
947 if (host->use_dma && dma_ch != -1) {
a45c6cb8 948 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
70a3341a 949 omap_hsmmc_get_dma_dir(host, host->data));
b417577d 950 omap_free_dma(dma_ch);
a45c6cb8
MC		 951 }
952 host->data = NULL;
a45c6cb8
MC		 953}
954
955/*
956 * Readable error output
957 */
958#ifdef CONFIG_MMC_DEBUG
70a3341a 959static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status)
a45c6cb8
MC		 960{
961 /* --- means reserved bit without definition at documentation */
70a3341a 962 static const char *omap_hsmmc_status_bits[] = {
a45c6cb8
MC		 963 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
964 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
965 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
966 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
967 };
968 char res[256];
969 char *buf = res;
970 int len, i;
971
972 len = sprintf(buf, "MMC IRQ 0x%x :", status);
973 buf += len;
974
70a3341a 975 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
a45c6cb8 976 if (status & (1 << i)) {
70a3341a 977 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
a45c6cb8
MC		 978 buf += len;
979 }
980
981 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
982}
983#endif /* CONFIG_MMC_DEBUG */
984
3ebf74b1
JP		 985/*
986 * MMC controller internal state machines reset
987 *
988 * Used to reset command or data internal state machines, using respectively
989 * SRC or SRD bit of SYSCTL register
990 * Can be called from interrupt context
991 */
70a3341a
DK		 992static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
993 unsigned long bit)
3ebf74b1
JP		 994{
995 unsigned long i = 0;
996 unsigned long limit = (loops_per_jiffy *
997 msecs_to_jiffies(MMC_TIMEOUT_MS));
998
999 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1000 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1001
07ad64b6
MC		 1002 /*
1003 * OMAP4 ES2 and greater has an updated reset logic.
1004 * Monitor a 0->1 transition first
1005 */
1006 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
1007 while ((!(OMAP_HSMMC_READ(host, SYSCTL) & bit))
1008 && (i++ < limit))
1009 cpu_relax();
1010 }
1011 i = 0;
1012
3ebf74b1
JP		 1013 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1014 (i++ < limit))
1015 cpu_relax();
1016
1017 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1018 dev_err(mmc_dev(host->mmc),
1019 "Timeout waiting on controller reset in %s\n",
1020 __func__);
1021}
a45c6cb8 1022
b417577d 1023static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
a45c6cb8 1024{
a45c6cb8 1025 struct mmc_data *data;
b417577d
AH		 1026 int end_cmd = 0, end_trans = 0;
1027
1028 if (!host->req_in_progress) {
1029 do {
1030 OMAP_HSMMC_WRITE(host->base, STAT, status);
1031 /* Flush posted write */
1032 status = OMAP_HSMMC_READ(host->base, STAT);
1033 } while (status & INT_EN_MASK);
1034 return;
a45c6cb8
MC		 1035 }
1036
1037 data = host->data;
a45c6cb8
MC		 1038 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1039
1040 if (status & ERR) {
1041#ifdef CONFIG_MMC_DEBUG
70a3341a 1042 omap_hsmmc_report_irq(host, status);
a45c6cb8
MC		 1043#endif
1044 if ((status & CMD_TIMEOUT) ||
1045 (status & CMD_CRC)) {
1046 if (host->cmd) {
1047 if (status & CMD_TIMEOUT) {
70a3341a
DK		 1048 omap_hsmmc_reset_controller_fsm(host,
1049 SRC);
a45c6cb8
MC		 1050 host->cmd->error = -ETIMEDOUT;
1051 } else {
1052 host->cmd->error = -EILSEQ;
1053 }
1054 end_cmd = 1;
1055 }
4a694dc9
AH		 1056 if (host->data || host->response_busy) {
1057 if (host->data)
70a3341a
DK		 1058 omap_hsmmc_dma_cleanup(host,
1059 -ETIMEDOUT);
4a694dc9 1060 host->response_busy = 0;
70a3341a 1061 omap_hsmmc_reset_controller_fsm(host, SRD);
c232f457 1062 }
a45c6cb8
MC		 1063 }
1064 if ((status & DATA_TIMEOUT) ||
1065 (status & DATA_CRC)) {
4a694dc9
AH		 1066 if (host->data || host->response_busy) {
1067 int err = (status & DATA_TIMEOUT) ?
1068 -ETIMEDOUT : -EILSEQ;
1069
1070 if (host->data)
70a3341a 1071 omap_hsmmc_dma_cleanup(host, err);
a45c6cb8 1072 else
4a694dc9
AH		 1073 host->mrq->cmd->error = err;
1074 host->response_busy = 0;
70a3341a 1075 omap_hsmmc_reset_controller_fsm(host, SRD);
a45c6cb8
MC		 1076 end_trans = 1;
1077 }
1078 }
1079 if (status & CARD_ERR) {
1080 dev_dbg(mmc_dev(host->mmc),
1081 "Ignoring card err CMD%d\n", host->cmd->opcode);
1082 if (host->cmd)
1083 end_cmd = 1;
1084 if (host->data)
1085 end_trans = 1;
1086 }
1087 }
1088
1089 OMAP_HSMMC_WRITE(host->base, STAT, status);
1090
a8fe29d8 1091 if (end_cmd || ((status & CC) && host->cmd))
70a3341a 1092 omap_hsmmc_cmd_done(host, host->cmd);
0a40e647 1093 if ((end_trans || (status & TC)) && host->mrq)
70a3341a 1094 omap_hsmmc_xfer_done(host, data);
b417577d 1095}
a45c6cb8 1096
b417577d
AH		 1097/*
1098 * MMC controller IRQ handler
1099 */
1100static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1101{
1102 struct omap_hsmmc_host *host = dev_id;
1103 int status;
1104
1105 status = OMAP_HSMMC_READ(host->base, STAT);
1106 do {
1107 omap_hsmmc_do_irq(host, status);
1108 /* Flush posted write */
1109 status = OMAP_HSMMC_READ(host->base, STAT);
1110 } while (status & INT_EN_MASK);
4dffd7a2 1111
a45c6cb8
MC		 1112 return IRQ_HANDLED;
1113}
1114
70a3341a 1115static void set_sd_bus_power(struct omap_hsmmc_host *host)
e13bb300
AH		 1116{
1117 unsigned long i;
1118
1119 OMAP_HSMMC_WRITE(host->base, HCTL,
1120 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1121 for (i = 0; i < loops_per_jiffy; i++) {
1122 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1123 break;
1124 cpu_relax();
1125 }
1126}
1127
a45c6cb8 1128/*
eb250826
DB		 1129 * Switch MMC interface voltage ... only relevant for MMC1.
1130 *
1131 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1132 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1133 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8 1134 */
70a3341a 1135static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
a45c6cb8
MC		 1136{
1137 u32 reg_val = 0;
1138 int ret;
1139
1140 /* Disable the clocks */
1141 clk_disable(host->fclk);
1142 clk_disable(host->iclk);
2bec0893
AH		 1143 if (host->got_dbclk)
1144 clk_disable(host->dbclk);
a45c6cb8
MC		 1145
1146 /* Turn the power off */
1147 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
a45c6cb8
MC		 1148
1149 /* Turn the power ON with given VDD 1.8 or 3.0v */
2bec0893
AH		 1150 if (!ret)
1151 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1152 vdd);
1153 clk_enable(host->iclk);
1154 clk_enable(host->fclk);
1155 if (host->got_dbclk)
1156 clk_enable(host->dbclk);
1157
a45c6cb8
MC		 1158 if (ret != 0)
1159 goto err;
1160
a45c6cb8
MC		 1161 OMAP_HSMMC_WRITE(host->base, HCTL,
1162 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1163 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 1164
a45c6cb8
MC		 1165 /*
1166 * If a MMC dual voltage card is detected, the set_ios fn calls
1167 * this fn with VDD bit set for 1.8V. Upon card removal from the
70a3341a 1168 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
a45c6cb8 1169 *
eb250826
DB		 1170 * Cope with a bit of slop in the range ... per data sheets:
1171 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1172 * but recommended values are 1.71V to 1.89V
1173 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1174 * but recommended values are 2.7V to 3.3V
1175 *
1176 * Board setup code shouldn't permit anything very out-of-range.
1177 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1178 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 1179 */
eb250826 1180 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 1181 reg_val |= SDVS18;
eb250826
DB		 1182 else
1183 reg_val |= SDVS30;
a45c6cb8
MC		 1184
1185 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 1186 set_sd_bus_power(host);
a45c6cb8
MC		 1187
1188 return 0;
1189err:
1190 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1191 return ret;
1192}
1193
b62f6228
AH		 1194/* Protect the card while the cover is open */
1195static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1196{
1197 if (!mmc_slot(host).get_cover_state)
1198 return;
1199
1200 host->reqs_blocked = 0;
1201 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1202 if (host->protect_card) {
1203 printk(KERN_INFO "%s: cover is closed, "
1204 "card is now accessible\n",
1205 mmc_hostname(host->mmc));
1206 host->protect_card = 0;
1207 }
1208 } else {
1209 if (!host->protect_card) {
1210 printk(KERN_INFO "%s: cover is open, "
1211 "card is now inaccessible\n",
1212 mmc_hostname(host->mmc));
1213 host->protect_card = 1;
1214 }
1215 }
1216}
1217
a45c6cb8
MC		 1218/*
1219 * Work Item to notify the core about card insertion/removal
1220 */
70a3341a 1221static void omap_hsmmc_detect(struct work_struct *work)
a45c6cb8 1222{
70a3341a
DK		 1223 struct omap_hsmmc_host *host =
1224 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
249d0fa9 1225 struct omap_mmc_slot_data *slot = &mmc_slot(host);
a6b2240d
AH		 1226 int carddetect;
1227
1228 if (host->suspended)
1229 return;
1230
1231 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
249d0fa9 1232
191d1f1d 1233 if (slot->card_detect)
db0fefc5 1234 carddetect = slot->card_detect(host->dev, host->slot_id);
b62f6228
AH		 1235 else {
1236 omap_hsmmc_protect_card(host);
a6b2240d 1237 carddetect = -ENOSYS;
b62f6228 1238 }
a45c6cb8 1239
cdeebadd 1240 if (carddetect)
a45c6cb8 1241 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
cdeebadd 1242 else
a45c6cb8 1243 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
a45c6cb8
MC		 1244}
1245
1246/*
1247 * ISR for handling card insertion and removal
1248 */
70a3341a 1249static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
a45c6cb8 1250{
70a3341a 1251 struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
a45c6cb8 1252
a6b2240d
AH		 1253 if (host->suspended)
1254 return IRQ_HANDLED;
a45c6cb8
MC		 1255 schedule_work(&host->mmc_carddetect_work);
1256
1257 return IRQ_HANDLED;
1258}
1259
70a3341a 1260static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1261 struct mmc_data *data)
1262{
1263 int sync_dev;
1264
f3e2f1dd
GI		 1265 if (data->flags & MMC_DATA_WRITE)
1266 sync_dev = host->dma_line_tx;
1267 else
1268 sync_dev = host->dma_line_rx;
0ccd76d4
JY		 1269 return sync_dev;
1270}
1271
70a3341a 1272static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1273 struct mmc_data *data,
1274 struct scatterlist *sgl)
1275{
1276 int blksz, nblk, dma_ch;
1277
1278 dma_ch = host->dma_ch;
1279 if (data->flags & MMC_DATA_WRITE) {
1280 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1281 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1282 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1283 sg_dma_address(sgl), 0, 0);
1284 } else {
1285 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
191d1f1d 1286 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
0ccd76d4
JY		 1287 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1288 sg_dma_address(sgl), 0, 0);
1289 }
1290
1291 blksz = host->data->blksz;
1292 nblk = sg_dma_len(sgl) / blksz;
1293
1294 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1295 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
70a3341a 1296 omap_hsmmc_get_dma_sync_dev(host, data),
0ccd76d4
JY		 1297 !(data->flags & MMC_DATA_WRITE));
1298
1299 omap_start_dma(dma_ch);
1300}
1301
a45c6cb8
MC		 1302/*
1303 * DMA call back function
1304 */
b417577d 1305static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
a45c6cb8 1306{
b417577d
AH		 1307 struct omap_hsmmc_host *host = cb_data;
1308 struct mmc_data *data = host->mrq->data;
1309 int dma_ch, req_in_progress;
a45c6cb8 1310
f3584e5e
V		 1311 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1312 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1313 ch_status);
1314 return;
1315 }
a45c6cb8 1316
b417577d
AH		 1317 spin_lock(&host->irq_lock);
1318 if (host->dma_ch < 0) {
1319 spin_unlock(&host->irq_lock);
a45c6cb8 1320 return;
b417577d 1321 }
a45c6cb8 1322
0ccd76d4
JY		 1323 host->dma_sg_idx++;
1324 if (host->dma_sg_idx < host->dma_len) {
1325 /* Fire up the next transfer. */
b417577d
AH		 1326 omap_hsmmc_config_dma_params(host, data,
1327 data->sg + host->dma_sg_idx);
1328 spin_unlock(&host->irq_lock);
0ccd76d4
JY		 1329 return;
1330 }
1331
b417577d
AH		 1332 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
1333 omap_hsmmc_get_dma_dir(host, data));
1334
1335 req_in_progress = host->req_in_progress;
1336 dma_ch = host->dma_ch;
a45c6cb8 1337 host->dma_ch = -1;
b417577d
AH		 1338 spin_unlock(&host->irq_lock);
1339
1340 omap_free_dma(dma_ch);
1341
1342 /* If DMA has finished after TC, complete the request */
1343 if (!req_in_progress) {
1344 struct mmc_request *mrq = host->mrq;
1345
1346 host->mrq = NULL;
1347 mmc_request_done(host->mmc, mrq);
1348 }
a45c6cb8
MC		 1349}
1350
a45c6cb8
MC		 1351/*
1352 * Routine to configure and start DMA for the MMC card
1353 */
70a3341a
DK		 1354static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1355 struct mmc_request *req)
a45c6cb8 1356{
b417577d 1357 int dma_ch = 0, ret = 0, i;
a45c6cb8
MC		 1358 struct mmc_data *data = req->data;
1359
0ccd76d4 1360 /* Sanity check: all the SG entries must be aligned by block size. */
a3f406f8 1361 for (i = 0; i < data->sg_len; i++) {
0ccd76d4
JY		 1362 struct scatterlist *sgl;
1363
1364 sgl = data->sg + i;
1365 if (sgl->length % data->blksz)
1366 return -EINVAL;
1367 }
1368 if ((data->blksz % 4) != 0)
1369 /* REVISIT: The MMC buffer increments only when MSB is written.
1370 * Return error for blksz which is non multiple of four.
1371 */
1372 return -EINVAL;
1373
b417577d 1374 BUG_ON(host->dma_ch != -1);
a45c6cb8 1375
70a3341a
DK		 1376 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1377 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
a45c6cb8 1378 if (ret != 0) {
0ccd76d4 1379 dev_err(mmc_dev(host->mmc),
a45c6cb8
MC		 1380 "%s: omap_request_dma() failed with %d\n",
1381 mmc_hostname(host->mmc), ret);
1382 return ret;
1383 }
1384
1385 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
70a3341a 1386 data->sg_len, omap_hsmmc_get_dma_dir(host, data));
a45c6cb8 1387 host->dma_ch = dma_ch;
0ccd76d4 1388 host->dma_sg_idx = 0;
a45c6cb8 1389
70a3341a 1390 omap_hsmmc_config_dma_params(host, data, data->sg);
a45c6cb8 1391
a45c6cb8
MC		 1392 return 0;
1393}
1394
70a3341a 1395static void set_data_timeout(struct omap_hsmmc_host *host,
e2bf08d6
AH		 1396 unsigned int timeout_ns,
1397 unsigned int timeout_clks)
a45c6cb8
MC		 1398{
1399 unsigned int timeout, cycle_ns;
1400 uint32_t reg, clkd, dto = 0;
1401
1402 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1403 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1404 if (clkd == 0)
1405 clkd = 1;
1406
1407 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
e2bf08d6
AH		 1408 timeout = timeout_ns / cycle_ns;
1409 timeout += timeout_clks;
a45c6cb8
MC		 1410 if (timeout) {
1411 while ((timeout & 0x80000000) == 0) {
1412 dto += 1;
1413 timeout <<= 1;
1414 }
1415 dto = 31 - dto;
1416 timeout <<= 1;
1417 if (timeout && dto)
1418 dto += 1;
1419 if (dto >= 13)
1420 dto -= 13;
1421 else
1422 dto = 0;
1423 if (dto > 14)
1424 dto = 14;
1425 }
1426
1427 reg &= ~DTO_MASK;
1428 reg |= dto << DTO_SHIFT;
1429 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1430}
1431
1432/*
1433 * Configure block length for MMC/SD cards and initiate the transfer.
1434 */
1435static int
70a3341a 1436omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
a45c6cb8
MC		 1437{
1438 int ret;
1439 host->data = req->data;
1440
1441 if (req->data == NULL) {
a45c6cb8 1442 OMAP_HSMMC_WRITE(host->base, BLK, 0);
e2bf08d6
AH		 1443 /*
1444 * Set an arbitrary 100ms data timeout for commands with
1445 * busy signal.
1446 */
1447 if (req->cmd->flags & MMC_RSP_BUSY)
1448 set_data_timeout(host, 100000000U, 0);
a45c6cb8
MC		 1449 return 0;
1450 }
1451
1452 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1453 | (req->data->blocks << 16));
e2bf08d6 1454 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
a45c6cb8 1455
a45c6cb8 1456 if (host->use_dma) {
70a3341a 1457 ret = omap_hsmmc_start_dma_transfer(host, req);
a45c6cb8
MC		 1458 if (ret != 0) {
1459 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1460 return ret;
1461 }
1462 }
1463 return 0;
1464}
1465
1466/*
1467 * Request function. for read/write operation
1468 */
70a3341a 1469static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
a45c6cb8 1470{
70a3341a 1471 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3f406f8 1472 int err;
a45c6cb8 1473
b417577d
AH		 1474 BUG_ON(host->req_in_progress);
1475 BUG_ON(host->dma_ch != -1);
1476 if (host->protect_card) {
1477 if (host->reqs_blocked < 3) {
1478 /*
1479 * Ensure the controller is left in a consistent
1480 * state by resetting the command and data state
1481 * machines.
1482 */
1483 omap_hsmmc_reset_controller_fsm(host, SRD);
1484 omap_hsmmc_reset_controller_fsm(host, SRC);
1485 host->reqs_blocked += 1;
1486 }
1487 req->cmd->error = -EBADF;
1488 if (req->data)
1489 req->data->error = -EBADF;
1490 req->cmd->retries = 0;
1491 mmc_request_done(mmc, req);
1492 return;
1493 } else if (host->reqs_blocked)
1494 host->reqs_blocked = 0;
a45c6cb8
MC		 1495 WARN_ON(host->mrq != NULL);
1496 host->mrq = req;
70a3341a 1497 err = omap_hsmmc_prepare_data(host, req);
a3f406f8
JL		 1498 if (err) {
1499 req->cmd->error = err;
1500 if (req->data)
1501 req->data->error = err;
1502 host->mrq = NULL;
1503 mmc_request_done(mmc, req);
1504 return;
1505 }
1506
70a3341a 1507 omap_hsmmc_start_command(host, req->cmd, req->data);
a45c6cb8
MC		 1508}
1509
a45c6cb8 1510/* Routine to configure clock values. Exposed API to core */
70a3341a 1511static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
a45c6cb8 1512{
70a3341a 1513 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8
MC		 1514 u16 dsor = 0;
1515 unsigned long regval;
1516 unsigned long timeout;
73153010 1517 u32 con;
a3621465 1518 int do_send_init_stream = 0;
a45c6cb8 1519
5e2ea617
AH		 1520 mmc_host_enable(host->mmc);
1521
a3621465
AH		 1522 if (ios->power_mode != host->power_mode) {
1523 switch (ios->power_mode) {
1524 case MMC_POWER_OFF:
1525 mmc_slot(host).set_power(host->dev, host->slot_id,
1526 0, 0);
623821f7 1527 host->vdd = 0;
a3621465
AH		 1528 break;
1529 case MMC_POWER_UP:
1530 mmc_slot(host).set_power(host->dev, host->slot_id,
1531 1, ios->vdd);
623821f7 1532 host->vdd = ios->vdd;
a3621465
AH		 1533 break;
1534 case MMC_POWER_ON:
1535 do_send_init_stream = 1;
1536 break;
1537 }
1538 host->power_mode = ios->power_mode;
a45c6cb8
MC		 1539 }
1540
dd498eff
DK		 1541 /* FIXME: set registers based only on changes to ios */
1542
73153010 1543 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 1544 switch (mmc->ios.bus_width) {
73153010
JL		 1545 case MMC_BUS_WIDTH_8:
1546 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1547 break;
a45c6cb8 1548 case MMC_BUS_WIDTH_4:
73153010 1549 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 1550 OMAP_HSMMC_WRITE(host->base, HCTL,
1551 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1552 break;
1553 case MMC_BUS_WIDTH_1:
73153010 1554 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 1555 OMAP_HSMMC_WRITE(host->base, HCTL,
1556 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1557 break;
1558 }
1559
1560 if (host->id == OMAP_MMC1_DEVID) {
eb250826
DB		 1561 /* Only MMC1 can interface at 3V without some flavor
1562 * of external transceiver; but they all handle 1.8V.
1563 */
a45c6cb8
MC		 1564 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1565 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1566 /*
1567 * The mmc_select_voltage fn of the core does
1568 * not seem to set the power_mode to
1569 * MMC_POWER_UP upon recalculating the voltage.
1570 * vdd 1.8v.
1571 */
70a3341a
DK		 1572 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1573 dev_dbg(mmc_dev(host->mmc),
a45c6cb8
MC		 1574 "Switch operation failed\n");
1575 }
1576 }
1577
1578 if (ios->clock) {
1579 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1580 if (dsor < 1)
1581 dsor = 1;
1582
1583 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1584 dsor++;
1585
1586 if (dsor > 250)
1587 dsor = 250;
1588 }
70a3341a 1589 omap_hsmmc_stop_clock(host);
a45c6cb8
MC		 1590 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1591 regval = regval & ~(CLKD_MASK);
1592 regval = regval | (dsor << 6) | (DTO << 16);
1593 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1594 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1595 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1596
1597 /* Wait till the ICS bit is set */
1598 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
11dd62a7 1599 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
a45c6cb8
MC		 1600 && time_before(jiffies, timeout))
1601 msleep(1);
1602
1603 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1604 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1605
a3621465 1606 if (do_send_init_stream)
a45c6cb8
MC		 1607 send_init_stream(host);
1608
abb28e73 1609 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 1610 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
abb28e73
DK		 1611 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1612 else
1613 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
5e2ea617 1614
dd498eff
DK		 1615 if (host->power_mode == MMC_POWER_OFF)
1616 mmc_host_disable(host->mmc);
1617 else
1618 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 1619}
1620
1621static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1622{
70a3341a 1623 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1624
191d1f1d 1625 if (!mmc_slot(host).card_detect)
a45c6cb8 1626 return -ENOSYS;
db0fefc5 1627 return mmc_slot(host).card_detect(host->dev, host->slot_id);
a45c6cb8
MC		 1628}
1629
1630static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1631{
70a3341a 1632 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1633
191d1f1d 1634 if (!mmc_slot(host).get_ro)
a45c6cb8 1635 return -ENOSYS;
191d1f1d 1636 return mmc_slot(host).get_ro(host->dev, 0);
a45c6cb8
MC		 1637}
1638
4816858c
GI		 1639static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1640{
1641 struct omap_hsmmc_host *host = mmc_priv(mmc);
1642
1643 if (mmc_slot(host).init_card)
1644 mmc_slot(host).init_card(card);
1645}
1646
70a3341a 1647static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1b331e69
KK		 1648{
1649 u32 hctl, capa, value;
1650
1651 /* Only MMC1 supports 3.0V */
1652 if (host->id == OMAP_MMC1_DEVID) {
1653 hctl = SDVS30;
1654 capa = VS30 | VS18;
1655 } else {
1656 hctl = SDVS18;
1657 capa = VS18;
1658 }
1659
1660 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1661 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1662
1663 value = OMAP_HSMMC_READ(host->base, CAPA);
1664 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1665
1666 /* Set the controller to AUTO IDLE mode */
1667 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1668 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1669
1670 /* Set SD bus power bit */
e13bb300 1671 set_sd_bus_power(host);
1b331e69
KK		 1672}
1673
dd498eff
DK		 1674/*
1675 * Dynamic power saving handling, FSM:
13189e78
JL		 1676 * ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF
1677 * ^___________| | |
1678 * |______________________|______________________|
dd498eff
DK		 1679 *
1680 * ENABLED: mmc host is fully functional
1681 * DISABLED: fclk is off
13189e78
JL		 1682 * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep
1683 * REGSLEEP: fclk is off, voltage regulator is asleep
1684 * OFF: fclk is off, voltage regulator is off
dd498eff
DK		 1685 *
1686 * Transition handlers return the timeout for the next state transition
1687 * or negative error.
1688 */
1689
13189e78 1690enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF};
dd498eff
DK		 1691
1692/* Handler for [ENABLED -> DISABLED] transition */
70a3341a 1693static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host)
dd498eff 1694{
70a3341a 1695 omap_hsmmc_context_save(host);
dd498eff
DK		 1696 clk_disable(host->fclk);
1697 host->dpm_state = DISABLED;
1698
1699 dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n");
1700
1701 if (host->power_mode == MMC_POWER_OFF)
1702 return 0;
1703
4380eea2 1704 return OMAP_MMC_SLEEP_TIMEOUT;
dd498eff
DK		 1705}
1706
13189e78 1707/* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */
70a3341a 1708static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host)
dd498eff 1709{
13189e78 1710 int err, new_state;
dd498eff
DK		 1711
1712 if (!mmc_try_claim_host(host->mmc))
1713 return 0;
1714
1715 clk_enable(host->fclk);
70a3341a 1716 omap_hsmmc_context_restore(host);
13189e78
JL		 1717 if (mmc_card_can_sleep(host->mmc)) {
1718 err = mmc_card_sleep(host->mmc);
1719 if (err < 0) {
1720 clk_disable(host->fclk);
1721 mmc_release_host(host->mmc);
1722 return err;
1723 }
1724 new_state = CARDSLEEP;
70a3341a 1725 } else {
13189e78 1726 new_state = REGSLEEP;
70a3341a 1727 }
13189e78
JL		 1728 if (mmc_slot(host).set_sleep)
1729 mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0,
1730 new_state == CARDSLEEP);
1731 /* FIXME: turn off bus power and perhaps interrupts too */
1732 clk_disable(host->fclk);
1733 host->dpm_state = new_state;
1734
1735 mmc_release_host(host->mmc);
1736
1737 dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n",
1738 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
dd498eff 1739
1df58db8
AH		 1740 if (mmc_slot(host).no_off)
1741 return 0;
1742
dd498eff
DK		 1743 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1744 mmc_slot(host).card_detect ||
1745 (mmc_slot(host).get_cover_state &&
13189e78 1746 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))
4380eea2 1747 return OMAP_MMC_OFF_TIMEOUT;
13189e78
JL		 1748
1749 return 0;
1750}
1751
1752/* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */
70a3341a 1753static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host)
13189e78
JL		 1754{
1755 if (!mmc_try_claim_host(host->mmc))
1756 return 0;
1757
1df58db8
AH		 1758 if (mmc_slot(host).no_off)
1759 return 0;
1760
13189e78
JL		 1761 if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1762 mmc_slot(host).card_detect ||
1763 (mmc_slot(host).get_cover_state &&
1764 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) {
1765 mmc_release_host(host->mmc);
1766 return 0;
623821f7 1767 }
dd498eff 1768
13189e78
JL		 1769 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1770 host->vdd = 0;
1771 host->power_mode = MMC_POWER_OFF;
dd498eff 1772
13189e78
JL		 1773 dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n",
1774 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
dd498eff 1775
13189e78 1776 host->dpm_state = OFF;
dd498eff
DK		 1777
1778 mmc_release_host(host->mmc);
1779
1780 return 0;
1781}
1782
1783/* Handler for [DISABLED -> ENABLED] transition */
70a3341a 1784static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host *host)
dd498eff
DK		 1785{
1786 int err;
1787
1788 err = clk_enable(host->fclk);
1789 if (err < 0)
1790 return err;
1791
70a3341a 1792 omap_hsmmc_context_restore(host);
dd498eff
DK		 1793 host->dpm_state = ENABLED;
1794
1795 dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n");
1796
1797 return 0;
1798}
1799
13189e78 1800/* Handler for [SLEEP -> ENABLED] transition */
70a3341a 1801static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host)
dd498eff 1802{
13189e78
JL		 1803 if (!mmc_try_claim_host(host->mmc))
1804 return 0;
dd498eff 1805
13189e78 1806 clk_enable(host->fclk);
70a3341a 1807 omap_hsmmc_context_restore(host);
13189e78
JL		 1808 if (mmc_slot(host).set_sleep)
1809 mmc_slot(host).set_sleep(host->dev, host->slot_id, 0,
1810 host->vdd, host->dpm_state == CARDSLEEP);
1811 if (mmc_card_can_sleep(host->mmc))
1812 mmc_card_awake(host->mmc);
1813
1814 dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n",
1815 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
dd498eff
DK		 1816
1817 host->dpm_state = ENABLED;
1818
13189e78 1819 mmc_release_host(host->mmc);
dd498eff
DK		 1820
1821 return 0;
1822}
1823
13189e78 1824/* Handler for [OFF -> ENABLED] transition */
70a3341a 1825static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host *host)
623821f7 1826{
623821f7 1827 clk_enable(host->fclk);
623821f7 1828
70a3341a
DK		 1829 omap_hsmmc_context_restore(host);
1830 omap_hsmmc_conf_bus_power(host);
13189e78 1831 mmc_power_restore_host(host->mmc);
623821f7
AH		 1832
1833 host->dpm_state = ENABLED;
1834
13189e78
JL		 1835 dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n");
1836
623821f7
AH		 1837 return 0;
1838}
1839
dd498eff
DK		 1840/*
1841 * Bring MMC host to ENABLED from any other PM state.
1842 */
70a3341a 1843static int omap_hsmmc_enable(struct mmc_host *mmc)
dd498eff 1844{
70a3341a 1845 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff
DK		 1846
1847 switch (host->dpm_state) {
1848 case DISABLED:
70a3341a 1849 return omap_hsmmc_disabled_to_enabled(host);
13189e78 1850 case CARDSLEEP:
623821f7 1851 case REGSLEEP:
70a3341a 1852 return omap_hsmmc_sleep_to_enabled(host);
dd498eff 1853 case OFF:
70a3341a 1854 return omap_hsmmc_off_to_enabled(host);
dd498eff
DK		 1855 default:
1856 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1857 return -EINVAL;
1858 }
1859}
1860
1861/*
1862 * Bring MMC host in PM state (one level deeper).
1863 */
70a3341a 1864static int omap_hsmmc_disable(struct mmc_host *mmc, int lazy)
dd498eff 1865{
70a3341a 1866 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff
DK		 1867
1868 switch (host->dpm_state) {
1869 case ENABLED: {
1870 int delay;
1871
70a3341a 1872 delay = omap_hsmmc_enabled_to_disabled(host);
dd498eff
DK		 1873 if (lazy || delay < 0)
1874 return delay;
1875 return 0;
1876 }
1877 case DISABLED:
70a3341a 1878 return omap_hsmmc_disabled_to_sleep(host);
13189e78
JL		 1879 case CARDSLEEP:
1880 case REGSLEEP:
70a3341a 1881 return omap_hsmmc_sleep_to_off(host);
dd498eff
DK		 1882 default:
1883 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1884 return -EINVAL;
1885 }
1886}
1887
70a3341a 1888static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
dd498eff 1889{
70a3341a 1890 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff
DK		 1891 int err;
1892
1893 err = clk_enable(host->fclk);
1894 if (err)
1895 return err;
1896 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
70a3341a 1897 omap_hsmmc_context_restore(host);
dd498eff
DK		 1898 return 0;
1899}
1900
70a3341a 1901static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
dd498eff 1902{
70a3341a 1903 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1904
70a3341a 1905 omap_hsmmc_context_save(host);
dd498eff
DK		 1906 clk_disable(host->fclk);
1907 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
1908 return 0;
1909}
1910
70a3341a
DK		 1911static const struct mmc_host_ops omap_hsmmc_ops = {
1912 .enable = omap_hsmmc_enable_fclk,
1913 .disable = omap_hsmmc_disable_fclk,
1914 .request = omap_hsmmc_request,
1915 .set_ios = omap_hsmmc_set_ios,
dd498eff
DK		 1916 .get_cd = omap_hsmmc_get_cd,
1917 .get_ro = omap_hsmmc_get_ro,
4816858c 1918 .init_card = omap_hsmmc_init_card,
dd498eff
DK		 1919 /* NYET -- enable_sdio_irq */
1920};
1921
70a3341a
DK		 1922static const struct mmc_host_ops omap_hsmmc_ps_ops = {
1923 .enable = omap_hsmmc_enable,
1924 .disable = omap_hsmmc_disable,
1925 .request = omap_hsmmc_request,
1926 .set_ios = omap_hsmmc_set_ios,
a45c6cb8
MC		 1927 .get_cd = omap_hsmmc_get_cd,
1928 .get_ro = omap_hsmmc_get_ro,
4816858c 1929 .init_card = omap_hsmmc_init_card,
a45c6cb8
MC		 1930 /* NYET -- enable_sdio_irq */
1931};
1932
d900f712
DK		 1933#ifdef CONFIG_DEBUG_FS
1934
70a3341a 1935static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
d900f712
DK		 1936{
1937 struct mmc_host *mmc = s->private;
70a3341a 1938 struct omap_hsmmc_host *host = mmc_priv(mmc);
11dd62a7
DK		 1939 int context_loss = 0;
1940
70a3341a
DK		 1941 if (host->pdata->get_context_loss_count)
1942 context_loss = host->pdata->get_context_loss_count(host->dev);
d900f712 1943
5e2ea617
AH		 1944 seq_printf(s, "mmc%d:\n"
1945 " enabled:\t%d\n"
dd498eff 1946 " dpm_state:\t%d\n"
5e2ea617 1947 " nesting_cnt:\t%d\n"
11dd62a7 1948 " ctx_loss:\t%d:%d\n"
5e2ea617 1949 "\nregs:\n",
dd498eff
DK		 1950 mmc->index, mmc->enabled ? 1 : 0,
1951 host->dpm_state, mmc->nesting_cnt,
11dd62a7 1952 host->context_loss, context_loss);
5e2ea617 1953
13189e78 1954 if (host->suspended || host->dpm_state == OFF) {
dd498eff
DK		 1955 seq_printf(s, "host suspended, can't read registers\n");
1956 return 0;
1957 }
1958
5e2ea617
AH		 1959 if (clk_enable(host->fclk) != 0) {
1960 seq_printf(s, "can't read the regs\n");
dd498eff 1961 return 0;
5e2ea617 1962 }
d900f712
DK		 1963
1964 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1965 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1966 seq_printf(s, "CON:\t\t0x%08x\n",
1967 OMAP_HSMMC_READ(host->base, CON));
1968 seq_printf(s, "HCTL:\t\t0x%08x\n",
1969 OMAP_HSMMC_READ(host->base, HCTL));
1970 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1971 OMAP_HSMMC_READ(host->base, SYSCTL));
1972 seq_printf(s, "IE:\t\t0x%08x\n",
1973 OMAP_HSMMC_READ(host->base, IE));
1974 seq_printf(s, "ISE:\t\t0x%08x\n",
1975 OMAP_HSMMC_READ(host->base, ISE));
1976 seq_printf(s, "CAPA:\t\t0x%08x\n",
1977 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617
AH		 1978
1979 clk_disable(host->fclk);
dd498eff 1980
d900f712
DK		 1981 return 0;
1982}
1983
70a3341a 1984static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
d900f712 1985{
70a3341a 1986 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
d900f712
DK		 1987}
1988
1989static const struct file_operations mmc_regs_fops = {
70a3341a 1990 .open = omap_hsmmc_regs_open,
d900f712
DK		 1991 .read = seq_read,
1992 .llseek = seq_lseek,
1993 .release = single_release,
1994};
1995
70a3341a 1996static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1997{
1998 if (mmc->debugfs_root)
1999 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
2000 mmc, &mmc_regs_fops);
2001}
2002
2003#else
2004
70a3341a 2005static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 2006{
2007}
2008
2009#endif
2010
70a3341a 2011static int __init omap_hsmmc_probe(struct platform_device *pdev)
a45c6cb8
MC		 2012{
2013 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
2014 struct mmc_host *mmc;
70a3341a 2015 struct omap_hsmmc_host *host = NULL;
a45c6cb8 2016 struct resource *res;
db0fefc5 2017 int ret, irq;
a45c6cb8
MC		 2018
2019 if (pdata == NULL) {
2020 dev_err(&pdev->dev, "Platform Data is missing\n");
2021 return -ENXIO;
2022 }
2023
2024 if (pdata->nr_slots == 0) {
2025 dev_err(&pdev->dev, "No Slots\n");
2026 return -ENXIO;
2027 }
2028
2029 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2030 irq = platform_get_irq(pdev, 0);
2031 if (res == NULL || irq < 0)
2032 return -ENXIO;
2033
91a0b089 2034 res->start += pdata->reg_offset;
2035 res->end += pdata->reg_offset;
a45c6cb8
MC		 2036 res = request_mem_region(res->start, res->end - res->start + 1,
2037 pdev->name);
2038 if (res == NULL)
2039 return -EBUSY;
2040
db0fefc5
AH		 2041 ret = omap_hsmmc_gpio_init(pdata);
2042 if (ret)
2043 goto err;
2044
70a3341a 2045 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
a45c6cb8
MC		 2046 if (!mmc) {
2047 ret = -ENOMEM;
db0fefc5 2048 goto err_alloc;
a45c6cb8
MC		 2049 }
2050
2051 host = mmc_priv(mmc);
2052 host->mmc = mmc;
2053 host->pdata = pdata;
2054 host->dev = &pdev->dev;
2055 host->use_dma = 1;
2056 host->dev->dma_mask = &pdata->dma_mask;
2057 host->dma_ch = -1;
2058 host->irq = irq;
2059 host->id = pdev->id;
2060 host->slot_id = 0;
2061 host->mapbase = res->start;
2062 host->base = ioremap(host->mapbase, SZ_4K);
6da20c89 2063 host->power_mode = MMC_POWER_OFF;
a45c6cb8
MC		 2064
2065 platform_set_drvdata(pdev, host);
70a3341a 2066 INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
a45c6cb8 2067
191d1f1d 2068 if (mmc_slot(host).power_saving)
70a3341a 2069 mmc->ops = &omap_hsmmc_ps_ops;
dd498eff 2070 else
70a3341a 2071 mmc->ops = &omap_hsmmc_ops;
dd498eff 2072
e0eb2424
AH		 2073 /*
2074 * If regulator_disable can only put vcc_aux to sleep then there is
2075 * no off state.
2076 */
2077 if (mmc_slot(host).vcc_aux_disable_is_sleep)
2078 mmc_slot(host).no_off = 1;
2079
a45c6cb8
MC		 2080 mmc->f_min = 400000;
2081 mmc->f_max = 52000000;
2082
4dffd7a2 2083 spin_lock_init(&host->irq_lock);
a45c6cb8 2084
6f7607cc 2085 host->iclk = clk_get(&pdev->dev, "ick");
a45c6cb8
MC		 2086 if (IS_ERR(host->iclk)) {
2087 ret = PTR_ERR(host->iclk);
2088 host->iclk = NULL;
2089 goto err1;
2090 }
6f7607cc 2091 host->fclk = clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 2092 if (IS_ERR(host->fclk)) {
2093 ret = PTR_ERR(host->fclk);
2094 host->fclk = NULL;
2095 clk_put(host->iclk);
2096 goto err1;
2097 }
2098
70a3341a 2099 omap_hsmmc_context_save(host);
11dd62a7 2100
5e2ea617 2101 mmc->caps |= MMC_CAP_DISABLE;
dd498eff
DK		 2102 mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT);
2103 /* we start off in DISABLED state */
2104 host->dpm_state = DISABLED;
2105
5e2ea617 2106 if (mmc_host_enable(host->mmc) != 0) {
a45c6cb8
MC		 2107 clk_put(host->iclk);
2108 clk_put(host->fclk);
2109 goto err1;
2110 }
2111
2112 if (clk_enable(host->iclk) != 0) {
5e2ea617 2113 mmc_host_disable(host->mmc);
a45c6cb8
MC		 2114 clk_put(host->iclk);
2115 clk_put(host->fclk);
2116 goto err1;
2117 }
2118
2bec0893
AH		 2119 if (cpu_is_omap2430()) {
2120 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
2121 /*
2122 * MMC can still work without debounce clock.
2123 */
2124 if (IS_ERR(host->dbclk))
2125 dev_warn(mmc_dev(host->mmc),
2126 "Failed to get debounce clock\n");
a45c6cb8 2127 else
2bec0893
AH		 2128 host->got_dbclk = 1;
2129
2130 if (host->got_dbclk)
2131 if (clk_enable(host->dbclk) != 0)
2132 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
2133 " clk failed\n");
2134 }
a45c6cb8 2135
0ccd76d4
JY		 2136 /* Since we do only SG emulation, we can have as many segs
2137 * as we want. */
a36274e0 2138 mmc->max_segs = 1024;
0ccd76d4 2139
a45c6cb8
MC		 2140 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
2141 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
2142 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2143 mmc->max_seg_size = mmc->max_req_size;
2144
13189e78 2145 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
93caf8e6 2146 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
a45c6cb8 2147
3a63833e
SG		 2148 mmc->caps |= mmc_slot(host).caps;
2149 if (mmc->caps & MMC_CAP_8_BIT_DATA)
a45c6cb8
MC		 2150 mmc->caps |= MMC_CAP_4_BIT_DATA;
2151
191d1f1d 2152 if (mmc_slot(host).nonremovable)
23d99bb9
AH		 2153 mmc->caps |= MMC_CAP_NONREMOVABLE;
2154
70a3341a 2155 omap_hsmmc_conf_bus_power(host);
a45c6cb8 2156
f3e2f1dd
GI		 2157 /* Select DMA lines */
2158 switch (host->id) {
2159 case OMAP_MMC1_DEVID:
2160 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
2161 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
2162 break;
2163 case OMAP_MMC2_DEVID:
2164 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
2165 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
2166 break;
2167 case OMAP_MMC3_DEVID:
2168 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2169 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2170 break;
82cf818d 2171 case OMAP_MMC4_DEVID:
2172 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2173 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2174 break;
2175 case OMAP_MMC5_DEVID:
2176 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2177 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2178 break;
f3e2f1dd
GI		 2179 default:
2180 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2181 goto err_irq;
2182 }
a45c6cb8
MC		 2183
2184 /* Request IRQ for MMC operations */
70a3341a 2185 ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED,
a45c6cb8
MC		 2186 mmc_hostname(mmc), host);
2187 if (ret) {
2188 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2189 goto err_irq;
2190 }
2191
2192 if (pdata->init != NULL) {
2193 if (pdata->init(&pdev->dev) != 0) {
70a3341a
DK		 2194 dev_dbg(mmc_dev(host->mmc),
2195 "Unable to configure MMC IRQs\n");
a45c6cb8
MC		 2196 goto err_irq_cd_init;
2197 }
2198 }
db0fefc5 2199
b702b106 2200 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
db0fefc5
AH		 2201 ret = omap_hsmmc_reg_get(host);
2202 if (ret)
2203 goto err_reg;
2204 host->use_reg = 1;
2205 }
2206
b583f26d 2207 mmc->ocr_avail = mmc_slot(host).ocr_mask;
a45c6cb8
MC		 2208
2209 /* Request IRQ for card detect */
e1a55f5e 2210 if ((mmc_slot(host).card_detect_irq)) {
a45c6cb8 2211 ret = request_irq(mmc_slot(host).card_detect_irq,
70a3341a 2212 omap_hsmmc_cd_handler,
a45c6cb8
MC		 2213 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2214 | IRQF_DISABLED,
2215 mmc_hostname(mmc), host);
2216 if (ret) {
2217 dev_dbg(mmc_dev(host->mmc),
2218 "Unable to grab MMC CD IRQ\n");
2219 goto err_irq_cd;
2220 }
2221 }
2222
b417577d 2223 omap_hsmmc_disable_irq(host);
a45c6cb8 2224
5e2ea617
AH		 2225 mmc_host_lazy_disable(host->mmc);
2226
b62f6228
AH		 2227 omap_hsmmc_protect_card(host);
2228
a45c6cb8
MC		 2229 mmc_add_host(mmc);
2230
191d1f1d 2231 if (mmc_slot(host).name != NULL) {
a45c6cb8
MC		 2232 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2233 if (ret < 0)
2234 goto err_slot_name;
2235 }
191d1f1d 2236 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
a45c6cb8
MC		 2237 ret = device_create_file(&mmc->class_dev,
2238 &dev_attr_cover_switch);
2239 if (ret < 0)
db0fefc5 2240 goto err_slot_name;
a45c6cb8
MC		 2241 }
2242
70a3341a 2243 omap_hsmmc_debugfs(mmc);
d900f712 2244
a45c6cb8
MC		 2245 return 0;
2246
a45c6cb8
MC		 2247err_slot_name:
2248 mmc_remove_host(mmc);
a45c6cb8 2249 free_irq(mmc_slot(host).card_detect_irq, host);
db0fefc5
AH		 2250err_irq_cd:
2251 if (host->use_reg)
2252 omap_hsmmc_reg_put(host);
2253err_reg:
2254 if (host->pdata->cleanup)
2255 host->pdata->cleanup(&pdev->dev);
a45c6cb8
MC		 2256err_irq_cd_init:
2257 free_irq(host->irq, host);
2258err_irq:
5e2ea617 2259 mmc_host_disable(host->mmc);
a45c6cb8
MC		 2260 clk_disable(host->iclk);
2261 clk_put(host->fclk);
2262 clk_put(host->iclk);
2bec0893 2263 if (host->got_dbclk) {
a45c6cb8
MC		 2264 clk_disable(host->dbclk);
2265 clk_put(host->dbclk);
2266 }
a45c6cb8
MC		 2267err1:
2268 iounmap(host->base);
db0fefc5
AH		 2269 platform_set_drvdata(pdev, NULL);
2270 mmc_free_host(mmc);
2271err_alloc:
2272 omap_hsmmc_gpio_free(pdata);
a45c6cb8 2273err:
a45c6cb8 2274 release_mem_region(res->start, res->end - res->start + 1);
a45c6cb8
MC		 2275 return ret;
2276}
2277
70a3341a 2278static int omap_hsmmc_remove(struct platform_device *pdev)
a45c6cb8 2279{
70a3341a 2280 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2281 struct resource *res;
2282
2283 if (host) {
5e2ea617 2284 mmc_host_enable(host->mmc);
a45c6cb8 2285 mmc_remove_host(host->mmc);
db0fefc5
AH		 2286 if (host->use_reg)
2287 omap_hsmmc_reg_put(host);
a45c6cb8
MC		 2288 if (host->pdata->cleanup)
2289 host->pdata->cleanup(&pdev->dev);
2290 free_irq(host->irq, host);
2291 if (mmc_slot(host).card_detect_irq)
2292 free_irq(mmc_slot(host).card_detect_irq, host);
2293 flush_scheduled_work();
2294
5e2ea617 2295 mmc_host_disable(host->mmc);
a45c6cb8
MC		 2296 clk_disable(host->iclk);
2297 clk_put(host->fclk);
2298 clk_put(host->iclk);
2bec0893 2299 if (host->got_dbclk) {
a45c6cb8
MC		 2300 clk_disable(host->dbclk);
2301 clk_put(host->dbclk);
2302 }
2303
2304 mmc_free_host(host->mmc);
2305 iounmap(host->base);
db0fefc5 2306 omap_hsmmc_gpio_free(pdev->dev.platform_data);
a45c6cb8
MC		 2307 }
2308
2309 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2310 if (res)
2311 release_mem_region(res->start, res->end - res->start + 1);
2312 platform_set_drvdata(pdev, NULL);
2313
2314 return 0;
2315}
2316
2317#ifdef CONFIG_PM
a791daa1 2318static int omap_hsmmc_suspend(struct device *dev)
a45c6cb8
MC		 2319{
2320 int ret = 0;
a791daa1 2321 struct platform_device *pdev = to_platform_device(dev);
70a3341a 2322 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2323
2324 if (host && host->suspended)
2325 return 0;
2326
2327 if (host) {
a6b2240d
AH		 2328 host->suspended = 1;
2329 if (host->pdata->suspend) {
2330 ret = host->pdata->suspend(&pdev->dev,
2331 host->slot_id);
2332 if (ret) {
2333 dev_dbg(mmc_dev(host->mmc),
2334 "Unable to handle MMC board"
2335 " level suspend\n");
2336 host->suspended = 0;
2337 return ret;
2338 }
2339 }
2340 cancel_work_sync(&host->mmc_carddetect_work);
1a13f8fa 2341 ret = mmc_suspend_host(host->mmc);
e7cb756f 2342 mmc_host_enable(host->mmc);
a45c6cb8 2343 if (ret == 0) {
b417577d 2344 omap_hsmmc_disable_irq(host);
0683af48 2345 OMAP_HSMMC_WRITE(host->base, HCTL,
191d1f1d 2346 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
5e2ea617 2347 mmc_host_disable(host->mmc);
a45c6cb8 2348 clk_disable(host->iclk);
2bec0893
AH		 2349 if (host->got_dbclk)
2350 clk_disable(host->dbclk);
a6b2240d
AH		 2351 } else {
2352 host->suspended = 0;
2353 if (host->pdata->resume) {
2354 ret = host->pdata->resume(&pdev->dev,
2355 host->slot_id);
2356 if (ret)
2357 dev_dbg(mmc_dev(host->mmc),
2358 "Unmask interrupt failed\n");
2359 }
5e2ea617 2360 mmc_host_disable(host->mmc);
a6b2240d 2361 }
a45c6cb8
MC		 2362
2363 }
2364 return ret;
2365}
2366
2367/* Routine to resume the MMC device */
a791daa1 2368static int omap_hsmmc_resume(struct device *dev)
a45c6cb8
MC		 2369{
2370 int ret = 0;
a791daa1 2371 struct platform_device *pdev = to_platform_device(dev);
70a3341a 2372 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2373
2374 if (host && !host->suspended)
2375 return 0;
2376
2377 if (host) {
a45c6cb8 2378 ret = clk_enable(host->iclk);
11dd62a7 2379 if (ret)
a45c6cb8 2380 goto clk_en_err;
a45c6cb8 2381
11dd62a7
DK		 2382 if (mmc_host_enable(host->mmc) != 0) {
2383 clk_disable(host->iclk);
2384 goto clk_en_err;
2385 }
2386
2bec0893
AH		 2387 if (host->got_dbclk)
2388 clk_enable(host->dbclk);
2389
70a3341a 2390 omap_hsmmc_conf_bus_power(host);
1b331e69 2391
a45c6cb8
MC		 2392 if (host->pdata->resume) {
2393 ret = host->pdata->resume(&pdev->dev, host->slot_id);
2394 if (ret)
2395 dev_dbg(mmc_dev(host->mmc),
2396 "Unmask interrupt failed\n");
2397 }
2398
b62f6228
AH		 2399 omap_hsmmc_protect_card(host);
2400
a45c6cb8
MC		 2401 /* Notify the core to resume the host */
2402 ret = mmc_resume_host(host->mmc);
2403 if (ret == 0)
2404 host->suspended = 0;
70a3341a 2405
5e2ea617 2406 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 2407 }
2408
2409 return ret;
2410
2411clk_en_err:
2412 dev_dbg(mmc_dev(host->mmc),
2413 "Failed to enable MMC clocks during resume\n");
2414 return ret;
2415}
2416
2417#else
70a3341a
DK		 2418#define omap_hsmmc_suspend NULL
2419#define omap_hsmmc_resume NULL
a45c6cb8
MC		 2420#endif
2421
a791daa1 2422static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
70a3341a
DK		 2423 .suspend = omap_hsmmc_suspend,
2424 .resume = omap_hsmmc_resume,
a791daa1
KH		 2425};
2426
2427static struct platform_driver omap_hsmmc_driver = {
2428 .remove = omap_hsmmc_remove,
a45c6cb8
MC		 2429 .driver = {
2430 .name = DRIVER_NAME,
2431 .owner = THIS_MODULE,
a791daa1 2432 .pm = &omap_hsmmc_dev_pm_ops,
a45c6cb8
MC		 2433 },
2434};
2435
70a3341a 2436static int __init omap_hsmmc_init(void)
a45c6cb8
MC		 2437{
2438 /* Register the MMC driver */
8753298a 2439 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
a45c6cb8
MC		 2440}
2441
70a3341a 2442static void __exit omap_hsmmc_cleanup(void)
a45c6cb8
MC		 2443{
2444 /* Unregister MMC driver */
70a3341a 2445 platform_driver_unregister(&omap_hsmmc_driver);
a45c6cb8
MC		 2446}
2447
70a3341a
DK		 2448module_init(omap_hsmmc_init);
2449module_exit(omap_hsmmc_cleanup);
a45c6cb8
MC		 2450
2451MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2452MODULE_LICENSE("GPL");
2453MODULE_ALIAS("platform:" DRIVER_NAME);
2454MODULE_AUTHOR("Texas Instruments Inc");
Linux kernel - Deliverables
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