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omap_hsmmc: Implement scatter-gather emulation
[deliverable/linux.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/delay.h>
22#include <linux/dma-mapping.h>
23#include <linux/platform_device.h>
24#include <linux/workqueue.h>
25#include <linux/timer.h>
26#include <linux/clk.h>
27#include <linux/mmc/host.h>
28#include <linux/io.h>
29#include <linux/semaphore.h>
30#include <mach/dma.h>
31#include <mach/hardware.h>
32#include <mach/board.h>
33#include <mach/mmc.h>
34#include <mach/cpu.h>
35
36/* OMAP HSMMC Host Controller Registers */
37#define OMAP_HSMMC_SYSCONFIG 0x0010
38#define OMAP_HSMMC_CON 0x002C
39#define OMAP_HSMMC_BLK 0x0104
40#define OMAP_HSMMC_ARG 0x0108
41#define OMAP_HSMMC_CMD 0x010C
42#define OMAP_HSMMC_RSP10 0x0110
43#define OMAP_HSMMC_RSP32 0x0114
44#define OMAP_HSMMC_RSP54 0x0118
45#define OMAP_HSMMC_RSP76 0x011C
46#define OMAP_HSMMC_DATA 0x0120
47#define OMAP_HSMMC_HCTL 0x0128
48#define OMAP_HSMMC_SYSCTL 0x012C
49#define OMAP_HSMMC_STAT 0x0130
50#define OMAP_HSMMC_IE 0x0134
51#define OMAP_HSMMC_ISE 0x0138
52#define OMAP_HSMMC_CAPA 0x0140
53
54#define VS18 (1 << 26)
55#define VS30 (1 << 25)
56#define SDVS18 (0x5 << 9)
57#define SDVS30 (0x6 << 9)
eb250826 58#define SDVS33 (0x7 << 9)
1b331e69 59#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 60#define SDVSCLR 0xFFFFF1FF
61#define SDVSDET 0x00000400
62#define AUTOIDLE 0x1
63#define SDBP (1 << 8)
64#define DTO 0xe
65#define ICE 0x1
66#define ICS 0x2
67#define CEN (1 << 2)
68#define CLKD_MASK 0x0000FFC0
69#define CLKD_SHIFT 6
70#define DTO_MASK 0x000F0000
71#define DTO_SHIFT 16
72#define INT_EN_MASK 0x307F0033
73#define INIT_STREAM (1 << 1)
74#define DP_SELECT (1 << 21)
75#define DDIR (1 << 4)
76#define DMA_EN 0x1
77#define MSBS (1 << 5)
78#define BCE (1 << 1)
79#define FOUR_BIT (1 << 1)
80#define CC 0x1
81#define TC 0x02
82#define OD 0x1
83#define ERR (1 << 15)
84#define CMD_TIMEOUT (1 << 16)
85#define DATA_TIMEOUT (1 << 20)
86#define CMD_CRC (1 << 17)
87#define DATA_CRC (1 << 21)
88#define CARD_ERR (1 << 28)
89#define STAT_CLEAR 0xFFFFFFFF
90#define INIT_STREAM_CMD 0x00000000
91#define DUAL_VOLT_OCR_BIT 7
92#define SRC (1 << 25)
93#define SRD (1 << 26)
94
95/*
96 * FIXME: Most likely all the data using these _DEVID defines should come
97 * from the platform_data, or implemented in controller and slot specific
98 * functions.
99 */
100#define OMAP_MMC1_DEVID 0
101#define OMAP_MMC2_DEVID 1
102
a45c6cb8
MC		 103#define MMC_TIMEOUT_MS 20
104#define OMAP_MMC_MASTER_CLOCK 96000000
105#define DRIVER_NAME "mmci-omap-hs"
106
107/*
108 * One controller can have multiple slots, like on some omap boards using
109 * omap.c controller driver. Luckily this is not currently done on any known
110 * omap_hsmmc.c device.
111 */
112#define mmc_slot(host) (host->pdata->slots[host->slot_id])
113
114/*
115 * MMC Host controller read/write API's
116 */
117#define OMAP_HSMMC_READ(base, reg) \
118 __raw_readl((base) + OMAP_HSMMC_##reg)
119
120#define OMAP_HSMMC_WRITE(base, reg, val) \
121 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
122
123struct mmc_omap_host {
124 struct device *dev;
125 struct mmc_host *mmc;
126 struct mmc_request *mrq;
127 struct mmc_command *cmd;
128 struct mmc_data *data;
129 struct clk *fclk;
130 struct clk *iclk;
131 struct clk *dbclk;
132 struct semaphore sem;
133 struct work_struct mmc_carddetect_work;
134 void __iomem *base;
135 resource_size_t mapbase;
136 unsigned int id;
137 unsigned int dma_len;
0ccd76d4 138 unsigned int dma_sg_idx;
a45c6cb8 139 unsigned char bus_mode;
a45c6cb8
MC		 140 u32 *buffer;
141 u32 bytesleft;
142 int suspended;
143 int irq;
144 int carddetect;
145 int use_dma, dma_ch;
a45c6cb8
MC		 146 int slot_id;
147 int dbclk_enabled;
4a694dc9 148 int response_busy;
a45c6cb8
MC		 149 struct omap_mmc_platform_data *pdata;
150};
151
152/*
153 * Stop clock to the card
154 */
155static void omap_mmc_stop_clock(struct mmc_omap_host *host)
156{
157 OMAP_HSMMC_WRITE(host->base, SYSCTL,
158 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
159 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
160 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
161}
162
163/*
164 * Send init stream sequence to card
165 * before sending IDLE command
166 */
167static void send_init_stream(struct mmc_omap_host *host)
168{
169 int reg = 0;
170 unsigned long timeout;
171
172 disable_irq(host->irq);
173 OMAP_HSMMC_WRITE(host->base, CON,
174 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
175 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
176
177 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
178 while ((reg != CC) && time_before(jiffies, timeout))
179 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
180
181 OMAP_HSMMC_WRITE(host->base, CON,
182 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
183 enable_irq(host->irq);
184}
185
186static inline
187int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
188{
189 int r = 1;
190
191 if (host->pdata->slots[host->slot_id].get_cover_state)
192 r = host->pdata->slots[host->slot_id].get_cover_state(host->dev,
193 host->slot_id);
194 return r;
195}
196
197static ssize_t
198mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
199 char *buf)
200{
201 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
202 struct mmc_omap_host *host = mmc_priv(mmc);
203
204 return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
205 "open");
206}
207
208static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
209
210static ssize_t
211mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
212 char *buf)
213{
214 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
215 struct mmc_omap_host *host = mmc_priv(mmc);
216 struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
217
218 return sprintf(buf, "slot:%s\n", slot.name);
219}
220
221static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
222
223/*
224 * Configure the response type and send the cmd.
225 */
226static void
227mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
228 struct mmc_data *data)
229{
230 int cmdreg = 0, resptype = 0, cmdtype = 0;
231
232 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
233 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
234 host->cmd = cmd;
235
236 /*
237 * Clear status bits and enable interrupts
238 */
239 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
240 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
241 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
242
4a694dc9 243 host->response_busy = 0;
a45c6cb8
MC		 244 if (cmd->flags & MMC_RSP_PRESENT) {
245 if (cmd->flags & MMC_RSP_136)
246 resptype = 1;
4a694dc9
AH		 247 else if (cmd->flags & MMC_RSP_BUSY) {
248 resptype = 3;
249 host->response_busy = 1;
250 } else
a45c6cb8
MC		 251 resptype = 2;
252 }
253
254 /*
255 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
256 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
257 * a val of 0x3, rest 0x0.
258 */
259 if (cmd == host->mrq->stop)
260 cmdtype = 0x3;
261
262 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
263
264 if (data) {
265 cmdreg |= DP_SELECT | MSBS | BCE;
266 if (data->flags & MMC_DATA_READ)
267 cmdreg |= DDIR;
268 else
269 cmdreg &= ~(DDIR);
270 }
271
272 if (host->use_dma)
273 cmdreg |= DMA_EN;
274
275 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
276 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
277}
278
0ccd76d4
JY		 279static int
280mmc_omap_get_dma_dir(struct mmc_omap_host *host, struct mmc_data *data)
281{
282 if (data->flags & MMC_DATA_WRITE)
283 return DMA_TO_DEVICE;
284 else
285 return DMA_FROM_DEVICE;
286}
287
a45c6cb8
MC		 288/*
289 * Notify the transfer complete to MMC core
290 */
291static void
292mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
293{
4a694dc9
AH		 294 if (!data) {
295 struct mmc_request *mrq = host->mrq;
296
297 host->mrq = NULL;
298 mmc_omap_fclk_lazy_disable(host);
299 mmc_request_done(host->mmc, mrq);
300 return;
301 }
302
a45c6cb8
MC		 303 host->data = NULL;
304
305 if (host->use_dma && host->dma_ch != -1)
306 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
0ccd76d4 307 mmc_omap_get_dma_dir(host, data));
a45c6cb8
MC		 308
309 if (!data->error)
310 data->bytes_xfered += data->blocks * (data->blksz);
311 else
312 data->bytes_xfered = 0;
313
314 if (!data->stop) {
315 host->mrq = NULL;
316 mmc_request_done(host->mmc, data->mrq);
317 return;
318 }
319 mmc_omap_start_command(host, data->stop, NULL);
320}
321
322/*
323 * Notify the core about command completion
324 */
325static void
326mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
327{
328 host->cmd = NULL;
329
330 if (cmd->flags & MMC_RSP_PRESENT) {
331 if (cmd->flags & MMC_RSP_136) {
332 /* response type 2 */
333 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
334 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
335 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
336 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
337 } else {
338 /* response types 1, 1b, 3, 4, 5, 6 */
339 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
340 }
341 }
4a694dc9 342 if ((host->data == NULL && !host->response_busy) || cmd->error) {
a45c6cb8
MC		 343 host->mrq = NULL;
344 mmc_request_done(host->mmc, cmd->mrq);
345 }
346}
347
348/*
349 * DMA clean up for command errors
350 */
82788ff5 351static void mmc_dma_cleanup(struct mmc_omap_host *host, int errno)
a45c6cb8 352{
82788ff5 353 host->data->error = errno;
a45c6cb8
MC		 354
355 if (host->use_dma && host->dma_ch != -1) {
356 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
0ccd76d4 357 mmc_omap_get_dma_dir(host, host->data));
a45c6cb8
MC		 358 omap_free_dma(host->dma_ch);
359 host->dma_ch = -1;
360 up(&host->sem);
361 }
362 host->data = NULL;
a45c6cb8
MC		 363}
364
365/*
366 * Readable error output
367 */
368#ifdef CONFIG_MMC_DEBUG
369static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
370{
371 /* --- means reserved bit without definition at documentation */
372 static const char *mmc_omap_status_bits[] = {
373 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
374 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
375 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
376 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
377 };
378 char res[256];
379 char *buf = res;
380 int len, i;
381
382 len = sprintf(buf, "MMC IRQ 0x%x :", status);
383 buf += len;
384
385 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
386 if (status & (1 << i)) {
387 len = sprintf(buf, " %s", mmc_omap_status_bits[i]);
388 buf += len;
389 }
390
391 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
392}
393#endif /* CONFIG_MMC_DEBUG */
394
3ebf74b1
JP		 395/*
396 * MMC controller internal state machines reset
397 *
398 * Used to reset command or data internal state machines, using respectively
399 * SRC or SRD bit of SYSCTL register
400 * Can be called from interrupt context
401 */
402static inline void mmc_omap_reset_controller_fsm(struct mmc_omap_host *host,
403 unsigned long bit)
404{
405 unsigned long i = 0;
406 unsigned long limit = (loops_per_jiffy *
407 msecs_to_jiffies(MMC_TIMEOUT_MS));
408
409 OMAP_HSMMC_WRITE(host->base, SYSCTL,
410 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
411
412 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
413 (i++ < limit))
414 cpu_relax();
415
416 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
417 dev_err(mmc_dev(host->mmc),
418 "Timeout waiting on controller reset in %s\n",
419 __func__);
420}
a45c6cb8
MC		 421
422/*
423 * MMC controller IRQ handler
424 */
425static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
426{
427 struct mmc_omap_host *host = dev_id;
428 struct mmc_data *data;
429 int end_cmd = 0, end_trans = 0, status;
430
4a694dc9 431 if (host->mrq == NULL) {
a45c6cb8
MC		 432 OMAP_HSMMC_WRITE(host->base, STAT,
433 OMAP_HSMMC_READ(host->base, STAT));
434 return IRQ_HANDLED;
435 }
436
437 data = host->data;
438 status = OMAP_HSMMC_READ(host->base, STAT);
439 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
440
441 if (status & ERR) {
442#ifdef CONFIG_MMC_DEBUG
443 mmc_omap_report_irq(host, status);
444#endif
445 if ((status & CMD_TIMEOUT) ||
446 (status & CMD_CRC)) {
447 if (host->cmd) {
448 if (status & CMD_TIMEOUT) {
3ebf74b1 449 mmc_omap_reset_controller_fsm(host, SRC);
a45c6cb8
MC		 450 host->cmd->error = -ETIMEDOUT;
451 } else {
452 host->cmd->error = -EILSEQ;
453 }
454 end_cmd = 1;
455 }
4a694dc9
AH		 456 if (host->data || host->response_busy) {
457 if (host->data)
458 mmc_dma_cleanup(host, -ETIMEDOUT);
459 host->response_busy = 0;
3ebf74b1 460 mmc_omap_reset_controller_fsm(host, SRD);
c232f457 461 }
a45c6cb8
MC		 462 }
463 if ((status & DATA_TIMEOUT) ||
464 (status & DATA_CRC)) {
4a694dc9
AH		 465 if (host->data || host->response_busy) {
466 int err = (status & DATA_TIMEOUT) ?
467 -ETIMEDOUT : -EILSEQ;
468
469 if (host->data)
470 mmc_dma_cleanup(host, err);
a45c6cb8 471 else
4a694dc9
AH		 472 host->mrq->cmd->error = err;
473 host->response_busy = 0;
3ebf74b1 474 mmc_omap_reset_controller_fsm(host, SRD);
a45c6cb8
MC		 475 end_trans = 1;
476 }
477 }
478 if (status & CARD_ERR) {
479 dev_dbg(mmc_dev(host->mmc),
480 "Ignoring card err CMD%d\n", host->cmd->opcode);
481 if (host->cmd)
482 end_cmd = 1;
483 if (host->data)
484 end_trans = 1;
485 }
486 }
487
488 OMAP_HSMMC_WRITE(host->base, STAT, status);
489
490 if (end_cmd || (status & CC))
491 mmc_omap_cmd_done(host, host->cmd);
492 if (end_trans || (status & TC))
493 mmc_omap_xfer_done(host, data);
494
495 return IRQ_HANDLED;
496}
497
498/*
eb250826
DB		 499 * Switch MMC interface voltage ... only relevant for MMC1.
500 *
501 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
502 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
503 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8
MC		 504 */
505static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
506{
507 u32 reg_val = 0;
508 int ret;
509
510 /* Disable the clocks */
511 clk_disable(host->fclk);
512 clk_disable(host->iclk);
513 clk_disable(host->dbclk);
514
515 /* Turn the power off */
516 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
517 if (ret != 0)
518 goto err;
519
520 /* Turn the power ON with given VDD 1.8 or 3.0v */
521 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
522 if (ret != 0)
523 goto err;
524
525 clk_enable(host->fclk);
526 clk_enable(host->iclk);
527 clk_enable(host->dbclk);
528
529 OMAP_HSMMC_WRITE(host->base, HCTL,
530 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
531 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 532
a45c6cb8
MC		 533 /*
534 * If a MMC dual voltage card is detected, the set_ios fn calls
535 * this fn with VDD bit set for 1.8V. Upon card removal from the
536 * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
537 *
eb250826
DB		 538 * Cope with a bit of slop in the range ... per data sheets:
539 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
540 * but recommended values are 1.71V to 1.89V
541 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
542 * but recommended values are 2.7V to 3.3V
543 *
544 * Board setup code shouldn't permit anything very out-of-range.
545 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
546 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 547 */
eb250826 548 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 549 reg_val |= SDVS18;
eb250826
DB		 550 else
551 reg_val |= SDVS30;
a45c6cb8
MC		 552
553 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
554
555 OMAP_HSMMC_WRITE(host->base, HCTL,
556 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
557
558 return 0;
559err:
560 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
561 return ret;
562}
563
564/*
565 * Work Item to notify the core about card insertion/removal
566 */
567static void mmc_omap_detect(struct work_struct *work)
568{
569 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
570 mmc_carddetect_work);
249d0fa9
DB		 571 struct omap_mmc_slot_data *slot = &mmc_slot(host);
572
573 host->carddetect = slot->card_detect(slot->card_detect_irq);
a45c6cb8
MC		 574
575 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
576 if (host->carddetect) {
577 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
578 } else {
3ebf74b1 579 mmc_omap_reset_controller_fsm(host, SRD);
a45c6cb8
MC		 580 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
581 }
582}
583
584/*
585 * ISR for handling card insertion and removal
586 */
587static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
588{
589 struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
590
a45c6cb8
MC		 591 schedule_work(&host->mmc_carddetect_work);
592
593 return IRQ_HANDLED;
594}
595
0ccd76d4
JY		 596static int mmc_omap_get_dma_sync_dev(struct mmc_omap_host *host,
597 struct mmc_data *data)
598{
599 int sync_dev;
600
601 if (data->flags & MMC_DATA_WRITE) {
602 if (host->id == OMAP_MMC1_DEVID)
603 sync_dev = OMAP24XX_DMA_MMC1_TX;
604 else
605 sync_dev = OMAP24XX_DMA_MMC2_TX;
606 } else {
607 if (host->id == OMAP_MMC1_DEVID)
608 sync_dev = OMAP24XX_DMA_MMC1_RX;
609 else
610 sync_dev = OMAP24XX_DMA_MMC2_RX;
611 }
612 return sync_dev;
613}
614
615static void mmc_omap_config_dma_params(struct mmc_omap_host *host,
616 struct mmc_data *data,
617 struct scatterlist *sgl)
618{
619 int blksz, nblk, dma_ch;
620
621 dma_ch = host->dma_ch;
622 if (data->flags & MMC_DATA_WRITE) {
623 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
624 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
625 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
626 sg_dma_address(sgl), 0, 0);
627 } else {
628 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
629 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
630 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
631 sg_dma_address(sgl), 0, 0);
632 }
633
634 blksz = host->data->blksz;
635 nblk = sg_dma_len(sgl) / blksz;
636
637 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
638 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
639 mmc_omap_get_dma_sync_dev(host, data),
640 !(data->flags & MMC_DATA_WRITE));
641
642 omap_start_dma(dma_ch);
643}
644
a45c6cb8
MC		 645/*
646 * DMA call back function
647 */
648static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
649{
650 struct mmc_omap_host *host = data;
651
652 if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
653 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
654
655 if (host->dma_ch < 0)
656 return;
657
0ccd76d4
JY		 658 host->dma_sg_idx++;
659 if (host->dma_sg_idx < host->dma_len) {
660 /* Fire up the next transfer. */
661 mmc_omap_config_dma_params(host, host->data,
662 host->data->sg + host->dma_sg_idx);
663 return;
664 }
665
a45c6cb8
MC		 666 omap_free_dma(host->dma_ch);
667 host->dma_ch = -1;
668 /*
669 * DMA Callback: run in interrupt context.
670 * mutex_unlock will through a kernel warning if used.
671 */
672 up(&host->sem);
673}
674
a45c6cb8
MC		 675/*
676 * Routine to configure and start DMA for the MMC card
677 */
678static int
679mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
680{
0ccd76d4 681 int dma_ch = 0, ret = 0, err = 1, i;
a45c6cb8
MC		 682 struct mmc_data *data = req->data;
683
0ccd76d4
JY		 684 /* Sanity check: all the SG entries must be aligned by block size. */
685 for (i = 0; i < host->dma_len; i++) {
686 struct scatterlist *sgl;
687
688 sgl = data->sg + i;
689 if (sgl->length % data->blksz)
690 return -EINVAL;
691 }
692 if ((data->blksz % 4) != 0)
693 /* REVISIT: The MMC buffer increments only when MSB is written.
694 * Return error for blksz which is non multiple of four.
695 */
696 return -EINVAL;
697
a45c6cb8
MC		 698 /*
699 * If for some reason the DMA transfer is still active,
700 * we wait for timeout period and free the dma
701 */
702 if (host->dma_ch != -1) {
703 set_current_state(TASK_UNINTERRUPTIBLE);
704 schedule_timeout(100);
705 if (down_trylock(&host->sem)) {
706 omap_free_dma(host->dma_ch);
707 host->dma_ch = -1;
708 up(&host->sem);
709 return err;
710 }
711 } else {
712 if (down_trylock(&host->sem))
713 return err;
714 }
715
0ccd76d4
JY		 716 ret = omap_request_dma(mmc_omap_get_dma_sync_dev(host, data), "MMC/SD",
717 mmc_omap_dma_cb,host, &dma_ch);
a45c6cb8 718 if (ret != 0) {
0ccd76d4 719 dev_err(mmc_dev(host->mmc),
a45c6cb8
MC		 720 "%s: omap_request_dma() failed with %d\n",
721 mmc_hostname(host->mmc), ret);
722 return ret;
723 }
724
725 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
0ccd76d4 726 data->sg_len, mmc_omap_get_dma_dir(host, data));
a45c6cb8 727 host->dma_ch = dma_ch;
0ccd76d4 728 host->dma_sg_idx = 0;
a45c6cb8 729
0ccd76d4 730 mmc_omap_config_dma_params(host, data, data->sg);
a45c6cb8 731
a45c6cb8
MC		 732 return 0;
733}
734
735static void set_data_timeout(struct mmc_omap_host *host,
736 struct mmc_request *req)
737{
738 unsigned int timeout, cycle_ns;
739 uint32_t reg, clkd, dto = 0;
740
741 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
742 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
743 if (clkd == 0)
744 clkd = 1;
745
746 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
747 timeout = req->data->timeout_ns / cycle_ns;
748 timeout += req->data->timeout_clks;
749 if (timeout) {
750 while ((timeout & 0x80000000) == 0) {
751 dto += 1;
752 timeout <<= 1;
753 }
754 dto = 31 - dto;
755 timeout <<= 1;
756 if (timeout && dto)
757 dto += 1;
758 if (dto >= 13)
759 dto -= 13;
760 else
761 dto = 0;
762 if (dto > 14)
763 dto = 14;
764 }
765
766 reg &= ~DTO_MASK;
767 reg |= dto << DTO_SHIFT;
768 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
769}
770
771/*
772 * Configure block length for MMC/SD cards and initiate the transfer.
773 */
774static int
775mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
776{
777 int ret;
778 host->data = req->data;
779
780 if (req->data == NULL) {
a45c6cb8
MC		 781 OMAP_HSMMC_WRITE(host->base, BLK, 0);
782 return 0;
783 }
784
785 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
786 | (req->data->blocks << 16));
787 set_data_timeout(host, req);
788
a45c6cb8
MC		 789 if (host->use_dma) {
790 ret = mmc_omap_start_dma_transfer(host, req);
791 if (ret != 0) {
792 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
793 return ret;
794 }
795 }
796 return 0;
797}
798
799/*
800 * Request function. for read/write operation
801 */
802static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
803{
804 struct mmc_omap_host *host = mmc_priv(mmc);
805
806 WARN_ON(host->mrq != NULL);
807 host->mrq = req;
808 mmc_omap_prepare_data(host, req);
809 mmc_omap_start_command(host, req->cmd, req->data);
810}
811
812
813/* Routine to configure clock values. Exposed API to core */
814static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
815{
816 struct mmc_omap_host *host = mmc_priv(mmc);
817 u16 dsor = 0;
818 unsigned long regval;
819 unsigned long timeout;
820
821 switch (ios->power_mode) {
822 case MMC_POWER_OFF:
823 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
a45c6cb8
MC		 824 break;
825 case MMC_POWER_UP:
826 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
827 break;
828 }
829
830 switch (mmc->ios.bus_width) {
831 case MMC_BUS_WIDTH_4:
832 OMAP_HSMMC_WRITE(host->base, HCTL,
833 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
834 break;
835 case MMC_BUS_WIDTH_1:
836 OMAP_HSMMC_WRITE(host->base, HCTL,
837 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
838 break;
839 }
840
841 if (host->id == OMAP_MMC1_DEVID) {
eb250826
DB		 842 /* Only MMC1 can interface at 3V without some flavor
843 * of external transceiver; but they all handle 1.8V.
844 */
a45c6cb8
MC		 845 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
846 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
847 /*
848 * The mmc_select_voltage fn of the core does
849 * not seem to set the power_mode to
850 * MMC_POWER_UP upon recalculating the voltage.
851 * vdd 1.8v.
852 */
853 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
854 dev_dbg(mmc_dev(host->mmc),
855 "Switch operation failed\n");
856 }
857 }
858
859 if (ios->clock) {
860 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
861 if (dsor < 1)
862 dsor = 1;
863
864 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
865 dsor++;
866
867 if (dsor > 250)
868 dsor = 250;
869 }
870 omap_mmc_stop_clock(host);
871 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
872 regval = regval & ~(CLKD_MASK);
873 regval = regval | (dsor << 6) | (DTO << 16);
874 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
875 OMAP_HSMMC_WRITE(host->base, SYSCTL,
876 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
877
878 /* Wait till the ICS bit is set */
879 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
880 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
881 && time_before(jiffies, timeout))
882 msleep(1);
883
884 OMAP_HSMMC_WRITE(host->base, SYSCTL,
885 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
886
887 if (ios->power_mode == MMC_POWER_ON)
888 send_init_stream(host);
889
890 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
891 OMAP_HSMMC_WRITE(host->base, CON,
892 OMAP_HSMMC_READ(host->base, CON) | OD);
893}
894
895static int omap_hsmmc_get_cd(struct mmc_host *mmc)
896{
897 struct mmc_omap_host *host = mmc_priv(mmc);
898 struct omap_mmc_platform_data *pdata = host->pdata;
899
900 if (!pdata->slots[0].card_detect)
901 return -ENOSYS;
902 return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq);
903}
904
905static int omap_hsmmc_get_ro(struct mmc_host *mmc)
906{
907 struct mmc_omap_host *host = mmc_priv(mmc);
908 struct omap_mmc_platform_data *pdata = host->pdata;
909
910 if (!pdata->slots[0].get_ro)
911 return -ENOSYS;
912 return pdata->slots[0].get_ro(host->dev, 0);
913}
914
1b331e69
KK		 915static void omap_hsmmc_init(struct mmc_omap_host *host)
916{
917 u32 hctl, capa, value;
918
919 /* Only MMC1 supports 3.0V */
920 if (host->id == OMAP_MMC1_DEVID) {
921 hctl = SDVS30;
922 capa = VS30 | VS18;
923 } else {
924 hctl = SDVS18;
925 capa = VS18;
926 }
927
928 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
929 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
930
931 value = OMAP_HSMMC_READ(host->base, CAPA);
932 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
933
934 /* Set the controller to AUTO IDLE mode */
935 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
936 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
937
938 /* Set SD bus power bit */
939 value = OMAP_HSMMC_READ(host->base, HCTL);
940 OMAP_HSMMC_WRITE(host->base, HCTL, value | SDBP);
941}
942
a45c6cb8
MC		 943static struct mmc_host_ops mmc_omap_ops = {
944 .request = omap_mmc_request,
945 .set_ios = omap_mmc_set_ios,
946 .get_cd = omap_hsmmc_get_cd,
947 .get_ro = omap_hsmmc_get_ro,
948 /* NYET -- enable_sdio_irq */
949};
950
951static int __init omap_mmc_probe(struct platform_device *pdev)
952{
953 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
954 struct mmc_host *mmc;
955 struct mmc_omap_host *host = NULL;
956 struct resource *res;
957 int ret = 0, irq;
a45c6cb8
MC		 958
959 if (pdata == NULL) {
960 dev_err(&pdev->dev, "Platform Data is missing\n");
961 return -ENXIO;
962 }
963
964 if (pdata->nr_slots == 0) {
965 dev_err(&pdev->dev, "No Slots\n");
966 return -ENXIO;
967 }
968
969 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
970 irq = platform_get_irq(pdev, 0);
971 if (res == NULL || irq < 0)
972 return -ENXIO;
973
974 res = request_mem_region(res->start, res->end - res->start + 1,
975 pdev->name);
976 if (res == NULL)
977 return -EBUSY;
978
979 mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
980 if (!mmc) {
981 ret = -ENOMEM;
982 goto err;
983 }
984
985 host = mmc_priv(mmc);
986 host->mmc = mmc;
987 host->pdata = pdata;
988 host->dev = &pdev->dev;
989 host->use_dma = 1;
990 host->dev->dma_mask = &pdata->dma_mask;
991 host->dma_ch = -1;
992 host->irq = irq;
993 host->id = pdev->id;
994 host->slot_id = 0;
995 host->mapbase = res->start;
996 host->base = ioremap(host->mapbase, SZ_4K);
997
998 platform_set_drvdata(pdev, host);
999 INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
1000
1001 mmc->ops = &mmc_omap_ops;
1002 mmc->f_min = 400000;
1003 mmc->f_max = 52000000;
1004
1005 sema_init(&host->sem, 1);
1006
1007 host->iclk = clk_get(&pdev->dev, "mmchs_ick");
1008 if (IS_ERR(host->iclk)) {
1009 ret = PTR_ERR(host->iclk);
1010 host->iclk = NULL;
1011 goto err1;
1012 }
1013 host->fclk = clk_get(&pdev->dev, "mmchs_fck");
1014 if (IS_ERR(host->fclk)) {
1015 ret = PTR_ERR(host->fclk);
1016 host->fclk = NULL;
1017 clk_put(host->iclk);
1018 goto err1;
1019 }
1020
1021 if (clk_enable(host->fclk) != 0) {
1022 clk_put(host->iclk);
1023 clk_put(host->fclk);
1024 goto err1;
1025 }
1026
1027 if (clk_enable(host->iclk) != 0) {
1028 clk_disable(host->fclk);
1029 clk_put(host->iclk);
1030 clk_put(host->fclk);
1031 goto err1;
1032 }
1033
1034 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1035 /*
1036 * MMC can still work without debounce clock.
1037 */
1038 if (IS_ERR(host->dbclk))
1039 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n");
1040 else
1041 if (clk_enable(host->dbclk) != 0)
1042 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1043 " clk failed\n");
1044 else
1045 host->dbclk_enabled = 1;
1046
0ccd76d4
JY		 1047 /* Since we do only SG emulation, we can have as many segs
1048 * as we want. */
1049 mmc->max_phys_segs = 1024;
1050 mmc->max_hw_segs = 1024;
1051
a45c6cb8
MC		 1052 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1053 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1054 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1055 mmc->max_seg_size = mmc->max_req_size;
1056
1057 mmc->ocr_avail = mmc_slot(host).ocr_mask;
1058 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1059
1060 if (pdata->slots[host->slot_id].wires >= 4)
1061 mmc->caps |= MMC_CAP_4_BIT_DATA;
1062
1b331e69 1063 omap_hsmmc_init(host);
a45c6cb8
MC		 1064
1065 /* Request IRQ for MMC operations */
1066 ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1067 mmc_hostname(mmc), host);
1068 if (ret) {
1069 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1070 goto err_irq;
1071 }
1072
1073 if (pdata->init != NULL) {
1074 if (pdata->init(&pdev->dev) != 0) {
1075 dev_dbg(mmc_dev(host->mmc),
1076 "Unable to configure MMC IRQs\n");
1077 goto err_irq_cd_init;
1078 }
1079 }
1080
1081 /* Request IRQ for card detect */
1082 if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) {
1083 ret = request_irq(mmc_slot(host).card_detect_irq,
1084 omap_mmc_cd_handler,
1085 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1086 | IRQF_DISABLED,
1087 mmc_hostname(mmc), host);
1088 if (ret) {
1089 dev_dbg(mmc_dev(host->mmc),
1090 "Unable to grab MMC CD IRQ\n");
1091 goto err_irq_cd;
1092 }
1093 }
1094
1095 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1096 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1097
1098 mmc_add_host(mmc);
1099
1100 if (host->pdata->slots[host->slot_id].name != NULL) {
1101 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1102 if (ret < 0)
1103 goto err_slot_name;
1104 }
1105 if (mmc_slot(host).card_detect_irq && mmc_slot(host).card_detect &&
1106 host->pdata->slots[host->slot_id].get_cover_state) {
1107 ret = device_create_file(&mmc->class_dev,
1108 &dev_attr_cover_switch);
1109 if (ret < 0)
1110 goto err_cover_switch;
1111 }
1112
1113 return 0;
1114
1115err_cover_switch:
1116 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1117err_slot_name:
1118 mmc_remove_host(mmc);
1119err_irq_cd:
1120 free_irq(mmc_slot(host).card_detect_irq, host);
1121err_irq_cd_init:
1122 free_irq(host->irq, host);
1123err_irq:
1124 clk_disable(host->fclk);
1125 clk_disable(host->iclk);
1126 clk_put(host->fclk);
1127 clk_put(host->iclk);
1128 if (host->dbclk_enabled) {
1129 clk_disable(host->dbclk);
1130 clk_put(host->dbclk);
1131 }
1132
1133err1:
1134 iounmap(host->base);
1135err:
1136 dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1137 release_mem_region(res->start, res->end - res->start + 1);
1138 if (host)
1139 mmc_free_host(mmc);
1140 return ret;
1141}
1142
1143static int omap_mmc_remove(struct platform_device *pdev)
1144{
1145 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1146 struct resource *res;
1147
1148 if (host) {
1149 mmc_remove_host(host->mmc);
1150 if (host->pdata->cleanup)
1151 host->pdata->cleanup(&pdev->dev);
1152 free_irq(host->irq, host);
1153 if (mmc_slot(host).card_detect_irq)
1154 free_irq(mmc_slot(host).card_detect_irq, host);
1155 flush_scheduled_work();
1156
1157 clk_disable(host->fclk);
1158 clk_disable(host->iclk);
1159 clk_put(host->fclk);
1160 clk_put(host->iclk);
1161 if (host->dbclk_enabled) {
1162 clk_disable(host->dbclk);
1163 clk_put(host->dbclk);
1164 }
1165
1166 mmc_free_host(host->mmc);
1167 iounmap(host->base);
1168 }
1169
1170 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1171 if (res)
1172 release_mem_region(res->start, res->end - res->start + 1);
1173 platform_set_drvdata(pdev, NULL);
1174
1175 return 0;
1176}
1177
1178#ifdef CONFIG_PM
1179static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1180{
1181 int ret = 0;
1182 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1183
1184 if (host && host->suspended)
1185 return 0;
1186
1187 if (host) {
1188 ret = mmc_suspend_host(host->mmc, state);
1189 if (ret == 0) {
1190 host->suspended = 1;
1191
1192 OMAP_HSMMC_WRITE(host->base, ISE, 0);
1193 OMAP_HSMMC_WRITE(host->base, IE, 0);
1194
1195 if (host->pdata->suspend) {
1196 ret = host->pdata->suspend(&pdev->dev,
1197 host->slot_id);
1198 if (ret)
1199 dev_dbg(mmc_dev(host->mmc),
1200 "Unable to handle MMC board"
1201 " level suspend\n");
1202 }
1203
eb250826
DB		 1204 if (host->id == OMAP_MMC1_DEVID
1205 && !(OMAP_HSMMC_READ(host->base, HCTL)
1206 & SDVSDET)) {
a45c6cb8
MC		 1207 OMAP_HSMMC_WRITE(host->base, HCTL,
1208 OMAP_HSMMC_READ(host->base, HCTL)
1209 & SDVSCLR);
1210 OMAP_HSMMC_WRITE(host->base, HCTL,
1211 OMAP_HSMMC_READ(host->base, HCTL)
1212 | SDVS30);
1213 OMAP_HSMMC_WRITE(host->base, HCTL,
1214 OMAP_HSMMC_READ(host->base, HCTL)
1215 | SDBP);
1216 }
1217
1218 clk_disable(host->fclk);
1219 clk_disable(host->iclk);
1220 clk_disable(host->dbclk);
1221 }
1222
1223 }
1224 return ret;
1225}
1226
1227/* Routine to resume the MMC device */
1228static int omap_mmc_resume(struct platform_device *pdev)
1229{
1230 int ret = 0;
1231 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1232
1233 if (host && !host->suspended)
1234 return 0;
1235
1236 if (host) {
1237
1238 ret = clk_enable(host->fclk);
1239 if (ret)
1240 goto clk_en_err;
1241
1242 ret = clk_enable(host->iclk);
1243 if (ret) {
1244 clk_disable(host->fclk);
1245 clk_put(host->fclk);
1246 goto clk_en_err;
1247 }
1248
1249 if (clk_enable(host->dbclk) != 0)
1250 dev_dbg(mmc_dev(host->mmc),
1251 "Enabling debounce clk failed\n");
1252
1b331e69
KK		 1253 omap_hsmmc_init(host);
1254
a45c6cb8
MC		 1255 if (host->pdata->resume) {
1256 ret = host->pdata->resume(&pdev->dev, host->slot_id);
1257 if (ret)
1258 dev_dbg(mmc_dev(host->mmc),
1259 "Unmask interrupt failed\n");
1260 }
1261
1262 /* Notify the core to resume the host */
1263 ret = mmc_resume_host(host->mmc);
1264 if (ret == 0)
1265 host->suspended = 0;
1266 }
1267
1268 return ret;
1269
1270clk_en_err:
1271 dev_dbg(mmc_dev(host->mmc),
1272 "Failed to enable MMC clocks during resume\n");
1273 return ret;
1274}
1275
1276#else
1277#define omap_mmc_suspend NULL
1278#define omap_mmc_resume NULL
1279#endif
1280
1281static struct platform_driver omap_mmc_driver = {
1282 .probe = omap_mmc_probe,
1283 .remove = omap_mmc_remove,
1284 .suspend = omap_mmc_suspend,
1285 .resume = omap_mmc_resume,
1286 .driver = {
1287 .name = DRIVER_NAME,
1288 .owner = THIS_MODULE,
1289 },
1290};
1291
1292static int __init omap_mmc_init(void)
1293{
1294 /* Register the MMC driver */
1295 return platform_driver_register(&omap_mmc_driver);
1296}
1297
1298static void __exit omap_mmc_cleanup(void)
1299{
1300 /* Unregister MMC driver */
1301 platform_driver_unregister(&omap_mmc_driver);
1302}
1303
1304module_init(omap_mmc_init);
1305module_exit(omap_mmc_cleanup);
1306
1307MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1308MODULE_LICENSE("GPL");
1309MODULE_ALIAS("platform:" DRIVER_NAME);
1310MODULE_AUTHOR("Texas Instruments Inc");
Linux kernel - Deliverables
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