projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
omap_hsmmc: prevent races with irq handler
[deliverable/linux.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
d900f712
DK		 20#include <linux/debugfs.h>
21#include <linux/seq_file.h>
a45c6cb8
MC		 22#include <linux/interrupt.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
25#include <linux/platform_device.h>
26#include <linux/workqueue.h>
27#include <linux/timer.h>
28#include <linux/clk.h>
29#include <linux/mmc/host.h>
13189e78 30#include <linux/mmc/core.h>
a45c6cb8
MC		 31#include <linux/io.h>
32#include <linux/semaphore.h>
33#include <mach/dma.h>
34#include <mach/hardware.h>
35#include <mach/board.h>
36#include <mach/mmc.h>
37#include <mach/cpu.h>
38
39/* OMAP HSMMC Host Controller Registers */
40#define OMAP_HSMMC_SYSCONFIG 0x0010
11dd62a7 41#define OMAP_HSMMC_SYSSTATUS 0x0014
a45c6cb8
MC		 42#define OMAP_HSMMC_CON 0x002C
43#define OMAP_HSMMC_BLK 0x0104
44#define OMAP_HSMMC_ARG 0x0108
45#define OMAP_HSMMC_CMD 0x010C
46#define OMAP_HSMMC_RSP10 0x0110
47#define OMAP_HSMMC_RSP32 0x0114
48#define OMAP_HSMMC_RSP54 0x0118
49#define OMAP_HSMMC_RSP76 0x011C
50#define OMAP_HSMMC_DATA 0x0120
51#define OMAP_HSMMC_HCTL 0x0128
52#define OMAP_HSMMC_SYSCTL 0x012C
53#define OMAP_HSMMC_STAT 0x0130
54#define OMAP_HSMMC_IE 0x0134
55#define OMAP_HSMMC_ISE 0x0138
56#define OMAP_HSMMC_CAPA 0x0140
57
58#define VS18 (1 << 26)
59#define VS30 (1 << 25)
60#define SDVS18 (0x5 << 9)
61#define SDVS30 (0x6 << 9)
eb250826 62#define SDVS33 (0x7 << 9)
1b331e69 63#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 64#define SDVSCLR 0xFFFFF1FF
65#define SDVSDET 0x00000400
66#define AUTOIDLE 0x1
67#define SDBP (1 << 8)
68#define DTO 0xe
69#define ICE 0x1
70#define ICS 0x2
71#define CEN (1 << 2)
72#define CLKD_MASK 0x0000FFC0
73#define CLKD_SHIFT 6
74#define DTO_MASK 0x000F0000
75#define DTO_SHIFT 16
76#define INT_EN_MASK 0x307F0033
ccdfe3a6
AG		 77#define BWR_ENABLE (1 << 4)
78#define BRR_ENABLE (1 << 5)
a45c6cb8
MC		 79#define INIT_STREAM (1 << 1)
80#define DP_SELECT (1 << 21)
81#define DDIR (1 << 4)
82#define DMA_EN 0x1
83#define MSBS (1 << 5)
84#define BCE (1 << 1)
85#define FOUR_BIT (1 << 1)
73153010 86#define DW8 (1 << 5)
a45c6cb8
MC		 87#define CC 0x1
88#define TC 0x02
89#define OD 0x1
90#define ERR (1 << 15)
91#define CMD_TIMEOUT (1 << 16)
92#define DATA_TIMEOUT (1 << 20)
93#define CMD_CRC (1 << 17)
94#define DATA_CRC (1 << 21)
95#define CARD_ERR (1 << 28)
96#define STAT_CLEAR 0xFFFFFFFF
97#define INIT_STREAM_CMD 0x00000000
98#define DUAL_VOLT_OCR_BIT 7
99#define SRC (1 << 25)
100#define SRD (1 << 26)
11dd62a7
DK		 101#define SOFTRESET (1 << 1)
102#define RESETDONE (1 << 0)
a45c6cb8
MC		 103
104/*
105 * FIXME: Most likely all the data using these _DEVID defines should come
106 * from the platform_data, or implemented in controller and slot specific
107 * functions.
108 */
109#define OMAP_MMC1_DEVID 0
110#define OMAP_MMC2_DEVID 1
f3e2f1dd 111#define OMAP_MMC3_DEVID 2
a45c6cb8 112
a45c6cb8
MC		 113#define MMC_TIMEOUT_MS 20
114#define OMAP_MMC_MASTER_CLOCK 96000000
115#define DRIVER_NAME "mmci-omap-hs"
116
dd498eff
DK		 117/* Timeouts for entering power saving states on inactivity, msec */
118#define OMAP_MMC_DISABLED_TIMEOUT 100
13189e78
JL		 119#define OMAP_MMC_SLEEP_TIMEOUT 1000
120#define OMAP_MMC_OFF_TIMEOUT 8000
dd498eff 121
a45c6cb8
MC		 122/*
123 * One controller can have multiple slots, like on some omap boards using
124 * omap.c controller driver. Luckily this is not currently done on any known
125 * omap_hsmmc.c device.
126 */
127#define mmc_slot(host) (host->pdata->slots[host->slot_id])
128
129/*
130 * MMC Host controller read/write API's
131 */
132#define OMAP_HSMMC_READ(base, reg) \
133 __raw_readl((base) + OMAP_HSMMC_##reg)
134
135#define OMAP_HSMMC_WRITE(base, reg, val) \
136 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
137
138struct mmc_omap_host {
139 struct device *dev;
140 struct mmc_host *mmc;
141 struct mmc_request *mrq;
142 struct mmc_command *cmd;
143 struct mmc_data *data;
144 struct clk *fclk;
145 struct clk *iclk;
146 struct clk *dbclk;
147 struct semaphore sem;
148 struct work_struct mmc_carddetect_work;
149 void __iomem *base;
150 resource_size_t mapbase;
4dffd7a2
AH		 151 spinlock_t irq_lock; /* Prevent races with irq handler */
152 unsigned long flags;
a45c6cb8
MC		 153 unsigned int id;
154 unsigned int dma_len;
0ccd76d4 155 unsigned int dma_sg_idx;
a45c6cb8 156 unsigned char bus_mode;
a3621465 157 unsigned char power_mode;
a45c6cb8
MC		 158 u32 *buffer;
159 u32 bytesleft;
160 int suspended;
161 int irq;
a45c6cb8 162 int use_dma, dma_ch;
f3e2f1dd 163 int dma_line_tx, dma_line_rx;
a45c6cb8
MC		 164 int slot_id;
165 int dbclk_enabled;
4a694dc9 166 int response_busy;
11dd62a7 167 int context_loss;
dd498eff 168 int dpm_state;
623821f7 169 int vdd;
11dd62a7 170
a45c6cb8
MC		 171 struct omap_mmc_platform_data *pdata;
172};
173
174/*
175 * Stop clock to the card
176 */
177static void omap_mmc_stop_clock(struct mmc_omap_host *host)
178{
179 OMAP_HSMMC_WRITE(host->base, SYSCTL,
180 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
181 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
182 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
183}
184
11dd62a7
DK		 185#ifdef CONFIG_PM
186
187/*
188 * Restore the MMC host context, if it was lost as result of a
189 * power state change.
190 */
191static int omap_mmc_restore_ctx(struct mmc_omap_host *host)
192{
193 struct mmc_ios *ios = &host->mmc->ios;
194 struct omap_mmc_platform_data *pdata = host->pdata;
195 int context_loss = 0;
196 u32 hctl, capa, con;
197 u16 dsor = 0;
198 unsigned long timeout;
199
200 if (pdata->get_context_loss_count) {
201 context_loss = pdata->get_context_loss_count(host->dev);
202 if (context_loss < 0)
203 return 1;
204 }
205
206 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
207 context_loss == host->context_loss ? "not " : "");
208 if (host->context_loss == context_loss)
209 return 1;
210
211 /* Wait for hardware reset */
212 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
213 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
214 && time_before(jiffies, timeout))
215 ;
216
217 /* Do software reset */
218 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
219 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
220 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
221 && time_before(jiffies, timeout))
222 ;
223
224 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
225 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
226
227 if (host->id == OMAP_MMC1_DEVID) {
228 if (host->power_mode != MMC_POWER_OFF &&
229 (1 << ios->vdd) <= MMC_VDD_23_24)
230 hctl = SDVS18;
231 else
232 hctl = SDVS30;
233 capa = VS30 | VS18;
234 } else {
235 hctl = SDVS18;
236 capa = VS18;
237 }
238
239 OMAP_HSMMC_WRITE(host->base, HCTL,
240 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
241
242 OMAP_HSMMC_WRITE(host->base, CAPA,
243 OMAP_HSMMC_READ(host->base, CAPA) | capa);
244
245 OMAP_HSMMC_WRITE(host->base, HCTL,
246 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
247
248 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
249 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
250 && time_before(jiffies, timeout))
251 ;
252
253 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
254 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
255 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
256
257 /* Do not initialize card-specific things if the power is off */
258 if (host->power_mode == MMC_POWER_OFF)
259 goto out;
260
261 con = OMAP_HSMMC_READ(host->base, CON);
262 switch (ios->bus_width) {
263 case MMC_BUS_WIDTH_8:
264 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
265 break;
266 case MMC_BUS_WIDTH_4:
267 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
268 OMAP_HSMMC_WRITE(host->base, HCTL,
269 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
270 break;
271 case MMC_BUS_WIDTH_1:
272 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
273 OMAP_HSMMC_WRITE(host->base, HCTL,
274 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
275 break;
276 }
277
278 if (ios->clock) {
279 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
280 if (dsor < 1)
281 dsor = 1;
282
283 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
284 dsor++;
285
286 if (dsor > 250)
287 dsor = 250;
288 }
289
290 OMAP_HSMMC_WRITE(host->base, SYSCTL,
291 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
292 OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
293 OMAP_HSMMC_WRITE(host->base, SYSCTL,
294 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
295
296 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
297 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
298 && time_before(jiffies, timeout))
299 ;
300
301 OMAP_HSMMC_WRITE(host->base, SYSCTL,
302 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
303
304 con = OMAP_HSMMC_READ(host->base, CON);
305 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
306 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
307 else
308 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
309out:
310 host->context_loss = context_loss;
311
312 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
313 return 0;
314}
315
316/*
317 * Save the MMC host context (store the number of power state changes so far).
318 */
319static void omap_mmc_save_ctx(struct mmc_omap_host *host)
320{
321 struct omap_mmc_platform_data *pdata = host->pdata;
322 int context_loss;
323
324 if (pdata->get_context_loss_count) {
325 context_loss = pdata->get_context_loss_count(host->dev);
326 if (context_loss < 0)
327 return;
328 host->context_loss = context_loss;
329 }
330}
331
332#else
333
334static int omap_mmc_restore_ctx(struct mmc_omap_host *host)
335{
336 return 0;
337}
338
339static void omap_mmc_save_ctx(struct mmc_omap_host *host)
340{
341}
342
343#endif
344
a45c6cb8
MC		 345/*
346 * Send init stream sequence to card
347 * before sending IDLE command
348 */
349static void send_init_stream(struct mmc_omap_host *host)
350{
351 int reg = 0;
352 unsigned long timeout;
353
354 disable_irq(host->irq);
355 OMAP_HSMMC_WRITE(host->base, CON,
356 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
357 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
358
359 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
360 while ((reg != CC) && time_before(jiffies, timeout))
361 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
362
363 OMAP_HSMMC_WRITE(host->base, CON,
364 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
c653a6d4
AH		 365
366 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
367 OMAP_HSMMC_READ(host->base, STAT);
368
a45c6cb8
MC		 369 enable_irq(host->irq);
370}
371
372static inline
373int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
374{
375 int r = 1;
376
191d1f1d
DK		 377 if (mmc_slot(host).get_cover_state)
378 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
a45c6cb8
MC		 379 return r;
380}
381
382static ssize_t
383mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
384 char *buf)
385{
386 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
387 struct mmc_omap_host *host = mmc_priv(mmc);
388
389 return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
390 "open");
391}
392
393static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
394
395static ssize_t
396mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
397 char *buf)
398{
399 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
400 struct mmc_omap_host *host = mmc_priv(mmc);
a45c6cb8 401
191d1f1d 402 return sprintf(buf, "%s\n", mmc_slot(host).name);
a45c6cb8
MC		 403}
404
405static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
406
407/*
408 * Configure the response type and send the cmd.
409 */
410static void
411mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
412 struct mmc_data *data)
413{
414 int cmdreg = 0, resptype = 0, cmdtype = 0;
415
416 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
417 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
418 host->cmd = cmd;
419
420 /*
421 * Clear status bits and enable interrupts
422 */
423 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
424 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
ccdfe3a6
AG		 425
426 if (host->use_dma)
427 OMAP_HSMMC_WRITE(host->base, IE,
428 INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE));
429 else
430 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8 431
4a694dc9 432 host->response_busy = 0;
a45c6cb8
MC		 433 if (cmd->flags & MMC_RSP_PRESENT) {
434 if (cmd->flags & MMC_RSP_136)
435 resptype = 1;
4a694dc9
AH		 436 else if (cmd->flags & MMC_RSP_BUSY) {
437 resptype = 3;
438 host->response_busy = 1;
439 } else
a45c6cb8
MC		 440 resptype = 2;
441 }
442
443 /*
444 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
445 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
446 * a val of 0x3, rest 0x0.
447 */
448 if (cmd == host->mrq->stop)
449 cmdtype = 0x3;
450
451 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
452
453 if (data) {
454 cmdreg |= DP_SELECT | MSBS | BCE;
455 if (data->flags & MMC_DATA_READ)
456 cmdreg |= DDIR;
457 else
458 cmdreg &= ~(DDIR);
459 }
460
461 if (host->use_dma)
462 cmdreg |= DMA_EN;
463
4dffd7a2
AH		 464 /*
465 * In an interrupt context (i.e. STOP command), the spinlock is unlocked
466 * by the interrupt handler, otherwise (i.e. for a new request) it is
467 * unlocked here.
468 */
469 if (!in_interrupt())
470 spin_unlock_irqrestore(&host->irq_lock, host->flags);
471
a45c6cb8
MC		 472 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
473 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
474}
475
0ccd76d4
JY		 476static int
477mmc_omap_get_dma_dir(struct mmc_omap_host *host, struct mmc_data *data)
478{
479 if (data->flags & MMC_DATA_WRITE)
480 return DMA_TO_DEVICE;
481 else
482 return DMA_FROM_DEVICE;
483}
484
a45c6cb8
MC		 485/*
486 * Notify the transfer complete to MMC core
487 */
488static void
489mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
490{
4a694dc9
AH		 491 if (!data) {
492 struct mmc_request *mrq = host->mrq;
493
23050103
AH		 494 /* TC before CC from CMD6 - don't know why, but it happens */
495 if (host->cmd && host->cmd->opcode == 6 &&
496 host->response_busy) {
497 host->response_busy = 0;
498 return;
499 }
500
4a694dc9 501 host->mrq = NULL;
4a694dc9
AH		 502 mmc_request_done(host->mmc, mrq);
503 return;
504 }
505
a45c6cb8
MC		 506 host->data = NULL;
507
508 if (host->use_dma && host->dma_ch != -1)
509 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
0ccd76d4 510 mmc_omap_get_dma_dir(host, data));
a45c6cb8
MC		 511
512 if (!data->error)
513 data->bytes_xfered += data->blocks * (data->blksz);
514 else
515 data->bytes_xfered = 0;
516
517 if (!data->stop) {
518 host->mrq = NULL;
519 mmc_request_done(host->mmc, data->mrq);
520 return;
521 }
522 mmc_omap_start_command(host, data->stop, NULL);
523}
524
525/*
526 * Notify the core about command completion
527 */
528static void
529mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
530{
531 host->cmd = NULL;
532
533 if (cmd->flags & MMC_RSP_PRESENT) {
534 if (cmd->flags & MMC_RSP_136) {
535 /* response type 2 */
536 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
537 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
538 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
539 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
540 } else {
541 /* response types 1, 1b, 3, 4, 5, 6 */
542 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
543 }
544 }
4a694dc9 545 if ((host->data == NULL && !host->response_busy) || cmd->error) {
a45c6cb8
MC		 546 host->mrq = NULL;
547 mmc_request_done(host->mmc, cmd->mrq);
548 }
549}
550
551/*
552 * DMA clean up for command errors
553 */
82788ff5 554static void mmc_dma_cleanup(struct mmc_omap_host *host, int errno)
a45c6cb8 555{
82788ff5 556 host->data->error = errno;
a45c6cb8
MC		 557
558 if (host->use_dma && host->dma_ch != -1) {
559 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
0ccd76d4 560 mmc_omap_get_dma_dir(host, host->data));
a45c6cb8
MC		 561 omap_free_dma(host->dma_ch);
562 host->dma_ch = -1;
563 up(&host->sem);
564 }
565 host->data = NULL;
a45c6cb8
MC		 566}
567
568/*
569 * Readable error output
570 */
571#ifdef CONFIG_MMC_DEBUG
572static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
573{
574 /* --- means reserved bit without definition at documentation */
575 static const char *mmc_omap_status_bits[] = {
576 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
577 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
578 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
579 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
580 };
581 char res[256];
582 char *buf = res;
583 int len, i;
584
585 len = sprintf(buf, "MMC IRQ 0x%x :", status);
586 buf += len;
587
588 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
589 if (status & (1 << i)) {
590 len = sprintf(buf, " %s", mmc_omap_status_bits[i]);
591 buf += len;
592 }
593
594 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
595}
596#endif /* CONFIG_MMC_DEBUG */
597
3ebf74b1
JP		 598/*
599 * MMC controller internal state machines reset
600 *
601 * Used to reset command or data internal state machines, using respectively
602 * SRC or SRD bit of SYSCTL register
603 * Can be called from interrupt context
604 */
605static inline void mmc_omap_reset_controller_fsm(struct mmc_omap_host *host,
606 unsigned long bit)
607{
608 unsigned long i = 0;
609 unsigned long limit = (loops_per_jiffy *
610 msecs_to_jiffies(MMC_TIMEOUT_MS));
611
612 OMAP_HSMMC_WRITE(host->base, SYSCTL,
613 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
614
615 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
616 (i++ < limit))
617 cpu_relax();
618
619 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
620 dev_err(mmc_dev(host->mmc),
621 "Timeout waiting on controller reset in %s\n",
622 __func__);
623}
a45c6cb8
MC		 624
625/*
626 * MMC controller IRQ handler
627 */
628static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
629{
630 struct mmc_omap_host *host = dev_id;
631 struct mmc_data *data;
632 int end_cmd = 0, end_trans = 0, status;
633
4dffd7a2
AH		 634 spin_lock(&host->irq_lock);
635
4a694dc9 636 if (host->mrq == NULL) {
a45c6cb8
MC		 637 OMAP_HSMMC_WRITE(host->base, STAT,
638 OMAP_HSMMC_READ(host->base, STAT));
00adadc1
KH		 639 /* Flush posted write */
640 OMAP_HSMMC_READ(host->base, STAT);
4dffd7a2 641 spin_unlock(&host->irq_lock);
a45c6cb8
MC		 642 return IRQ_HANDLED;
643 }
644
645 data = host->data;
646 status = OMAP_HSMMC_READ(host->base, STAT);
647 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
648
649 if (status & ERR) {
650#ifdef CONFIG_MMC_DEBUG
651 mmc_omap_report_irq(host, status);
652#endif
653 if ((status & CMD_TIMEOUT) ||
654 (status & CMD_CRC)) {
655 if (host->cmd) {
656 if (status & CMD_TIMEOUT) {
191d1f1d
DK		 657 mmc_omap_reset_controller_fsm(host,
658 SRC);
a45c6cb8
MC		 659 host->cmd->error = -ETIMEDOUT;
660 } else {
661 host->cmd->error = -EILSEQ;
662 }
663 end_cmd = 1;
664 }
4a694dc9
AH		 665 if (host->data || host->response_busy) {
666 if (host->data)
667 mmc_dma_cleanup(host, -ETIMEDOUT);
668 host->response_busy = 0;
3ebf74b1 669 mmc_omap_reset_controller_fsm(host, SRD);
c232f457 670 }
a45c6cb8
MC		 671 }
672 if ((status & DATA_TIMEOUT) ||
673 (status & DATA_CRC)) {
4a694dc9
AH		 674 if (host->data || host->response_busy) {
675 int err = (status & DATA_TIMEOUT) ?
676 -ETIMEDOUT : -EILSEQ;
677
678 if (host->data)
679 mmc_dma_cleanup(host, err);
a45c6cb8 680 else
4a694dc9
AH		 681 host->mrq->cmd->error = err;
682 host->response_busy = 0;
3ebf74b1 683 mmc_omap_reset_controller_fsm(host, SRD);
a45c6cb8
MC		 684 end_trans = 1;
685 }
686 }
687 if (status & CARD_ERR) {
688 dev_dbg(mmc_dev(host->mmc),
689 "Ignoring card err CMD%d\n", host->cmd->opcode);
690 if (host->cmd)
691 end_cmd = 1;
692 if (host->data)
693 end_trans = 1;
694 }
695 }
696
697 OMAP_HSMMC_WRITE(host->base, STAT, status);
00adadc1
KH		 698 /* Flush posted write */
699 OMAP_HSMMC_READ(host->base, STAT);
a45c6cb8 700
a8fe29d8 701 if (end_cmd || ((status & CC) && host->cmd))
a45c6cb8 702 mmc_omap_cmd_done(host, host->cmd);
0a40e647 703 if ((end_trans || (status & TC)) && host->mrq)
a45c6cb8
MC		 704 mmc_omap_xfer_done(host, data);
705
4dffd7a2
AH		 706 spin_unlock(&host->irq_lock);
707
a45c6cb8
MC		 708 return IRQ_HANDLED;
709}
710
e13bb300
AH		 711static void set_sd_bus_power(struct mmc_omap_host *host)
712{
713 unsigned long i;
714
715 OMAP_HSMMC_WRITE(host->base, HCTL,
716 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
717 for (i = 0; i < loops_per_jiffy; i++) {
718 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
719 break;
720 cpu_relax();
721 }
722}
723
a45c6cb8 724/*
eb250826
DB		 725 * Switch MMC interface voltage ... only relevant for MMC1.
726 *
727 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
728 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
729 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8
MC		 730 */
731static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
732{
733 u32 reg_val = 0;
734 int ret;
735
736 /* Disable the clocks */
737 clk_disable(host->fclk);
738 clk_disable(host->iclk);
739 clk_disable(host->dbclk);
740
741 /* Turn the power off */
742 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
743 if (ret != 0)
744 goto err;
745
746 /* Turn the power ON with given VDD 1.8 or 3.0v */
747 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
748 if (ret != 0)
749 goto err;
750
751 clk_enable(host->fclk);
752 clk_enable(host->iclk);
753 clk_enable(host->dbclk);
754
755 OMAP_HSMMC_WRITE(host->base, HCTL,
756 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
757 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 758
a45c6cb8
MC		 759 /*
760 * If a MMC dual voltage card is detected, the set_ios fn calls
761 * this fn with VDD bit set for 1.8V. Upon card removal from the
762 * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
763 *
eb250826
DB		 764 * Cope with a bit of slop in the range ... per data sheets:
765 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
766 * but recommended values are 1.71V to 1.89V
767 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
768 * but recommended values are 2.7V to 3.3V
769 *
770 * Board setup code shouldn't permit anything very out-of-range.
771 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
772 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 773 */
eb250826 774 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 775 reg_val |= SDVS18;
eb250826
DB		 776 else
777 reg_val |= SDVS30;
a45c6cb8
MC		 778
779 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 780 set_sd_bus_power(host);
a45c6cb8
MC		 781
782 return 0;
783err:
784 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
785 return ret;
786}
787
788/*
789 * Work Item to notify the core about card insertion/removal
790 */
791static void mmc_omap_detect(struct work_struct *work)
792{
793 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
794 mmc_carddetect_work);
249d0fa9 795 struct omap_mmc_slot_data *slot = &mmc_slot(host);
a6b2240d
AH		 796 int carddetect;
797
798 if (host->suspended)
799 return;
800
801 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
249d0fa9 802
191d1f1d 803 if (slot->card_detect)
a6b2240d 804 carddetect = slot->card_detect(slot->card_detect_irq);
e1a55f5e 805 else
a6b2240d 806 carddetect = -ENOSYS;
a45c6cb8 807
a6b2240d 808 if (carddetect) {
a45c6cb8
MC		 809 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
810 } else {
5e2ea617 811 mmc_host_enable(host->mmc);
3ebf74b1 812 mmc_omap_reset_controller_fsm(host, SRD);
5e2ea617 813 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 814 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
815 }
816}
817
818/*
819 * ISR for handling card insertion and removal
820 */
821static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
822{
823 struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
824
a6b2240d
AH		 825 if (host->suspended)
826 return IRQ_HANDLED;
a45c6cb8
MC		 827 schedule_work(&host->mmc_carddetect_work);
828
829 return IRQ_HANDLED;
830}
831
0ccd76d4
JY		 832static int mmc_omap_get_dma_sync_dev(struct mmc_omap_host *host,
833 struct mmc_data *data)
834{
835 int sync_dev;
836
f3e2f1dd
GI		 837 if (data->flags & MMC_DATA_WRITE)
838 sync_dev = host->dma_line_tx;
839 else
840 sync_dev = host->dma_line_rx;
0ccd76d4
JY		 841 return sync_dev;
842}
843
844static void mmc_omap_config_dma_params(struct mmc_omap_host *host,
845 struct mmc_data *data,
846 struct scatterlist *sgl)
847{
848 int blksz, nblk, dma_ch;
849
850 dma_ch = host->dma_ch;
851 if (data->flags & MMC_DATA_WRITE) {
852 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
853 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
854 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
855 sg_dma_address(sgl), 0, 0);
856 } else {
857 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
191d1f1d 858 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
0ccd76d4
JY		 859 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
860 sg_dma_address(sgl), 0, 0);
861 }
862
863 blksz = host->data->blksz;
864 nblk = sg_dma_len(sgl) / blksz;
865
866 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
867 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
868 mmc_omap_get_dma_sync_dev(host, data),
869 !(data->flags & MMC_DATA_WRITE));
870
871 omap_start_dma(dma_ch);
872}
873
a45c6cb8
MC		 874/*
875 * DMA call back function
876 */
877static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
878{
879 struct mmc_omap_host *host = data;
880
881 if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
882 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
883
884 if (host->dma_ch < 0)
885 return;
886
0ccd76d4
JY		 887 host->dma_sg_idx++;
888 if (host->dma_sg_idx < host->dma_len) {
889 /* Fire up the next transfer. */
890 mmc_omap_config_dma_params(host, host->data,
891 host->data->sg + host->dma_sg_idx);
892 return;
893 }
894
a45c6cb8
MC		 895 omap_free_dma(host->dma_ch);
896 host->dma_ch = -1;
897 /*
898 * DMA Callback: run in interrupt context.
85b84322 899 * mutex_unlock will throw a kernel warning if used.
a45c6cb8
MC		 900 */
901 up(&host->sem);
902}
903
a45c6cb8
MC		 904/*
905 * Routine to configure and start DMA for the MMC card
906 */
907static int
908mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
909{
0ccd76d4 910 int dma_ch = 0, ret = 0, err = 1, i;
a45c6cb8
MC		 911 struct mmc_data *data = req->data;
912
0ccd76d4 913 /* Sanity check: all the SG entries must be aligned by block size. */
a3f406f8 914 for (i = 0; i < data->sg_len; i++) {
0ccd76d4
JY		 915 struct scatterlist *sgl;
916
917 sgl = data->sg + i;
918 if (sgl->length % data->blksz)
919 return -EINVAL;
920 }
921 if ((data->blksz % 4) != 0)
922 /* REVISIT: The MMC buffer increments only when MSB is written.
923 * Return error for blksz which is non multiple of four.
924 */
925 return -EINVAL;
926
a45c6cb8
MC		 927 /*
928 * If for some reason the DMA transfer is still active,
929 * we wait for timeout period and free the dma
930 */
931 if (host->dma_ch != -1) {
932 set_current_state(TASK_UNINTERRUPTIBLE);
933 schedule_timeout(100);
934 if (down_trylock(&host->sem)) {
935 omap_free_dma(host->dma_ch);
936 host->dma_ch = -1;
937 up(&host->sem);
938 return err;
939 }
940 } else {
941 if (down_trylock(&host->sem))
942 return err;
943 }
944
0ccd76d4 945 ret = omap_request_dma(mmc_omap_get_dma_sync_dev(host, data), "MMC/SD",
191d1f1d 946 mmc_omap_dma_cb, host, &dma_ch);
a45c6cb8 947 if (ret != 0) {
0ccd76d4 948 dev_err(mmc_dev(host->mmc),
a45c6cb8
MC		 949 "%s: omap_request_dma() failed with %d\n",
950 mmc_hostname(host->mmc), ret);
951 return ret;
952 }
953
954 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
0ccd76d4 955 data->sg_len, mmc_omap_get_dma_dir(host, data));
a45c6cb8 956 host->dma_ch = dma_ch;
0ccd76d4 957 host->dma_sg_idx = 0;
a45c6cb8 958
0ccd76d4 959 mmc_omap_config_dma_params(host, data, data->sg);
a45c6cb8 960
a45c6cb8
MC		 961 return 0;
962}
963
964static void set_data_timeout(struct mmc_omap_host *host,
965 struct mmc_request *req)
966{
967 unsigned int timeout, cycle_ns;
968 uint32_t reg, clkd, dto = 0;
969
970 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
971 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
972 if (clkd == 0)
973 clkd = 1;
974
975 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
976 timeout = req->data->timeout_ns / cycle_ns;
977 timeout += req->data->timeout_clks;
978 if (timeout) {
979 while ((timeout & 0x80000000) == 0) {
980 dto += 1;
981 timeout <<= 1;
982 }
983 dto = 31 - dto;
984 timeout <<= 1;
985 if (timeout && dto)
986 dto += 1;
987 if (dto >= 13)
988 dto -= 13;
989 else
990 dto = 0;
991 if (dto > 14)
992 dto = 14;
993 }
994
995 reg &= ~DTO_MASK;
996 reg |= dto << DTO_SHIFT;
997 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
998}
999
1000/*
1001 * Configure block length for MMC/SD cards and initiate the transfer.
1002 */
1003static int
1004mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
1005{
1006 int ret;
1007 host->data = req->data;
1008
1009 if (req->data == NULL) {
a45c6cb8
MC		 1010 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1011 return 0;
1012 }
1013
1014 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1015 | (req->data->blocks << 16));
1016 set_data_timeout(host, req);
1017
a45c6cb8
MC		 1018 if (host->use_dma) {
1019 ret = mmc_omap_start_dma_transfer(host, req);
1020 if (ret != 0) {
1021 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1022 return ret;
1023 }
1024 }
1025 return 0;
1026}
1027
1028/*
1029 * Request function. for read/write operation
1030 */
1031static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
1032{
1033 struct mmc_omap_host *host = mmc_priv(mmc);
a3f406f8 1034 int err;
a45c6cb8 1035
4dffd7a2
AH		 1036 /*
1037 * Prevent races with the interrupt handler because of unexpected
1038 * interrupts, but not if we are already in interrupt context i.e.
1039 * retries.
1040 */
1041 if (!in_interrupt())
1042 spin_lock_irqsave(&host->irq_lock, host->flags);
a45c6cb8
MC		 1043 WARN_ON(host->mrq != NULL);
1044 host->mrq = req;
a3f406f8
JL		 1045 err = mmc_omap_prepare_data(host, req);
1046 if (err) {
1047 req->cmd->error = err;
1048 if (req->data)
1049 req->data->error = err;
1050 host->mrq = NULL;
4dffd7a2
AH		 1051 if (!in_interrupt())
1052 spin_unlock_irqrestore(&host->irq_lock, host->flags);
a3f406f8
JL		 1053 mmc_request_done(mmc, req);
1054 return;
1055 }
1056
a45c6cb8
MC		 1057 mmc_omap_start_command(host, req->cmd, req->data);
1058}
1059
1060
1061/* Routine to configure clock values. Exposed API to core */
1062static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1063{
1064 struct mmc_omap_host *host = mmc_priv(mmc);
1065 u16 dsor = 0;
1066 unsigned long regval;
1067 unsigned long timeout;
73153010 1068 u32 con;
a3621465 1069 int do_send_init_stream = 0;
a45c6cb8 1070
5e2ea617
AH		 1071 mmc_host_enable(host->mmc);
1072
a3621465
AH		 1073 if (ios->power_mode != host->power_mode) {
1074 switch (ios->power_mode) {
1075 case MMC_POWER_OFF:
1076 mmc_slot(host).set_power(host->dev, host->slot_id,
1077 0, 0);
623821f7 1078 host->vdd = 0;
a3621465
AH		 1079 break;
1080 case MMC_POWER_UP:
1081 mmc_slot(host).set_power(host->dev, host->slot_id,
1082 1, ios->vdd);
623821f7 1083 host->vdd = ios->vdd;
a3621465
AH		 1084 break;
1085 case MMC_POWER_ON:
1086 do_send_init_stream = 1;
1087 break;
1088 }
1089 host->power_mode = ios->power_mode;
a45c6cb8
MC		 1090 }
1091
dd498eff
DK		 1092 /* FIXME: set registers based only on changes to ios */
1093
73153010 1094 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 1095 switch (mmc->ios.bus_width) {
73153010
JL		 1096 case MMC_BUS_WIDTH_8:
1097 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1098 break;
a45c6cb8 1099 case MMC_BUS_WIDTH_4:
73153010 1100 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 1101 OMAP_HSMMC_WRITE(host->base, HCTL,
1102 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1103 break;
1104 case MMC_BUS_WIDTH_1:
73153010 1105 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 1106 OMAP_HSMMC_WRITE(host->base, HCTL,
1107 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1108 break;
1109 }
1110
1111 if (host->id == OMAP_MMC1_DEVID) {
eb250826
DB		 1112 /* Only MMC1 can interface at 3V without some flavor
1113 * of external transceiver; but they all handle 1.8V.
1114 */
a45c6cb8
MC		 1115 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1116 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1117 /*
1118 * The mmc_select_voltage fn of the core does
1119 * not seem to set the power_mode to
1120 * MMC_POWER_UP upon recalculating the voltage.
1121 * vdd 1.8v.
1122 */
1123 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
1124 dev_dbg(mmc_dev(host->mmc),
1125 "Switch operation failed\n");
1126 }
1127 }
1128
1129 if (ios->clock) {
1130 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1131 if (dsor < 1)
1132 dsor = 1;
1133
1134 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1135 dsor++;
1136
1137 if (dsor > 250)
1138 dsor = 250;
1139 }
1140 omap_mmc_stop_clock(host);
1141 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1142 regval = regval & ~(CLKD_MASK);
1143 regval = regval | (dsor << 6) | (DTO << 16);
1144 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1145 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1146 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1147
1148 /* Wait till the ICS bit is set */
1149 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
11dd62a7 1150 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
a45c6cb8
MC		 1151 && time_before(jiffies, timeout))
1152 msleep(1);
1153
1154 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1155 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1156
a3621465 1157 if (do_send_init_stream)
a45c6cb8
MC		 1158 send_init_stream(host);
1159
abb28e73 1160 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 1161 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
abb28e73
DK		 1162 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1163 else
1164 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
5e2ea617 1165
dd498eff
DK		 1166 if (host->power_mode == MMC_POWER_OFF)
1167 mmc_host_disable(host->mmc);
1168 else
1169 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 1170}
1171
1172static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1173{
1174 struct mmc_omap_host *host = mmc_priv(mmc);
a45c6cb8 1175
191d1f1d 1176 if (!mmc_slot(host).card_detect)
a45c6cb8 1177 return -ENOSYS;
191d1f1d 1178 return mmc_slot(host).card_detect(mmc_slot(host).card_detect_irq);
a45c6cb8
MC		 1179}
1180
1181static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1182{
1183 struct mmc_omap_host *host = mmc_priv(mmc);
a45c6cb8 1184
191d1f1d 1185 if (!mmc_slot(host).get_ro)
a45c6cb8 1186 return -ENOSYS;
191d1f1d 1187 return mmc_slot(host).get_ro(host->dev, 0);
a45c6cb8
MC		 1188}
1189
1b331e69
KK		 1190static void omap_hsmmc_init(struct mmc_omap_host *host)
1191{
1192 u32 hctl, capa, value;
1193
1194 /* Only MMC1 supports 3.0V */
1195 if (host->id == OMAP_MMC1_DEVID) {
1196 hctl = SDVS30;
1197 capa = VS30 | VS18;
1198 } else {
1199 hctl = SDVS18;
1200 capa = VS18;
1201 }
1202
1203 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1204 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1205
1206 value = OMAP_HSMMC_READ(host->base, CAPA);
1207 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1208
1209 /* Set the controller to AUTO IDLE mode */
1210 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1211 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1212
1213 /* Set SD bus power bit */
e13bb300 1214 set_sd_bus_power(host);
1b331e69
KK		 1215}
1216
dd498eff
DK		 1217/*
1218 * Dynamic power saving handling, FSM:
13189e78
JL		 1219 * ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF
1220 * ^___________| | |
1221 * |______________________|______________________|
dd498eff
DK		 1222 *
1223 * ENABLED: mmc host is fully functional
1224 * DISABLED: fclk is off
13189e78
JL		 1225 * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep
1226 * REGSLEEP: fclk is off, voltage regulator is asleep
1227 * OFF: fclk is off, voltage regulator is off
dd498eff
DK		 1228 *
1229 * Transition handlers return the timeout for the next state transition
1230 * or negative error.
1231 */
1232
13189e78 1233enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF};
dd498eff
DK		 1234
1235/* Handler for [ENABLED -> DISABLED] transition */
1236static int omap_mmc_enabled_to_disabled(struct mmc_omap_host *host)
1237{
1238 omap_mmc_save_ctx(host);
1239 clk_disable(host->fclk);
1240 host->dpm_state = DISABLED;
1241
1242 dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n");
1243
1244 if (host->power_mode == MMC_POWER_OFF)
1245 return 0;
1246
13189e78 1247 return msecs_to_jiffies(OMAP_MMC_SLEEP_TIMEOUT);
dd498eff
DK		 1248}
1249
13189e78
JL		 1250/* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */
1251static int omap_mmc_disabled_to_sleep(struct mmc_omap_host *host)
dd498eff 1252{
13189e78 1253 int err, new_state;
dd498eff
DK		 1254
1255 if (!mmc_try_claim_host(host->mmc))
1256 return 0;
1257
1258 clk_enable(host->fclk);
dd498eff 1259 omap_mmc_restore_ctx(host);
13189e78
JL		 1260 if (mmc_card_can_sleep(host->mmc)) {
1261 err = mmc_card_sleep(host->mmc);
1262 if (err < 0) {
1263 clk_disable(host->fclk);
1264 mmc_release_host(host->mmc);
1265 return err;
1266 }
1267 new_state = CARDSLEEP;
1268 } else
1269 new_state = REGSLEEP;
1270 if (mmc_slot(host).set_sleep)
1271 mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0,
1272 new_state == CARDSLEEP);
1273 /* FIXME: turn off bus power and perhaps interrupts too */
1274 clk_disable(host->fclk);
1275 host->dpm_state = new_state;
1276
1277 mmc_release_host(host->mmc);
1278
1279 dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n",
1280 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
dd498eff
DK		 1281
1282 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1283 mmc_slot(host).card_detect ||
1284 (mmc_slot(host).get_cover_state &&
13189e78
JL		 1285 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))
1286 return msecs_to_jiffies(OMAP_MMC_OFF_TIMEOUT);
1287
1288 return 0;
1289}
1290
1291/* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */
1292static int omap_mmc_sleep_to_off(struct mmc_omap_host *host)
1293{
1294 if (!mmc_try_claim_host(host->mmc))
1295 return 0;
1296
1297 if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1298 mmc_slot(host).card_detect ||
1299 (mmc_slot(host).get_cover_state &&
1300 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) {
1301 mmc_release_host(host->mmc);
1302 return 0;
623821f7 1303 }
dd498eff 1304
13189e78
JL		 1305 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1306 host->vdd = 0;
1307 host->power_mode = MMC_POWER_OFF;
dd498eff 1308
13189e78
JL		 1309 dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n",
1310 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
dd498eff 1311
13189e78 1312 host->dpm_state = OFF;
dd498eff
DK		 1313
1314 mmc_release_host(host->mmc);
1315
1316 return 0;
1317}
1318
1319/* Handler for [DISABLED -> ENABLED] transition */
1320static int omap_mmc_disabled_to_enabled(struct mmc_omap_host *host)
1321{
1322 int err;
1323
1324 err = clk_enable(host->fclk);
1325 if (err < 0)
1326 return err;
1327
1328 omap_mmc_restore_ctx(host);
1329
1330 host->dpm_state = ENABLED;
1331
1332 dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n");
1333
1334 return 0;
1335}
1336
13189e78
JL		 1337/* Handler for [SLEEP -> ENABLED] transition */
1338static int omap_mmc_sleep_to_enabled(struct mmc_omap_host *host)
dd498eff 1339{
13189e78
JL		 1340 if (!mmc_try_claim_host(host->mmc))
1341 return 0;
dd498eff 1342
13189e78 1343 clk_enable(host->fclk);
dd498eff 1344 omap_mmc_restore_ctx(host);
13189e78
JL		 1345 if (mmc_slot(host).set_sleep)
1346 mmc_slot(host).set_sleep(host->dev, host->slot_id, 0,
1347 host->vdd, host->dpm_state == CARDSLEEP);
1348 if (mmc_card_can_sleep(host->mmc))
1349 mmc_card_awake(host->mmc);
1350
1351 dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n",
1352 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
dd498eff
DK		 1353
1354 host->dpm_state = ENABLED;
1355
13189e78 1356 mmc_release_host(host->mmc);
dd498eff
DK		 1357
1358 return 0;
1359}
1360
13189e78
JL		 1361/* Handler for [OFF -> ENABLED] transition */
1362static int omap_mmc_off_to_enabled(struct mmc_omap_host *host)
623821f7 1363{
623821f7 1364 clk_enable(host->fclk);
623821f7
AH		 1365
1366 omap_mmc_restore_ctx(host);
13189e78
JL		 1367 omap_hsmmc_init(host);
1368 mmc_power_restore_host(host->mmc);
623821f7
AH		 1369
1370 host->dpm_state = ENABLED;
1371
13189e78
JL		 1372 dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n");
1373
623821f7
AH		 1374 return 0;
1375}
1376
dd498eff
DK		 1377/*
1378 * Bring MMC host to ENABLED from any other PM state.
1379 */
1380static int omap_mmc_enable(struct mmc_host *mmc)
1381{
1382 struct mmc_omap_host *host = mmc_priv(mmc);
1383
1384 switch (host->dpm_state) {
1385 case DISABLED:
1386 return omap_mmc_disabled_to_enabled(host);
13189e78 1387 case CARDSLEEP:
623821f7 1388 case REGSLEEP:
13189e78 1389 return omap_mmc_sleep_to_enabled(host);
dd498eff
DK		 1390 case OFF:
1391 return omap_mmc_off_to_enabled(host);
1392 default:
1393 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1394 return -EINVAL;
1395 }
1396}
1397
1398/*
1399 * Bring MMC host in PM state (one level deeper).
1400 */
1401static int omap_mmc_disable(struct mmc_host *mmc, int lazy)
1402{
1403 struct mmc_omap_host *host = mmc_priv(mmc);
1404
1405 switch (host->dpm_state) {
1406 case ENABLED: {
1407 int delay;
1408
1409 delay = omap_mmc_enabled_to_disabled(host);
1410 if (lazy || delay < 0)
1411 return delay;
1412 return 0;
1413 }
1414 case DISABLED:
13189e78
JL		 1415 return omap_mmc_disabled_to_sleep(host);
1416 case CARDSLEEP:
1417 case REGSLEEP:
1418 return omap_mmc_sleep_to_off(host);
dd498eff
DK		 1419 default:
1420 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1421 return -EINVAL;
1422 }
1423}
1424
1425static int omap_mmc_enable_fclk(struct mmc_host *mmc)
1426{
1427 struct mmc_omap_host *host = mmc_priv(mmc);
1428 int err;
1429
1430 err = clk_enable(host->fclk);
1431 if (err)
1432 return err;
1433 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
1434 omap_mmc_restore_ctx(host);
1435 return 0;
1436}
1437
1438static int omap_mmc_disable_fclk(struct mmc_host *mmc, int lazy)
1439{
1440 struct mmc_omap_host *host = mmc_priv(mmc);
1441
1442 omap_mmc_save_ctx(host);
1443 clk_disable(host->fclk);
1444 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
1445 return 0;
1446}
1447
1448static const struct mmc_host_ops mmc_omap_ops = {
1449 .enable = omap_mmc_enable_fclk,
1450 .disable = omap_mmc_disable_fclk,
1451 .request = omap_mmc_request,
1452 .set_ios = omap_mmc_set_ios,
1453 .get_cd = omap_hsmmc_get_cd,
1454 .get_ro = omap_hsmmc_get_ro,
1455 /* NYET -- enable_sdio_irq */
1456};
1457
1458static const struct mmc_host_ops mmc_omap_ps_ops = {
5e2ea617
AH		 1459 .enable = omap_mmc_enable,
1460 .disable = omap_mmc_disable,
a45c6cb8
MC		 1461 .request = omap_mmc_request,
1462 .set_ios = omap_mmc_set_ios,
1463 .get_cd = omap_hsmmc_get_cd,
1464 .get_ro = omap_hsmmc_get_ro,
1465 /* NYET -- enable_sdio_irq */
1466};
1467
d900f712
DK		 1468#ifdef CONFIG_DEBUG_FS
1469
1470static int mmc_regs_show(struct seq_file *s, void *data)
1471{
1472 struct mmc_host *mmc = s->private;
1473 struct mmc_omap_host *host = mmc_priv(mmc);
11dd62a7
DK		 1474 struct omap_mmc_platform_data *pdata = host->pdata;
1475 int context_loss = 0;
1476
1477 if (pdata->get_context_loss_count)
1478 context_loss = pdata->get_context_loss_count(host->dev);
d900f712 1479
5e2ea617
AH		 1480 seq_printf(s, "mmc%d:\n"
1481 " enabled:\t%d\n"
dd498eff 1482 " dpm_state:\t%d\n"
5e2ea617 1483 " nesting_cnt:\t%d\n"
11dd62a7 1484 " ctx_loss:\t%d:%d\n"
5e2ea617 1485 "\nregs:\n",
dd498eff
DK		 1486 mmc->index, mmc->enabled ? 1 : 0,
1487 host->dpm_state, mmc->nesting_cnt,
11dd62a7 1488 host->context_loss, context_loss);
5e2ea617 1489
13189e78 1490 if (host->suspended || host->dpm_state == OFF) {
dd498eff
DK		 1491 seq_printf(s, "host suspended, can't read registers\n");
1492 return 0;
1493 }
1494
5e2ea617
AH		 1495 if (clk_enable(host->fclk) != 0) {
1496 seq_printf(s, "can't read the regs\n");
dd498eff 1497 return 0;
5e2ea617 1498 }
d900f712
DK		 1499
1500 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1501 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1502 seq_printf(s, "CON:\t\t0x%08x\n",
1503 OMAP_HSMMC_READ(host->base, CON));
1504 seq_printf(s, "HCTL:\t\t0x%08x\n",
1505 OMAP_HSMMC_READ(host->base, HCTL));
1506 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1507 OMAP_HSMMC_READ(host->base, SYSCTL));
1508 seq_printf(s, "IE:\t\t0x%08x\n",
1509 OMAP_HSMMC_READ(host->base, IE));
1510 seq_printf(s, "ISE:\t\t0x%08x\n",
1511 OMAP_HSMMC_READ(host->base, ISE));
1512 seq_printf(s, "CAPA:\t\t0x%08x\n",
1513 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617
AH		 1514
1515 clk_disable(host->fclk);
dd498eff 1516
d900f712
DK		 1517 return 0;
1518}
1519
1520static int mmc_regs_open(struct inode *inode, struct file *file)
1521{
1522 return single_open(file, mmc_regs_show, inode->i_private);
1523}
1524
1525static const struct file_operations mmc_regs_fops = {
1526 .open = mmc_regs_open,
1527 .read = seq_read,
1528 .llseek = seq_lseek,
1529 .release = single_release,
1530};
1531
1532static void omap_mmc_debugfs(struct mmc_host *mmc)
1533{
1534 if (mmc->debugfs_root)
1535 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1536 mmc, &mmc_regs_fops);
1537}
1538
1539#else
1540
1541static void omap_mmc_debugfs(struct mmc_host *mmc)
1542{
1543}
1544
1545#endif
1546
a45c6cb8
MC		 1547static int __init omap_mmc_probe(struct platform_device *pdev)
1548{
1549 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1550 struct mmc_host *mmc;
1551 struct mmc_omap_host *host = NULL;
1552 struct resource *res;
1553 int ret = 0, irq;
a45c6cb8
MC		 1554
1555 if (pdata == NULL) {
1556 dev_err(&pdev->dev, "Platform Data is missing\n");
1557 return -ENXIO;
1558 }
1559
1560 if (pdata->nr_slots == 0) {
1561 dev_err(&pdev->dev, "No Slots\n");
1562 return -ENXIO;
1563 }
1564
1565 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1566 irq = platform_get_irq(pdev, 0);
1567 if (res == NULL || irq < 0)
1568 return -ENXIO;
1569
1570 res = request_mem_region(res->start, res->end - res->start + 1,
1571 pdev->name);
1572 if (res == NULL)
1573 return -EBUSY;
1574
1575 mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
1576 if (!mmc) {
1577 ret = -ENOMEM;
1578 goto err;
1579 }
1580
1581 host = mmc_priv(mmc);
1582 host->mmc = mmc;
1583 host->pdata = pdata;
1584 host->dev = &pdev->dev;
1585 host->use_dma = 1;
1586 host->dev->dma_mask = &pdata->dma_mask;
1587 host->dma_ch = -1;
1588 host->irq = irq;
1589 host->id = pdev->id;
1590 host->slot_id = 0;
1591 host->mapbase = res->start;
1592 host->base = ioremap(host->mapbase, SZ_4K);
a3621465 1593 host->power_mode = -1;
a45c6cb8
MC		 1594
1595 platform_set_drvdata(pdev, host);
1596 INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
1597
191d1f1d 1598 if (mmc_slot(host).power_saving)
dd498eff
DK		 1599 mmc->ops = &mmc_omap_ps_ops;
1600 else
1601 mmc->ops = &mmc_omap_ops;
1602
a45c6cb8
MC		 1603 mmc->f_min = 400000;
1604 mmc->f_max = 52000000;
1605
1606 sema_init(&host->sem, 1);
4dffd7a2 1607 spin_lock_init(&host->irq_lock);
a45c6cb8 1608
6f7607cc 1609 host->iclk = clk_get(&pdev->dev, "ick");
a45c6cb8
MC		 1610 if (IS_ERR(host->iclk)) {
1611 ret = PTR_ERR(host->iclk);
1612 host->iclk = NULL;
1613 goto err1;
1614 }
6f7607cc 1615 host->fclk = clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 1616 if (IS_ERR(host->fclk)) {
1617 ret = PTR_ERR(host->fclk);
1618 host->fclk = NULL;
1619 clk_put(host->iclk);
1620 goto err1;
1621 }
1622
11dd62a7
DK		 1623 omap_mmc_save_ctx(host);
1624
5e2ea617 1625 mmc->caps |= MMC_CAP_DISABLE;
dd498eff
DK		 1626 mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT);
1627 /* we start off in DISABLED state */
1628 host->dpm_state = DISABLED;
1629
5e2ea617 1630 if (mmc_host_enable(host->mmc) != 0) {
a45c6cb8
MC		 1631 clk_put(host->iclk);
1632 clk_put(host->fclk);
1633 goto err1;
1634 }
1635
1636 if (clk_enable(host->iclk) != 0) {
5e2ea617 1637 mmc_host_disable(host->mmc);
a45c6cb8
MC		 1638 clk_put(host->iclk);
1639 clk_put(host->fclk);
1640 goto err1;
1641 }
1642
1643 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1644 /*
1645 * MMC can still work without debounce clock.
1646 */
1647 if (IS_ERR(host->dbclk))
1648 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n");
1649 else
1650 if (clk_enable(host->dbclk) != 0)
1651 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1652 " clk failed\n");
1653 else
1654 host->dbclk_enabled = 1;
1655
0ccd76d4
JY		 1656 /* Since we do only SG emulation, we can have as many segs
1657 * as we want. */
1658 mmc->max_phys_segs = 1024;
1659 mmc->max_hw_segs = 1024;
1660
a45c6cb8
MC		 1661 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1662 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1663 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1664 mmc->max_seg_size = mmc->max_req_size;
1665
13189e78
JL		 1666 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1667 MMC_CAP_WAIT_WHILE_BUSY;
a45c6cb8 1668
191d1f1d 1669 if (mmc_slot(host).wires >= 8)
73153010 1670 mmc->caps |= MMC_CAP_8_BIT_DATA;
191d1f1d 1671 else if (mmc_slot(host).wires >= 4)
a45c6cb8
MC		 1672 mmc->caps |= MMC_CAP_4_BIT_DATA;
1673
191d1f1d 1674 if (mmc_slot(host).nonremovable)
23d99bb9
AH		 1675 mmc->caps |= MMC_CAP_NONREMOVABLE;
1676
1b331e69 1677 omap_hsmmc_init(host);
a45c6cb8 1678
f3e2f1dd
GI		 1679 /* Select DMA lines */
1680 switch (host->id) {
1681 case OMAP_MMC1_DEVID:
1682 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
1683 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
1684 break;
1685 case OMAP_MMC2_DEVID:
1686 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
1687 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
1688 break;
1689 case OMAP_MMC3_DEVID:
1690 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
1691 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
1692 break;
1693 default:
1694 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
1695 goto err_irq;
1696 }
a45c6cb8
MC		 1697
1698 /* Request IRQ for MMC operations */
1699 ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1700 mmc_hostname(mmc), host);
1701 if (ret) {
1702 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1703 goto err_irq;
1704 }
1705
b583f26d 1706 /* initialize power supplies, gpios, etc */
a45c6cb8
MC		 1707 if (pdata->init != NULL) {
1708 if (pdata->init(&pdev->dev) != 0) {
b583f26d 1709 dev_dbg(mmc_dev(host->mmc), "late init error\n");
a45c6cb8
MC		 1710 goto err_irq_cd_init;
1711 }
1712 }
b583f26d 1713 mmc->ocr_avail = mmc_slot(host).ocr_mask;
a45c6cb8
MC		 1714
1715 /* Request IRQ for card detect */
e1a55f5e 1716 if ((mmc_slot(host).card_detect_irq)) {
a45c6cb8
MC		 1717 ret = request_irq(mmc_slot(host).card_detect_irq,
1718 omap_mmc_cd_handler,
1719 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1720 | IRQF_DISABLED,
1721 mmc_hostname(mmc), host);
1722 if (ret) {
1723 dev_dbg(mmc_dev(host->mmc),
1724 "Unable to grab MMC CD IRQ\n");
1725 goto err_irq_cd;
1726 }
1727 }
1728
1729 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1730 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1731
5e2ea617
AH		 1732 mmc_host_lazy_disable(host->mmc);
1733
a45c6cb8
MC		 1734 mmc_add_host(mmc);
1735
191d1f1d 1736 if (mmc_slot(host).name != NULL) {
a45c6cb8
MC		 1737 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1738 if (ret < 0)
1739 goto err_slot_name;
1740 }
191d1f1d 1741 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
a45c6cb8
MC		 1742 ret = device_create_file(&mmc->class_dev,
1743 &dev_attr_cover_switch);
1744 if (ret < 0)
1745 goto err_cover_switch;
1746 }
1747
d900f712
DK		 1748 omap_mmc_debugfs(mmc);
1749
a45c6cb8
MC		 1750 return 0;
1751
1752err_cover_switch:
1753 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1754err_slot_name:
1755 mmc_remove_host(mmc);
1756err_irq_cd:
1757 free_irq(mmc_slot(host).card_detect_irq, host);
1758err_irq_cd_init:
1759 free_irq(host->irq, host);
1760err_irq:
5e2ea617 1761 mmc_host_disable(host->mmc);
a45c6cb8
MC		 1762 clk_disable(host->iclk);
1763 clk_put(host->fclk);
1764 clk_put(host->iclk);
1765 if (host->dbclk_enabled) {
1766 clk_disable(host->dbclk);
1767 clk_put(host->dbclk);
1768 }
1769
1770err1:
1771 iounmap(host->base);
1772err:
1773 dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1774 release_mem_region(res->start, res->end - res->start + 1);
1775 if (host)
1776 mmc_free_host(mmc);
1777 return ret;
1778}
1779
1780static int omap_mmc_remove(struct platform_device *pdev)
1781{
1782 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1783 struct resource *res;
1784
1785 if (host) {
5e2ea617 1786 mmc_host_enable(host->mmc);
a45c6cb8
MC		 1787 mmc_remove_host(host->mmc);
1788 if (host->pdata->cleanup)
1789 host->pdata->cleanup(&pdev->dev);
1790 free_irq(host->irq, host);
1791 if (mmc_slot(host).card_detect_irq)
1792 free_irq(mmc_slot(host).card_detect_irq, host);
1793 flush_scheduled_work();
1794
5e2ea617 1795 mmc_host_disable(host->mmc);
a45c6cb8
MC		 1796 clk_disable(host->iclk);
1797 clk_put(host->fclk);
1798 clk_put(host->iclk);
1799 if (host->dbclk_enabled) {
1800 clk_disable(host->dbclk);
1801 clk_put(host->dbclk);
1802 }
1803
1804 mmc_free_host(host->mmc);
1805 iounmap(host->base);
1806 }
1807
1808 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1809 if (res)
1810 release_mem_region(res->start, res->end - res->start + 1);
1811 platform_set_drvdata(pdev, NULL);
1812
1813 return 0;
1814}
1815
1816#ifdef CONFIG_PM
1817static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1818{
1819 int ret = 0;
1820 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1821
1822 if (host && host->suspended)
1823 return 0;
1824
1825 if (host) {
a6b2240d
AH		 1826 host->suspended = 1;
1827 if (host->pdata->suspend) {
1828 ret = host->pdata->suspend(&pdev->dev,
1829 host->slot_id);
1830 if (ret) {
1831 dev_dbg(mmc_dev(host->mmc),
1832 "Unable to handle MMC board"
1833 " level suspend\n");
1834 host->suspended = 0;
1835 return ret;
1836 }
1837 }
1838 cancel_work_sync(&host->mmc_carddetect_work);
5e2ea617 1839 mmc_host_enable(host->mmc);
a45c6cb8
MC		 1840 ret = mmc_suspend_host(host->mmc, state);
1841 if (ret == 0) {
a45c6cb8
MC		 1842 OMAP_HSMMC_WRITE(host->base, ISE, 0);
1843 OMAP_HSMMC_WRITE(host->base, IE, 0);
1844
a45c6cb8 1845
0683af48 1846 OMAP_HSMMC_WRITE(host->base, HCTL,
191d1f1d 1847 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
5e2ea617 1848 mmc_host_disable(host->mmc);
a45c6cb8
MC		 1849 clk_disable(host->iclk);
1850 clk_disable(host->dbclk);
a6b2240d
AH		 1851 } else {
1852 host->suspended = 0;
1853 if (host->pdata->resume) {
1854 ret = host->pdata->resume(&pdev->dev,
1855 host->slot_id);
1856 if (ret)
1857 dev_dbg(mmc_dev(host->mmc),
1858 "Unmask interrupt failed\n");
1859 }
5e2ea617 1860 mmc_host_disable(host->mmc);
a6b2240d 1861 }
a45c6cb8
MC		 1862
1863 }
1864 return ret;
1865}
1866
1867/* Routine to resume the MMC device */
1868static int omap_mmc_resume(struct platform_device *pdev)
1869{
1870 int ret = 0;
1871 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1872
1873 if (host && !host->suspended)
1874 return 0;
1875
1876 if (host) {
a45c6cb8 1877 ret = clk_enable(host->iclk);
11dd62a7 1878 if (ret)
a45c6cb8 1879 goto clk_en_err;
a45c6cb8
MC		 1880
1881 if (clk_enable(host->dbclk) != 0)
1882 dev_dbg(mmc_dev(host->mmc),
1883 "Enabling debounce clk failed\n");
1884
11dd62a7
DK		 1885 if (mmc_host_enable(host->mmc) != 0) {
1886 clk_disable(host->iclk);
1887 goto clk_en_err;
1888 }
1889
1b331e69
KK		 1890 omap_hsmmc_init(host);
1891
a45c6cb8
MC		 1892 if (host->pdata->resume) {
1893 ret = host->pdata->resume(&pdev->dev, host->slot_id);
1894 if (ret)
1895 dev_dbg(mmc_dev(host->mmc),
1896 "Unmask interrupt failed\n");
1897 }
1898
1899 /* Notify the core to resume the host */
1900 ret = mmc_resume_host(host->mmc);
1901 if (ret == 0)
1902 host->suspended = 0;
5e2ea617 1903 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 1904 }
1905
1906 return ret;
1907
1908clk_en_err:
1909 dev_dbg(mmc_dev(host->mmc),
1910 "Failed to enable MMC clocks during resume\n");
1911 return ret;
1912}
1913
1914#else
1915#define omap_mmc_suspend NULL
1916#define omap_mmc_resume NULL
1917#endif
1918
1919static struct platform_driver omap_mmc_driver = {
a45c6cb8
MC		 1920 .remove = omap_mmc_remove,
1921 .suspend = omap_mmc_suspend,
1922 .resume = omap_mmc_resume,
1923 .driver = {
1924 .name = DRIVER_NAME,
1925 .owner = THIS_MODULE,
1926 },
1927};
1928
1929static int __init omap_mmc_init(void)
1930{
1931 /* Register the MMC driver */
f400cd8c 1932 return platform_driver_probe(&omap_mmc_driver, omap_mmc_probe);
a45c6cb8
MC		 1933}
1934
1935static void __exit omap_mmc_cleanup(void)
1936{
1937 /* Unregister MMC driver */
1938 platform_driver_unregister(&omap_mmc_driver);
1939}
1940
1941module_init(omap_mmc_init);
1942module_exit(omap_mmc_cleanup);
1943
1944MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1945MODULE_LICENSE("GPL");
1946MODULE_ALIAS("platform:" DRIVER_NAME);
1947MODULE_AUTHOR("Texas Instruments Inc");
Linux kernel - Deliverables
This page took 0.245692 seconds and 5 git commands to generate.