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omap_hsmmc: ensure workqueues are empty before suspend
[deliverable/linux.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
d900f712
DK		 20#include <linux/debugfs.h>
21#include <linux/seq_file.h>
a45c6cb8
MC		 22#include <linux/interrupt.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
25#include <linux/platform_device.h>
26#include <linux/workqueue.h>
27#include <linux/timer.h>
28#include <linux/clk.h>
29#include <linux/mmc/host.h>
30#include <linux/io.h>
31#include <linux/semaphore.h>
32#include <mach/dma.h>
33#include <mach/hardware.h>
34#include <mach/board.h>
35#include <mach/mmc.h>
36#include <mach/cpu.h>
37
38/* OMAP HSMMC Host Controller Registers */
39#define OMAP_HSMMC_SYSCONFIG 0x0010
11dd62a7 40#define OMAP_HSMMC_SYSSTATUS 0x0014
a45c6cb8
MC		 41#define OMAP_HSMMC_CON 0x002C
42#define OMAP_HSMMC_BLK 0x0104
43#define OMAP_HSMMC_ARG 0x0108
44#define OMAP_HSMMC_CMD 0x010C
45#define OMAP_HSMMC_RSP10 0x0110
46#define OMAP_HSMMC_RSP32 0x0114
47#define OMAP_HSMMC_RSP54 0x0118
48#define OMAP_HSMMC_RSP76 0x011C
49#define OMAP_HSMMC_DATA 0x0120
50#define OMAP_HSMMC_HCTL 0x0128
51#define OMAP_HSMMC_SYSCTL 0x012C
52#define OMAP_HSMMC_STAT 0x0130
53#define OMAP_HSMMC_IE 0x0134
54#define OMAP_HSMMC_ISE 0x0138
55#define OMAP_HSMMC_CAPA 0x0140
56
57#define VS18 (1 << 26)
58#define VS30 (1 << 25)
59#define SDVS18 (0x5 << 9)
60#define SDVS30 (0x6 << 9)
eb250826 61#define SDVS33 (0x7 << 9)
1b331e69 62#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 63#define SDVSCLR 0xFFFFF1FF
64#define SDVSDET 0x00000400
65#define AUTOIDLE 0x1
66#define SDBP (1 << 8)
67#define DTO 0xe
68#define ICE 0x1
69#define ICS 0x2
70#define CEN (1 << 2)
71#define CLKD_MASK 0x0000FFC0
72#define CLKD_SHIFT 6
73#define DTO_MASK 0x000F0000
74#define DTO_SHIFT 16
75#define INT_EN_MASK 0x307F0033
ccdfe3a6
AG		 76#define BWR_ENABLE (1 << 4)
77#define BRR_ENABLE (1 << 5)
a45c6cb8
MC		 78#define INIT_STREAM (1 << 1)
79#define DP_SELECT (1 << 21)
80#define DDIR (1 << 4)
81#define DMA_EN 0x1
82#define MSBS (1 << 5)
83#define BCE (1 << 1)
84#define FOUR_BIT (1 << 1)
73153010 85#define DW8 (1 << 5)
a45c6cb8
MC		 86#define CC 0x1
87#define TC 0x02
88#define OD 0x1
89#define ERR (1 << 15)
90#define CMD_TIMEOUT (1 << 16)
91#define DATA_TIMEOUT (1 << 20)
92#define CMD_CRC (1 << 17)
93#define DATA_CRC (1 << 21)
94#define CARD_ERR (1 << 28)
95#define STAT_CLEAR 0xFFFFFFFF
96#define INIT_STREAM_CMD 0x00000000
97#define DUAL_VOLT_OCR_BIT 7
98#define SRC (1 << 25)
99#define SRD (1 << 26)
11dd62a7
DK		 100#define SOFTRESET (1 << 1)
101#define RESETDONE (1 << 0)
a45c6cb8
MC		 102
103/*
104 * FIXME: Most likely all the data using these _DEVID defines should come
105 * from the platform_data, or implemented in controller and slot specific
106 * functions.
107 */
108#define OMAP_MMC1_DEVID 0
109#define OMAP_MMC2_DEVID 1
f3e2f1dd 110#define OMAP_MMC3_DEVID 2
a45c6cb8 111
a45c6cb8
MC		 112#define MMC_TIMEOUT_MS 20
113#define OMAP_MMC_MASTER_CLOCK 96000000
114#define DRIVER_NAME "mmci-omap-hs"
115
116/*
117 * One controller can have multiple slots, like on some omap boards using
118 * omap.c controller driver. Luckily this is not currently done on any known
119 * omap_hsmmc.c device.
120 */
121#define mmc_slot(host) (host->pdata->slots[host->slot_id])
122
123/*
124 * MMC Host controller read/write API's
125 */
126#define OMAP_HSMMC_READ(base, reg) \
127 __raw_readl((base) + OMAP_HSMMC_##reg)
128
129#define OMAP_HSMMC_WRITE(base, reg, val) \
130 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
131
132struct mmc_omap_host {
133 struct device *dev;
134 struct mmc_host *mmc;
135 struct mmc_request *mrq;
136 struct mmc_command *cmd;
137 struct mmc_data *data;
138 struct clk *fclk;
139 struct clk *iclk;
140 struct clk *dbclk;
141 struct semaphore sem;
142 struct work_struct mmc_carddetect_work;
143 void __iomem *base;
144 resource_size_t mapbase;
145 unsigned int id;
146 unsigned int dma_len;
0ccd76d4 147 unsigned int dma_sg_idx;
a45c6cb8 148 unsigned char bus_mode;
a3621465 149 unsigned char power_mode;
a45c6cb8
MC		 150 u32 *buffer;
151 u32 bytesleft;
152 int suspended;
153 int irq;
a45c6cb8 154 int use_dma, dma_ch;
f3e2f1dd 155 int dma_line_tx, dma_line_rx;
a45c6cb8
MC		 156 int slot_id;
157 int dbclk_enabled;
4a694dc9 158 int response_busy;
11dd62a7
DK		 159 int context_loss;
160
a45c6cb8
MC		 161 struct omap_mmc_platform_data *pdata;
162};
163
164/*
165 * Stop clock to the card
166 */
167static void omap_mmc_stop_clock(struct mmc_omap_host *host)
168{
169 OMAP_HSMMC_WRITE(host->base, SYSCTL,
170 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
171 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
172 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
173}
174
11dd62a7
DK		 175#ifdef CONFIG_PM
176
177/*
178 * Restore the MMC host context, if it was lost as result of a
179 * power state change.
180 */
181static int omap_mmc_restore_ctx(struct mmc_omap_host *host)
182{
183 struct mmc_ios *ios = &host->mmc->ios;
184 struct omap_mmc_platform_data *pdata = host->pdata;
185 int context_loss = 0;
186 u32 hctl, capa, con;
187 u16 dsor = 0;
188 unsigned long timeout;
189
190 if (pdata->get_context_loss_count) {
191 context_loss = pdata->get_context_loss_count(host->dev);
192 if (context_loss < 0)
193 return 1;
194 }
195
196 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
197 context_loss == host->context_loss ? "not " : "");
198 if (host->context_loss == context_loss)
199 return 1;
200
201 /* Wait for hardware reset */
202 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
203 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
204 && time_before(jiffies, timeout))
205 ;
206
207 /* Do software reset */
208 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
209 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
210 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
211 && time_before(jiffies, timeout))
212 ;
213
214 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
215 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
216
217 if (host->id == OMAP_MMC1_DEVID) {
218 if (host->power_mode != MMC_POWER_OFF &&
219 (1 << ios->vdd) <= MMC_VDD_23_24)
220 hctl = SDVS18;
221 else
222 hctl = SDVS30;
223 capa = VS30 | VS18;
224 } else {
225 hctl = SDVS18;
226 capa = VS18;
227 }
228
229 OMAP_HSMMC_WRITE(host->base, HCTL,
230 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
231
232 OMAP_HSMMC_WRITE(host->base, CAPA,
233 OMAP_HSMMC_READ(host->base, CAPA) | capa);
234
235 OMAP_HSMMC_WRITE(host->base, HCTL,
236 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
237
238 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
239 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
240 && time_before(jiffies, timeout))
241 ;
242
243 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
244 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
245 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
246
247 /* Do not initialize card-specific things if the power is off */
248 if (host->power_mode == MMC_POWER_OFF)
249 goto out;
250
251 con = OMAP_HSMMC_READ(host->base, CON);
252 switch (ios->bus_width) {
253 case MMC_BUS_WIDTH_8:
254 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
255 break;
256 case MMC_BUS_WIDTH_4:
257 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
258 OMAP_HSMMC_WRITE(host->base, HCTL,
259 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
260 break;
261 case MMC_BUS_WIDTH_1:
262 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
263 OMAP_HSMMC_WRITE(host->base, HCTL,
264 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
265 break;
266 }
267
268 if (ios->clock) {
269 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
270 if (dsor < 1)
271 dsor = 1;
272
273 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
274 dsor++;
275
276 if (dsor > 250)
277 dsor = 250;
278 }
279
280 OMAP_HSMMC_WRITE(host->base, SYSCTL,
281 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
282 OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
283 OMAP_HSMMC_WRITE(host->base, SYSCTL,
284 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
285
286 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
287 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
288 && time_before(jiffies, timeout))
289 ;
290
291 OMAP_HSMMC_WRITE(host->base, SYSCTL,
292 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
293
294 con = OMAP_HSMMC_READ(host->base, CON);
295 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
296 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
297 else
298 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
299out:
300 host->context_loss = context_loss;
301
302 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
303 return 0;
304}
305
306/*
307 * Save the MMC host context (store the number of power state changes so far).
308 */
309static void omap_mmc_save_ctx(struct mmc_omap_host *host)
310{
311 struct omap_mmc_platform_data *pdata = host->pdata;
312 int context_loss;
313
314 if (pdata->get_context_loss_count) {
315 context_loss = pdata->get_context_loss_count(host->dev);
316 if (context_loss < 0)
317 return;
318 host->context_loss = context_loss;
319 }
320}
321
322#else
323
324static int omap_mmc_restore_ctx(struct mmc_omap_host *host)
325{
326 return 0;
327}
328
329static void omap_mmc_save_ctx(struct mmc_omap_host *host)
330{
331}
332
333#endif
334
a45c6cb8
MC		 335/*
336 * Send init stream sequence to card
337 * before sending IDLE command
338 */
339static void send_init_stream(struct mmc_omap_host *host)
340{
341 int reg = 0;
342 unsigned long timeout;
343
344 disable_irq(host->irq);
345 OMAP_HSMMC_WRITE(host->base, CON,
346 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
347 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
348
349 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
350 while ((reg != CC) && time_before(jiffies, timeout))
351 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
352
353 OMAP_HSMMC_WRITE(host->base, CON,
354 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
355 enable_irq(host->irq);
356}
357
358static inline
359int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
360{
361 int r = 1;
362
363 if (host->pdata->slots[host->slot_id].get_cover_state)
364 r = host->pdata->slots[host->slot_id].get_cover_state(host->dev,
365 host->slot_id);
366 return r;
367}
368
369static ssize_t
370mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
371 char *buf)
372{
373 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
374 struct mmc_omap_host *host = mmc_priv(mmc);
375
376 return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
377 "open");
378}
379
380static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
381
382static ssize_t
383mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
384 char *buf)
385{
386 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
387 struct mmc_omap_host *host = mmc_priv(mmc);
388 struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
389
e68fdabc 390 return sprintf(buf, "%s\n", slot.name);
a45c6cb8
MC		 391}
392
393static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
394
395/*
396 * Configure the response type and send the cmd.
397 */
398static void
399mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
400 struct mmc_data *data)
401{
402 int cmdreg = 0, resptype = 0, cmdtype = 0;
403
404 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
405 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
406 host->cmd = cmd;
407
408 /*
409 * Clear status bits and enable interrupts
410 */
411 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
412 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
ccdfe3a6
AG		 413
414 if (host->use_dma)
415 OMAP_HSMMC_WRITE(host->base, IE,
416 INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE));
417 else
418 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8 419
4a694dc9 420 host->response_busy = 0;
a45c6cb8
MC		 421 if (cmd->flags & MMC_RSP_PRESENT) {
422 if (cmd->flags & MMC_RSP_136)
423 resptype = 1;
4a694dc9
AH		 424 else if (cmd->flags & MMC_RSP_BUSY) {
425 resptype = 3;
426 host->response_busy = 1;
427 } else
a45c6cb8
MC		 428 resptype = 2;
429 }
430
431 /*
432 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
433 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
434 * a val of 0x3, rest 0x0.
435 */
436 if (cmd == host->mrq->stop)
437 cmdtype = 0x3;
438
439 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
440
441 if (data) {
442 cmdreg |= DP_SELECT | MSBS | BCE;
443 if (data->flags & MMC_DATA_READ)
444 cmdreg |= DDIR;
445 else
446 cmdreg &= ~(DDIR);
447 }
448
449 if (host->use_dma)
450 cmdreg |= DMA_EN;
451
452 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
453 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
454}
455
0ccd76d4
JY		 456static int
457mmc_omap_get_dma_dir(struct mmc_omap_host *host, struct mmc_data *data)
458{
459 if (data->flags & MMC_DATA_WRITE)
460 return DMA_TO_DEVICE;
461 else
462 return DMA_FROM_DEVICE;
463}
464
a45c6cb8
MC		 465/*
466 * Notify the transfer complete to MMC core
467 */
468static void
469mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
470{
4a694dc9
AH		 471 if (!data) {
472 struct mmc_request *mrq = host->mrq;
473
474 host->mrq = NULL;
4a694dc9
AH		 475 mmc_request_done(host->mmc, mrq);
476 return;
477 }
478
a45c6cb8
MC		 479 host->data = NULL;
480
481 if (host->use_dma && host->dma_ch != -1)
482 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
0ccd76d4 483 mmc_omap_get_dma_dir(host, data));
a45c6cb8
MC		 484
485 if (!data->error)
486 data->bytes_xfered += data->blocks * (data->blksz);
487 else
488 data->bytes_xfered = 0;
489
490 if (!data->stop) {
491 host->mrq = NULL;
492 mmc_request_done(host->mmc, data->mrq);
493 return;
494 }
495 mmc_omap_start_command(host, data->stop, NULL);
496}
497
498/*
499 * Notify the core about command completion
500 */
501static void
502mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
503{
504 host->cmd = NULL;
505
506 if (cmd->flags & MMC_RSP_PRESENT) {
507 if (cmd->flags & MMC_RSP_136) {
508 /* response type 2 */
509 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
510 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
511 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
512 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
513 } else {
514 /* response types 1, 1b, 3, 4, 5, 6 */
515 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
516 }
517 }
4a694dc9 518 if ((host->data == NULL && !host->response_busy) || cmd->error) {
a45c6cb8
MC		 519 host->mrq = NULL;
520 mmc_request_done(host->mmc, cmd->mrq);
521 }
522}
523
524/*
525 * DMA clean up for command errors
526 */
82788ff5 527static void mmc_dma_cleanup(struct mmc_omap_host *host, int errno)
a45c6cb8 528{
82788ff5 529 host->data->error = errno;
a45c6cb8
MC		 530
531 if (host->use_dma && host->dma_ch != -1) {
532 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
0ccd76d4 533 mmc_omap_get_dma_dir(host, host->data));
a45c6cb8
MC		 534 omap_free_dma(host->dma_ch);
535 host->dma_ch = -1;
536 up(&host->sem);
537 }
538 host->data = NULL;
a45c6cb8
MC		 539}
540
541/*
542 * Readable error output
543 */
544#ifdef CONFIG_MMC_DEBUG
545static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
546{
547 /* --- means reserved bit without definition at documentation */
548 static const char *mmc_omap_status_bits[] = {
549 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
550 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
551 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
552 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
553 };
554 char res[256];
555 char *buf = res;
556 int len, i;
557
558 len = sprintf(buf, "MMC IRQ 0x%x :", status);
559 buf += len;
560
561 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
562 if (status & (1 << i)) {
563 len = sprintf(buf, " %s", mmc_omap_status_bits[i]);
564 buf += len;
565 }
566
567 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
568}
569#endif /* CONFIG_MMC_DEBUG */
570
3ebf74b1
JP		 571/*
572 * MMC controller internal state machines reset
573 *
574 * Used to reset command or data internal state machines, using respectively
575 * SRC or SRD bit of SYSCTL register
576 * Can be called from interrupt context
577 */
578static inline void mmc_omap_reset_controller_fsm(struct mmc_omap_host *host,
579 unsigned long bit)
580{
581 unsigned long i = 0;
582 unsigned long limit = (loops_per_jiffy *
583 msecs_to_jiffies(MMC_TIMEOUT_MS));
584
585 OMAP_HSMMC_WRITE(host->base, SYSCTL,
586 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
587
588 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
589 (i++ < limit))
590 cpu_relax();
591
592 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
593 dev_err(mmc_dev(host->mmc),
594 "Timeout waiting on controller reset in %s\n",
595 __func__);
596}
a45c6cb8
MC		 597
598/*
599 * MMC controller IRQ handler
600 */
601static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
602{
603 struct mmc_omap_host *host = dev_id;
604 struct mmc_data *data;
605 int end_cmd = 0, end_trans = 0, status;
606
4a694dc9 607 if (host->mrq == NULL) {
a45c6cb8
MC		 608 OMAP_HSMMC_WRITE(host->base, STAT,
609 OMAP_HSMMC_READ(host->base, STAT));
00adadc1
KH		 610 /* Flush posted write */
611 OMAP_HSMMC_READ(host->base, STAT);
a45c6cb8
MC		 612 return IRQ_HANDLED;
613 }
614
615 data = host->data;
616 status = OMAP_HSMMC_READ(host->base, STAT);
617 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
618
619 if (status & ERR) {
620#ifdef CONFIG_MMC_DEBUG
621 mmc_omap_report_irq(host, status);
622#endif
623 if ((status & CMD_TIMEOUT) ||
624 (status & CMD_CRC)) {
625 if (host->cmd) {
626 if (status & CMD_TIMEOUT) {
3ebf74b1 627 mmc_omap_reset_controller_fsm(host, SRC);
a45c6cb8
MC		 628 host->cmd->error = -ETIMEDOUT;
629 } else {
630 host->cmd->error = -EILSEQ;
631 }
632 end_cmd = 1;
633 }
4a694dc9
AH		 634 if (host->data || host->response_busy) {
635 if (host->data)
636 mmc_dma_cleanup(host, -ETIMEDOUT);
637 host->response_busy = 0;
3ebf74b1 638 mmc_omap_reset_controller_fsm(host, SRD);
c232f457 639 }
a45c6cb8
MC		 640 }
641 if ((status & DATA_TIMEOUT) ||
642 (status & DATA_CRC)) {
4a694dc9
AH		 643 if (host->data || host->response_busy) {
644 int err = (status & DATA_TIMEOUT) ?
645 -ETIMEDOUT : -EILSEQ;
646
647 if (host->data)
648 mmc_dma_cleanup(host, err);
a45c6cb8 649 else
4a694dc9
AH		 650 host->mrq->cmd->error = err;
651 host->response_busy = 0;
3ebf74b1 652 mmc_omap_reset_controller_fsm(host, SRD);
a45c6cb8
MC		 653 end_trans = 1;
654 }
655 }
656 if (status & CARD_ERR) {
657 dev_dbg(mmc_dev(host->mmc),
658 "Ignoring card err CMD%d\n", host->cmd->opcode);
659 if (host->cmd)
660 end_cmd = 1;
661 if (host->data)
662 end_trans = 1;
663 }
664 }
665
666 OMAP_HSMMC_WRITE(host->base, STAT, status);
00adadc1
KH		 667 /* Flush posted write */
668 OMAP_HSMMC_READ(host->base, STAT);
a45c6cb8 669
a8fe29d8 670 if (end_cmd || ((status & CC) && host->cmd))
a45c6cb8
MC		 671 mmc_omap_cmd_done(host, host->cmd);
672 if (end_trans || (status & TC))
673 mmc_omap_xfer_done(host, data);
674
675 return IRQ_HANDLED;
676}
677
e13bb300
AH		 678static void set_sd_bus_power(struct mmc_omap_host *host)
679{
680 unsigned long i;
681
682 OMAP_HSMMC_WRITE(host->base, HCTL,
683 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
684 for (i = 0; i < loops_per_jiffy; i++) {
685 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
686 break;
687 cpu_relax();
688 }
689}
690
a45c6cb8 691/*
eb250826
DB		 692 * Switch MMC interface voltage ... only relevant for MMC1.
693 *
694 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
695 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
696 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8
MC		 697 */
698static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
699{
700 u32 reg_val = 0;
701 int ret;
702
703 /* Disable the clocks */
704 clk_disable(host->fclk);
705 clk_disable(host->iclk);
706 clk_disable(host->dbclk);
707
708 /* Turn the power off */
709 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
710 if (ret != 0)
711 goto err;
712
713 /* Turn the power ON with given VDD 1.8 or 3.0v */
714 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
715 if (ret != 0)
716 goto err;
717
718 clk_enable(host->fclk);
719 clk_enable(host->iclk);
720 clk_enable(host->dbclk);
721
722 OMAP_HSMMC_WRITE(host->base, HCTL,
723 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
724 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 725
a45c6cb8
MC		 726 /*
727 * If a MMC dual voltage card is detected, the set_ios fn calls
728 * this fn with VDD bit set for 1.8V. Upon card removal from the
729 * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
730 *
eb250826
DB		 731 * Cope with a bit of slop in the range ... per data sheets:
732 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
733 * but recommended values are 1.71V to 1.89V
734 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
735 * but recommended values are 2.7V to 3.3V
736 *
737 * Board setup code shouldn't permit anything very out-of-range.
738 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
739 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 740 */
eb250826 741 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 742 reg_val |= SDVS18;
eb250826
DB		 743 else
744 reg_val |= SDVS30;
a45c6cb8
MC		 745
746 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 747 set_sd_bus_power(host);
a45c6cb8
MC		 748
749 return 0;
750err:
751 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
752 return ret;
753}
754
755/*
756 * Work Item to notify the core about card insertion/removal
757 */
758static void mmc_omap_detect(struct work_struct *work)
759{
760 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
761 mmc_carddetect_work);
249d0fa9 762 struct omap_mmc_slot_data *slot = &mmc_slot(host);
a6b2240d
AH		 763 int carddetect;
764
765 if (host->suspended)
766 return;
767
768 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
249d0fa9 769
e1a55f5e 770 if (mmc_slot(host).card_detect)
a6b2240d 771 carddetect = slot->card_detect(slot->card_detect_irq);
e1a55f5e 772 else
a6b2240d 773 carddetect = -ENOSYS;
a45c6cb8 774
a6b2240d 775 if (carddetect) {
a45c6cb8
MC		 776 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
777 } else {
5e2ea617 778 mmc_host_enable(host->mmc);
3ebf74b1 779 mmc_omap_reset_controller_fsm(host, SRD);
5e2ea617 780 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 781 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
782 }
783}
784
785/*
786 * ISR for handling card insertion and removal
787 */
788static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
789{
790 struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
791
a6b2240d
AH		 792 if (host->suspended)
793 return IRQ_HANDLED;
a45c6cb8
MC		 794 schedule_work(&host->mmc_carddetect_work);
795
796 return IRQ_HANDLED;
797}
798
0ccd76d4
JY		 799static int mmc_omap_get_dma_sync_dev(struct mmc_omap_host *host,
800 struct mmc_data *data)
801{
802 int sync_dev;
803
f3e2f1dd
GI		 804 if (data->flags & MMC_DATA_WRITE)
805 sync_dev = host->dma_line_tx;
806 else
807 sync_dev = host->dma_line_rx;
0ccd76d4
JY		 808 return sync_dev;
809}
810
811static void mmc_omap_config_dma_params(struct mmc_omap_host *host,
812 struct mmc_data *data,
813 struct scatterlist *sgl)
814{
815 int blksz, nblk, dma_ch;
816
817 dma_ch = host->dma_ch;
818 if (data->flags & MMC_DATA_WRITE) {
819 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
820 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
821 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
822 sg_dma_address(sgl), 0, 0);
823 } else {
824 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
825 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
826 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
827 sg_dma_address(sgl), 0, 0);
828 }
829
830 blksz = host->data->blksz;
831 nblk = sg_dma_len(sgl) / blksz;
832
833 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
834 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
835 mmc_omap_get_dma_sync_dev(host, data),
836 !(data->flags & MMC_DATA_WRITE));
837
838 omap_start_dma(dma_ch);
839}
840
a45c6cb8
MC		 841/*
842 * DMA call back function
843 */
844static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
845{
846 struct mmc_omap_host *host = data;
847
848 if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
849 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
850
851 if (host->dma_ch < 0)
852 return;
853
0ccd76d4
JY		 854 host->dma_sg_idx++;
855 if (host->dma_sg_idx < host->dma_len) {
856 /* Fire up the next transfer. */
857 mmc_omap_config_dma_params(host, host->data,
858 host->data->sg + host->dma_sg_idx);
859 return;
860 }
861
a45c6cb8
MC		 862 omap_free_dma(host->dma_ch);
863 host->dma_ch = -1;
864 /*
865 * DMA Callback: run in interrupt context.
85b84322 866 * mutex_unlock will throw a kernel warning if used.
a45c6cb8
MC		 867 */
868 up(&host->sem);
869}
870
a45c6cb8
MC		 871/*
872 * Routine to configure and start DMA for the MMC card
873 */
874static int
875mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
876{
0ccd76d4 877 int dma_ch = 0, ret = 0, err = 1, i;
a45c6cb8
MC		 878 struct mmc_data *data = req->data;
879
0ccd76d4
JY		 880 /* Sanity check: all the SG entries must be aligned by block size. */
881 for (i = 0; i < host->dma_len; i++) {
882 struct scatterlist *sgl;
883
884 sgl = data->sg + i;
885 if (sgl->length % data->blksz)
886 return -EINVAL;
887 }
888 if ((data->blksz % 4) != 0)
889 /* REVISIT: The MMC buffer increments only when MSB is written.
890 * Return error for blksz which is non multiple of four.
891 */
892 return -EINVAL;
893
a45c6cb8
MC		 894 /*
895 * If for some reason the DMA transfer is still active,
896 * we wait for timeout period and free the dma
897 */
898 if (host->dma_ch != -1) {
899 set_current_state(TASK_UNINTERRUPTIBLE);
900 schedule_timeout(100);
901 if (down_trylock(&host->sem)) {
902 omap_free_dma(host->dma_ch);
903 host->dma_ch = -1;
904 up(&host->sem);
905 return err;
906 }
907 } else {
908 if (down_trylock(&host->sem))
909 return err;
910 }
911
0ccd76d4
JY		 912 ret = omap_request_dma(mmc_omap_get_dma_sync_dev(host, data), "MMC/SD",
913 mmc_omap_dma_cb,host, &dma_ch);
a45c6cb8 914 if (ret != 0) {
0ccd76d4 915 dev_err(mmc_dev(host->mmc),
a45c6cb8
MC		 916 "%s: omap_request_dma() failed with %d\n",
917 mmc_hostname(host->mmc), ret);
918 return ret;
919 }
920
921 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
0ccd76d4 922 data->sg_len, mmc_omap_get_dma_dir(host, data));
a45c6cb8 923 host->dma_ch = dma_ch;
0ccd76d4 924 host->dma_sg_idx = 0;
a45c6cb8 925
0ccd76d4 926 mmc_omap_config_dma_params(host, data, data->sg);
a45c6cb8 927
a45c6cb8
MC		 928 return 0;
929}
930
931static void set_data_timeout(struct mmc_omap_host *host,
932 struct mmc_request *req)
933{
934 unsigned int timeout, cycle_ns;
935 uint32_t reg, clkd, dto = 0;
936
937 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
938 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
939 if (clkd == 0)
940 clkd = 1;
941
942 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
943 timeout = req->data->timeout_ns / cycle_ns;
944 timeout += req->data->timeout_clks;
945 if (timeout) {
946 while ((timeout & 0x80000000) == 0) {
947 dto += 1;
948 timeout <<= 1;
949 }
950 dto = 31 - dto;
951 timeout <<= 1;
952 if (timeout && dto)
953 dto += 1;
954 if (dto >= 13)
955 dto -= 13;
956 else
957 dto = 0;
958 if (dto > 14)
959 dto = 14;
960 }
961
962 reg &= ~DTO_MASK;
963 reg |= dto << DTO_SHIFT;
964 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
965}
966
967/*
968 * Configure block length for MMC/SD cards and initiate the transfer.
969 */
970static int
971mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
972{
973 int ret;
974 host->data = req->data;
975
976 if (req->data == NULL) {
a45c6cb8
MC		 977 OMAP_HSMMC_WRITE(host->base, BLK, 0);
978 return 0;
979 }
980
981 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
982 | (req->data->blocks << 16));
983 set_data_timeout(host, req);
984
a45c6cb8
MC		 985 if (host->use_dma) {
986 ret = mmc_omap_start_dma_transfer(host, req);
987 if (ret != 0) {
988 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
989 return ret;
990 }
991 }
992 return 0;
993}
994
5e2ea617
AH		 995static int omap_mmc_enable(struct mmc_host *mmc)
996{
997 struct mmc_omap_host *host = mmc_priv(mmc);
998 int err;
999
1000 err = clk_enable(host->fclk);
1001 if (err)
1002 return err;
1003 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
11dd62a7 1004 omap_mmc_restore_ctx(host);
5e2ea617
AH		 1005 return 0;
1006}
1007
1008static int omap_mmc_disable(struct mmc_host *mmc, int lazy)
1009{
1010 struct mmc_omap_host *host = mmc_priv(mmc);
1011
11dd62a7 1012 omap_mmc_save_ctx(host);
5e2ea617
AH		 1013 clk_disable(host->fclk);
1014 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
1015 return 0;
1016}
1017
a45c6cb8
MC		 1018/*
1019 * Request function. for read/write operation
1020 */
1021static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
1022{
1023 struct mmc_omap_host *host = mmc_priv(mmc);
1024
1025 WARN_ON(host->mrq != NULL);
1026 host->mrq = req;
1027 mmc_omap_prepare_data(host, req);
1028 mmc_omap_start_command(host, req->cmd, req->data);
1029}
1030
1031
1032/* Routine to configure clock values. Exposed API to core */
1033static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1034{
1035 struct mmc_omap_host *host = mmc_priv(mmc);
1036 u16 dsor = 0;
1037 unsigned long regval;
1038 unsigned long timeout;
73153010 1039 u32 con;
a3621465 1040 int do_send_init_stream = 0;
a45c6cb8 1041
5e2ea617
AH		 1042 mmc_host_enable(host->mmc);
1043
a3621465
AH		 1044 if (ios->power_mode != host->power_mode) {
1045 switch (ios->power_mode) {
1046 case MMC_POWER_OFF:
1047 mmc_slot(host).set_power(host->dev, host->slot_id,
1048 0, 0);
1049 break;
1050 case MMC_POWER_UP:
1051 mmc_slot(host).set_power(host->dev, host->slot_id,
1052 1, ios->vdd);
1053 break;
1054 case MMC_POWER_ON:
1055 do_send_init_stream = 1;
1056 break;
1057 }
1058 host->power_mode = ios->power_mode;
a45c6cb8
MC		 1059 }
1060
73153010 1061 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 1062 switch (mmc->ios.bus_width) {
73153010
JL		 1063 case MMC_BUS_WIDTH_8:
1064 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1065 break;
a45c6cb8 1066 case MMC_BUS_WIDTH_4:
73153010 1067 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 1068 OMAP_HSMMC_WRITE(host->base, HCTL,
1069 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1070 break;
1071 case MMC_BUS_WIDTH_1:
73153010 1072 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 1073 OMAP_HSMMC_WRITE(host->base, HCTL,
1074 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1075 break;
1076 }
1077
1078 if (host->id == OMAP_MMC1_DEVID) {
eb250826
DB		 1079 /* Only MMC1 can interface at 3V without some flavor
1080 * of external transceiver; but they all handle 1.8V.
1081 */
a45c6cb8
MC		 1082 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1083 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1084 /*
1085 * The mmc_select_voltage fn of the core does
1086 * not seem to set the power_mode to
1087 * MMC_POWER_UP upon recalculating the voltage.
1088 * vdd 1.8v.
1089 */
1090 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
1091 dev_dbg(mmc_dev(host->mmc),
1092 "Switch operation failed\n");
1093 }
1094 }
1095
1096 if (ios->clock) {
1097 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1098 if (dsor < 1)
1099 dsor = 1;
1100
1101 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1102 dsor++;
1103
1104 if (dsor > 250)
1105 dsor = 250;
1106 }
1107 omap_mmc_stop_clock(host);
1108 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1109 regval = regval & ~(CLKD_MASK);
1110 regval = regval | (dsor << 6) | (DTO << 16);
1111 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1112 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1113 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1114
1115 /* Wait till the ICS bit is set */
1116 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
11dd62a7 1117 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
a45c6cb8
MC		 1118 && time_before(jiffies, timeout))
1119 msleep(1);
1120
1121 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1122 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1123
a3621465 1124 if (do_send_init_stream)
a45c6cb8
MC		 1125 send_init_stream(host);
1126
abb28e73 1127 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 1128 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
abb28e73
DK		 1129 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1130 else
1131 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
5e2ea617
AH		 1132
1133 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 1134}
1135
1136static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1137{
1138 struct mmc_omap_host *host = mmc_priv(mmc);
1139 struct omap_mmc_platform_data *pdata = host->pdata;
1140
1141 if (!pdata->slots[0].card_detect)
1142 return -ENOSYS;
1143 return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq);
1144}
1145
1146static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1147{
1148 struct mmc_omap_host *host = mmc_priv(mmc);
1149 struct omap_mmc_platform_data *pdata = host->pdata;
1150
1151 if (!pdata->slots[0].get_ro)
1152 return -ENOSYS;
1153 return pdata->slots[0].get_ro(host->dev, 0);
1154}
1155
1b331e69
KK		 1156static void omap_hsmmc_init(struct mmc_omap_host *host)
1157{
1158 u32 hctl, capa, value;
1159
1160 /* Only MMC1 supports 3.0V */
1161 if (host->id == OMAP_MMC1_DEVID) {
1162 hctl = SDVS30;
1163 capa = VS30 | VS18;
1164 } else {
1165 hctl = SDVS18;
1166 capa = VS18;
1167 }
1168
1169 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1170 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1171
1172 value = OMAP_HSMMC_READ(host->base, CAPA);
1173 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1174
1175 /* Set the controller to AUTO IDLE mode */
1176 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1177 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1178
1179 /* Set SD bus power bit */
e13bb300 1180 set_sd_bus_power(host);
1b331e69
KK		 1181}
1182
a45c6cb8 1183static struct mmc_host_ops mmc_omap_ops = {
5e2ea617
AH		 1184 .enable = omap_mmc_enable,
1185 .disable = omap_mmc_disable,
a45c6cb8
MC		 1186 .request = omap_mmc_request,
1187 .set_ios = omap_mmc_set_ios,
1188 .get_cd = omap_hsmmc_get_cd,
1189 .get_ro = omap_hsmmc_get_ro,
1190 /* NYET -- enable_sdio_irq */
1191};
1192
d900f712
DK		 1193#ifdef CONFIG_DEBUG_FS
1194
1195static int mmc_regs_show(struct seq_file *s, void *data)
1196{
1197 struct mmc_host *mmc = s->private;
1198 struct mmc_omap_host *host = mmc_priv(mmc);
11dd62a7
DK		 1199 struct omap_mmc_platform_data *pdata = host->pdata;
1200 int context_loss = 0;
1201
1202 if (pdata->get_context_loss_count)
1203 context_loss = pdata->get_context_loss_count(host->dev);
d900f712 1204
5e2ea617
AH		 1205 seq_printf(s, "mmc%d:\n"
1206 " enabled:\t%d\n"
1207 " nesting_cnt:\t%d\n"
11dd62a7 1208 " ctx_loss:\t%d:%d\n"
5e2ea617 1209 "\nregs:\n",
11dd62a7
DK		 1210 mmc->index, mmc->enabled ? 1 : 0, mmc->nesting_cnt,
1211 host->context_loss, context_loss);
5e2ea617
AH		 1212
1213 if (clk_enable(host->fclk) != 0) {
1214 seq_printf(s, "can't read the regs\n");
1215 goto err;
1216 }
d900f712
DK		 1217
1218 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1219 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1220 seq_printf(s, "CON:\t\t0x%08x\n",
1221 OMAP_HSMMC_READ(host->base, CON));
1222 seq_printf(s, "HCTL:\t\t0x%08x\n",
1223 OMAP_HSMMC_READ(host->base, HCTL));
1224 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1225 OMAP_HSMMC_READ(host->base, SYSCTL));
1226 seq_printf(s, "IE:\t\t0x%08x\n",
1227 OMAP_HSMMC_READ(host->base, IE));
1228 seq_printf(s, "ISE:\t\t0x%08x\n",
1229 OMAP_HSMMC_READ(host->base, ISE));
1230 seq_printf(s, "CAPA:\t\t0x%08x\n",
1231 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617
AH		 1232
1233 clk_disable(host->fclk);
1234err:
d900f712
DK		 1235 return 0;
1236}
1237
1238static int mmc_regs_open(struct inode *inode, struct file *file)
1239{
1240 return single_open(file, mmc_regs_show, inode->i_private);
1241}
1242
1243static const struct file_operations mmc_regs_fops = {
1244 .open = mmc_regs_open,
1245 .read = seq_read,
1246 .llseek = seq_lseek,
1247 .release = single_release,
1248};
1249
1250static void omap_mmc_debugfs(struct mmc_host *mmc)
1251{
1252 if (mmc->debugfs_root)
1253 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1254 mmc, &mmc_regs_fops);
1255}
1256
1257#else
1258
1259static void omap_mmc_debugfs(struct mmc_host *mmc)
1260{
1261}
1262
1263#endif
1264
a45c6cb8
MC		 1265static int __init omap_mmc_probe(struct platform_device *pdev)
1266{
1267 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1268 struct mmc_host *mmc;
1269 struct mmc_omap_host *host = NULL;
1270 struct resource *res;
1271 int ret = 0, irq;
a45c6cb8
MC		 1272
1273 if (pdata == NULL) {
1274 dev_err(&pdev->dev, "Platform Data is missing\n");
1275 return -ENXIO;
1276 }
1277
1278 if (pdata->nr_slots == 0) {
1279 dev_err(&pdev->dev, "No Slots\n");
1280 return -ENXIO;
1281 }
1282
1283 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1284 irq = platform_get_irq(pdev, 0);
1285 if (res == NULL || irq < 0)
1286 return -ENXIO;
1287
1288 res = request_mem_region(res->start, res->end - res->start + 1,
1289 pdev->name);
1290 if (res == NULL)
1291 return -EBUSY;
1292
1293 mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
1294 if (!mmc) {
1295 ret = -ENOMEM;
1296 goto err;
1297 }
1298
1299 host = mmc_priv(mmc);
1300 host->mmc = mmc;
1301 host->pdata = pdata;
1302 host->dev = &pdev->dev;
1303 host->use_dma = 1;
1304 host->dev->dma_mask = &pdata->dma_mask;
1305 host->dma_ch = -1;
1306 host->irq = irq;
1307 host->id = pdev->id;
1308 host->slot_id = 0;
1309 host->mapbase = res->start;
1310 host->base = ioremap(host->mapbase, SZ_4K);
a3621465 1311 host->power_mode = -1;
a45c6cb8
MC		 1312
1313 platform_set_drvdata(pdev, host);
1314 INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
1315
1316 mmc->ops = &mmc_omap_ops;
1317 mmc->f_min = 400000;
1318 mmc->f_max = 52000000;
1319
1320 sema_init(&host->sem, 1);
1321
6f7607cc 1322 host->iclk = clk_get(&pdev->dev, "ick");
a45c6cb8
MC		 1323 if (IS_ERR(host->iclk)) {
1324 ret = PTR_ERR(host->iclk);
1325 host->iclk = NULL;
1326 goto err1;
1327 }
6f7607cc 1328 host->fclk = clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 1329 if (IS_ERR(host->fclk)) {
1330 ret = PTR_ERR(host->fclk);
1331 host->fclk = NULL;
1332 clk_put(host->iclk);
1333 goto err1;
1334 }
1335
11dd62a7
DK		 1336 omap_mmc_save_ctx(host);
1337
5e2ea617
AH		 1338 mmc->caps |= MMC_CAP_DISABLE;
1339 mmc_set_disable_delay(mmc, 100);
1340 if (mmc_host_enable(host->mmc) != 0) {
a45c6cb8
MC		 1341 clk_put(host->iclk);
1342 clk_put(host->fclk);
1343 goto err1;
1344 }
1345
1346 if (clk_enable(host->iclk) != 0) {
5e2ea617 1347 mmc_host_disable(host->mmc);
a45c6cb8
MC		 1348 clk_put(host->iclk);
1349 clk_put(host->fclk);
1350 goto err1;
1351 }
1352
1353 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1354 /*
1355 * MMC can still work without debounce clock.
1356 */
1357 if (IS_ERR(host->dbclk))
1358 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n");
1359 else
1360 if (clk_enable(host->dbclk) != 0)
1361 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1362 " clk failed\n");
1363 else
1364 host->dbclk_enabled = 1;
1365
0ccd76d4
JY		 1366 /* Since we do only SG emulation, we can have as many segs
1367 * as we want. */
1368 mmc->max_phys_segs = 1024;
1369 mmc->max_hw_segs = 1024;
1370
a45c6cb8
MC		 1371 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1372 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1373 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1374 mmc->max_seg_size = mmc->max_req_size;
1375
a45c6cb8
MC		 1376 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1377
73153010
JL		 1378 if (pdata->slots[host->slot_id].wires >= 8)
1379 mmc->caps |= MMC_CAP_8_BIT_DATA;
1380 else if (pdata->slots[host->slot_id].wires >= 4)
a45c6cb8
MC		 1381 mmc->caps |= MMC_CAP_4_BIT_DATA;
1382
1b331e69 1383 omap_hsmmc_init(host);
a45c6cb8 1384
f3e2f1dd
GI		 1385 /* Select DMA lines */
1386 switch (host->id) {
1387 case OMAP_MMC1_DEVID:
1388 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
1389 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
1390 break;
1391 case OMAP_MMC2_DEVID:
1392 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
1393 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
1394 break;
1395 case OMAP_MMC3_DEVID:
1396 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
1397 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
1398 break;
1399 default:
1400 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
1401 goto err_irq;
1402 }
a45c6cb8
MC		 1403
1404 /* Request IRQ for MMC operations */
1405 ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1406 mmc_hostname(mmc), host);
1407 if (ret) {
1408 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1409 goto err_irq;
1410 }
1411
b583f26d 1412 /* initialize power supplies, gpios, etc */
a45c6cb8
MC		 1413 if (pdata->init != NULL) {
1414 if (pdata->init(&pdev->dev) != 0) {
b583f26d 1415 dev_dbg(mmc_dev(host->mmc), "late init error\n");
a45c6cb8
MC		 1416 goto err_irq_cd_init;
1417 }
1418 }
b583f26d 1419 mmc->ocr_avail = mmc_slot(host).ocr_mask;
a45c6cb8
MC		 1420
1421 /* Request IRQ for card detect */
e1a55f5e 1422 if ((mmc_slot(host).card_detect_irq)) {
a45c6cb8
MC		 1423 ret = request_irq(mmc_slot(host).card_detect_irq,
1424 omap_mmc_cd_handler,
1425 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1426 | IRQF_DISABLED,
1427 mmc_hostname(mmc), host);
1428 if (ret) {
1429 dev_dbg(mmc_dev(host->mmc),
1430 "Unable to grab MMC CD IRQ\n");
1431 goto err_irq_cd;
1432 }
1433 }
1434
1435 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1436 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1437
5e2ea617
AH		 1438 mmc_host_lazy_disable(host->mmc);
1439
a45c6cb8
MC		 1440 mmc_add_host(mmc);
1441
1442 if (host->pdata->slots[host->slot_id].name != NULL) {
1443 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1444 if (ret < 0)
1445 goto err_slot_name;
1446 }
e1a55f5e
AH		 1447 if (mmc_slot(host).card_detect_irq &&
1448 host->pdata->slots[host->slot_id].get_cover_state) {
a45c6cb8
MC		 1449 ret = device_create_file(&mmc->class_dev,
1450 &dev_attr_cover_switch);
1451 if (ret < 0)
1452 goto err_cover_switch;
1453 }
1454
d900f712
DK		 1455 omap_mmc_debugfs(mmc);
1456
a45c6cb8
MC		 1457 return 0;
1458
1459err_cover_switch:
1460 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1461err_slot_name:
1462 mmc_remove_host(mmc);
1463err_irq_cd:
1464 free_irq(mmc_slot(host).card_detect_irq, host);
1465err_irq_cd_init:
1466 free_irq(host->irq, host);
1467err_irq:
5e2ea617 1468 mmc_host_disable(host->mmc);
a45c6cb8
MC		 1469 clk_disable(host->iclk);
1470 clk_put(host->fclk);
1471 clk_put(host->iclk);
1472 if (host->dbclk_enabled) {
1473 clk_disable(host->dbclk);
1474 clk_put(host->dbclk);
1475 }
1476
1477err1:
1478 iounmap(host->base);
1479err:
1480 dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1481 release_mem_region(res->start, res->end - res->start + 1);
1482 if (host)
1483 mmc_free_host(mmc);
1484 return ret;
1485}
1486
1487static int omap_mmc_remove(struct platform_device *pdev)
1488{
1489 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1490 struct resource *res;
1491
1492 if (host) {
5e2ea617 1493 mmc_host_enable(host->mmc);
a45c6cb8
MC		 1494 mmc_remove_host(host->mmc);
1495 if (host->pdata->cleanup)
1496 host->pdata->cleanup(&pdev->dev);
1497 free_irq(host->irq, host);
1498 if (mmc_slot(host).card_detect_irq)
1499 free_irq(mmc_slot(host).card_detect_irq, host);
1500 flush_scheduled_work();
1501
5e2ea617 1502 mmc_host_disable(host->mmc);
a45c6cb8
MC		 1503 clk_disable(host->iclk);
1504 clk_put(host->fclk);
1505 clk_put(host->iclk);
1506 if (host->dbclk_enabled) {
1507 clk_disable(host->dbclk);
1508 clk_put(host->dbclk);
1509 }
1510
1511 mmc_free_host(host->mmc);
1512 iounmap(host->base);
1513 }
1514
1515 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1516 if (res)
1517 release_mem_region(res->start, res->end - res->start + 1);
1518 platform_set_drvdata(pdev, NULL);
1519
1520 return 0;
1521}
1522
1523#ifdef CONFIG_PM
1524static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1525{
1526 int ret = 0;
1527 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1528
1529 if (host && host->suspended)
1530 return 0;
1531
1532 if (host) {
a6b2240d
AH		 1533 host->suspended = 1;
1534 if (host->pdata->suspend) {
1535 ret = host->pdata->suspend(&pdev->dev,
1536 host->slot_id);
1537 if (ret) {
1538 dev_dbg(mmc_dev(host->mmc),
1539 "Unable to handle MMC board"
1540 " level suspend\n");
1541 host->suspended = 0;
1542 return ret;
1543 }
1544 }
1545 cancel_work_sync(&host->mmc_carddetect_work);
5e2ea617 1546 mmc_host_enable(host->mmc);
a45c6cb8
MC		 1547 ret = mmc_suspend_host(host->mmc, state);
1548 if (ret == 0) {
a45c6cb8
MC		 1549 OMAP_HSMMC_WRITE(host->base, ISE, 0);
1550 OMAP_HSMMC_WRITE(host->base, IE, 0);
1551
a45c6cb8 1552
0683af48
JL		 1553 OMAP_HSMMC_WRITE(host->base, HCTL,
1554 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
5e2ea617 1555 mmc_host_disable(host->mmc);
a45c6cb8
MC		 1556 clk_disable(host->iclk);
1557 clk_disable(host->dbclk);
a6b2240d
AH		 1558 } else {
1559 host->suspended = 0;
1560 if (host->pdata->resume) {
1561 ret = host->pdata->resume(&pdev->dev,
1562 host->slot_id);
1563 if (ret)
1564 dev_dbg(mmc_dev(host->mmc),
1565 "Unmask interrupt failed\n");
1566 }
5e2ea617 1567 mmc_host_disable(host->mmc);
a6b2240d 1568 }
a45c6cb8
MC		 1569
1570 }
1571 return ret;
1572}
1573
1574/* Routine to resume the MMC device */
1575static int omap_mmc_resume(struct platform_device *pdev)
1576{
1577 int ret = 0;
1578 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1579
1580 if (host && !host->suspended)
1581 return 0;
1582
1583 if (host) {
a45c6cb8 1584 ret = clk_enable(host->iclk);
11dd62a7 1585 if (ret)
a45c6cb8 1586 goto clk_en_err;
a45c6cb8
MC		 1587
1588 if (clk_enable(host->dbclk) != 0)
1589 dev_dbg(mmc_dev(host->mmc),
1590 "Enabling debounce clk failed\n");
1591
11dd62a7
DK		 1592 if (mmc_host_enable(host->mmc) != 0) {
1593 clk_disable(host->iclk);
1594 goto clk_en_err;
1595 }
1596
1b331e69
KK		 1597 omap_hsmmc_init(host);
1598
a45c6cb8
MC		 1599 if (host->pdata->resume) {
1600 ret = host->pdata->resume(&pdev->dev, host->slot_id);
1601 if (ret)
1602 dev_dbg(mmc_dev(host->mmc),
1603 "Unmask interrupt failed\n");
1604 }
1605
1606 /* Notify the core to resume the host */
1607 ret = mmc_resume_host(host->mmc);
1608 if (ret == 0)
1609 host->suspended = 0;
5e2ea617 1610 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 1611 }
1612
1613 return ret;
1614
1615clk_en_err:
1616 dev_dbg(mmc_dev(host->mmc),
1617 "Failed to enable MMC clocks during resume\n");
1618 return ret;
1619}
1620
1621#else
1622#define omap_mmc_suspend NULL
1623#define omap_mmc_resume NULL
1624#endif
1625
1626static struct platform_driver omap_mmc_driver = {
a45c6cb8
MC		 1627 .remove = omap_mmc_remove,
1628 .suspend = omap_mmc_suspend,
1629 .resume = omap_mmc_resume,
1630 .driver = {
1631 .name = DRIVER_NAME,
1632 .owner = THIS_MODULE,
1633 },
1634};
1635
1636static int __init omap_mmc_init(void)
1637{
1638 /* Register the MMC driver */
f400cd8c 1639 return platform_driver_probe(&omap_mmc_driver, omap_mmc_probe);
a45c6cb8
MC		 1640}
1641
1642static void __exit omap_mmc_cleanup(void)
1643{
1644 /* Unregister MMC driver */
1645 platform_driver_unregister(&omap_mmc_driver);
1646}
1647
1648module_init(omap_mmc_init);
1649module_exit(omap_mmc_cleanup);
1650
1651MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1652MODULE_LICENSE("GPL");
1653MODULE_ALIAS("platform:" DRIVER_NAME);
1654MODULE_AUTHOR("Texas Instruments Inc");
Linux kernel - Deliverables
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