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mmc: omap_hsmmc: Use OMAP_HSMMC_SUPPORTS_DUAL_VOLT flag to remove host->id based...
[deliverable/linux.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
ac330f44 20#include <linux/kernel.h>
d900f712
DK		 21#include <linux/debugfs.h>
22#include <linux/seq_file.h>
a45c6cb8
MC		 23#include <linux/interrupt.h>
24#include <linux/delay.h>
25#include <linux/dma-mapping.h>
26#include <linux/platform_device.h>
a45c6cb8
MC		 27#include <linux/timer.h>
28#include <linux/clk.h>
29#include <linux/mmc/host.h>
13189e78 30#include <linux/mmc/core.h>
93caf8e6 31#include <linux/mmc/mmc.h>
a45c6cb8
MC		 32#include <linux/io.h>
33#include <linux/semaphore.h>
db0fefc5
AH		 34#include <linux/gpio.h>
35#include <linux/regulator/consumer.h>
fa4aa2d4 36#include <linux/pm_runtime.h>
ce491cf8 37#include <plat/dma.h>
a45c6cb8 38#include <mach/hardware.h>
ce491cf8
TL		 39#include <plat/board.h>
40#include <plat/mmc.h>
41#include <plat/cpu.h>
a45c6cb8
MC		 42
43/* OMAP HSMMC Host Controller Registers */
44#define OMAP_HSMMC_SYSCONFIG 0x0010
11dd62a7 45#define OMAP_HSMMC_SYSSTATUS 0x0014
a45c6cb8
MC		 46#define OMAP_HSMMC_CON 0x002C
47#define OMAP_HSMMC_BLK 0x0104
48#define OMAP_HSMMC_ARG 0x0108
49#define OMAP_HSMMC_CMD 0x010C
50#define OMAP_HSMMC_RSP10 0x0110
51#define OMAP_HSMMC_RSP32 0x0114
52#define OMAP_HSMMC_RSP54 0x0118
53#define OMAP_HSMMC_RSP76 0x011C
54#define OMAP_HSMMC_DATA 0x0120
55#define OMAP_HSMMC_HCTL 0x0128
56#define OMAP_HSMMC_SYSCTL 0x012C
57#define OMAP_HSMMC_STAT 0x0130
58#define OMAP_HSMMC_IE 0x0134
59#define OMAP_HSMMC_ISE 0x0138
60#define OMAP_HSMMC_CAPA 0x0140
61
62#define VS18 (1 << 26)
63#define VS30 (1 << 25)
64#define SDVS18 (0x5 << 9)
65#define SDVS30 (0x6 << 9)
eb250826 66#define SDVS33 (0x7 << 9)
1b331e69 67#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 68#define SDVSCLR 0xFFFFF1FF
69#define SDVSDET 0x00000400
70#define AUTOIDLE 0x1
71#define SDBP (1 << 8)
72#define DTO 0xe
73#define ICE 0x1
74#define ICS 0x2
75#define CEN (1 << 2)
76#define CLKD_MASK 0x0000FFC0
77#define CLKD_SHIFT 6
78#define DTO_MASK 0x000F0000
79#define DTO_SHIFT 16
80#define INT_EN_MASK 0x307F0033
ccdfe3a6
AG		 81#define BWR_ENABLE (1 << 4)
82#define BRR_ENABLE (1 << 5)
93caf8e6 83#define DTO_ENABLE (1 << 20)
a45c6cb8
MC		 84#define INIT_STREAM (1 << 1)
85#define DP_SELECT (1 << 21)
86#define DDIR (1 << 4)
87#define DMA_EN 0x1
88#define MSBS (1 << 5)
89#define BCE (1 << 1)
90#define FOUR_BIT (1 << 1)
73153010 91#define DW8 (1 << 5)
a45c6cb8
MC		 92#define CC 0x1
93#define TC 0x02
94#define OD 0x1
95#define ERR (1 << 15)
96#define CMD_TIMEOUT (1 << 16)
97#define DATA_TIMEOUT (1 << 20)
98#define CMD_CRC (1 << 17)
99#define DATA_CRC (1 << 21)
100#define CARD_ERR (1 << 28)
101#define STAT_CLEAR 0xFFFFFFFF
102#define INIT_STREAM_CMD 0x00000000
103#define DUAL_VOLT_OCR_BIT 7
104#define SRC (1 << 25)
105#define SRD (1 << 26)
11dd62a7
DK		 106#define SOFTRESET (1 << 1)
107#define RESETDONE (1 << 0)
a45c6cb8
MC		 108
109/*
110 * FIXME: Most likely all the data using these _DEVID defines should come
111 * from the platform_data, or implemented in controller and slot specific
112 * functions.
113 */
114#define OMAP_MMC1_DEVID 0
115#define OMAP_MMC2_DEVID 1
f3e2f1dd 116#define OMAP_MMC3_DEVID 2
82cf818d 117#define OMAP_MMC4_DEVID 3
118#define OMAP_MMC5_DEVID 4
a45c6cb8 119
fa4aa2d4 120#define MMC_AUTOSUSPEND_DELAY 100
a45c6cb8 121#define MMC_TIMEOUT_MS 20
6b206efe
AS		 122#define OMAP_MMC_MIN_CLOCK 400000
123#define OMAP_MMC_MAX_CLOCK 52000000
0005ae73 124#define DRIVER_NAME "omap_hsmmc"
a45c6cb8
MC		 125
126/*
127 * One controller can have multiple slots, like on some omap boards using
128 * omap.c controller driver. Luckily this is not currently done on any known
129 * omap_hsmmc.c device.
130 */
131#define mmc_slot(host) (host->pdata->slots[host->slot_id])
132
133/*
134 * MMC Host controller read/write API's
135 */
136#define OMAP_HSMMC_READ(base, reg) \
137 __raw_readl((base) + OMAP_HSMMC_##reg)
138
139#define OMAP_HSMMC_WRITE(base, reg, val) \
140 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
141
9782aff8
PF		 142struct omap_hsmmc_next {
143 unsigned int dma_len;
144 s32 cookie;
145};
146
70a3341a 147struct omap_hsmmc_host {
a45c6cb8
MC		 148 struct device *dev;
149 struct mmc_host *mmc;
150 struct mmc_request *mrq;
151 struct mmc_command *cmd;
152 struct mmc_data *data;
153 struct clk *fclk;
a45c6cb8 154 struct clk *dbclk;
db0fefc5
AH		 155 /*
156 * vcc == configured supply
157 * vcc_aux == optional
158 * - MMC1, supply for DAT4..DAT7
159 * - MMC2/MMC2, external level shifter voltage supply, for
160 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
161 */
162 struct regulator *vcc;
163 struct regulator *vcc_aux;
a45c6cb8
MC		 164 void __iomem *base;
165 resource_size_t mapbase;
4dffd7a2 166 spinlock_t irq_lock; /* Prevent races with irq handler */
a45c6cb8
MC		 167 unsigned int id;
168 unsigned int dma_len;
0ccd76d4 169 unsigned int dma_sg_idx;
a45c6cb8 170 unsigned char bus_mode;
a3621465 171 unsigned char power_mode;
a45c6cb8
MC		 172 u32 *buffer;
173 u32 bytesleft;
174 int suspended;
175 int irq;
a45c6cb8 176 int use_dma, dma_ch;
f3e2f1dd 177 int dma_line_tx, dma_line_rx;
a45c6cb8 178 int slot_id;
2bec0893 179 int got_dbclk;
4a694dc9 180 int response_busy;
11dd62a7 181 int context_loss;
dd498eff 182 int dpm_state;
623821f7 183 int vdd;
b62f6228
AH		 184 int protect_card;
185 int reqs_blocked;
db0fefc5 186 int use_reg;
b417577d 187 int req_in_progress;
9782aff8 188 struct omap_hsmmc_next next_data;
11dd62a7 189
a45c6cb8
MC		 190 struct omap_mmc_platform_data *pdata;
191};
192
db0fefc5
AH		 193static int omap_hsmmc_card_detect(struct device *dev, int slot)
194{
195 struct omap_mmc_platform_data *mmc = dev->platform_data;
196
197 /* NOTE: assumes card detect signal is active-low */
198 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
199}
200
201static int omap_hsmmc_get_wp(struct device *dev, int slot)
202{
203 struct omap_mmc_platform_data *mmc = dev->platform_data;
204
205 /* NOTE: assumes write protect signal is active-high */
206 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
207}
208
209static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
210{
211 struct omap_mmc_platform_data *mmc = dev->platform_data;
212
213 /* NOTE: assumes card detect signal is active-low */
214 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
215}
216
217#ifdef CONFIG_PM
218
219static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
220{
221 struct omap_mmc_platform_data *mmc = dev->platform_data;
222
223 disable_irq(mmc->slots[0].card_detect_irq);
224 return 0;
225}
226
227static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
228{
229 struct omap_mmc_platform_data *mmc = dev->platform_data;
230
231 enable_irq(mmc->slots[0].card_detect_irq);
232 return 0;
233}
234
235#else
236
237#define omap_hsmmc_suspend_cdirq NULL
238#define omap_hsmmc_resume_cdirq NULL
239
240#endif
241
b702b106
AH		 242#ifdef CONFIG_REGULATOR
243
db0fefc5
AH		 244static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
245 int vdd)
246{
247 struct omap_hsmmc_host *host =
248 platform_get_drvdata(to_platform_device(dev));
249 int ret;
250
251 if (mmc_slot(host).before_set_reg)
252 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
253
254 if (power_on)
99fc5131 255 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5 256 else
99fc5131 257 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
db0fefc5
AH		 258
259 if (mmc_slot(host).after_set_reg)
260 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
261
262 return ret;
263}
264
7715db5a 265static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on,
db0fefc5
AH		 266 int vdd)
267{
268 struct omap_hsmmc_host *host =
269 platform_get_drvdata(to_platform_device(dev));
270 int ret = 0;
271
272 /*
273 * If we don't see a Vcc regulator, assume it's a fixed
274 * voltage always-on regulator.
275 */
276 if (!host->vcc)
277 return 0;
278
279 if (mmc_slot(host).before_set_reg)
280 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
281
282 /*
283 * Assume Vcc regulator is used only to power the card ... OMAP
284 * VDDS is used to power the pins, optionally with a transceiver to
285 * support cards using voltages other than VDDS (1.8V nominal). When a
286 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
287 *
288 * In some cases this regulator won't support enable/disable;
289 * e.g. it's a fixed rail for a WLAN chip.
290 *
291 * In other cases vcc_aux switches interface power. Example, for
292 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
293 * chips/cards need an interface voltage rail too.
294 */
295 if (power_on) {
99fc5131 296 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5
AH		 297 /* Enable interface voltage rail, if needed */
298 if (ret == 0 && host->vcc_aux) {
299 ret = regulator_enable(host->vcc_aux);
300 if (ret < 0)
99fc5131
LW		 301 ret = mmc_regulator_set_ocr(host->mmc,
302 host->vcc, 0);
db0fefc5
AH		 303 }
304 } else {
99fc5131 305 /* Shut down the rail */
6da20c89
AH		 306 if (host->vcc_aux)
307 ret = regulator_disable(host->vcc_aux);
99fc5131
LW		 308 if (!ret) {
309 /* Then proceed to shut down the local regulator */
310 ret = mmc_regulator_set_ocr(host->mmc,
311 host->vcc, 0);
312 }
db0fefc5
AH		 313 }
314
315 if (mmc_slot(host).after_set_reg)
316 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
317
318 return ret;
319}
320
7715db5a
KK		 321static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on,
322 int vdd)
323{
324 return 0;
325}
326
db0fefc5
AH		 327static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
328{
329 struct regulator *reg;
330 int ret = 0;
64be9782 331 int ocr_value = 0;
db0fefc5
AH		 332
333 switch (host->id) {
334 case OMAP_MMC1_DEVID:
335 /* On-chip level shifting via PBIAS0/PBIAS1 */
336 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
db0fefc5
AH		 337 break;
338 case OMAP_MMC2_DEVID:
339 case OMAP_MMC3_DEVID:
7715db5a 340 case OMAP_MMC5_DEVID:
db0fefc5 341 /* Off-chip level shifting, or none */
7715db5a 342 mmc_slot(host).set_power = omap_hsmmc_235_set_power;
db0fefc5 343 break;
7715db5a
KK		 344 case OMAP_MMC4_DEVID:
345 mmc_slot(host).set_power = omap_hsmmc_4_set_power;
db0fefc5
AH		 346 default:
347 pr_err("MMC%d configuration not supported!\n", host->id);
348 return -EINVAL;
349 }
350
351 reg = regulator_get(host->dev, "vmmc");
352 if (IS_ERR(reg)) {
353 dev_dbg(host->dev, "vmmc regulator missing\n");
354 /*
355 * HACK: until fixed.c regulator is usable,
356 * we don't require a main regulator
357 * for MMC2 or MMC3
358 */
359 if (host->id == OMAP_MMC1_DEVID) {
360 ret = PTR_ERR(reg);
361 goto err;
362 }
363 } else {
364 host->vcc = reg;
64be9782 365 ocr_value = mmc_regulator_get_ocrmask(reg);
366 if (!mmc_slot(host).ocr_mask) {
367 mmc_slot(host).ocr_mask = ocr_value;
368 } else {
369 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
370 pr_err("MMC%d ocrmask %x is not supported\n",
371 host->id, mmc_slot(host).ocr_mask);
372 mmc_slot(host).ocr_mask = 0;
373 return -EINVAL;
374 }
375 }
db0fefc5
AH		 376
377 /* Allow an aux regulator */
378 reg = regulator_get(host->dev, "vmmc_aux");
379 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
380
b1c1df7a
B		 381 /* For eMMC do not power off when not in sleep state */
382 if (mmc_slot(host).no_regulator_off_init)
383 return 0;
db0fefc5
AH		 384 /*
385 * UGLY HACK: workaround regulator framework bugs.
386 * When the bootloader leaves a supply active, it's
387 * initialized with zero usecount ... and we can't
388 * disable it without first enabling it. Until the
389 * framework is fixed, we need a workaround like this
390 * (which is safe for MMC, but not in general).
391 */
e840ce13
AH		 392 if (regulator_is_enabled(host->vcc) > 0 ||
393 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
394 int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
395
396 mmc_slot(host).set_power(host->dev, host->slot_id,
397 1, vdd);
398 mmc_slot(host).set_power(host->dev, host->slot_id,
399 0, 0);
db0fefc5
AH		 400 }
401 }
402
403 return 0;
404
405err:
406 mmc_slot(host).set_power = NULL;
db0fefc5
AH		 407 return ret;
408}
409
410static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
411{
412 regulator_put(host->vcc);
413 regulator_put(host->vcc_aux);
414 mmc_slot(host).set_power = NULL;
db0fefc5
AH		 415}
416
b702b106
AH		 417static inline int omap_hsmmc_have_reg(void)
418{
419 return 1;
420}
421
422#else
423
424static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
425{
426 return -EINVAL;
427}
428
429static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
430{
431}
432
433static inline int omap_hsmmc_have_reg(void)
434{
435 return 0;
436}
437
438#endif
439
440static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
441{
442 int ret;
443
444 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
b702b106
AH		 445 if (pdata->slots[0].cover)
446 pdata->slots[0].get_cover_state =
447 omap_hsmmc_get_cover_state;
448 else
449 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
450 pdata->slots[0].card_detect_irq =
451 gpio_to_irq(pdata->slots[0].switch_pin);
452 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
453 if (ret)
454 return ret;
455 ret = gpio_direction_input(pdata->slots[0].switch_pin);
456 if (ret)
457 goto err_free_sp;
458 } else
459 pdata->slots[0].switch_pin = -EINVAL;
460
461 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
462 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
463 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
464 if (ret)
465 goto err_free_cd;
466 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
467 if (ret)
468 goto err_free_wp;
469 } else
470 pdata->slots[0].gpio_wp = -EINVAL;
471
472 return 0;
473
474err_free_wp:
475 gpio_free(pdata->slots[0].gpio_wp);
476err_free_cd:
477 if (gpio_is_valid(pdata->slots[0].switch_pin))
478err_free_sp:
479 gpio_free(pdata->slots[0].switch_pin);
480 return ret;
481}
482
483static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
484{
485 if (gpio_is_valid(pdata->slots[0].gpio_wp))
486 gpio_free(pdata->slots[0].gpio_wp);
487 if (gpio_is_valid(pdata->slots[0].switch_pin))
488 gpio_free(pdata->slots[0].switch_pin);
489}
490
e0c7f99b
AS		 491/*
492 * Start clock to the card
493 */
494static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
495{
496 OMAP_HSMMC_WRITE(host->base, SYSCTL,
497 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
498}
499
a45c6cb8
MC		 500/*
501 * Stop clock to the card
502 */
70a3341a 503static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
a45c6cb8
MC		 504{
505 OMAP_HSMMC_WRITE(host->base, SYSCTL,
506 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
507 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
508 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
509}
510
93caf8e6
AH		 511static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
512 struct mmc_command *cmd)
b417577d
AH		 513{
514 unsigned int irq_mask;
515
516 if (host->use_dma)
517 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
518 else
519 irq_mask = INT_EN_MASK;
520
93caf8e6
AH		 521 /* Disable timeout for erases */
522 if (cmd->opcode == MMC_ERASE)
523 irq_mask &= ~DTO_ENABLE;
524
b417577d
AH		 525 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
526 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
527 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
528}
529
530static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
531{
532 OMAP_HSMMC_WRITE(host->base, ISE, 0);
533 OMAP_HSMMC_WRITE(host->base, IE, 0);
534 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
535}
536
ac330f44 537/* Calculate divisor for the given clock frequency */
d83b6e03 538static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
ac330f44
AS		 539{
540 u16 dsor = 0;
541
542 if (ios->clock) {
d83b6e03 543 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
ac330f44
AS		 544 if (dsor > 250)
545 dsor = 250;
546 }
547
548 return dsor;
549}
550
5934df2f
AS		 551static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
552{
553 struct mmc_ios *ios = &host->mmc->ios;
554 unsigned long regval;
555 unsigned long timeout;
556
557 dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
558
559 omap_hsmmc_stop_clock(host);
560
561 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
562 regval = regval & ~(CLKD_MASK | DTO_MASK);
d83b6e03 563 regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16);
5934df2f
AS		 564 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
565 OMAP_HSMMC_WRITE(host->base, SYSCTL,
566 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
567
568 /* Wait till the ICS bit is set */
569 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
570 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
571 && time_before(jiffies, timeout))
572 cpu_relax();
573
574 omap_hsmmc_start_clock(host);
575}
576
3796fb8a
AS		 577static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
578{
579 struct mmc_ios *ios = &host->mmc->ios;
580 u32 con;
581
582 con = OMAP_HSMMC_READ(host->base, CON);
583 switch (ios->bus_width) {
584 case MMC_BUS_WIDTH_8:
585 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
586 break;
587 case MMC_BUS_WIDTH_4:
588 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
589 OMAP_HSMMC_WRITE(host->base, HCTL,
590 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
591 break;
592 case MMC_BUS_WIDTH_1:
593 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
594 OMAP_HSMMC_WRITE(host->base, HCTL,
595 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
596 break;
597 }
598}
599
600static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
601{
602 struct mmc_ios *ios = &host->mmc->ios;
603 u32 con;
604
605 con = OMAP_HSMMC_READ(host->base, CON);
606 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
607 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
608 else
609 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
610}
611
11dd62a7
DK		 612#ifdef CONFIG_PM
613
614/*
615 * Restore the MMC host context, if it was lost as result of a
616 * power state change.
617 */
70a3341a 618static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 619{
620 struct mmc_ios *ios = &host->mmc->ios;
621 struct omap_mmc_platform_data *pdata = host->pdata;
622 int context_loss = 0;
3796fb8a 623 u32 hctl, capa;
11dd62a7
DK		 624 unsigned long timeout;
625
626 if (pdata->get_context_loss_count) {
627 context_loss = pdata->get_context_loss_count(host->dev);
628 if (context_loss < 0)
629 return 1;
630 }
631
632 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
633 context_loss == host->context_loss ? "not " : "");
634 if (host->context_loss == context_loss)
635 return 1;
636
637 /* Wait for hardware reset */
638 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
639 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
640 && time_before(jiffies, timeout))
641 ;
642
643 /* Do software reset */
644 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
645 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
646 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
647 && time_before(jiffies, timeout))
648 ;
649
650 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
651 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
652
c2200efb 653 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
11dd62a7
DK		 654 if (host->power_mode != MMC_POWER_OFF &&
655 (1 << ios->vdd) <= MMC_VDD_23_24)
656 hctl = SDVS18;
657 else
658 hctl = SDVS30;
659 capa = VS30 | VS18;
660 } else {
661 hctl = SDVS18;
662 capa = VS18;
663 }
664
665 OMAP_HSMMC_WRITE(host->base, HCTL,
666 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
667
668 OMAP_HSMMC_WRITE(host->base, CAPA,
669 OMAP_HSMMC_READ(host->base, CAPA) | capa);
670
671 OMAP_HSMMC_WRITE(host->base, HCTL,
672 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
673
674 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
675 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
676 && time_before(jiffies, timeout))
677 ;
678
b417577d 679 omap_hsmmc_disable_irq(host);
11dd62a7
DK		 680
681 /* Do not initialize card-specific things if the power is off */
682 if (host->power_mode == MMC_POWER_OFF)
683 goto out;
684
3796fb8a 685 omap_hsmmc_set_bus_width(host);
11dd62a7 686
5934df2f 687 omap_hsmmc_set_clock(host);
11dd62a7 688
3796fb8a
AS		 689 omap_hsmmc_set_bus_mode(host);
690
11dd62a7
DK		 691out:
692 host->context_loss = context_loss;
693
694 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
695 return 0;
696}
697
698/*
699 * Save the MMC host context (store the number of power state changes so far).
700 */
70a3341a 701static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 702{
703 struct omap_mmc_platform_data *pdata = host->pdata;
704 int context_loss;
705
706 if (pdata->get_context_loss_count) {
707 context_loss = pdata->get_context_loss_count(host->dev);
708 if (context_loss < 0)
709 return;
710 host->context_loss = context_loss;
711 }
712}
713
714#else
715
70a3341a 716static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 717{
718 return 0;
719}
720
70a3341a 721static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 722{
723}
724
725#endif
726
a45c6cb8
MC		 727/*
728 * Send init stream sequence to card
729 * before sending IDLE command
730 */
70a3341a 731static void send_init_stream(struct omap_hsmmc_host *host)
a45c6cb8
MC		 732{
733 int reg = 0;
734 unsigned long timeout;
735
b62f6228
AH		 736 if (host->protect_card)
737 return;
738
a45c6cb8 739 disable_irq(host->irq);
b417577d
AH		 740
741 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8
MC		 742 OMAP_HSMMC_WRITE(host->base, CON,
743 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
744 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
745
746 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
747 while ((reg != CC) && time_before(jiffies, timeout))
748 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
749
750 OMAP_HSMMC_WRITE(host->base, CON,
751 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
c653a6d4
AH		 752
753 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
754 OMAP_HSMMC_READ(host->base, STAT);
755
a45c6cb8
MC		 756 enable_irq(host->irq);
757}
758
759static inline
70a3341a 760int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
a45c6cb8
MC		 761{
762 int r = 1;
763
191d1f1d
DK		 764 if (mmc_slot(host).get_cover_state)
765 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
a45c6cb8
MC		 766 return r;
767}
768
769static ssize_t
70a3341a 770omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 771 char *buf)
772{
773 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 774 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 775
70a3341a
DK		 776 return sprintf(buf, "%s\n",
777 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
a45c6cb8
MC		 778}
779
70a3341a 780static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
a45c6cb8
MC		 781
782static ssize_t
70a3341a 783omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 784 char *buf)
785{
786 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 787 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 788
191d1f1d 789 return sprintf(buf, "%s\n", mmc_slot(host).name);
a45c6cb8
MC		 790}
791
70a3341a 792static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
a45c6cb8
MC		 793
794/*
795 * Configure the response type and send the cmd.
796 */
797static void
70a3341a 798omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
a45c6cb8
MC		 799 struct mmc_data *data)
800{
801 int cmdreg = 0, resptype = 0, cmdtype = 0;
802
803 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
804 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
805 host->cmd = cmd;
806
93caf8e6 807 omap_hsmmc_enable_irq(host, cmd);
a45c6cb8 808
4a694dc9 809 host->response_busy = 0;
a45c6cb8
MC		 810 if (cmd->flags & MMC_RSP_PRESENT) {
811 if (cmd->flags & MMC_RSP_136)
812 resptype = 1;
4a694dc9
AH		 813 else if (cmd->flags & MMC_RSP_BUSY) {
814 resptype = 3;
815 host->response_busy = 1;
816 } else
a45c6cb8
MC		 817 resptype = 2;
818 }
819
820 /*
821 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
822 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
823 * a val of 0x3, rest 0x0.
824 */
825 if (cmd == host->mrq->stop)
826 cmdtype = 0x3;
827
828 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
829
830 if (data) {
831 cmdreg |= DP_SELECT | MSBS | BCE;
832 if (data->flags & MMC_DATA_READ)
833 cmdreg |= DDIR;
834 else
835 cmdreg &= ~(DDIR);
836 }
837
838 if (host->use_dma)
839 cmdreg |= DMA_EN;
840
b417577d 841 host->req_in_progress = 1;
4dffd7a2 842
a45c6cb8
MC		 843 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
844 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
845}
846
0ccd76d4 847static int
70a3341a 848omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
0ccd76d4
JY		 849{
850 if (data->flags & MMC_DATA_WRITE)
851 return DMA_TO_DEVICE;
852 else
853 return DMA_FROM_DEVICE;
854}
855
b417577d
AH		 856static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
857{
858 int dma_ch;
859
860 spin_lock(&host->irq_lock);
861 host->req_in_progress = 0;
862 dma_ch = host->dma_ch;
863 spin_unlock(&host->irq_lock);
864
865 omap_hsmmc_disable_irq(host);
866 /* Do not complete the request if DMA is still in progress */
867 if (mrq->data && host->use_dma && dma_ch != -1)
868 return;
869 host->mrq = NULL;
870 mmc_request_done(host->mmc, mrq);
871}
872
a45c6cb8
MC		 873/*
874 * Notify the transfer complete to MMC core
875 */
876static void
70a3341a 877omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
a45c6cb8 878{
4a694dc9
AH		 879 if (!data) {
880 struct mmc_request *mrq = host->mrq;
881
23050103
AH		 882 /* TC before CC from CMD6 - don't know why, but it happens */
883 if (host->cmd && host->cmd->opcode == 6 &&
884 host->response_busy) {
885 host->response_busy = 0;
886 return;
887 }
888
b417577d 889 omap_hsmmc_request_done(host, mrq);
4a694dc9
AH		 890 return;
891 }
892
a45c6cb8
MC		 893 host->data = NULL;
894
a45c6cb8
MC		 895 if (!data->error)
896 data->bytes_xfered += data->blocks * (data->blksz);
897 else
898 data->bytes_xfered = 0;
899
900 if (!data->stop) {
b417577d 901 omap_hsmmc_request_done(host, data->mrq);
a45c6cb8
MC		 902 return;
903 }
70a3341a 904 omap_hsmmc_start_command(host, data->stop, NULL);
a45c6cb8
MC		 905}
906
907/*
908 * Notify the core about command completion
909 */
910static void
70a3341a 911omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
a45c6cb8
MC		 912{
913 host->cmd = NULL;
914
915 if (cmd->flags & MMC_RSP_PRESENT) {
916 if (cmd->flags & MMC_RSP_136) {
917 /* response type 2 */
918 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
919 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
920 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
921 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
922 } else {
923 /* response types 1, 1b, 3, 4, 5, 6 */
924 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
925 }
926 }
b417577d
AH		 927 if ((host->data == NULL && !host->response_busy) || cmd->error)
928 omap_hsmmc_request_done(host, cmd->mrq);
a45c6cb8
MC		 929}
930
931/*
932 * DMA clean up for command errors
933 */
70a3341a 934static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
a45c6cb8 935{
b417577d
AH		 936 int dma_ch;
937
82788ff5 938 host->data->error = errno;
a45c6cb8 939
b417577d
AH		 940 spin_lock(&host->irq_lock);
941 dma_ch = host->dma_ch;
942 host->dma_ch = -1;
943 spin_unlock(&host->irq_lock);
944
945 if (host->use_dma && dma_ch != -1) {
a9120c33
PF		 946 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
947 host->data->sg_len,
70a3341a 948 omap_hsmmc_get_dma_dir(host, host->data));
b417577d 949 omap_free_dma(dma_ch);
053bf34f 950 host->data->host_cookie = 0;
a45c6cb8
MC		 951 }
952 host->data = NULL;
a45c6cb8
MC		 953}
954
955/*
956 * Readable error output
957 */
958#ifdef CONFIG_MMC_DEBUG
699b958b 959static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
a45c6cb8
MC		 960{
961 /* --- means reserved bit without definition at documentation */
70a3341a 962 static const char *omap_hsmmc_status_bits[] = {
699b958b
AH		 963 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
964 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
965 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
966 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
a45c6cb8
MC		 967 };
968 char res[256];
969 char *buf = res;
970 int len, i;
971
972 len = sprintf(buf, "MMC IRQ 0x%x :", status);
973 buf += len;
974
70a3341a 975 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
a45c6cb8 976 if (status & (1 << i)) {
70a3341a 977 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
a45c6cb8
MC		 978 buf += len;
979 }
980
981 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
982}
699b958b
AH		 983#else
984static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
985 u32 status)
986{
987}
a45c6cb8
MC		 988#endif /* CONFIG_MMC_DEBUG */
989
3ebf74b1
JP		 990/*
991 * MMC controller internal state machines reset
992 *
993 * Used to reset command or data internal state machines, using respectively
994 * SRC or SRD bit of SYSCTL register
995 * Can be called from interrupt context
996 */
70a3341a
DK		 997static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
998 unsigned long bit)
3ebf74b1
JP		 999{
1000 unsigned long i = 0;
1001 unsigned long limit = (loops_per_jiffy *
1002 msecs_to_jiffies(MMC_TIMEOUT_MS));
1003
1004 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1005 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1006
07ad64b6
MC		 1007 /*
1008 * OMAP4 ES2 and greater has an updated reset logic.
1009 * Monitor a 0->1 transition first
1010 */
1011 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
b432b4b3 1012 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
07ad64b6
MC		 1013 && (i++ < limit))
1014 cpu_relax();
1015 }
1016 i = 0;
1017
3ebf74b1
JP		 1018 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1019 (i++ < limit))
1020 cpu_relax();
1021
1022 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1023 dev_err(mmc_dev(host->mmc),
1024 "Timeout waiting on controller reset in %s\n",
1025 __func__);
1026}
a45c6cb8 1027
b417577d 1028static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
a45c6cb8 1029{
a45c6cb8 1030 struct mmc_data *data;
b417577d
AH		 1031 int end_cmd = 0, end_trans = 0;
1032
1033 if (!host->req_in_progress) {
1034 do {
1035 OMAP_HSMMC_WRITE(host->base, STAT, status);
1036 /* Flush posted write */
1037 status = OMAP_HSMMC_READ(host->base, STAT);
1038 } while (status & INT_EN_MASK);
1039 return;
a45c6cb8
MC		 1040 }
1041
1042 data = host->data;
a45c6cb8
MC		 1043 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1044
1045 if (status & ERR) {
699b958b 1046 omap_hsmmc_dbg_report_irq(host, status);
a45c6cb8
MC		 1047 if ((status & CMD_TIMEOUT) ||
1048 (status & CMD_CRC)) {
1049 if (host->cmd) {
1050 if (status & CMD_TIMEOUT) {
70a3341a
DK		 1051 omap_hsmmc_reset_controller_fsm(host,
1052 SRC);
a45c6cb8
MC		 1053 host->cmd->error = -ETIMEDOUT;
1054 } else {
1055 host->cmd->error = -EILSEQ;
1056 }
1057 end_cmd = 1;
1058 }
4a694dc9
AH		 1059 if (host->data || host->response_busy) {
1060 if (host->data)
70a3341a
DK		 1061 omap_hsmmc_dma_cleanup(host,
1062 -ETIMEDOUT);
4a694dc9 1063 host->response_busy = 0;
70a3341a 1064 omap_hsmmc_reset_controller_fsm(host, SRD);
c232f457 1065 }
a45c6cb8
MC		 1066 }
1067 if ((status & DATA_TIMEOUT) ||
1068 (status & DATA_CRC)) {
4a694dc9
AH		 1069 if (host->data || host->response_busy) {
1070 int err = (status & DATA_TIMEOUT) ?
1071 -ETIMEDOUT : -EILSEQ;
1072
1073 if (host->data)
70a3341a 1074 omap_hsmmc_dma_cleanup(host, err);
a45c6cb8 1075 else
4a694dc9
AH		 1076 host->mrq->cmd->error = err;
1077 host->response_busy = 0;
70a3341a 1078 omap_hsmmc_reset_controller_fsm(host, SRD);
a45c6cb8
MC		 1079 end_trans = 1;
1080 }
1081 }
1082 if (status & CARD_ERR) {
1083 dev_dbg(mmc_dev(host->mmc),
1084 "Ignoring card err CMD%d\n", host->cmd->opcode);
1085 if (host->cmd)
1086 end_cmd = 1;
1087 if (host->data)
1088 end_trans = 1;
1089 }
1090 }
1091
1092 OMAP_HSMMC_WRITE(host->base, STAT, status);
1093
a8fe29d8 1094 if (end_cmd || ((status & CC) && host->cmd))
70a3341a 1095 omap_hsmmc_cmd_done(host, host->cmd);
0a40e647 1096 if ((end_trans || (status & TC)) && host->mrq)
70a3341a 1097 omap_hsmmc_xfer_done(host, data);
b417577d 1098}
a45c6cb8 1099
b417577d
AH		 1100/*
1101 * MMC controller IRQ handler
1102 */
1103static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1104{
1105 struct omap_hsmmc_host *host = dev_id;
1106 int status;
1107
1108 status = OMAP_HSMMC_READ(host->base, STAT);
1109 do {
1110 omap_hsmmc_do_irq(host, status);
1111 /* Flush posted write */
1112 status = OMAP_HSMMC_READ(host->base, STAT);
1113 } while (status & INT_EN_MASK);
4dffd7a2 1114
a45c6cb8
MC		 1115 return IRQ_HANDLED;
1116}
1117
70a3341a 1118static void set_sd_bus_power(struct omap_hsmmc_host *host)
e13bb300
AH		 1119{
1120 unsigned long i;
1121
1122 OMAP_HSMMC_WRITE(host->base, HCTL,
1123 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1124 for (i = 0; i < loops_per_jiffy; i++) {
1125 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1126 break;
1127 cpu_relax();
1128 }
1129}
1130
a45c6cb8 1131/*
eb250826
DB		 1132 * Switch MMC interface voltage ... only relevant for MMC1.
1133 *
1134 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1135 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1136 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8 1137 */
70a3341a 1138static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
a45c6cb8
MC		 1139{
1140 u32 reg_val = 0;
1141 int ret;
1142
1143 /* Disable the clocks */
fa4aa2d4 1144 pm_runtime_put_sync(host->dev);
2bec0893
AH		 1145 if (host->got_dbclk)
1146 clk_disable(host->dbclk);
a45c6cb8
MC		 1147
1148 /* Turn the power off */
1149 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
a45c6cb8
MC		 1150
1151 /* Turn the power ON with given VDD 1.8 or 3.0v */
2bec0893
AH		 1152 if (!ret)
1153 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1154 vdd);
fa4aa2d4 1155 pm_runtime_get_sync(host->dev);
2bec0893
AH		 1156 if (host->got_dbclk)
1157 clk_enable(host->dbclk);
1158
a45c6cb8
MC		 1159 if (ret != 0)
1160 goto err;
1161
a45c6cb8
MC		 1162 OMAP_HSMMC_WRITE(host->base, HCTL,
1163 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1164 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 1165
a45c6cb8
MC		 1166 /*
1167 * If a MMC dual voltage card is detected, the set_ios fn calls
1168 * this fn with VDD bit set for 1.8V. Upon card removal from the
70a3341a 1169 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
a45c6cb8 1170 *
eb250826
DB		 1171 * Cope with a bit of slop in the range ... per data sheets:
1172 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1173 * but recommended values are 1.71V to 1.89V
1174 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1175 * but recommended values are 2.7V to 3.3V
1176 *
1177 * Board setup code shouldn't permit anything very out-of-range.
1178 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1179 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 1180 */
eb250826 1181 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 1182 reg_val |= SDVS18;
eb250826
DB		 1183 else
1184 reg_val |= SDVS30;
a45c6cb8
MC		 1185
1186 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 1187 set_sd_bus_power(host);
a45c6cb8
MC		 1188
1189 return 0;
1190err:
1191 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1192 return ret;
1193}
1194
b62f6228
AH		 1195/* Protect the card while the cover is open */
1196static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1197{
1198 if (!mmc_slot(host).get_cover_state)
1199 return;
1200
1201 host->reqs_blocked = 0;
1202 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1203 if (host->protect_card) {
a3c76eb9 1204 pr_info("%s: cover is closed, "
b62f6228
AH		 1205 "card is now accessible\n",
1206 mmc_hostname(host->mmc));
1207 host->protect_card = 0;
1208 }
1209 } else {
1210 if (!host->protect_card) {
3f8ddb03 1211 pr_info("%s: cover is open, "
b62f6228
AH		 1212 "card is now inaccessible\n",
1213 mmc_hostname(host->mmc));
1214 host->protect_card = 1;
1215 }
1216 }
1217}
1218
a45c6cb8 1219/*
7efab4f3 1220 * irq handler to notify the core about card insertion/removal
a45c6cb8 1221 */
7efab4f3 1222static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
a45c6cb8 1223{
7efab4f3 1224 struct omap_hsmmc_host *host = dev_id;
249d0fa9 1225 struct omap_mmc_slot_data *slot = &mmc_slot(host);
a6b2240d
AH		 1226 int carddetect;
1227
1228 if (host->suspended)
7efab4f3 1229 return IRQ_HANDLED;
a6b2240d
AH		 1230
1231 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
249d0fa9 1232
191d1f1d 1233 if (slot->card_detect)
db0fefc5 1234 carddetect = slot->card_detect(host->dev, host->slot_id);
b62f6228
AH		 1235 else {
1236 omap_hsmmc_protect_card(host);
a6b2240d 1237 carddetect = -ENOSYS;
b62f6228 1238 }
a45c6cb8 1239
cdeebadd 1240 if (carddetect)
a45c6cb8 1241 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
cdeebadd 1242 else
a45c6cb8 1243 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
a45c6cb8
MC		 1244 return IRQ_HANDLED;
1245}
1246
70a3341a 1247static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1248 struct mmc_data *data)
1249{
1250 int sync_dev;
1251
f3e2f1dd
GI		 1252 if (data->flags & MMC_DATA_WRITE)
1253 sync_dev = host->dma_line_tx;
1254 else
1255 sync_dev = host->dma_line_rx;
0ccd76d4
JY		 1256 return sync_dev;
1257}
1258
70a3341a 1259static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1260 struct mmc_data *data,
1261 struct scatterlist *sgl)
1262{
1263 int blksz, nblk, dma_ch;
1264
1265 dma_ch = host->dma_ch;
1266 if (data->flags & MMC_DATA_WRITE) {
1267 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1268 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1269 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1270 sg_dma_address(sgl), 0, 0);
1271 } else {
1272 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
191d1f1d 1273 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
0ccd76d4
JY		 1274 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1275 sg_dma_address(sgl), 0, 0);
1276 }
1277
1278 blksz = host->data->blksz;
1279 nblk = sg_dma_len(sgl) / blksz;
1280
1281 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1282 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
70a3341a 1283 omap_hsmmc_get_dma_sync_dev(host, data),
0ccd76d4
JY		 1284 !(data->flags & MMC_DATA_WRITE));
1285
1286 omap_start_dma(dma_ch);
1287}
1288
a45c6cb8
MC		 1289/*
1290 * DMA call back function
1291 */
b417577d 1292static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
a45c6cb8 1293{
b417577d 1294 struct omap_hsmmc_host *host = cb_data;
770d7432 1295 struct mmc_data *data;
b417577d 1296 int dma_ch, req_in_progress;
a45c6cb8 1297
f3584e5e
V		 1298 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1299 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1300 ch_status);
1301 return;
1302 }
a45c6cb8 1303
b417577d
AH		 1304 spin_lock(&host->irq_lock);
1305 if (host->dma_ch < 0) {
1306 spin_unlock(&host->irq_lock);
a45c6cb8 1307 return;
b417577d 1308 }
a45c6cb8 1309
770d7432 1310 data = host->mrq->data;
0ccd76d4
JY		 1311 host->dma_sg_idx++;
1312 if (host->dma_sg_idx < host->dma_len) {
1313 /* Fire up the next transfer. */
b417577d
AH		 1314 omap_hsmmc_config_dma_params(host, data,
1315 data->sg + host->dma_sg_idx);
1316 spin_unlock(&host->irq_lock);
0ccd76d4
JY		 1317 return;
1318 }
1319
9782aff8
PF		 1320 if (!data->host_cookie)
1321 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1322 omap_hsmmc_get_dma_dir(host, data));
b417577d
AH		 1323
1324 req_in_progress = host->req_in_progress;
1325 dma_ch = host->dma_ch;
a45c6cb8 1326 host->dma_ch = -1;
b417577d
AH		 1327 spin_unlock(&host->irq_lock);
1328
1329 omap_free_dma(dma_ch);
1330
1331 /* If DMA has finished after TC, complete the request */
1332 if (!req_in_progress) {
1333 struct mmc_request *mrq = host->mrq;
1334
1335 host->mrq = NULL;
1336 mmc_request_done(host->mmc, mrq);
1337 }
a45c6cb8
MC		 1338}
1339
9782aff8
PF		 1340static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1341 struct mmc_data *data,
1342 struct omap_hsmmc_next *next)
1343{
1344 int dma_len;
1345
1346 if (!next && data->host_cookie &&
1347 data->host_cookie != host->next_data.cookie) {
a3c76eb9 1348 pr_warning("[%s] invalid cookie: data->host_cookie %d"
9782aff8
PF		 1349 " host->next_data.cookie %d\n",
1350 __func__, data->host_cookie, host->next_data.cookie);
1351 data->host_cookie = 0;
1352 }
1353
1354 /* Check if next job is already prepared */
1355 if (next ||
1356 (!next && data->host_cookie != host->next_data.cookie)) {
1357 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1358 data->sg_len,
1359 omap_hsmmc_get_dma_dir(host, data));
1360
1361 } else {
1362 dma_len = host->next_data.dma_len;
1363 host->next_data.dma_len = 0;
1364 }
1365
1366
1367 if (dma_len == 0)
1368 return -EINVAL;
1369
1370 if (next) {
1371 next->dma_len = dma_len;
1372 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1373 } else
1374 host->dma_len = dma_len;
1375
1376 return 0;
1377}
1378
a45c6cb8
MC		 1379/*
1380 * Routine to configure and start DMA for the MMC card
1381 */
70a3341a
DK		 1382static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1383 struct mmc_request *req)
a45c6cb8 1384{
b417577d 1385 int dma_ch = 0, ret = 0, i;
a45c6cb8
MC		 1386 struct mmc_data *data = req->data;
1387
0ccd76d4 1388 /* Sanity check: all the SG entries must be aligned by block size. */
a3f406f8 1389 for (i = 0; i < data->sg_len; i++) {
0ccd76d4
JY		 1390 struct scatterlist *sgl;
1391
1392 sgl = data->sg + i;
1393 if (sgl->length % data->blksz)
1394 return -EINVAL;
1395 }
1396 if ((data->blksz % 4) != 0)
1397 /* REVISIT: The MMC buffer increments only when MSB is written.
1398 * Return error for blksz which is non multiple of four.
1399 */
1400 return -EINVAL;
1401
b417577d 1402 BUG_ON(host->dma_ch != -1);
a45c6cb8 1403
70a3341a
DK		 1404 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1405 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
a45c6cb8 1406 if (ret != 0) {
0ccd76d4 1407 dev_err(mmc_dev(host->mmc),
a45c6cb8
MC		 1408 "%s: omap_request_dma() failed with %d\n",
1409 mmc_hostname(host->mmc), ret);
1410 return ret;
1411 }
9782aff8
PF		 1412 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1413 if (ret)
1414 return ret;
a45c6cb8 1415
a45c6cb8 1416 host->dma_ch = dma_ch;
0ccd76d4 1417 host->dma_sg_idx = 0;
a45c6cb8 1418
70a3341a 1419 omap_hsmmc_config_dma_params(host, data, data->sg);
a45c6cb8 1420
a45c6cb8
MC		 1421 return 0;
1422}
1423
70a3341a 1424static void set_data_timeout(struct omap_hsmmc_host *host,
e2bf08d6
AH		 1425 unsigned int timeout_ns,
1426 unsigned int timeout_clks)
a45c6cb8
MC		 1427{
1428 unsigned int timeout, cycle_ns;
1429 uint32_t reg, clkd, dto = 0;
1430
1431 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1432 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1433 if (clkd == 0)
1434 clkd = 1;
1435
1436 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
e2bf08d6
AH		 1437 timeout = timeout_ns / cycle_ns;
1438 timeout += timeout_clks;
a45c6cb8
MC		 1439 if (timeout) {
1440 while ((timeout & 0x80000000) == 0) {
1441 dto += 1;
1442 timeout <<= 1;
1443 }
1444 dto = 31 - dto;
1445 timeout <<= 1;
1446 if (timeout && dto)
1447 dto += 1;
1448 if (dto >= 13)
1449 dto -= 13;
1450 else
1451 dto = 0;
1452 if (dto > 14)
1453 dto = 14;
1454 }
1455
1456 reg &= ~DTO_MASK;
1457 reg |= dto << DTO_SHIFT;
1458 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1459}
1460
1461/*
1462 * Configure block length for MMC/SD cards and initiate the transfer.
1463 */
1464static int
70a3341a 1465omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
a45c6cb8
MC		 1466{
1467 int ret;
1468 host->data = req->data;
1469
1470 if (req->data == NULL) {
a45c6cb8 1471 OMAP_HSMMC_WRITE(host->base, BLK, 0);
e2bf08d6
AH		 1472 /*
1473 * Set an arbitrary 100ms data timeout for commands with
1474 * busy signal.
1475 */
1476 if (req->cmd->flags & MMC_RSP_BUSY)
1477 set_data_timeout(host, 100000000U, 0);
a45c6cb8
MC		 1478 return 0;
1479 }
1480
1481 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1482 | (req->data->blocks << 16));
e2bf08d6 1483 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
a45c6cb8 1484
a45c6cb8 1485 if (host->use_dma) {
70a3341a 1486 ret = omap_hsmmc_start_dma_transfer(host, req);
a45c6cb8
MC		 1487 if (ret != 0) {
1488 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1489 return ret;
1490 }
1491 }
1492 return 0;
1493}
1494
9782aff8
PF		 1495static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1496 int err)
1497{
1498 struct omap_hsmmc_host *host = mmc_priv(mmc);
1499 struct mmc_data *data = mrq->data;
1500
1501 if (host->use_dma) {
053bf34f
PF		 1502 if (data->host_cookie)
1503 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
1504 data->sg_len,
1505 omap_hsmmc_get_dma_dir(host, data));
9782aff8
PF		 1506 data->host_cookie = 0;
1507 }
1508}
1509
1510static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1511 bool is_first_req)
1512{
1513 struct omap_hsmmc_host *host = mmc_priv(mmc);
1514
1515 if (mrq->data->host_cookie) {
1516 mrq->data->host_cookie = 0;
1517 return ;
1518 }
1519
1520 if (host->use_dma)
1521 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1522 &host->next_data))
1523 mrq->data->host_cookie = 0;
1524}
1525
a45c6cb8
MC		 1526/*
1527 * Request function. for read/write operation
1528 */
70a3341a 1529static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
a45c6cb8 1530{
70a3341a 1531 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3f406f8 1532 int err;
a45c6cb8 1533
b417577d
AH		 1534 BUG_ON(host->req_in_progress);
1535 BUG_ON(host->dma_ch != -1);
1536 if (host->protect_card) {
1537 if (host->reqs_blocked < 3) {
1538 /*
1539 * Ensure the controller is left in a consistent
1540 * state by resetting the command and data state
1541 * machines.
1542 */
1543 omap_hsmmc_reset_controller_fsm(host, SRD);
1544 omap_hsmmc_reset_controller_fsm(host, SRC);
1545 host->reqs_blocked += 1;
1546 }
1547 req->cmd->error = -EBADF;
1548 if (req->data)
1549 req->data->error = -EBADF;
1550 req->cmd->retries = 0;
1551 mmc_request_done(mmc, req);
1552 return;
1553 } else if (host->reqs_blocked)
1554 host->reqs_blocked = 0;
a45c6cb8
MC		 1555 WARN_ON(host->mrq != NULL);
1556 host->mrq = req;
70a3341a 1557 err = omap_hsmmc_prepare_data(host, req);
a3f406f8
JL		 1558 if (err) {
1559 req->cmd->error = err;
1560 if (req->data)
1561 req->data->error = err;
1562 host->mrq = NULL;
1563 mmc_request_done(mmc, req);
1564 return;
1565 }
1566
70a3341a 1567 omap_hsmmc_start_command(host, req->cmd, req->data);
a45c6cb8
MC		 1568}
1569
a45c6cb8 1570/* Routine to configure clock values. Exposed API to core */
70a3341a 1571static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
a45c6cb8 1572{
70a3341a 1573 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3621465 1574 int do_send_init_stream = 0;
a45c6cb8 1575
fa4aa2d4 1576 pm_runtime_get_sync(host->dev);
5e2ea617 1577
a3621465
AH		 1578 if (ios->power_mode != host->power_mode) {
1579 switch (ios->power_mode) {
1580 case MMC_POWER_OFF:
1581 mmc_slot(host).set_power(host->dev, host->slot_id,
1582 0, 0);
623821f7 1583 host->vdd = 0;
a3621465
AH		 1584 break;
1585 case MMC_POWER_UP:
1586 mmc_slot(host).set_power(host->dev, host->slot_id,
1587 1, ios->vdd);
623821f7 1588 host->vdd = ios->vdd;
a3621465
AH		 1589 break;
1590 case MMC_POWER_ON:
1591 do_send_init_stream = 1;
1592 break;
1593 }
1594 host->power_mode = ios->power_mode;
a45c6cb8
MC		 1595 }
1596
dd498eff
DK		 1597 /* FIXME: set registers based only on changes to ios */
1598
3796fb8a 1599 omap_hsmmc_set_bus_width(host);
a45c6cb8 1600
4621d5f8 1601 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
eb250826
DB		 1602 /* Only MMC1 can interface at 3V without some flavor
1603 * of external transceiver; but they all handle 1.8V.
1604 */
a45c6cb8
MC		 1605 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1606 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1607 /*
1608 * The mmc_select_voltage fn of the core does
1609 * not seem to set the power_mode to
1610 * MMC_POWER_UP upon recalculating the voltage.
1611 * vdd 1.8v.
1612 */
70a3341a
DK		 1613 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1614 dev_dbg(mmc_dev(host->mmc),
a45c6cb8
MC		 1615 "Switch operation failed\n");
1616 }
1617 }
1618
5934df2f 1619 omap_hsmmc_set_clock(host);
a45c6cb8 1620
a3621465 1621 if (do_send_init_stream)
a45c6cb8
MC		 1622 send_init_stream(host);
1623
3796fb8a 1624 omap_hsmmc_set_bus_mode(host);
5e2ea617 1625
fa4aa2d4 1626 pm_runtime_put_autosuspend(host->dev);
a45c6cb8
MC		 1627}
1628
1629static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1630{
70a3341a 1631 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1632
191d1f1d 1633 if (!mmc_slot(host).card_detect)
a45c6cb8 1634 return -ENOSYS;
db0fefc5 1635 return mmc_slot(host).card_detect(host->dev, host->slot_id);
a45c6cb8
MC		 1636}
1637
1638static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1639{
70a3341a 1640 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1641
191d1f1d 1642 if (!mmc_slot(host).get_ro)
a45c6cb8 1643 return -ENOSYS;
191d1f1d 1644 return mmc_slot(host).get_ro(host->dev, 0);
a45c6cb8
MC		 1645}
1646
4816858c
GI		 1647static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1648{
1649 struct omap_hsmmc_host *host = mmc_priv(mmc);
1650
1651 if (mmc_slot(host).init_card)
1652 mmc_slot(host).init_card(card);
1653}
1654
70a3341a 1655static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1b331e69
KK		 1656{
1657 u32 hctl, capa, value;
1658
1659 /* Only MMC1 supports 3.0V */
4621d5f8 1660 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1b331e69
KK		 1661 hctl = SDVS30;
1662 capa = VS30 | VS18;
1663 } else {
1664 hctl = SDVS18;
1665 capa = VS18;
1666 }
1667
1668 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1669 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1670
1671 value = OMAP_HSMMC_READ(host->base, CAPA);
1672 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1673
1674 /* Set the controller to AUTO IDLE mode */
1675 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1676 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1677
1678 /* Set SD bus power bit */
e13bb300 1679 set_sd_bus_power(host);
1b331e69
KK		 1680}
1681
70a3341a 1682static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
dd498eff 1683{
70a3341a 1684 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1685
fa4aa2d4
B		 1686 pm_runtime_get_sync(host->dev);
1687
dd498eff
DK		 1688 return 0;
1689}
1690
70a3341a 1691static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
dd498eff 1692{
70a3341a 1693 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1694
fa4aa2d4
B		 1695 pm_runtime_mark_last_busy(host->dev);
1696 pm_runtime_put_autosuspend(host->dev);
1697
dd498eff
DK		 1698 return 0;
1699}
1700
70a3341a
DK		 1701static const struct mmc_host_ops omap_hsmmc_ops = {
1702 .enable = omap_hsmmc_enable_fclk,
1703 .disable = omap_hsmmc_disable_fclk,
9782aff8
PF		 1704 .post_req = omap_hsmmc_post_req,
1705 .pre_req = omap_hsmmc_pre_req,
70a3341a
DK		 1706 .request = omap_hsmmc_request,
1707 .set_ios = omap_hsmmc_set_ios,
dd498eff
DK		 1708 .get_cd = omap_hsmmc_get_cd,
1709 .get_ro = omap_hsmmc_get_ro,
4816858c 1710 .init_card = omap_hsmmc_init_card,
dd498eff
DK		 1711 /* NYET -- enable_sdio_irq */
1712};
1713
d900f712
DK		 1714#ifdef CONFIG_DEBUG_FS
1715
70a3341a 1716static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
d900f712
DK		 1717{
1718 struct mmc_host *mmc = s->private;
70a3341a 1719 struct omap_hsmmc_host *host = mmc_priv(mmc);
11dd62a7
DK		 1720 int context_loss = 0;
1721
70a3341a
DK		 1722 if (host->pdata->get_context_loss_count)
1723 context_loss = host->pdata->get_context_loss_count(host->dev);
d900f712 1724
5e2ea617
AH		 1725 seq_printf(s, "mmc%d:\n"
1726 " enabled:\t%d\n"
dd498eff 1727 " dpm_state:\t%d\n"
5e2ea617 1728 " nesting_cnt:\t%d\n"
11dd62a7 1729 " ctx_loss:\t%d:%d\n"
5e2ea617 1730 "\nregs:\n",
dd498eff
DK		 1731 mmc->index, mmc->enabled ? 1 : 0,
1732 host->dpm_state, mmc->nesting_cnt,
11dd62a7 1733 host->context_loss, context_loss);
5e2ea617 1734
7a8c2cef 1735 if (host->suspended) {
dd498eff
DK		 1736 seq_printf(s, "host suspended, can't read registers\n");
1737 return 0;
1738 }
1739
fa4aa2d4 1740 pm_runtime_get_sync(host->dev);
d900f712
DK		 1741
1742 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1743 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1744 seq_printf(s, "CON:\t\t0x%08x\n",
1745 OMAP_HSMMC_READ(host->base, CON));
1746 seq_printf(s, "HCTL:\t\t0x%08x\n",
1747 OMAP_HSMMC_READ(host->base, HCTL));
1748 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1749 OMAP_HSMMC_READ(host->base, SYSCTL));
1750 seq_printf(s, "IE:\t\t0x%08x\n",
1751 OMAP_HSMMC_READ(host->base, IE));
1752 seq_printf(s, "ISE:\t\t0x%08x\n",
1753 OMAP_HSMMC_READ(host->base, ISE));
1754 seq_printf(s, "CAPA:\t\t0x%08x\n",
1755 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617 1756
fa4aa2d4
B		 1757 pm_runtime_mark_last_busy(host->dev);
1758 pm_runtime_put_autosuspend(host->dev);
dd498eff 1759
d900f712
DK		 1760 return 0;
1761}
1762
70a3341a 1763static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
d900f712 1764{
70a3341a 1765 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
d900f712
DK		 1766}
1767
1768static const struct file_operations mmc_regs_fops = {
70a3341a 1769 .open = omap_hsmmc_regs_open,
d900f712
DK		 1770 .read = seq_read,
1771 .llseek = seq_lseek,
1772 .release = single_release,
1773};
1774
70a3341a 1775static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1776{
1777 if (mmc->debugfs_root)
1778 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1779 mmc, &mmc_regs_fops);
1780}
1781
1782#else
1783
70a3341a 1784static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1785{
1786}
1787
1788#endif
1789
70a3341a 1790static int __init omap_hsmmc_probe(struct platform_device *pdev)
a45c6cb8
MC		 1791{
1792 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1793 struct mmc_host *mmc;
70a3341a 1794 struct omap_hsmmc_host *host = NULL;
a45c6cb8 1795 struct resource *res;
db0fefc5 1796 int ret, irq;
a45c6cb8
MC		 1797
1798 if (pdata == NULL) {
1799 dev_err(&pdev->dev, "Platform Data is missing\n");
1800 return -ENXIO;
1801 }
1802
1803 if (pdata->nr_slots == 0) {
1804 dev_err(&pdev->dev, "No Slots\n");
1805 return -ENXIO;
1806 }
1807
1808 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1809 irq = platform_get_irq(pdev, 0);
1810 if (res == NULL || irq < 0)
1811 return -ENXIO;
1812
91a0b089 1813 res->start += pdata->reg_offset;
1814 res->end += pdata->reg_offset;
984b203a 1815 res = request_mem_region(res->start, resource_size(res), pdev->name);
a45c6cb8
MC		 1816 if (res == NULL)
1817 return -EBUSY;
1818
db0fefc5
AH		 1819 ret = omap_hsmmc_gpio_init(pdata);
1820 if (ret)
1821 goto err;
1822
70a3341a 1823 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
a45c6cb8
MC		 1824 if (!mmc) {
1825 ret = -ENOMEM;
db0fefc5 1826 goto err_alloc;
a45c6cb8
MC		 1827 }
1828
1829 host = mmc_priv(mmc);
1830 host->mmc = mmc;
1831 host->pdata = pdata;
1832 host->dev = &pdev->dev;
1833 host->use_dma = 1;
1834 host->dev->dma_mask = &pdata->dma_mask;
1835 host->dma_ch = -1;
1836 host->irq = irq;
1837 host->id = pdev->id;
1838 host->slot_id = 0;
1839 host->mapbase = res->start;
1840 host->base = ioremap(host->mapbase, SZ_4K);
6da20c89 1841 host->power_mode = MMC_POWER_OFF;
9782aff8 1842 host->next_data.cookie = 1;
a45c6cb8
MC		 1843
1844 platform_set_drvdata(pdev, host);
a45c6cb8 1845
7a8c2cef 1846 mmc->ops = &omap_hsmmc_ops;
dd498eff 1847
e0eb2424
AH		 1848 /*
1849 * If regulator_disable can only put vcc_aux to sleep then there is
1850 * no off state.
1851 */
1852 if (mmc_slot(host).vcc_aux_disable_is_sleep)
1853 mmc_slot(host).no_off = 1;
1854
d418ed87
DM		 1855 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1856
1857 if (pdata->max_freq > 0)
1858 mmc->f_max = pdata->max_freq;
1859 else
1860 mmc->f_max = OMAP_MMC_MAX_CLOCK;
a45c6cb8 1861
4dffd7a2 1862 spin_lock_init(&host->irq_lock);
a45c6cb8 1863
6f7607cc 1864 host->fclk = clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 1865 if (IS_ERR(host->fclk)) {
1866 ret = PTR_ERR(host->fclk);
1867 host->fclk = NULL;
a45c6cb8
MC		 1868 goto err1;
1869 }
1870
70a3341a 1871 omap_hsmmc_context_save(host);
11dd62a7 1872
5e2ea617 1873 mmc->caps |= MMC_CAP_DISABLE;
9b68256c
PW		 1874 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1875 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1876 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1877 }
dd498eff 1878
fa4aa2d4
B		 1879 pm_runtime_enable(host->dev);
1880 pm_runtime_get_sync(host->dev);
1881 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1882 pm_runtime_use_autosuspend(host->dev);
a45c6cb8 1883
2bec0893
AH		 1884 if (cpu_is_omap2430()) {
1885 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1886 /*
1887 * MMC can still work without debounce clock.
1888 */
1889 if (IS_ERR(host->dbclk))
1890 dev_warn(mmc_dev(host->mmc),
1891 "Failed to get debounce clock\n");
a45c6cb8 1892 else
2bec0893
AH		 1893 host->got_dbclk = 1;
1894
1895 if (host->got_dbclk)
1896 if (clk_enable(host->dbclk) != 0)
1897 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1898 " clk failed\n");
1899 }
a45c6cb8 1900
0ccd76d4
JY		 1901 /* Since we do only SG emulation, we can have as many segs
1902 * as we want. */
a36274e0 1903 mmc->max_segs = 1024;
0ccd76d4 1904
a45c6cb8
MC		 1905 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1906 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1907 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1908 mmc->max_seg_size = mmc->max_req_size;
1909
13189e78 1910 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
93caf8e6 1911 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
a45c6cb8 1912
3a63833e
SG		 1913 mmc->caps |= mmc_slot(host).caps;
1914 if (mmc->caps & MMC_CAP_8_BIT_DATA)
a45c6cb8
MC		 1915 mmc->caps |= MMC_CAP_4_BIT_DATA;
1916
191d1f1d 1917 if (mmc_slot(host).nonremovable)
23d99bb9
AH		 1918 mmc->caps |= MMC_CAP_NONREMOVABLE;
1919
6fdc75de
EP		 1920 mmc->pm_caps = mmc_slot(host).pm_caps;
1921
70a3341a 1922 omap_hsmmc_conf_bus_power(host);
a45c6cb8 1923
b7bf773b
B		 1924 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1925 if (!res) {
1926 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
1927 goto err_irq;
1928 }
1929 host->dma_line_tx = res->start;
1930
1931 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1932 if (!res) {
1933 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
f3e2f1dd
GI		 1934 goto err_irq;
1935 }
b7bf773b 1936 host->dma_line_rx = res->start;
a45c6cb8
MC		 1937
1938 /* Request IRQ for MMC operations */
d9618e9f 1939 ret = request_irq(host->irq, omap_hsmmc_irq, 0,
a45c6cb8
MC		 1940 mmc_hostname(mmc), host);
1941 if (ret) {
1942 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1943 goto err_irq;
1944 }
1945
1946 if (pdata->init != NULL) {
1947 if (pdata->init(&pdev->dev) != 0) {
70a3341a
DK		 1948 dev_dbg(mmc_dev(host->mmc),
1949 "Unable to configure MMC IRQs\n");
a45c6cb8
MC		 1950 goto err_irq_cd_init;
1951 }
1952 }
db0fefc5 1953
b702b106 1954 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
db0fefc5
AH		 1955 ret = omap_hsmmc_reg_get(host);
1956 if (ret)
1957 goto err_reg;
1958 host->use_reg = 1;
1959 }
1960
b583f26d 1961 mmc->ocr_avail = mmc_slot(host).ocr_mask;
a45c6cb8
MC		 1962
1963 /* Request IRQ for card detect */
e1a55f5e 1964 if ((mmc_slot(host).card_detect_irq)) {
7efab4f3
N		 1965 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
1966 NULL,
1967 omap_hsmmc_detect,
1968 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
1969 mmc_hostname(mmc), host);
a45c6cb8
MC		 1970 if (ret) {
1971 dev_dbg(mmc_dev(host->mmc),
1972 "Unable to grab MMC CD IRQ\n");
1973 goto err_irq_cd;
1974 }
72f2e2c7 1975 pdata->suspend = omap_hsmmc_suspend_cdirq;
1976 pdata->resume = omap_hsmmc_resume_cdirq;
a45c6cb8
MC		 1977 }
1978
b417577d 1979 omap_hsmmc_disable_irq(host);
a45c6cb8 1980
b62f6228
AH		 1981 omap_hsmmc_protect_card(host);
1982
a45c6cb8
MC		 1983 mmc_add_host(mmc);
1984
191d1f1d 1985 if (mmc_slot(host).name != NULL) {
a45c6cb8
MC		 1986 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1987 if (ret < 0)
1988 goto err_slot_name;
1989 }
191d1f1d 1990 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
a45c6cb8
MC		 1991 ret = device_create_file(&mmc->class_dev,
1992 &dev_attr_cover_switch);
1993 if (ret < 0)
db0fefc5 1994 goto err_slot_name;
a45c6cb8
MC		 1995 }
1996
70a3341a 1997 omap_hsmmc_debugfs(mmc);
fa4aa2d4
B		 1998 pm_runtime_mark_last_busy(host->dev);
1999 pm_runtime_put_autosuspend(host->dev);
d900f712 2000
a45c6cb8
MC		 2001 return 0;
2002
a45c6cb8
MC		 2003err_slot_name:
2004 mmc_remove_host(mmc);
a45c6cb8 2005 free_irq(mmc_slot(host).card_detect_irq, host);
db0fefc5
AH		 2006err_irq_cd:
2007 if (host->use_reg)
2008 omap_hsmmc_reg_put(host);
2009err_reg:
2010 if (host->pdata->cleanup)
2011 host->pdata->cleanup(&pdev->dev);
a45c6cb8
MC		 2012err_irq_cd_init:
2013 free_irq(host->irq, host);
2014err_irq:
fa4aa2d4
B		 2015 pm_runtime_mark_last_busy(host->dev);
2016 pm_runtime_put_autosuspend(host->dev);
a45c6cb8 2017 clk_put(host->fclk);
2bec0893 2018 if (host->got_dbclk) {
a45c6cb8
MC		 2019 clk_disable(host->dbclk);
2020 clk_put(host->dbclk);
2021 }
a45c6cb8
MC		 2022err1:
2023 iounmap(host->base);
db0fefc5
AH		 2024 platform_set_drvdata(pdev, NULL);
2025 mmc_free_host(mmc);
2026err_alloc:
2027 omap_hsmmc_gpio_free(pdata);
a45c6cb8 2028err:
984b203a 2029 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 2030 return ret;
2031}
2032
70a3341a 2033static int omap_hsmmc_remove(struct platform_device *pdev)
a45c6cb8 2034{
70a3341a 2035 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2036 struct resource *res;
2037
2038 if (host) {
fa4aa2d4 2039 pm_runtime_get_sync(host->dev);
a45c6cb8 2040 mmc_remove_host(host->mmc);
db0fefc5
AH		 2041 if (host->use_reg)
2042 omap_hsmmc_reg_put(host);
a45c6cb8
MC		 2043 if (host->pdata->cleanup)
2044 host->pdata->cleanup(&pdev->dev);
2045 free_irq(host->irq, host);
2046 if (mmc_slot(host).card_detect_irq)
2047 free_irq(mmc_slot(host).card_detect_irq, host);
a45c6cb8 2048
fa4aa2d4
B		 2049 pm_runtime_put_sync(host->dev);
2050 pm_runtime_disable(host->dev);
a45c6cb8 2051 clk_put(host->fclk);
2bec0893 2052 if (host->got_dbclk) {
a45c6cb8
MC		 2053 clk_disable(host->dbclk);
2054 clk_put(host->dbclk);
2055 }
2056
2057 mmc_free_host(host->mmc);
2058 iounmap(host->base);
db0fefc5 2059 omap_hsmmc_gpio_free(pdev->dev.platform_data);
a45c6cb8
MC		 2060 }
2061
2062 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2063 if (res)
984b203a 2064 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 2065 platform_set_drvdata(pdev, NULL);
2066
2067 return 0;
2068}
2069
2070#ifdef CONFIG_PM
a791daa1 2071static int omap_hsmmc_suspend(struct device *dev)
a45c6cb8
MC		 2072{
2073 int ret = 0;
a791daa1 2074 struct platform_device *pdev = to_platform_device(dev);
70a3341a 2075 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2076
2077 if (host && host->suspended)
2078 return 0;
2079
2080 if (host) {
fa4aa2d4 2081 pm_runtime_get_sync(host->dev);
a6b2240d
AH		 2082 host->suspended = 1;
2083 if (host->pdata->suspend) {
2084 ret = host->pdata->suspend(&pdev->dev,
2085 host->slot_id);
2086 if (ret) {
2087 dev_dbg(mmc_dev(host->mmc),
2088 "Unable to handle MMC board"
2089 " level suspend\n");
2090 host->suspended = 0;
2091 return ret;
2092 }
2093 }
1a13f8fa 2094 ret = mmc_suspend_host(host->mmc);
fa4aa2d4 2095
31f9d463 2096 if (ret) {
a6b2240d
AH		 2097 host->suspended = 0;
2098 if (host->pdata->resume) {
2099 ret = host->pdata->resume(&pdev->dev,
2100 host->slot_id);
2101 if (ret)
2102 dev_dbg(mmc_dev(host->mmc),
2103 "Unmask interrupt failed\n");
2104 }
31f9d463 2105 goto err;
a6b2240d 2106 }
31f9d463
EP		 2107
2108 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2109 omap_hsmmc_disable_irq(host);
2110 OMAP_HSMMC_WRITE(host->base, HCTL,
2111 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2112 }
2113 if (host->got_dbclk)
2114 clk_disable(host->dbclk);
2115
a45c6cb8 2116 }
31f9d463
EP		 2117err:
2118 pm_runtime_put_sync(host->dev);
a45c6cb8
MC		 2119 return ret;
2120}
2121
2122/* Routine to resume the MMC device */
a791daa1 2123static int omap_hsmmc_resume(struct device *dev)
a45c6cb8
MC		 2124{
2125 int ret = 0;
a791daa1 2126 struct platform_device *pdev = to_platform_device(dev);
70a3341a 2127 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2128
2129 if (host && !host->suspended)
2130 return 0;
2131
2132 if (host) {
fa4aa2d4 2133 pm_runtime_get_sync(host->dev);
11dd62a7 2134
2bec0893
AH		 2135 if (host->got_dbclk)
2136 clk_enable(host->dbclk);
2137
31f9d463
EP		 2138 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2139 omap_hsmmc_conf_bus_power(host);
1b331e69 2140
a45c6cb8
MC		 2141 if (host->pdata->resume) {
2142 ret = host->pdata->resume(&pdev->dev, host->slot_id);
2143 if (ret)
2144 dev_dbg(mmc_dev(host->mmc),
2145 "Unmask interrupt failed\n");
2146 }
2147
b62f6228
AH		 2148 omap_hsmmc_protect_card(host);
2149
a45c6cb8
MC		 2150 /* Notify the core to resume the host */
2151 ret = mmc_resume_host(host->mmc);
2152 if (ret == 0)
2153 host->suspended = 0;
fa4aa2d4
B		 2154
2155 pm_runtime_mark_last_busy(host->dev);
2156 pm_runtime_put_autosuspend(host->dev);
a45c6cb8
MC		 2157 }
2158
2159 return ret;
2160
a45c6cb8
MC		 2161}
2162
2163#else
70a3341a
DK		 2164#define omap_hsmmc_suspend NULL
2165#define omap_hsmmc_resume NULL
a45c6cb8
MC		 2166#endif
2167
fa4aa2d4
B		 2168static int omap_hsmmc_runtime_suspend(struct device *dev)
2169{
2170 struct omap_hsmmc_host *host;
2171
2172 host = platform_get_drvdata(to_platform_device(dev));
2173 omap_hsmmc_context_save(host);
2174 dev_dbg(mmc_dev(host->mmc), "disabled\n");
2175
2176 return 0;
2177}
2178
2179static int omap_hsmmc_runtime_resume(struct device *dev)
2180{
2181 struct omap_hsmmc_host *host;
2182
2183 host = platform_get_drvdata(to_platform_device(dev));
2184 omap_hsmmc_context_restore(host);
2185 dev_dbg(mmc_dev(host->mmc), "enabled\n");
2186
2187 return 0;
2188}
2189
a791daa1 2190static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
70a3341a
DK		 2191 .suspend = omap_hsmmc_suspend,
2192 .resume = omap_hsmmc_resume,
fa4aa2d4
B		 2193 .runtime_suspend = omap_hsmmc_runtime_suspend,
2194 .runtime_resume = omap_hsmmc_runtime_resume,
a791daa1
KH		 2195};
2196
2197static struct platform_driver omap_hsmmc_driver = {
2198 .remove = omap_hsmmc_remove,
a45c6cb8
MC		 2199 .driver = {
2200 .name = DRIVER_NAME,
2201 .owner = THIS_MODULE,
a791daa1 2202 .pm = &omap_hsmmc_dev_pm_ops,
a45c6cb8
MC		 2203 },
2204};
2205
70a3341a 2206static int __init omap_hsmmc_init(void)
a45c6cb8
MC		 2207{
2208 /* Register the MMC driver */
8753298a 2209 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
a45c6cb8
MC		 2210}
2211
70a3341a 2212static void __exit omap_hsmmc_cleanup(void)
a45c6cb8
MC		 2213{
2214 /* Unregister MMC driver */
70a3341a 2215 platform_driver_unregister(&omap_hsmmc_driver);
a45c6cb8
MC		 2216}
2217
70a3341a
DK		 2218module_init(omap_hsmmc_init);
2219module_exit(omap_hsmmc_cleanup);
a45c6cb8
MC		 2220
2221MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2222MODULE_LICENSE("GPL");
2223MODULE_ALIAS("platform:" DRIVER_NAME);
2224MODULE_AUTHOR("Texas Instruments Inc");
Linux kernel - Deliverables
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