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mmc: omap_hsmmc: introduce start_clock and re-use stop_clock
[deliverable/linux.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
ac330f44 20#include <linux/kernel.h>
d900f712
DK		 21#include <linux/debugfs.h>
22#include <linux/seq_file.h>
a45c6cb8
MC		 23#include <linux/interrupt.h>
24#include <linux/delay.h>
25#include <linux/dma-mapping.h>
26#include <linux/platform_device.h>
27#include <linux/workqueue.h>
28#include <linux/timer.h>
29#include <linux/clk.h>
30#include <linux/mmc/host.h>
13189e78 31#include <linux/mmc/core.h>
93caf8e6 32#include <linux/mmc/mmc.h>
a45c6cb8
MC		 33#include <linux/io.h>
34#include <linux/semaphore.h>
db0fefc5
AH		 35#include <linux/gpio.h>
36#include <linux/regulator/consumer.h>
fa4aa2d4 37#include <linux/pm_runtime.h>
ce491cf8 38#include <plat/dma.h>
a45c6cb8 39#include <mach/hardware.h>
ce491cf8
TL		 40#include <plat/board.h>
41#include <plat/mmc.h>
42#include <plat/cpu.h>
a45c6cb8
MC		 43
44/* OMAP HSMMC Host Controller Registers */
45#define OMAP_HSMMC_SYSCONFIG 0x0010
11dd62a7 46#define OMAP_HSMMC_SYSSTATUS 0x0014
a45c6cb8
MC		 47#define OMAP_HSMMC_CON 0x002C
48#define OMAP_HSMMC_BLK 0x0104
49#define OMAP_HSMMC_ARG 0x0108
50#define OMAP_HSMMC_CMD 0x010C
51#define OMAP_HSMMC_RSP10 0x0110
52#define OMAP_HSMMC_RSP32 0x0114
53#define OMAP_HSMMC_RSP54 0x0118
54#define OMAP_HSMMC_RSP76 0x011C
55#define OMAP_HSMMC_DATA 0x0120
56#define OMAP_HSMMC_HCTL 0x0128
57#define OMAP_HSMMC_SYSCTL 0x012C
58#define OMAP_HSMMC_STAT 0x0130
59#define OMAP_HSMMC_IE 0x0134
60#define OMAP_HSMMC_ISE 0x0138
61#define OMAP_HSMMC_CAPA 0x0140
62
63#define VS18 (1 << 26)
64#define VS30 (1 << 25)
65#define SDVS18 (0x5 << 9)
66#define SDVS30 (0x6 << 9)
eb250826 67#define SDVS33 (0x7 << 9)
1b331e69 68#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 69#define SDVSCLR 0xFFFFF1FF
70#define SDVSDET 0x00000400
71#define AUTOIDLE 0x1
72#define SDBP (1 << 8)
73#define DTO 0xe
74#define ICE 0x1
75#define ICS 0x2
76#define CEN (1 << 2)
77#define CLKD_MASK 0x0000FFC0
78#define CLKD_SHIFT 6
79#define DTO_MASK 0x000F0000
80#define DTO_SHIFT 16
81#define INT_EN_MASK 0x307F0033
ccdfe3a6
AG		 82#define BWR_ENABLE (1 << 4)
83#define BRR_ENABLE (1 << 5)
93caf8e6 84#define DTO_ENABLE (1 << 20)
a45c6cb8
MC		 85#define INIT_STREAM (1 << 1)
86#define DP_SELECT (1 << 21)
87#define DDIR (1 << 4)
88#define DMA_EN 0x1
89#define MSBS (1 << 5)
90#define BCE (1 << 1)
91#define FOUR_BIT (1 << 1)
73153010 92#define DW8 (1 << 5)
a45c6cb8
MC		 93#define CC 0x1
94#define TC 0x02
95#define OD 0x1
96#define ERR (1 << 15)
97#define CMD_TIMEOUT (1 << 16)
98#define DATA_TIMEOUT (1 << 20)
99#define CMD_CRC (1 << 17)
100#define DATA_CRC (1 << 21)
101#define CARD_ERR (1 << 28)
102#define STAT_CLEAR 0xFFFFFFFF
103#define INIT_STREAM_CMD 0x00000000
104#define DUAL_VOLT_OCR_BIT 7
105#define SRC (1 << 25)
106#define SRD (1 << 26)
11dd62a7
DK		 107#define SOFTRESET (1 << 1)
108#define RESETDONE (1 << 0)
a45c6cb8
MC		 109
110/*
111 * FIXME: Most likely all the data using these _DEVID defines should come
112 * from the platform_data, or implemented in controller and slot specific
113 * functions.
114 */
115#define OMAP_MMC1_DEVID 0
116#define OMAP_MMC2_DEVID 1
f3e2f1dd 117#define OMAP_MMC3_DEVID 2
82cf818d 118#define OMAP_MMC4_DEVID 3
119#define OMAP_MMC5_DEVID 4
a45c6cb8 120
fa4aa2d4 121#define MMC_AUTOSUSPEND_DELAY 100
a45c6cb8
MC		 122#define MMC_TIMEOUT_MS 20
123#define OMAP_MMC_MASTER_CLOCK 96000000
6b206efe
AS		 124#define OMAP_MMC_MIN_CLOCK 400000
125#define OMAP_MMC_MAX_CLOCK 52000000
0005ae73 126#define DRIVER_NAME "omap_hsmmc"
a45c6cb8
MC		 127
128/*
129 * One controller can have multiple slots, like on some omap boards using
130 * omap.c controller driver. Luckily this is not currently done on any known
131 * omap_hsmmc.c device.
132 */
133#define mmc_slot(host) (host->pdata->slots[host->slot_id])
134
135/*
136 * MMC Host controller read/write API's
137 */
138#define OMAP_HSMMC_READ(base, reg) \
139 __raw_readl((base) + OMAP_HSMMC_##reg)
140
141#define OMAP_HSMMC_WRITE(base, reg, val) \
142 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
143
9782aff8
PF		 144struct omap_hsmmc_next {
145 unsigned int dma_len;
146 s32 cookie;
147};
148
70a3341a 149struct omap_hsmmc_host {
a45c6cb8
MC		 150 struct device *dev;
151 struct mmc_host *mmc;
152 struct mmc_request *mrq;
153 struct mmc_command *cmd;
154 struct mmc_data *data;
155 struct clk *fclk;
a45c6cb8 156 struct clk *dbclk;
db0fefc5
AH		 157 /*
158 * vcc == configured supply
159 * vcc_aux == optional
160 * - MMC1, supply for DAT4..DAT7
161 * - MMC2/MMC2, external level shifter voltage supply, for
162 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
163 */
164 struct regulator *vcc;
165 struct regulator *vcc_aux;
a45c6cb8
MC		 166 struct work_struct mmc_carddetect_work;
167 void __iomem *base;
168 resource_size_t mapbase;
4dffd7a2 169 spinlock_t irq_lock; /* Prevent races with irq handler */
a45c6cb8
MC		 170 unsigned int id;
171 unsigned int dma_len;
0ccd76d4 172 unsigned int dma_sg_idx;
a45c6cb8 173 unsigned char bus_mode;
a3621465 174 unsigned char power_mode;
a45c6cb8
MC		 175 u32 *buffer;
176 u32 bytesleft;
177 int suspended;
178 int irq;
a45c6cb8 179 int use_dma, dma_ch;
f3e2f1dd 180 int dma_line_tx, dma_line_rx;
a45c6cb8 181 int slot_id;
2bec0893 182 int got_dbclk;
4a694dc9 183 int response_busy;
11dd62a7 184 int context_loss;
dd498eff 185 int dpm_state;
623821f7 186 int vdd;
b62f6228
AH		 187 int protect_card;
188 int reqs_blocked;
db0fefc5 189 int use_reg;
b417577d 190 int req_in_progress;
9782aff8 191 struct omap_hsmmc_next next_data;
11dd62a7 192
a45c6cb8
MC		 193 struct omap_mmc_platform_data *pdata;
194};
195
db0fefc5
AH		 196static int omap_hsmmc_card_detect(struct device *dev, int slot)
197{
198 struct omap_mmc_platform_data *mmc = dev->platform_data;
199
200 /* NOTE: assumes card detect signal is active-low */
201 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
202}
203
204static int omap_hsmmc_get_wp(struct device *dev, int slot)
205{
206 struct omap_mmc_platform_data *mmc = dev->platform_data;
207
208 /* NOTE: assumes write protect signal is active-high */
209 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
210}
211
212static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
213{
214 struct omap_mmc_platform_data *mmc = dev->platform_data;
215
216 /* NOTE: assumes card detect signal is active-low */
217 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
218}
219
220#ifdef CONFIG_PM
221
222static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
223{
224 struct omap_mmc_platform_data *mmc = dev->platform_data;
225
226 disable_irq(mmc->slots[0].card_detect_irq);
227 return 0;
228}
229
230static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
231{
232 struct omap_mmc_platform_data *mmc = dev->platform_data;
233
234 enable_irq(mmc->slots[0].card_detect_irq);
235 return 0;
236}
237
238#else
239
240#define omap_hsmmc_suspend_cdirq NULL
241#define omap_hsmmc_resume_cdirq NULL
242
243#endif
244
b702b106
AH		 245#ifdef CONFIG_REGULATOR
246
db0fefc5
AH		 247static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
248 int vdd)
249{
250 struct omap_hsmmc_host *host =
251 platform_get_drvdata(to_platform_device(dev));
252 int ret;
253
254 if (mmc_slot(host).before_set_reg)
255 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
256
257 if (power_on)
99fc5131 258 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5 259 else
99fc5131 260 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
db0fefc5
AH		 261
262 if (mmc_slot(host).after_set_reg)
263 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
264
265 return ret;
266}
267
7715db5a 268static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on,
db0fefc5
AH		 269 int vdd)
270{
271 struct omap_hsmmc_host *host =
272 platform_get_drvdata(to_platform_device(dev));
273 int ret = 0;
274
275 /*
276 * If we don't see a Vcc regulator, assume it's a fixed
277 * voltage always-on regulator.
278 */
279 if (!host->vcc)
280 return 0;
281
282 if (mmc_slot(host).before_set_reg)
283 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
284
285 /*
286 * Assume Vcc regulator is used only to power the card ... OMAP
287 * VDDS is used to power the pins, optionally with a transceiver to
288 * support cards using voltages other than VDDS (1.8V nominal). When a
289 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
290 *
291 * In some cases this regulator won't support enable/disable;
292 * e.g. it's a fixed rail for a WLAN chip.
293 *
294 * In other cases vcc_aux switches interface power. Example, for
295 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
296 * chips/cards need an interface voltage rail too.
297 */
298 if (power_on) {
99fc5131 299 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5
AH		 300 /* Enable interface voltage rail, if needed */
301 if (ret == 0 && host->vcc_aux) {
302 ret = regulator_enable(host->vcc_aux);
303 if (ret < 0)
99fc5131
LW		 304 ret = mmc_regulator_set_ocr(host->mmc,
305 host->vcc, 0);
db0fefc5
AH		 306 }
307 } else {
99fc5131 308 /* Shut down the rail */
6da20c89
AH		 309 if (host->vcc_aux)
310 ret = regulator_disable(host->vcc_aux);
99fc5131
LW		 311 if (!ret) {
312 /* Then proceed to shut down the local regulator */
313 ret = mmc_regulator_set_ocr(host->mmc,
314 host->vcc, 0);
315 }
db0fefc5
AH		 316 }
317
318 if (mmc_slot(host).after_set_reg)
319 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
320
321 return ret;
322}
323
7715db5a
KK		 324static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on,
325 int vdd)
326{
327 return 0;
328}
329
db0fefc5
AH		 330static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
331 int vdd, int cardsleep)
332{
333 struct omap_hsmmc_host *host =
334 platform_get_drvdata(to_platform_device(dev));
335 int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
336
337 return regulator_set_mode(host->vcc, mode);
338}
339
7715db5a 340static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep,
db0fefc5
AH		 341 int vdd, int cardsleep)
342{
343 struct omap_hsmmc_host *host =
344 platform_get_drvdata(to_platform_device(dev));
345 int err, mode;
346
347 /*
348 * If we don't see a Vcc regulator, assume it's a fixed
349 * voltage always-on regulator.
350 */
351 if (!host->vcc)
352 return 0;
353
354 mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
355
356 if (!host->vcc_aux)
357 return regulator_set_mode(host->vcc, mode);
358
359 if (cardsleep) {
360 /* VCC can be turned off if card is asleep */
361 if (sleep)
99fc5131 362 err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
db0fefc5 363 else
99fc5131 364 err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5
AH		 365 } else
366 err = regulator_set_mode(host->vcc, mode);
367 if (err)
368 return err;
e0eb2424
AH		 369
370 if (!mmc_slot(host).vcc_aux_disable_is_sleep)
371 return regulator_set_mode(host->vcc_aux, mode);
372
373 if (sleep)
374 return regulator_disable(host->vcc_aux);
375 else
376 return regulator_enable(host->vcc_aux);
db0fefc5
AH		 377}
378
7715db5a
KK		 379static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep,
380 int vdd, int cardsleep)
381{
382 return 0;
383}
384
db0fefc5
AH		 385static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
386{
387 struct regulator *reg;
388 int ret = 0;
64be9782 389 int ocr_value = 0;
db0fefc5
AH		 390
391 switch (host->id) {
392 case OMAP_MMC1_DEVID:
393 /* On-chip level shifting via PBIAS0/PBIAS1 */
394 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
395 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
396 break;
397 case OMAP_MMC2_DEVID:
398 case OMAP_MMC3_DEVID:
7715db5a 399 case OMAP_MMC5_DEVID:
db0fefc5 400 /* Off-chip level shifting, or none */
7715db5a
KK		 401 mmc_slot(host).set_power = omap_hsmmc_235_set_power;
402 mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep;
db0fefc5 403 break;
7715db5a
KK		 404 case OMAP_MMC4_DEVID:
405 mmc_slot(host).set_power = omap_hsmmc_4_set_power;
406 mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep;
db0fefc5
AH		 407 default:
408 pr_err("MMC%d configuration not supported!\n", host->id);
409 return -EINVAL;
410 }
411
412 reg = regulator_get(host->dev, "vmmc");
413 if (IS_ERR(reg)) {
414 dev_dbg(host->dev, "vmmc regulator missing\n");
415 /*
416 * HACK: until fixed.c regulator is usable,
417 * we don't require a main regulator
418 * for MMC2 or MMC3
419 */
420 if (host->id == OMAP_MMC1_DEVID) {
421 ret = PTR_ERR(reg);
422 goto err;
423 }
424 } else {
425 host->vcc = reg;
64be9782 426 ocr_value = mmc_regulator_get_ocrmask(reg);
427 if (!mmc_slot(host).ocr_mask) {
428 mmc_slot(host).ocr_mask = ocr_value;
429 } else {
430 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
431 pr_err("MMC%d ocrmask %x is not supported\n",
432 host->id, mmc_slot(host).ocr_mask);
433 mmc_slot(host).ocr_mask = 0;
434 return -EINVAL;
435 }
436 }
db0fefc5
AH		 437
438 /* Allow an aux regulator */
439 reg = regulator_get(host->dev, "vmmc_aux");
440 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
441
b1c1df7a
B		 442 /* For eMMC do not power off when not in sleep state */
443 if (mmc_slot(host).no_regulator_off_init)
444 return 0;
db0fefc5
AH		 445 /*
446 * UGLY HACK: workaround regulator framework bugs.
447 * When the bootloader leaves a supply active, it's
448 * initialized with zero usecount ... and we can't
449 * disable it without first enabling it. Until the
450 * framework is fixed, we need a workaround like this
451 * (which is safe for MMC, but not in general).
452 */
453 if (regulator_is_enabled(host->vcc) > 0) {
454 regulator_enable(host->vcc);
455 regulator_disable(host->vcc);
456 }
457 if (host->vcc_aux) {
458 if (regulator_is_enabled(reg) > 0) {
459 regulator_enable(reg);
460 regulator_disable(reg);
461 }
462 }
463 }
464
465 return 0;
466
467err:
468 mmc_slot(host).set_power = NULL;
469 mmc_slot(host).set_sleep = NULL;
470 return ret;
471}
472
473static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
474{
475 regulator_put(host->vcc);
476 regulator_put(host->vcc_aux);
477 mmc_slot(host).set_power = NULL;
478 mmc_slot(host).set_sleep = NULL;
479}
480
b702b106
AH		 481static inline int omap_hsmmc_have_reg(void)
482{
483 return 1;
484}
485
486#else
487
488static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
489{
490 return -EINVAL;
491}
492
493static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
494{
495}
496
497static inline int omap_hsmmc_have_reg(void)
498{
499 return 0;
500}
501
502#endif
503
504static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
505{
506 int ret;
507
508 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
b702b106
AH		 509 if (pdata->slots[0].cover)
510 pdata->slots[0].get_cover_state =
511 omap_hsmmc_get_cover_state;
512 else
513 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
514 pdata->slots[0].card_detect_irq =
515 gpio_to_irq(pdata->slots[0].switch_pin);
516 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
517 if (ret)
518 return ret;
519 ret = gpio_direction_input(pdata->slots[0].switch_pin);
520 if (ret)
521 goto err_free_sp;
522 } else
523 pdata->slots[0].switch_pin = -EINVAL;
524
525 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
526 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
527 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
528 if (ret)
529 goto err_free_cd;
530 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
531 if (ret)
532 goto err_free_wp;
533 } else
534 pdata->slots[0].gpio_wp = -EINVAL;
535
536 return 0;
537
538err_free_wp:
539 gpio_free(pdata->slots[0].gpio_wp);
540err_free_cd:
541 if (gpio_is_valid(pdata->slots[0].switch_pin))
542err_free_sp:
543 gpio_free(pdata->slots[0].switch_pin);
544 return ret;
545}
546
547static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
548{
549 if (gpio_is_valid(pdata->slots[0].gpio_wp))
550 gpio_free(pdata->slots[0].gpio_wp);
551 if (gpio_is_valid(pdata->slots[0].switch_pin))
552 gpio_free(pdata->slots[0].switch_pin);
553}
554
e0c7f99b
AS		 555/*
556 * Start clock to the card
557 */
558static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
559{
560 OMAP_HSMMC_WRITE(host->base, SYSCTL,
561 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
562}
563
a45c6cb8
MC		 564/*
565 * Stop clock to the card
566 */
70a3341a 567static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
a45c6cb8
MC		 568{
569 OMAP_HSMMC_WRITE(host->base, SYSCTL,
570 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
571 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
572 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
573}
574
93caf8e6
AH		 575static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
576 struct mmc_command *cmd)
b417577d
AH		 577{
578 unsigned int irq_mask;
579
580 if (host->use_dma)
581 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
582 else
583 irq_mask = INT_EN_MASK;
584
93caf8e6
AH		 585 /* Disable timeout for erases */
586 if (cmd->opcode == MMC_ERASE)
587 irq_mask &= ~DTO_ENABLE;
588
b417577d
AH		 589 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
590 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
591 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
592}
593
594static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
595{
596 OMAP_HSMMC_WRITE(host->base, ISE, 0);
597 OMAP_HSMMC_WRITE(host->base, IE, 0);
598 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
599}
600
ac330f44
AS		 601/* Calculate divisor for the given clock frequency */
602static u16 calc_divisor(struct mmc_ios *ios)
603{
604 u16 dsor = 0;
605
606 if (ios->clock) {
607 dsor = DIV_ROUND_UP(OMAP_MMC_MASTER_CLOCK, ios->clock);
608 if (dsor > 250)
609 dsor = 250;
610 }
611
612 return dsor;
613}
614
11dd62a7
DK		 615#ifdef CONFIG_PM
616
617/*
618 * Restore the MMC host context, if it was lost as result of a
619 * power state change.
620 */
70a3341a 621static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 622{
623 struct mmc_ios *ios = &host->mmc->ios;
624 struct omap_mmc_platform_data *pdata = host->pdata;
625 int context_loss = 0;
626 u32 hctl, capa, con;
11dd62a7
DK		 627 unsigned long timeout;
628
629 if (pdata->get_context_loss_count) {
630 context_loss = pdata->get_context_loss_count(host->dev);
631 if (context_loss < 0)
632 return 1;
633 }
634
635 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
636 context_loss == host->context_loss ? "not " : "");
637 if (host->context_loss == context_loss)
638 return 1;
639
640 /* Wait for hardware reset */
641 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
642 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
643 && time_before(jiffies, timeout))
644 ;
645
646 /* Do software reset */
647 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
648 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
649 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
650 && time_before(jiffies, timeout))
651 ;
652
653 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
654 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
655
656 if (host->id == OMAP_MMC1_DEVID) {
657 if (host->power_mode != MMC_POWER_OFF &&
658 (1 << ios->vdd) <= MMC_VDD_23_24)
659 hctl = SDVS18;
660 else
661 hctl = SDVS30;
662 capa = VS30 | VS18;
663 } else {
664 hctl = SDVS18;
665 capa = VS18;
666 }
667
668 OMAP_HSMMC_WRITE(host->base, HCTL,
669 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
670
671 OMAP_HSMMC_WRITE(host->base, CAPA,
672 OMAP_HSMMC_READ(host->base, CAPA) | capa);
673
674 OMAP_HSMMC_WRITE(host->base, HCTL,
675 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
676
677 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
678 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
679 && time_before(jiffies, timeout))
680 ;
681
b417577d 682 omap_hsmmc_disable_irq(host);
11dd62a7
DK		 683
684 /* Do not initialize card-specific things if the power is off */
685 if (host->power_mode == MMC_POWER_OFF)
686 goto out;
687
688 con = OMAP_HSMMC_READ(host->base, CON);
689 switch (ios->bus_width) {
690 case MMC_BUS_WIDTH_8:
691 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
692 break;
693 case MMC_BUS_WIDTH_4:
694 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
695 OMAP_HSMMC_WRITE(host->base, HCTL,
696 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
697 break;
698 case MMC_BUS_WIDTH_1:
699 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
700 OMAP_HSMMC_WRITE(host->base, HCTL,
701 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
702 break;
703 }
704
e0c7f99b
AS		 705 omap_hsmmc_stop_clock(host);
706
ac330f44
AS		 707 OMAP_HSMMC_WRITE(host->base, SYSCTL,
708 (calc_divisor(ios) << 6) | (DTO << 16));
11dd62a7
DK		 709 OMAP_HSMMC_WRITE(host->base, SYSCTL,
710 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
711
712 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
713 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
714 && time_before(jiffies, timeout))
715 ;
716
e0c7f99b 717 omap_hsmmc_start_clock(host);
11dd62a7
DK		 718
719 con = OMAP_HSMMC_READ(host->base, CON);
720 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
721 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
722 else
723 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
724out:
725 host->context_loss = context_loss;
726
727 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
728 return 0;
729}
730
731/*
732 * Save the MMC host context (store the number of power state changes so far).
733 */
70a3341a 734static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 735{
736 struct omap_mmc_platform_data *pdata = host->pdata;
737 int context_loss;
738
739 if (pdata->get_context_loss_count) {
740 context_loss = pdata->get_context_loss_count(host->dev);
741 if (context_loss < 0)
742 return;
743 host->context_loss = context_loss;
744 }
745}
746
747#else
748
70a3341a 749static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 750{
751 return 0;
752}
753
70a3341a 754static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 755{
756}
757
758#endif
759
a45c6cb8
MC		 760/*
761 * Send init stream sequence to card
762 * before sending IDLE command
763 */
70a3341a 764static void send_init_stream(struct omap_hsmmc_host *host)
a45c6cb8
MC		 765{
766 int reg = 0;
767 unsigned long timeout;
768
b62f6228
AH		 769 if (host->protect_card)
770 return;
771
a45c6cb8 772 disable_irq(host->irq);
b417577d
AH		 773
774 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8
MC		 775 OMAP_HSMMC_WRITE(host->base, CON,
776 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
777 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
778
779 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
780 while ((reg != CC) && time_before(jiffies, timeout))
781 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
782
783 OMAP_HSMMC_WRITE(host->base, CON,
784 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
c653a6d4
AH		 785
786 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
787 OMAP_HSMMC_READ(host->base, STAT);
788
a45c6cb8
MC		 789 enable_irq(host->irq);
790}
791
792static inline
70a3341a 793int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
a45c6cb8
MC		 794{
795 int r = 1;
796
191d1f1d
DK		 797 if (mmc_slot(host).get_cover_state)
798 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
a45c6cb8
MC		 799 return r;
800}
801
802static ssize_t
70a3341a 803omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 804 char *buf)
805{
806 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 807 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 808
70a3341a
DK		 809 return sprintf(buf, "%s\n",
810 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
a45c6cb8
MC		 811}
812
70a3341a 813static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
a45c6cb8
MC		 814
815static ssize_t
70a3341a 816omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 817 char *buf)
818{
819 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 820 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 821
191d1f1d 822 return sprintf(buf, "%s\n", mmc_slot(host).name);
a45c6cb8
MC		 823}
824
70a3341a 825static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
a45c6cb8
MC		 826
827/*
828 * Configure the response type and send the cmd.
829 */
830static void
70a3341a 831omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
a45c6cb8
MC		 832 struct mmc_data *data)
833{
834 int cmdreg = 0, resptype = 0, cmdtype = 0;
835
836 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
837 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
838 host->cmd = cmd;
839
93caf8e6 840 omap_hsmmc_enable_irq(host, cmd);
a45c6cb8 841
4a694dc9 842 host->response_busy = 0;
a45c6cb8
MC		 843 if (cmd->flags & MMC_RSP_PRESENT) {
844 if (cmd->flags & MMC_RSP_136)
845 resptype = 1;
4a694dc9
AH		 846 else if (cmd->flags & MMC_RSP_BUSY) {
847 resptype = 3;
848 host->response_busy = 1;
849 } else
a45c6cb8
MC		 850 resptype = 2;
851 }
852
853 /*
854 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
855 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
856 * a val of 0x3, rest 0x0.
857 */
858 if (cmd == host->mrq->stop)
859 cmdtype = 0x3;
860
861 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
862
863 if (data) {
864 cmdreg |= DP_SELECT | MSBS | BCE;
865 if (data->flags & MMC_DATA_READ)
866 cmdreg |= DDIR;
867 else
868 cmdreg &= ~(DDIR);
869 }
870
871 if (host->use_dma)
872 cmdreg |= DMA_EN;
873
b417577d 874 host->req_in_progress = 1;
4dffd7a2 875
a45c6cb8
MC		 876 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
877 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
878}
879
0ccd76d4 880static int
70a3341a 881omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
0ccd76d4
JY		 882{
883 if (data->flags & MMC_DATA_WRITE)
884 return DMA_TO_DEVICE;
885 else
886 return DMA_FROM_DEVICE;
887}
888
b417577d
AH		 889static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
890{
891 int dma_ch;
892
893 spin_lock(&host->irq_lock);
894 host->req_in_progress = 0;
895 dma_ch = host->dma_ch;
896 spin_unlock(&host->irq_lock);
897
898 omap_hsmmc_disable_irq(host);
899 /* Do not complete the request if DMA is still in progress */
900 if (mrq->data && host->use_dma && dma_ch != -1)
901 return;
902 host->mrq = NULL;
903 mmc_request_done(host->mmc, mrq);
904}
905
a45c6cb8
MC		 906/*
907 * Notify the transfer complete to MMC core
908 */
909static void
70a3341a 910omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
a45c6cb8 911{
4a694dc9
AH		 912 if (!data) {
913 struct mmc_request *mrq = host->mrq;
914
23050103
AH		 915 /* TC before CC from CMD6 - don't know why, but it happens */
916 if (host->cmd && host->cmd->opcode == 6 &&
917 host->response_busy) {
918 host->response_busy = 0;
919 return;
920 }
921
b417577d 922 omap_hsmmc_request_done(host, mrq);
4a694dc9
AH		 923 return;
924 }
925
a45c6cb8
MC		 926 host->data = NULL;
927
a45c6cb8
MC		 928 if (!data->error)
929 data->bytes_xfered += data->blocks * (data->blksz);
930 else
931 data->bytes_xfered = 0;
932
933 if (!data->stop) {
b417577d 934 omap_hsmmc_request_done(host, data->mrq);
a45c6cb8
MC		 935 return;
936 }
70a3341a 937 omap_hsmmc_start_command(host, data->stop, NULL);
a45c6cb8
MC		 938}
939
940/*
941 * Notify the core about command completion
942 */
943static void
70a3341a 944omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
a45c6cb8
MC		 945{
946 host->cmd = NULL;
947
948 if (cmd->flags & MMC_RSP_PRESENT) {
949 if (cmd->flags & MMC_RSP_136) {
950 /* response type 2 */
951 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
952 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
953 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
954 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
955 } else {
956 /* response types 1, 1b, 3, 4, 5, 6 */
957 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
958 }
959 }
b417577d
AH		 960 if ((host->data == NULL && !host->response_busy) || cmd->error)
961 omap_hsmmc_request_done(host, cmd->mrq);
a45c6cb8
MC		 962}
963
964/*
965 * DMA clean up for command errors
966 */
70a3341a 967static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
a45c6cb8 968{
b417577d
AH		 969 int dma_ch;
970
82788ff5 971 host->data->error = errno;
a45c6cb8 972
b417577d
AH		 973 spin_lock(&host->irq_lock);
974 dma_ch = host->dma_ch;
975 host->dma_ch = -1;
976 spin_unlock(&host->irq_lock);
977
978 if (host->use_dma && dma_ch != -1) {
a9120c33
PF		 979 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
980 host->data->sg_len,
70a3341a 981 omap_hsmmc_get_dma_dir(host, host->data));
b417577d 982 omap_free_dma(dma_ch);
a45c6cb8
MC		 983 }
984 host->data = NULL;
a45c6cb8
MC		 985}
986
987/*
988 * Readable error output
989 */
990#ifdef CONFIG_MMC_DEBUG
699b958b 991static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
a45c6cb8
MC		 992{
993 /* --- means reserved bit without definition at documentation */
70a3341a 994 static const char *omap_hsmmc_status_bits[] = {
699b958b
AH		 995 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
996 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
997 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
998 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
a45c6cb8
MC		 999 };
1000 char res[256];
1001 char *buf = res;
1002 int len, i;
1003
1004 len = sprintf(buf, "MMC IRQ 0x%x :", status);
1005 buf += len;
1006
70a3341a 1007 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
a45c6cb8 1008 if (status & (1 << i)) {
70a3341a 1009 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
a45c6cb8
MC		 1010 buf += len;
1011 }
1012
1013 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
1014}
699b958b
AH		 1015#else
1016static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1017 u32 status)
1018{
1019}
a45c6cb8
MC		 1020#endif /* CONFIG_MMC_DEBUG */
1021
3ebf74b1
JP		 1022/*
1023 * MMC controller internal state machines reset
1024 *
1025 * Used to reset command or data internal state machines, using respectively
1026 * SRC or SRD bit of SYSCTL register
1027 * Can be called from interrupt context
1028 */
70a3341a
DK		 1029static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1030 unsigned long bit)
3ebf74b1
JP		 1031{
1032 unsigned long i = 0;
1033 unsigned long limit = (loops_per_jiffy *
1034 msecs_to_jiffies(MMC_TIMEOUT_MS));
1035
1036 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1037 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1038
07ad64b6
MC		 1039 /*
1040 * OMAP4 ES2 and greater has an updated reset logic.
1041 * Monitor a 0->1 transition first
1042 */
1043 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
b432b4b3 1044 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
07ad64b6
MC		 1045 && (i++ < limit))
1046 cpu_relax();
1047 }
1048 i = 0;
1049
3ebf74b1
JP		 1050 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1051 (i++ < limit))
1052 cpu_relax();
1053
1054 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1055 dev_err(mmc_dev(host->mmc),
1056 "Timeout waiting on controller reset in %s\n",
1057 __func__);
1058}
a45c6cb8 1059
b417577d 1060static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
a45c6cb8 1061{
a45c6cb8 1062 struct mmc_data *data;
b417577d
AH		 1063 int end_cmd = 0, end_trans = 0;
1064
1065 if (!host->req_in_progress) {
1066 do {
1067 OMAP_HSMMC_WRITE(host->base, STAT, status);
1068 /* Flush posted write */
1069 status = OMAP_HSMMC_READ(host->base, STAT);
1070 } while (status & INT_EN_MASK);
1071 return;
a45c6cb8
MC		 1072 }
1073
1074 data = host->data;
a45c6cb8
MC		 1075 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1076
1077 if (status & ERR) {
699b958b 1078 omap_hsmmc_dbg_report_irq(host, status);
a45c6cb8
MC		 1079 if ((status & CMD_TIMEOUT) ||
1080 (status & CMD_CRC)) {
1081 if (host->cmd) {
1082 if (status & CMD_TIMEOUT) {
70a3341a
DK		 1083 omap_hsmmc_reset_controller_fsm(host,
1084 SRC);
a45c6cb8
MC		 1085 host->cmd->error = -ETIMEDOUT;
1086 } else {
1087 host->cmd->error = -EILSEQ;
1088 }
1089 end_cmd = 1;
1090 }
4a694dc9
AH		 1091 if (host->data || host->response_busy) {
1092 if (host->data)
70a3341a
DK		 1093 omap_hsmmc_dma_cleanup(host,
1094 -ETIMEDOUT);
4a694dc9 1095 host->response_busy = 0;
70a3341a 1096 omap_hsmmc_reset_controller_fsm(host, SRD);
c232f457 1097 }
a45c6cb8
MC		 1098 }
1099 if ((status & DATA_TIMEOUT) ||
1100 (status & DATA_CRC)) {
4a694dc9
AH		 1101 if (host->data || host->response_busy) {
1102 int err = (status & DATA_TIMEOUT) ?
1103 -ETIMEDOUT : -EILSEQ;
1104
1105 if (host->data)
70a3341a 1106 omap_hsmmc_dma_cleanup(host, err);
a45c6cb8 1107 else
4a694dc9
AH		 1108 host->mrq->cmd->error = err;
1109 host->response_busy = 0;
70a3341a 1110 omap_hsmmc_reset_controller_fsm(host, SRD);
a45c6cb8
MC		 1111 end_trans = 1;
1112 }
1113 }
1114 if (status & CARD_ERR) {
1115 dev_dbg(mmc_dev(host->mmc),
1116 "Ignoring card err CMD%d\n", host->cmd->opcode);
1117 if (host->cmd)
1118 end_cmd = 1;
1119 if (host->data)
1120 end_trans = 1;
1121 }
1122 }
1123
1124 OMAP_HSMMC_WRITE(host->base, STAT, status);
1125
a8fe29d8 1126 if (end_cmd || ((status & CC) && host->cmd))
70a3341a 1127 omap_hsmmc_cmd_done(host, host->cmd);
0a40e647 1128 if ((end_trans || (status & TC)) && host->mrq)
70a3341a 1129 omap_hsmmc_xfer_done(host, data);
b417577d 1130}
a45c6cb8 1131
b417577d
AH		 1132/*
1133 * MMC controller IRQ handler
1134 */
1135static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1136{
1137 struct omap_hsmmc_host *host = dev_id;
1138 int status;
1139
1140 status = OMAP_HSMMC_READ(host->base, STAT);
1141 do {
1142 omap_hsmmc_do_irq(host, status);
1143 /* Flush posted write */
1144 status = OMAP_HSMMC_READ(host->base, STAT);
1145 } while (status & INT_EN_MASK);
4dffd7a2 1146
a45c6cb8
MC		 1147 return IRQ_HANDLED;
1148}
1149
70a3341a 1150static void set_sd_bus_power(struct omap_hsmmc_host *host)
e13bb300
AH		 1151{
1152 unsigned long i;
1153
1154 OMAP_HSMMC_WRITE(host->base, HCTL,
1155 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1156 for (i = 0; i < loops_per_jiffy; i++) {
1157 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1158 break;
1159 cpu_relax();
1160 }
1161}
1162
a45c6cb8 1163/*
eb250826
DB		 1164 * Switch MMC interface voltage ... only relevant for MMC1.
1165 *
1166 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1167 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1168 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8 1169 */
70a3341a 1170static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
a45c6cb8
MC		 1171{
1172 u32 reg_val = 0;
1173 int ret;
1174
1175 /* Disable the clocks */
fa4aa2d4 1176 pm_runtime_put_sync(host->dev);
2bec0893
AH		 1177 if (host->got_dbclk)
1178 clk_disable(host->dbclk);
a45c6cb8
MC		 1179
1180 /* Turn the power off */
1181 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
a45c6cb8
MC		 1182
1183 /* Turn the power ON with given VDD 1.8 or 3.0v */
2bec0893
AH		 1184 if (!ret)
1185 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1186 vdd);
fa4aa2d4 1187 pm_runtime_get_sync(host->dev);
2bec0893
AH		 1188 if (host->got_dbclk)
1189 clk_enable(host->dbclk);
1190
a45c6cb8
MC		 1191 if (ret != 0)
1192 goto err;
1193
a45c6cb8
MC		 1194 OMAP_HSMMC_WRITE(host->base, HCTL,
1195 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1196 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 1197
a45c6cb8
MC		 1198 /*
1199 * If a MMC dual voltage card is detected, the set_ios fn calls
1200 * this fn with VDD bit set for 1.8V. Upon card removal from the
70a3341a 1201 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
a45c6cb8 1202 *
eb250826
DB		 1203 * Cope with a bit of slop in the range ... per data sheets:
1204 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1205 * but recommended values are 1.71V to 1.89V
1206 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1207 * but recommended values are 2.7V to 3.3V
1208 *
1209 * Board setup code shouldn't permit anything very out-of-range.
1210 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1211 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 1212 */
eb250826 1213 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 1214 reg_val |= SDVS18;
eb250826
DB		 1215 else
1216 reg_val |= SDVS30;
a45c6cb8
MC		 1217
1218 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 1219 set_sd_bus_power(host);
a45c6cb8
MC		 1220
1221 return 0;
1222err:
1223 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1224 return ret;
1225}
1226
b62f6228
AH		 1227/* Protect the card while the cover is open */
1228static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1229{
1230 if (!mmc_slot(host).get_cover_state)
1231 return;
1232
1233 host->reqs_blocked = 0;
1234 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1235 if (host->protect_card) {
1236 printk(KERN_INFO "%s: cover is closed, "
1237 "card is now accessible\n",
1238 mmc_hostname(host->mmc));
1239 host->protect_card = 0;
1240 }
1241 } else {
1242 if (!host->protect_card) {
1243 printk(KERN_INFO "%s: cover is open, "
1244 "card is now inaccessible\n",
1245 mmc_hostname(host->mmc));
1246 host->protect_card = 1;
1247 }
1248 }
1249}
1250
a45c6cb8
MC		 1251/*
1252 * Work Item to notify the core about card insertion/removal
1253 */
70a3341a 1254static void omap_hsmmc_detect(struct work_struct *work)
a45c6cb8 1255{
70a3341a
DK		 1256 struct omap_hsmmc_host *host =
1257 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
249d0fa9 1258 struct omap_mmc_slot_data *slot = &mmc_slot(host);
a6b2240d
AH		 1259 int carddetect;
1260
1261 if (host->suspended)
1262 return;
1263
1264 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
249d0fa9 1265
191d1f1d 1266 if (slot->card_detect)
db0fefc5 1267 carddetect = slot->card_detect(host->dev, host->slot_id);
b62f6228
AH		 1268 else {
1269 omap_hsmmc_protect_card(host);
a6b2240d 1270 carddetect = -ENOSYS;
b62f6228 1271 }
a45c6cb8 1272
cdeebadd 1273 if (carddetect)
a45c6cb8 1274 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
cdeebadd 1275 else
a45c6cb8 1276 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
a45c6cb8
MC		 1277}
1278
1279/*
1280 * ISR for handling card insertion and removal
1281 */
70a3341a 1282static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
a45c6cb8 1283{
70a3341a 1284 struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
a45c6cb8 1285
a6b2240d
AH		 1286 if (host->suspended)
1287 return IRQ_HANDLED;
a45c6cb8
MC		 1288 schedule_work(&host->mmc_carddetect_work);
1289
1290 return IRQ_HANDLED;
1291}
1292
70a3341a 1293static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1294 struct mmc_data *data)
1295{
1296 int sync_dev;
1297
f3e2f1dd
GI		 1298 if (data->flags & MMC_DATA_WRITE)
1299 sync_dev = host->dma_line_tx;
1300 else
1301 sync_dev = host->dma_line_rx;
0ccd76d4
JY		 1302 return sync_dev;
1303}
1304
70a3341a 1305static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1306 struct mmc_data *data,
1307 struct scatterlist *sgl)
1308{
1309 int blksz, nblk, dma_ch;
1310
1311 dma_ch = host->dma_ch;
1312 if (data->flags & MMC_DATA_WRITE) {
1313 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1314 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1315 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1316 sg_dma_address(sgl), 0, 0);
1317 } else {
1318 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
191d1f1d 1319 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
0ccd76d4
JY		 1320 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1321 sg_dma_address(sgl), 0, 0);
1322 }
1323
1324 blksz = host->data->blksz;
1325 nblk = sg_dma_len(sgl) / blksz;
1326
1327 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1328 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
70a3341a 1329 omap_hsmmc_get_dma_sync_dev(host, data),
0ccd76d4
JY		 1330 !(data->flags & MMC_DATA_WRITE));
1331
1332 omap_start_dma(dma_ch);
1333}
1334
a45c6cb8
MC		 1335/*
1336 * DMA call back function
1337 */
b417577d 1338static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
a45c6cb8 1339{
b417577d
AH		 1340 struct omap_hsmmc_host *host = cb_data;
1341 struct mmc_data *data = host->mrq->data;
1342 int dma_ch, req_in_progress;
a45c6cb8 1343
f3584e5e
V		 1344 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1345 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1346 ch_status);
1347 return;
1348 }
a45c6cb8 1349
b417577d
AH		 1350 spin_lock(&host->irq_lock);
1351 if (host->dma_ch < 0) {
1352 spin_unlock(&host->irq_lock);
a45c6cb8 1353 return;
b417577d 1354 }
a45c6cb8 1355
0ccd76d4
JY		 1356 host->dma_sg_idx++;
1357 if (host->dma_sg_idx < host->dma_len) {
1358 /* Fire up the next transfer. */
b417577d
AH		 1359 omap_hsmmc_config_dma_params(host, data,
1360 data->sg + host->dma_sg_idx);
1361 spin_unlock(&host->irq_lock);
0ccd76d4
JY		 1362 return;
1363 }
1364
9782aff8
PF		 1365 if (!data->host_cookie)
1366 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1367 omap_hsmmc_get_dma_dir(host, data));
b417577d
AH		 1368
1369 req_in_progress = host->req_in_progress;
1370 dma_ch = host->dma_ch;
a45c6cb8 1371 host->dma_ch = -1;
b417577d
AH		 1372 spin_unlock(&host->irq_lock);
1373
1374 omap_free_dma(dma_ch);
1375
1376 /* If DMA has finished after TC, complete the request */
1377 if (!req_in_progress) {
1378 struct mmc_request *mrq = host->mrq;
1379
1380 host->mrq = NULL;
1381 mmc_request_done(host->mmc, mrq);
1382 }
a45c6cb8
MC		 1383}
1384
9782aff8
PF		 1385static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1386 struct mmc_data *data,
1387 struct omap_hsmmc_next *next)
1388{
1389 int dma_len;
1390
1391 if (!next && data->host_cookie &&
1392 data->host_cookie != host->next_data.cookie) {
1393 printk(KERN_WARNING "[%s] invalid cookie: data->host_cookie %d"
1394 " host->next_data.cookie %d\n",
1395 __func__, data->host_cookie, host->next_data.cookie);
1396 data->host_cookie = 0;
1397 }
1398
1399 /* Check if next job is already prepared */
1400 if (next ||
1401 (!next && data->host_cookie != host->next_data.cookie)) {
1402 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1403 data->sg_len,
1404 omap_hsmmc_get_dma_dir(host, data));
1405
1406 } else {
1407 dma_len = host->next_data.dma_len;
1408 host->next_data.dma_len = 0;
1409 }
1410
1411
1412 if (dma_len == 0)
1413 return -EINVAL;
1414
1415 if (next) {
1416 next->dma_len = dma_len;
1417 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1418 } else
1419 host->dma_len = dma_len;
1420
1421 return 0;
1422}
1423
a45c6cb8
MC		 1424/*
1425 * Routine to configure and start DMA for the MMC card
1426 */
70a3341a
DK		 1427static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1428 struct mmc_request *req)
a45c6cb8 1429{
b417577d 1430 int dma_ch = 0, ret = 0, i;
a45c6cb8
MC		 1431 struct mmc_data *data = req->data;
1432
0ccd76d4 1433 /* Sanity check: all the SG entries must be aligned by block size. */
a3f406f8 1434 for (i = 0; i < data->sg_len; i++) {
0ccd76d4
JY		 1435 struct scatterlist *sgl;
1436
1437 sgl = data->sg + i;
1438 if (sgl->length % data->blksz)
1439 return -EINVAL;
1440 }
1441 if ((data->blksz % 4) != 0)
1442 /* REVISIT: The MMC buffer increments only when MSB is written.
1443 * Return error for blksz which is non multiple of four.
1444 */
1445 return -EINVAL;
1446
b417577d 1447 BUG_ON(host->dma_ch != -1);
a45c6cb8 1448
70a3341a
DK		 1449 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1450 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
a45c6cb8 1451 if (ret != 0) {
0ccd76d4 1452 dev_err(mmc_dev(host->mmc),
a45c6cb8
MC		 1453 "%s: omap_request_dma() failed with %d\n",
1454 mmc_hostname(host->mmc), ret);
1455 return ret;
1456 }
9782aff8
PF		 1457 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1458 if (ret)
1459 return ret;
a45c6cb8 1460
a45c6cb8 1461 host->dma_ch = dma_ch;
0ccd76d4 1462 host->dma_sg_idx = 0;
a45c6cb8 1463
70a3341a 1464 omap_hsmmc_config_dma_params(host, data, data->sg);
a45c6cb8 1465
a45c6cb8
MC		 1466 return 0;
1467}
1468
70a3341a 1469static void set_data_timeout(struct omap_hsmmc_host *host,
e2bf08d6
AH		 1470 unsigned int timeout_ns,
1471 unsigned int timeout_clks)
a45c6cb8
MC		 1472{
1473 unsigned int timeout, cycle_ns;
1474 uint32_t reg, clkd, dto = 0;
1475
1476 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1477 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1478 if (clkd == 0)
1479 clkd = 1;
1480
1481 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
e2bf08d6
AH		 1482 timeout = timeout_ns / cycle_ns;
1483 timeout += timeout_clks;
a45c6cb8
MC		 1484 if (timeout) {
1485 while ((timeout & 0x80000000) == 0) {
1486 dto += 1;
1487 timeout <<= 1;
1488 }
1489 dto = 31 - dto;
1490 timeout <<= 1;
1491 if (timeout && dto)
1492 dto += 1;
1493 if (dto >= 13)
1494 dto -= 13;
1495 else
1496 dto = 0;
1497 if (dto > 14)
1498 dto = 14;
1499 }
1500
1501 reg &= ~DTO_MASK;
1502 reg |= dto << DTO_SHIFT;
1503 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1504}
1505
1506/*
1507 * Configure block length for MMC/SD cards and initiate the transfer.
1508 */
1509static int
70a3341a 1510omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
a45c6cb8
MC		 1511{
1512 int ret;
1513 host->data = req->data;
1514
1515 if (req->data == NULL) {
a45c6cb8 1516 OMAP_HSMMC_WRITE(host->base, BLK, 0);
e2bf08d6
AH		 1517 /*
1518 * Set an arbitrary 100ms data timeout for commands with
1519 * busy signal.
1520 */
1521 if (req->cmd->flags & MMC_RSP_BUSY)
1522 set_data_timeout(host, 100000000U, 0);
a45c6cb8
MC		 1523 return 0;
1524 }
1525
1526 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1527 | (req->data->blocks << 16));
e2bf08d6 1528 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
a45c6cb8 1529
a45c6cb8 1530 if (host->use_dma) {
70a3341a 1531 ret = omap_hsmmc_start_dma_transfer(host, req);
a45c6cb8
MC		 1532 if (ret != 0) {
1533 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1534 return ret;
1535 }
1536 }
1537 return 0;
1538}
1539
9782aff8
PF		 1540static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1541 int err)
1542{
1543 struct omap_hsmmc_host *host = mmc_priv(mmc);
1544 struct mmc_data *data = mrq->data;
1545
1546 if (host->use_dma) {
1547 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1548 omap_hsmmc_get_dma_dir(host, data));
1549 data->host_cookie = 0;
1550 }
1551}
1552
1553static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1554 bool is_first_req)
1555{
1556 struct omap_hsmmc_host *host = mmc_priv(mmc);
1557
1558 if (mrq->data->host_cookie) {
1559 mrq->data->host_cookie = 0;
1560 return ;
1561 }
1562
1563 if (host->use_dma)
1564 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1565 &host->next_data))
1566 mrq->data->host_cookie = 0;
1567}
1568
a45c6cb8
MC		 1569/*
1570 * Request function. for read/write operation
1571 */
70a3341a 1572static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
a45c6cb8 1573{
70a3341a 1574 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3f406f8 1575 int err;
a45c6cb8 1576
b417577d
AH		 1577 BUG_ON(host->req_in_progress);
1578 BUG_ON(host->dma_ch != -1);
1579 if (host->protect_card) {
1580 if (host->reqs_blocked < 3) {
1581 /*
1582 * Ensure the controller is left in a consistent
1583 * state by resetting the command and data state
1584 * machines.
1585 */
1586 omap_hsmmc_reset_controller_fsm(host, SRD);
1587 omap_hsmmc_reset_controller_fsm(host, SRC);
1588 host->reqs_blocked += 1;
1589 }
1590 req->cmd->error = -EBADF;
1591 if (req->data)
1592 req->data->error = -EBADF;
1593 req->cmd->retries = 0;
1594 mmc_request_done(mmc, req);
1595 return;
1596 } else if (host->reqs_blocked)
1597 host->reqs_blocked = 0;
a45c6cb8
MC		 1598 WARN_ON(host->mrq != NULL);
1599 host->mrq = req;
70a3341a 1600 err = omap_hsmmc_prepare_data(host, req);
a3f406f8
JL		 1601 if (err) {
1602 req->cmd->error = err;
1603 if (req->data)
1604 req->data->error = err;
1605 host->mrq = NULL;
1606 mmc_request_done(mmc, req);
1607 return;
1608 }
1609
70a3341a 1610 omap_hsmmc_start_command(host, req->cmd, req->data);
a45c6cb8
MC		 1611}
1612
a45c6cb8 1613/* Routine to configure clock values. Exposed API to core */
70a3341a 1614static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
a45c6cb8 1615{
70a3341a 1616 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8
MC		 1617 unsigned long regval;
1618 unsigned long timeout;
73153010 1619 u32 con;
a3621465 1620 int do_send_init_stream = 0;
a45c6cb8 1621
fa4aa2d4 1622 pm_runtime_get_sync(host->dev);
5e2ea617 1623
a3621465
AH		 1624 if (ios->power_mode != host->power_mode) {
1625 switch (ios->power_mode) {
1626 case MMC_POWER_OFF:
1627 mmc_slot(host).set_power(host->dev, host->slot_id,
1628 0, 0);
623821f7 1629 host->vdd = 0;
a3621465
AH		 1630 break;
1631 case MMC_POWER_UP:
1632 mmc_slot(host).set_power(host->dev, host->slot_id,
1633 1, ios->vdd);
623821f7 1634 host->vdd = ios->vdd;
a3621465
AH		 1635 break;
1636 case MMC_POWER_ON:
1637 do_send_init_stream = 1;
1638 break;
1639 }
1640 host->power_mode = ios->power_mode;
a45c6cb8
MC		 1641 }
1642
dd498eff
DK		 1643 /* FIXME: set registers based only on changes to ios */
1644
73153010 1645 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 1646 switch (mmc->ios.bus_width) {
73153010
JL		 1647 case MMC_BUS_WIDTH_8:
1648 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1649 break;
a45c6cb8 1650 case MMC_BUS_WIDTH_4:
73153010 1651 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 1652 OMAP_HSMMC_WRITE(host->base, HCTL,
1653 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1654 break;
1655 case MMC_BUS_WIDTH_1:
73153010 1656 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 1657 OMAP_HSMMC_WRITE(host->base, HCTL,
1658 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1659 break;
1660 }
1661
4621d5f8 1662 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
eb250826
DB		 1663 /* Only MMC1 can interface at 3V without some flavor
1664 * of external transceiver; but they all handle 1.8V.
1665 */
a45c6cb8
MC		 1666 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1667 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1668 /*
1669 * The mmc_select_voltage fn of the core does
1670 * not seem to set the power_mode to
1671 * MMC_POWER_UP upon recalculating the voltage.
1672 * vdd 1.8v.
1673 */
70a3341a
DK		 1674 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1675 dev_dbg(mmc_dev(host->mmc),
a45c6cb8
MC		 1676 "Switch operation failed\n");
1677 }
1678 }
1679
70a3341a 1680 omap_hsmmc_stop_clock(host);
ac330f44 1681
a45c6cb8
MC		 1682 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1683 regval = regval & ~(CLKD_MASK);
ac330f44 1684 regval = regval | (calc_divisor(ios) << 6) | (DTO << 16);
a45c6cb8
MC		 1685 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1686 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1687 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1688
1689 /* Wait till the ICS bit is set */
1690 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
11dd62a7 1691 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
a45c6cb8
MC		 1692 && time_before(jiffies, timeout))
1693 msleep(1);
1694
e0c7f99b 1695 omap_hsmmc_start_clock(host);
a45c6cb8 1696
a3621465 1697 if (do_send_init_stream)
a45c6cb8
MC		 1698 send_init_stream(host);
1699
abb28e73 1700 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 1701 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
abb28e73
DK		 1702 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1703 else
1704 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
5e2ea617 1705
fa4aa2d4 1706 pm_runtime_put_autosuspend(host->dev);
a45c6cb8
MC		 1707}
1708
1709static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1710{
70a3341a 1711 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1712
191d1f1d 1713 if (!mmc_slot(host).card_detect)
a45c6cb8 1714 return -ENOSYS;
db0fefc5 1715 return mmc_slot(host).card_detect(host->dev, host->slot_id);
a45c6cb8
MC		 1716}
1717
1718static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1719{
70a3341a 1720 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1721
191d1f1d 1722 if (!mmc_slot(host).get_ro)
a45c6cb8 1723 return -ENOSYS;
191d1f1d 1724 return mmc_slot(host).get_ro(host->dev, 0);
a45c6cb8
MC		 1725}
1726
4816858c
GI		 1727static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1728{
1729 struct omap_hsmmc_host *host = mmc_priv(mmc);
1730
1731 if (mmc_slot(host).init_card)
1732 mmc_slot(host).init_card(card);
1733}
1734
70a3341a 1735static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1b331e69
KK		 1736{
1737 u32 hctl, capa, value;
1738
1739 /* Only MMC1 supports 3.0V */
4621d5f8 1740 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1b331e69
KK		 1741 hctl = SDVS30;
1742 capa = VS30 | VS18;
1743 } else {
1744 hctl = SDVS18;
1745 capa = VS18;
1746 }
1747
1748 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1749 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1750
1751 value = OMAP_HSMMC_READ(host->base, CAPA);
1752 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1753
1754 /* Set the controller to AUTO IDLE mode */
1755 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1756 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1757
1758 /* Set SD bus power bit */
e13bb300 1759 set_sd_bus_power(host);
1b331e69
KK		 1760}
1761
70a3341a 1762static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
dd498eff 1763{
70a3341a 1764 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1765
fa4aa2d4
B		 1766 pm_runtime_get_sync(host->dev);
1767
dd498eff
DK		 1768 return 0;
1769}
1770
70a3341a 1771static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
dd498eff 1772{
70a3341a 1773 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1774
fa4aa2d4
B		 1775 pm_runtime_mark_last_busy(host->dev);
1776 pm_runtime_put_autosuspend(host->dev);
1777
dd498eff
DK		 1778 return 0;
1779}
1780
70a3341a
DK		 1781static const struct mmc_host_ops omap_hsmmc_ops = {
1782 .enable = omap_hsmmc_enable_fclk,
1783 .disable = omap_hsmmc_disable_fclk,
9782aff8
PF		 1784 .post_req = omap_hsmmc_post_req,
1785 .pre_req = omap_hsmmc_pre_req,
70a3341a
DK		 1786 .request = omap_hsmmc_request,
1787 .set_ios = omap_hsmmc_set_ios,
dd498eff
DK		 1788 .get_cd = omap_hsmmc_get_cd,
1789 .get_ro = omap_hsmmc_get_ro,
4816858c 1790 .init_card = omap_hsmmc_init_card,
dd498eff
DK		 1791 /* NYET -- enable_sdio_irq */
1792};
1793
d900f712
DK		 1794#ifdef CONFIG_DEBUG_FS
1795
70a3341a 1796static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
d900f712
DK		 1797{
1798 struct mmc_host *mmc = s->private;
70a3341a 1799 struct omap_hsmmc_host *host = mmc_priv(mmc);
11dd62a7
DK		 1800 int context_loss = 0;
1801
70a3341a
DK		 1802 if (host->pdata->get_context_loss_count)
1803 context_loss = host->pdata->get_context_loss_count(host->dev);
d900f712 1804
5e2ea617
AH		 1805 seq_printf(s, "mmc%d:\n"
1806 " enabled:\t%d\n"
dd498eff 1807 " dpm_state:\t%d\n"
5e2ea617 1808 " nesting_cnt:\t%d\n"
11dd62a7 1809 " ctx_loss:\t%d:%d\n"
5e2ea617 1810 "\nregs:\n",
dd498eff
DK		 1811 mmc->index, mmc->enabled ? 1 : 0,
1812 host->dpm_state, mmc->nesting_cnt,
11dd62a7 1813 host->context_loss, context_loss);
5e2ea617 1814
7a8c2cef 1815 if (host->suspended) {
dd498eff
DK		 1816 seq_printf(s, "host suspended, can't read registers\n");
1817 return 0;
1818 }
1819
fa4aa2d4 1820 pm_runtime_get_sync(host->dev);
d900f712
DK		 1821
1822 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1823 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1824 seq_printf(s, "CON:\t\t0x%08x\n",
1825 OMAP_HSMMC_READ(host->base, CON));
1826 seq_printf(s, "HCTL:\t\t0x%08x\n",
1827 OMAP_HSMMC_READ(host->base, HCTL));
1828 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1829 OMAP_HSMMC_READ(host->base, SYSCTL));
1830 seq_printf(s, "IE:\t\t0x%08x\n",
1831 OMAP_HSMMC_READ(host->base, IE));
1832 seq_printf(s, "ISE:\t\t0x%08x\n",
1833 OMAP_HSMMC_READ(host->base, ISE));
1834 seq_printf(s, "CAPA:\t\t0x%08x\n",
1835 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617 1836
fa4aa2d4
B		 1837 pm_runtime_mark_last_busy(host->dev);
1838 pm_runtime_put_autosuspend(host->dev);
dd498eff 1839
d900f712
DK		 1840 return 0;
1841}
1842
70a3341a 1843static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
d900f712 1844{
70a3341a 1845 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
d900f712
DK		 1846}
1847
1848static const struct file_operations mmc_regs_fops = {
70a3341a 1849 .open = omap_hsmmc_regs_open,
d900f712
DK		 1850 .read = seq_read,
1851 .llseek = seq_lseek,
1852 .release = single_release,
1853};
1854
70a3341a 1855static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1856{
1857 if (mmc->debugfs_root)
1858 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1859 mmc, &mmc_regs_fops);
1860}
1861
1862#else
1863
70a3341a 1864static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1865{
1866}
1867
1868#endif
1869
70a3341a 1870static int __init omap_hsmmc_probe(struct platform_device *pdev)
a45c6cb8
MC		 1871{
1872 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1873 struct mmc_host *mmc;
70a3341a 1874 struct omap_hsmmc_host *host = NULL;
a45c6cb8 1875 struct resource *res;
db0fefc5 1876 int ret, irq;
a45c6cb8
MC		 1877
1878 if (pdata == NULL) {
1879 dev_err(&pdev->dev, "Platform Data is missing\n");
1880 return -ENXIO;
1881 }
1882
1883 if (pdata->nr_slots == 0) {
1884 dev_err(&pdev->dev, "No Slots\n");
1885 return -ENXIO;
1886 }
1887
1888 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1889 irq = platform_get_irq(pdev, 0);
1890 if (res == NULL || irq < 0)
1891 return -ENXIO;
1892
91a0b089 1893 res->start += pdata->reg_offset;
1894 res->end += pdata->reg_offset;
984b203a 1895 res = request_mem_region(res->start, resource_size(res), pdev->name);
a45c6cb8
MC		 1896 if (res == NULL)
1897 return -EBUSY;
1898
db0fefc5
AH		 1899 ret = omap_hsmmc_gpio_init(pdata);
1900 if (ret)
1901 goto err;
1902
70a3341a 1903 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
a45c6cb8
MC		 1904 if (!mmc) {
1905 ret = -ENOMEM;
db0fefc5 1906 goto err_alloc;
a45c6cb8
MC		 1907 }
1908
1909 host = mmc_priv(mmc);
1910 host->mmc = mmc;
1911 host->pdata = pdata;
1912 host->dev = &pdev->dev;
1913 host->use_dma = 1;
1914 host->dev->dma_mask = &pdata->dma_mask;
1915 host->dma_ch = -1;
1916 host->irq = irq;
1917 host->id = pdev->id;
1918 host->slot_id = 0;
1919 host->mapbase = res->start;
1920 host->base = ioremap(host->mapbase, SZ_4K);
6da20c89 1921 host->power_mode = MMC_POWER_OFF;
9782aff8 1922 host->next_data.cookie = 1;
a45c6cb8
MC		 1923
1924 platform_set_drvdata(pdev, host);
70a3341a 1925 INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
a45c6cb8 1926
7a8c2cef 1927 mmc->ops = &omap_hsmmc_ops;
dd498eff 1928
e0eb2424
AH		 1929 /*
1930 * If regulator_disable can only put vcc_aux to sleep then there is
1931 * no off state.
1932 */
1933 if (mmc_slot(host).vcc_aux_disable_is_sleep)
1934 mmc_slot(host).no_off = 1;
1935
6b206efe
AS		 1936 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1937 mmc->f_max = OMAP_MMC_MAX_CLOCK;
a45c6cb8 1938
4dffd7a2 1939 spin_lock_init(&host->irq_lock);
a45c6cb8 1940
6f7607cc 1941 host->fclk = clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 1942 if (IS_ERR(host->fclk)) {
1943 ret = PTR_ERR(host->fclk);
1944 host->fclk = NULL;
a45c6cb8
MC		 1945 goto err1;
1946 }
1947
70a3341a 1948 omap_hsmmc_context_save(host);
11dd62a7 1949
5e2ea617 1950 mmc->caps |= MMC_CAP_DISABLE;
dd498eff 1951
fa4aa2d4
B		 1952 pm_runtime_enable(host->dev);
1953 pm_runtime_get_sync(host->dev);
1954 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1955 pm_runtime_use_autosuspend(host->dev);
a45c6cb8 1956
2bec0893
AH		 1957 if (cpu_is_omap2430()) {
1958 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1959 /*
1960 * MMC can still work without debounce clock.
1961 */
1962 if (IS_ERR(host->dbclk))
1963 dev_warn(mmc_dev(host->mmc),
1964 "Failed to get debounce clock\n");
a45c6cb8 1965 else
2bec0893
AH		 1966 host->got_dbclk = 1;
1967
1968 if (host->got_dbclk)
1969 if (clk_enable(host->dbclk) != 0)
1970 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1971 " clk failed\n");
1972 }
a45c6cb8 1973
0ccd76d4
JY		 1974 /* Since we do only SG emulation, we can have as many segs
1975 * as we want. */
a36274e0 1976 mmc->max_segs = 1024;
0ccd76d4 1977
a45c6cb8
MC		 1978 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1979 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1980 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1981 mmc->max_seg_size = mmc->max_req_size;
1982
13189e78 1983 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
93caf8e6 1984 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
a45c6cb8 1985
3a63833e
SG		 1986 mmc->caps |= mmc_slot(host).caps;
1987 if (mmc->caps & MMC_CAP_8_BIT_DATA)
a45c6cb8
MC		 1988 mmc->caps |= MMC_CAP_4_BIT_DATA;
1989
191d1f1d 1990 if (mmc_slot(host).nonremovable)
23d99bb9
AH		 1991 mmc->caps |= MMC_CAP_NONREMOVABLE;
1992
70a3341a 1993 omap_hsmmc_conf_bus_power(host);
a45c6cb8 1994
f3e2f1dd
GI		 1995 /* Select DMA lines */
1996 switch (host->id) {
1997 case OMAP_MMC1_DEVID:
1998 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
1999 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
2000 break;
2001 case OMAP_MMC2_DEVID:
2002 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
2003 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
2004 break;
2005 case OMAP_MMC3_DEVID:
2006 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2007 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2008 break;
82cf818d 2009 case OMAP_MMC4_DEVID:
2010 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2011 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2012 break;
2013 case OMAP_MMC5_DEVID:
2014 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2015 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2016 break;
f3e2f1dd
GI		 2017 default:
2018 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2019 goto err_irq;
2020 }
a45c6cb8
MC		 2021
2022 /* Request IRQ for MMC operations */
70a3341a 2023 ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED,
a45c6cb8
MC		 2024 mmc_hostname(mmc), host);
2025 if (ret) {
2026 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2027 goto err_irq;
2028 }
2029
2030 if (pdata->init != NULL) {
2031 if (pdata->init(&pdev->dev) != 0) {
70a3341a
DK		 2032 dev_dbg(mmc_dev(host->mmc),
2033 "Unable to configure MMC IRQs\n");
a45c6cb8
MC		 2034 goto err_irq_cd_init;
2035 }
2036 }
db0fefc5 2037
b702b106 2038 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
db0fefc5
AH		 2039 ret = omap_hsmmc_reg_get(host);
2040 if (ret)
2041 goto err_reg;
2042 host->use_reg = 1;
2043 }
2044
b583f26d 2045 mmc->ocr_avail = mmc_slot(host).ocr_mask;
a45c6cb8
MC		 2046
2047 /* Request IRQ for card detect */
e1a55f5e 2048 if ((mmc_slot(host).card_detect_irq)) {
a45c6cb8 2049 ret = request_irq(mmc_slot(host).card_detect_irq,
70a3341a 2050 omap_hsmmc_cd_handler,
a45c6cb8
MC		 2051 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2052 | IRQF_DISABLED,
2053 mmc_hostname(mmc), host);
2054 if (ret) {
2055 dev_dbg(mmc_dev(host->mmc),
2056 "Unable to grab MMC CD IRQ\n");
2057 goto err_irq_cd;
2058 }
72f2e2c7 2059 pdata->suspend = omap_hsmmc_suspend_cdirq;
2060 pdata->resume = omap_hsmmc_resume_cdirq;
a45c6cb8
MC		 2061 }
2062
b417577d 2063 omap_hsmmc_disable_irq(host);
a45c6cb8 2064
b62f6228
AH		 2065 omap_hsmmc_protect_card(host);
2066
a45c6cb8
MC		 2067 mmc_add_host(mmc);
2068
191d1f1d 2069 if (mmc_slot(host).name != NULL) {
a45c6cb8
MC		 2070 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2071 if (ret < 0)
2072 goto err_slot_name;
2073 }
191d1f1d 2074 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
a45c6cb8
MC		 2075 ret = device_create_file(&mmc->class_dev,
2076 &dev_attr_cover_switch);
2077 if (ret < 0)
db0fefc5 2078 goto err_slot_name;
a45c6cb8
MC		 2079 }
2080
70a3341a 2081 omap_hsmmc_debugfs(mmc);
fa4aa2d4
B		 2082 pm_runtime_mark_last_busy(host->dev);
2083 pm_runtime_put_autosuspend(host->dev);
d900f712 2084
a45c6cb8
MC		 2085 return 0;
2086
a45c6cb8
MC		 2087err_slot_name:
2088 mmc_remove_host(mmc);
a45c6cb8 2089 free_irq(mmc_slot(host).card_detect_irq, host);
db0fefc5
AH		 2090err_irq_cd:
2091 if (host->use_reg)
2092 omap_hsmmc_reg_put(host);
2093err_reg:
2094 if (host->pdata->cleanup)
2095 host->pdata->cleanup(&pdev->dev);
a45c6cb8
MC		 2096err_irq_cd_init:
2097 free_irq(host->irq, host);
2098err_irq:
fa4aa2d4
B		 2099 pm_runtime_mark_last_busy(host->dev);
2100 pm_runtime_put_autosuspend(host->dev);
a45c6cb8 2101 clk_put(host->fclk);
2bec0893 2102 if (host->got_dbclk) {
a45c6cb8
MC		 2103 clk_disable(host->dbclk);
2104 clk_put(host->dbclk);
2105 }
a45c6cb8
MC		 2106err1:
2107 iounmap(host->base);
db0fefc5
AH		 2108 platform_set_drvdata(pdev, NULL);
2109 mmc_free_host(mmc);
2110err_alloc:
2111 omap_hsmmc_gpio_free(pdata);
a45c6cb8 2112err:
984b203a 2113 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 2114 return ret;
2115}
2116
70a3341a 2117static int omap_hsmmc_remove(struct platform_device *pdev)
a45c6cb8 2118{
70a3341a 2119 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2120 struct resource *res;
2121
2122 if (host) {
fa4aa2d4 2123 pm_runtime_get_sync(host->dev);
a45c6cb8 2124 mmc_remove_host(host->mmc);
db0fefc5
AH		 2125 if (host->use_reg)
2126 omap_hsmmc_reg_put(host);
a45c6cb8
MC		 2127 if (host->pdata->cleanup)
2128 host->pdata->cleanup(&pdev->dev);
2129 free_irq(host->irq, host);
2130 if (mmc_slot(host).card_detect_irq)
2131 free_irq(mmc_slot(host).card_detect_irq, host);
0d9ee5b2 2132 flush_work_sync(&host->mmc_carddetect_work);
a45c6cb8 2133
fa4aa2d4
B		 2134 pm_runtime_put_sync(host->dev);
2135 pm_runtime_disable(host->dev);
a45c6cb8 2136 clk_put(host->fclk);
2bec0893 2137 if (host->got_dbclk) {
a45c6cb8
MC		 2138 clk_disable(host->dbclk);
2139 clk_put(host->dbclk);
2140 }
2141
2142 mmc_free_host(host->mmc);
2143 iounmap(host->base);
db0fefc5 2144 omap_hsmmc_gpio_free(pdev->dev.platform_data);
a45c6cb8
MC		 2145 }
2146
2147 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2148 if (res)
984b203a 2149 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 2150 platform_set_drvdata(pdev, NULL);
2151
2152 return 0;
2153}
2154
2155#ifdef CONFIG_PM
a791daa1 2156static int omap_hsmmc_suspend(struct device *dev)
a45c6cb8
MC		 2157{
2158 int ret = 0;
a791daa1 2159 struct platform_device *pdev = to_platform_device(dev);
70a3341a 2160 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2161
2162 if (host && host->suspended)
2163 return 0;
2164
2165 if (host) {
fa4aa2d4 2166 pm_runtime_get_sync(host->dev);
a6b2240d
AH		 2167 host->suspended = 1;
2168 if (host->pdata->suspend) {
2169 ret = host->pdata->suspend(&pdev->dev,
2170 host->slot_id);
2171 if (ret) {
2172 dev_dbg(mmc_dev(host->mmc),
2173 "Unable to handle MMC board"
2174 " level suspend\n");
2175 host->suspended = 0;
2176 return ret;
2177 }
2178 }
2179 cancel_work_sync(&host->mmc_carddetect_work);
1a13f8fa 2180 ret = mmc_suspend_host(host->mmc);
fa4aa2d4 2181
a45c6cb8 2182 if (ret == 0) {
b417577d 2183 omap_hsmmc_disable_irq(host);
0683af48 2184 OMAP_HSMMC_WRITE(host->base, HCTL,
191d1f1d 2185 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2bec0893
AH		 2186 if (host->got_dbclk)
2187 clk_disable(host->dbclk);
a6b2240d
AH		 2188 } else {
2189 host->suspended = 0;
2190 if (host->pdata->resume) {
2191 ret = host->pdata->resume(&pdev->dev,
2192 host->slot_id);
2193 if (ret)
2194 dev_dbg(mmc_dev(host->mmc),
2195 "Unmask interrupt failed\n");
2196 }
a6b2240d 2197 }
fa4aa2d4 2198 pm_runtime_put_sync(host->dev);
a45c6cb8
MC		 2199 }
2200 return ret;
2201}
2202
2203/* Routine to resume the MMC device */
a791daa1 2204static int omap_hsmmc_resume(struct device *dev)
a45c6cb8
MC		 2205{
2206 int ret = 0;
a791daa1 2207 struct platform_device *pdev = to_platform_device(dev);
70a3341a 2208 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2209
2210 if (host && !host->suspended)
2211 return 0;
2212
2213 if (host) {
fa4aa2d4 2214 pm_runtime_get_sync(host->dev);
11dd62a7 2215
2bec0893
AH		 2216 if (host->got_dbclk)
2217 clk_enable(host->dbclk);
2218
70a3341a 2219 omap_hsmmc_conf_bus_power(host);
1b331e69 2220
a45c6cb8
MC		 2221 if (host->pdata->resume) {
2222 ret = host->pdata->resume(&pdev->dev, host->slot_id);
2223 if (ret)
2224 dev_dbg(mmc_dev(host->mmc),
2225 "Unmask interrupt failed\n");
2226 }
2227
b62f6228
AH		 2228 omap_hsmmc_protect_card(host);
2229
a45c6cb8
MC		 2230 /* Notify the core to resume the host */
2231 ret = mmc_resume_host(host->mmc);
2232 if (ret == 0)
2233 host->suspended = 0;
fa4aa2d4
B		 2234
2235 pm_runtime_mark_last_busy(host->dev);
2236 pm_runtime_put_autosuspend(host->dev);
a45c6cb8
MC		 2237 }
2238
2239 return ret;
2240
a45c6cb8
MC		 2241}
2242
2243#else
70a3341a
DK		 2244#define omap_hsmmc_suspend NULL
2245#define omap_hsmmc_resume NULL
a45c6cb8
MC		 2246#endif
2247
fa4aa2d4
B		 2248static int omap_hsmmc_runtime_suspend(struct device *dev)
2249{
2250 struct omap_hsmmc_host *host;
2251
2252 host = platform_get_drvdata(to_platform_device(dev));
2253 omap_hsmmc_context_save(host);
2254 dev_dbg(mmc_dev(host->mmc), "disabled\n");
2255
2256 return 0;
2257}
2258
2259static int omap_hsmmc_runtime_resume(struct device *dev)
2260{
2261 struct omap_hsmmc_host *host;
2262
2263 host = platform_get_drvdata(to_platform_device(dev));
2264 omap_hsmmc_context_restore(host);
2265 dev_dbg(mmc_dev(host->mmc), "enabled\n");
2266
2267 return 0;
2268}
2269
a791daa1 2270static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
70a3341a
DK		 2271 .suspend = omap_hsmmc_suspend,
2272 .resume = omap_hsmmc_resume,
fa4aa2d4
B		 2273 .runtime_suspend = omap_hsmmc_runtime_suspend,
2274 .runtime_resume = omap_hsmmc_runtime_resume,
a791daa1
KH		 2275};
2276
2277static struct platform_driver omap_hsmmc_driver = {
2278 .remove = omap_hsmmc_remove,
a45c6cb8
MC		 2279 .driver = {
2280 .name = DRIVER_NAME,
2281 .owner = THIS_MODULE,
a791daa1 2282 .pm = &omap_hsmmc_dev_pm_ops,
a45c6cb8
MC		 2283 },
2284};
2285
70a3341a 2286static int __init omap_hsmmc_init(void)
a45c6cb8
MC		 2287{
2288 /* Register the MMC driver */
8753298a 2289 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
a45c6cb8
MC		 2290}
2291
70a3341a 2292static void __exit omap_hsmmc_cleanup(void)
a45c6cb8
MC		 2293{
2294 /* Unregister MMC driver */
70a3341a 2295 platform_driver_unregister(&omap_hsmmc_driver);
a45c6cb8
MC		 2296}
2297
70a3341a
DK		 2298module_init(omap_hsmmc_init);
2299module_exit(omap_hsmmc_cleanup);
a45c6cb8
MC		 2300
2301MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2302MODULE_LICENSE("GPL");
2303MODULE_ALIAS("platform:" DRIVER_NAME);
2304MODULE_AUTHOR("Texas Instruments Inc");
Linux kernel - Deliverables
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