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arm: omap2plus: fix ads7846 pendown gpio request
[deliverable/linux.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
d900f712
DK		 20#include <linux/debugfs.h>
21#include <linux/seq_file.h>
a45c6cb8
MC		 22#include <linux/interrupt.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
25#include <linux/platform_device.h>
26#include <linux/workqueue.h>
27#include <linux/timer.h>
28#include <linux/clk.h>
29#include <linux/mmc/host.h>
13189e78 30#include <linux/mmc/core.h>
93caf8e6 31#include <linux/mmc/mmc.h>
a45c6cb8
MC		 32#include <linux/io.h>
33#include <linux/semaphore.h>
db0fefc5
AH		 34#include <linux/gpio.h>
35#include <linux/regulator/consumer.h>
ce491cf8 36#include <plat/dma.h>
a45c6cb8 37#include <mach/hardware.h>
ce491cf8
TL		 38#include <plat/board.h>
39#include <plat/mmc.h>
40#include <plat/cpu.h>
a45c6cb8
MC		 41
42/* OMAP HSMMC Host Controller Registers */
43#define OMAP_HSMMC_SYSCONFIG 0x0010
11dd62a7 44#define OMAP_HSMMC_SYSSTATUS 0x0014
a45c6cb8
MC		 45#define OMAP_HSMMC_CON 0x002C
46#define OMAP_HSMMC_BLK 0x0104
47#define OMAP_HSMMC_ARG 0x0108
48#define OMAP_HSMMC_CMD 0x010C
49#define OMAP_HSMMC_RSP10 0x0110
50#define OMAP_HSMMC_RSP32 0x0114
51#define OMAP_HSMMC_RSP54 0x0118
52#define OMAP_HSMMC_RSP76 0x011C
53#define OMAP_HSMMC_DATA 0x0120
54#define OMAP_HSMMC_HCTL 0x0128
55#define OMAP_HSMMC_SYSCTL 0x012C
56#define OMAP_HSMMC_STAT 0x0130
57#define OMAP_HSMMC_IE 0x0134
58#define OMAP_HSMMC_ISE 0x0138
59#define OMAP_HSMMC_CAPA 0x0140
60
61#define VS18 (1 << 26)
62#define VS30 (1 << 25)
63#define SDVS18 (0x5 << 9)
64#define SDVS30 (0x6 << 9)
eb250826 65#define SDVS33 (0x7 << 9)
1b331e69 66#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 67#define SDVSCLR 0xFFFFF1FF
68#define SDVSDET 0x00000400
69#define AUTOIDLE 0x1
70#define SDBP (1 << 8)
71#define DTO 0xe
72#define ICE 0x1
73#define ICS 0x2
74#define CEN (1 << 2)
75#define CLKD_MASK 0x0000FFC0
76#define CLKD_SHIFT 6
77#define DTO_MASK 0x000F0000
78#define DTO_SHIFT 16
79#define INT_EN_MASK 0x307F0033
ccdfe3a6
AG		 80#define BWR_ENABLE (1 << 4)
81#define BRR_ENABLE (1 << 5)
93caf8e6 82#define DTO_ENABLE (1 << 20)
a45c6cb8
MC		 83#define INIT_STREAM (1 << 1)
84#define DP_SELECT (1 << 21)
85#define DDIR (1 << 4)
86#define DMA_EN 0x1
87#define MSBS (1 << 5)
88#define BCE (1 << 1)
89#define FOUR_BIT (1 << 1)
73153010 90#define DW8 (1 << 5)
a45c6cb8
MC		 91#define CC 0x1
92#define TC 0x02
93#define OD 0x1
94#define ERR (1 << 15)
95#define CMD_TIMEOUT (1 << 16)
96#define DATA_TIMEOUT (1 << 20)
97#define CMD_CRC (1 << 17)
98#define DATA_CRC (1 << 21)
99#define CARD_ERR (1 << 28)
100#define STAT_CLEAR 0xFFFFFFFF
101#define INIT_STREAM_CMD 0x00000000
102#define DUAL_VOLT_OCR_BIT 7
103#define SRC (1 << 25)
104#define SRD (1 << 26)
11dd62a7
DK		 105#define SOFTRESET (1 << 1)
106#define RESETDONE (1 << 0)
a45c6cb8
MC		 107
108/*
109 * FIXME: Most likely all the data using these _DEVID defines should come
110 * from the platform_data, or implemented in controller and slot specific
111 * functions.
112 */
113#define OMAP_MMC1_DEVID 0
114#define OMAP_MMC2_DEVID 1
f3e2f1dd 115#define OMAP_MMC3_DEVID 2
82cf818d 116#define OMAP_MMC4_DEVID 3
117#define OMAP_MMC5_DEVID 4
a45c6cb8 118
a45c6cb8
MC		 119#define MMC_TIMEOUT_MS 20
120#define OMAP_MMC_MASTER_CLOCK 96000000
0005ae73 121#define DRIVER_NAME "omap_hsmmc"
a45c6cb8 122
dd498eff
DK		 123/* Timeouts for entering power saving states on inactivity, msec */
124#define OMAP_MMC_DISABLED_TIMEOUT 100
13189e78
JL		 125#define OMAP_MMC_SLEEP_TIMEOUT 1000
126#define OMAP_MMC_OFF_TIMEOUT 8000
dd498eff 127
a45c6cb8
MC		 128/*
129 * One controller can have multiple slots, like on some omap boards using
130 * omap.c controller driver. Luckily this is not currently done on any known
131 * omap_hsmmc.c device.
132 */
133#define mmc_slot(host) (host->pdata->slots[host->slot_id])
134
135/*
136 * MMC Host controller read/write API's
137 */
138#define OMAP_HSMMC_READ(base, reg) \
139 __raw_readl((base) + OMAP_HSMMC_##reg)
140
141#define OMAP_HSMMC_WRITE(base, reg, val) \
142 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
143
70a3341a 144struct omap_hsmmc_host {
a45c6cb8
MC		 145 struct device *dev;
146 struct mmc_host *mmc;
147 struct mmc_request *mrq;
148 struct mmc_command *cmd;
149 struct mmc_data *data;
150 struct clk *fclk;
151 struct clk *iclk;
152 struct clk *dbclk;
db0fefc5
AH		 153 /*
154 * vcc == configured supply
155 * vcc_aux == optional
156 * - MMC1, supply for DAT4..DAT7
157 * - MMC2/MMC2, external level shifter voltage supply, for
158 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
159 */
160 struct regulator *vcc;
161 struct regulator *vcc_aux;
a45c6cb8
MC		 162 struct work_struct mmc_carddetect_work;
163 void __iomem *base;
164 resource_size_t mapbase;
4dffd7a2 165 spinlock_t irq_lock; /* Prevent races with irq handler */
a45c6cb8
MC		 166 unsigned int id;
167 unsigned int dma_len;
0ccd76d4 168 unsigned int dma_sg_idx;
a45c6cb8 169 unsigned char bus_mode;
a3621465 170 unsigned char power_mode;
a45c6cb8
MC		 171 u32 *buffer;
172 u32 bytesleft;
173 int suspended;
174 int irq;
a45c6cb8 175 int use_dma, dma_ch;
f3e2f1dd 176 int dma_line_tx, dma_line_rx;
a45c6cb8 177 int slot_id;
2bec0893 178 int got_dbclk;
4a694dc9 179 int response_busy;
11dd62a7 180 int context_loss;
dd498eff 181 int dpm_state;
623821f7 182 int vdd;
b62f6228
AH		 183 int protect_card;
184 int reqs_blocked;
db0fefc5 185 int use_reg;
b417577d 186 int req_in_progress;
11dd62a7 187
a45c6cb8
MC		 188 struct omap_mmc_platform_data *pdata;
189};
190
db0fefc5
AH		 191static int omap_hsmmc_card_detect(struct device *dev, int slot)
192{
193 struct omap_mmc_platform_data *mmc = dev->platform_data;
194
195 /* NOTE: assumes card detect signal is active-low */
196 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
197}
198
199static int omap_hsmmc_get_wp(struct device *dev, int slot)
200{
201 struct omap_mmc_platform_data *mmc = dev->platform_data;
202
203 /* NOTE: assumes write protect signal is active-high */
204 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
205}
206
207static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
208{
209 struct omap_mmc_platform_data *mmc = dev->platform_data;
210
211 /* NOTE: assumes card detect signal is active-low */
212 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
213}
214
215#ifdef CONFIG_PM
216
217static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
218{
219 struct omap_mmc_platform_data *mmc = dev->platform_data;
220
221 disable_irq(mmc->slots[0].card_detect_irq);
222 return 0;
223}
224
225static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
226{
227 struct omap_mmc_platform_data *mmc = dev->platform_data;
228
229 enable_irq(mmc->slots[0].card_detect_irq);
230 return 0;
231}
232
233#else
234
235#define omap_hsmmc_suspend_cdirq NULL
236#define omap_hsmmc_resume_cdirq NULL
237
238#endif
239
b702b106
AH		 240#ifdef CONFIG_REGULATOR
241
db0fefc5
AH		 242static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
243 int vdd)
244{
245 struct omap_hsmmc_host *host =
246 platform_get_drvdata(to_platform_device(dev));
247 int ret;
248
249 if (mmc_slot(host).before_set_reg)
250 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
251
252 if (power_on)
99fc5131 253 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5 254 else
99fc5131 255 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
db0fefc5
AH		 256
257 if (mmc_slot(host).after_set_reg)
258 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
259
260 return ret;
261}
262
7715db5a 263static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on,
db0fefc5
AH		 264 int vdd)
265{
266 struct omap_hsmmc_host *host =
267 platform_get_drvdata(to_platform_device(dev));
268 int ret = 0;
269
270 /*
271 * If we don't see a Vcc regulator, assume it's a fixed
272 * voltage always-on regulator.
273 */
274 if (!host->vcc)
275 return 0;
276
277 if (mmc_slot(host).before_set_reg)
278 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
279
280 /*
281 * Assume Vcc regulator is used only to power the card ... OMAP
282 * VDDS is used to power the pins, optionally with a transceiver to
283 * support cards using voltages other than VDDS (1.8V nominal). When a
284 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
285 *
286 * In some cases this regulator won't support enable/disable;
287 * e.g. it's a fixed rail for a WLAN chip.
288 *
289 * In other cases vcc_aux switches interface power. Example, for
290 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
291 * chips/cards need an interface voltage rail too.
292 */
293 if (power_on) {
99fc5131 294 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5
AH		 295 /* Enable interface voltage rail, if needed */
296 if (ret == 0 && host->vcc_aux) {
297 ret = regulator_enable(host->vcc_aux);
298 if (ret < 0)
99fc5131
LW		 299 ret = mmc_regulator_set_ocr(host->mmc,
300 host->vcc, 0);
db0fefc5
AH		 301 }
302 } else {
99fc5131 303 /* Shut down the rail */
6da20c89
AH		 304 if (host->vcc_aux)
305 ret = regulator_disable(host->vcc_aux);
99fc5131
LW		 306 if (!ret) {
307 /* Then proceed to shut down the local regulator */
308 ret = mmc_regulator_set_ocr(host->mmc,
309 host->vcc, 0);
310 }
db0fefc5
AH		 311 }
312
313 if (mmc_slot(host).after_set_reg)
314 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
315
316 return ret;
317}
318
7715db5a
KK		 319static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on,
320 int vdd)
321{
322 return 0;
323}
324
db0fefc5
AH		 325static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
326 int vdd, int cardsleep)
327{
328 struct omap_hsmmc_host *host =
329 platform_get_drvdata(to_platform_device(dev));
330 int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
331
332 return regulator_set_mode(host->vcc, mode);
333}
334
7715db5a 335static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep,
db0fefc5
AH		 336 int vdd, int cardsleep)
337{
338 struct omap_hsmmc_host *host =
339 platform_get_drvdata(to_platform_device(dev));
340 int err, mode;
341
342 /*
343 * If we don't see a Vcc regulator, assume it's a fixed
344 * voltage always-on regulator.
345 */
346 if (!host->vcc)
347 return 0;
348
349 mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
350
351 if (!host->vcc_aux)
352 return regulator_set_mode(host->vcc, mode);
353
354 if (cardsleep) {
355 /* VCC can be turned off if card is asleep */
356 if (sleep)
99fc5131 357 err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
db0fefc5 358 else
99fc5131 359 err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5
AH		 360 } else
361 err = regulator_set_mode(host->vcc, mode);
362 if (err)
363 return err;
e0eb2424
AH		 364
365 if (!mmc_slot(host).vcc_aux_disable_is_sleep)
366 return regulator_set_mode(host->vcc_aux, mode);
367
368 if (sleep)
369 return regulator_disable(host->vcc_aux);
370 else
371 return regulator_enable(host->vcc_aux);
db0fefc5
AH		 372}
373
7715db5a
KK		 374static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep,
375 int vdd, int cardsleep)
376{
377 return 0;
378}
379
db0fefc5
AH		 380static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
381{
382 struct regulator *reg;
383 int ret = 0;
64be9782 384 int ocr_value = 0;
db0fefc5
AH		 385
386 switch (host->id) {
387 case OMAP_MMC1_DEVID:
388 /* On-chip level shifting via PBIAS0/PBIAS1 */
389 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
390 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
391 break;
392 case OMAP_MMC2_DEVID:
393 case OMAP_MMC3_DEVID:
7715db5a 394 case OMAP_MMC5_DEVID:
db0fefc5 395 /* Off-chip level shifting, or none */
7715db5a
KK		 396 mmc_slot(host).set_power = omap_hsmmc_235_set_power;
397 mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep;
db0fefc5 398 break;
7715db5a
KK		 399 case OMAP_MMC4_DEVID:
400 mmc_slot(host).set_power = omap_hsmmc_4_set_power;
401 mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep;
db0fefc5
AH		 402 default:
403 pr_err("MMC%d configuration not supported!\n", host->id);
404 return -EINVAL;
405 }
406
407 reg = regulator_get(host->dev, "vmmc");
408 if (IS_ERR(reg)) {
409 dev_dbg(host->dev, "vmmc regulator missing\n");
410 /*
411 * HACK: until fixed.c regulator is usable,
412 * we don't require a main regulator
413 * for MMC2 or MMC3
414 */
415 if (host->id == OMAP_MMC1_DEVID) {
416 ret = PTR_ERR(reg);
417 goto err;
418 }
419 } else {
420 host->vcc = reg;
64be9782 421 ocr_value = mmc_regulator_get_ocrmask(reg);
422 if (!mmc_slot(host).ocr_mask) {
423 mmc_slot(host).ocr_mask = ocr_value;
424 } else {
425 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
426 pr_err("MMC%d ocrmask %x is not supported\n",
427 host->id, mmc_slot(host).ocr_mask);
428 mmc_slot(host).ocr_mask = 0;
429 return -EINVAL;
430 }
431 }
db0fefc5
AH		 432 mmc_slot(host).ocr_mask = mmc_regulator_get_ocrmask(reg);
433
434 /* Allow an aux regulator */
435 reg = regulator_get(host->dev, "vmmc_aux");
436 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
437
438 /*
439 * UGLY HACK: workaround regulator framework bugs.
440 * When the bootloader leaves a supply active, it's
441 * initialized with zero usecount ... and we can't
442 * disable it without first enabling it. Until the
443 * framework is fixed, we need a workaround like this
444 * (which is safe for MMC, but not in general).
445 */
446 if (regulator_is_enabled(host->vcc) > 0) {
447 regulator_enable(host->vcc);
448 regulator_disable(host->vcc);
449 }
450 if (host->vcc_aux) {
451 if (regulator_is_enabled(reg) > 0) {
452 regulator_enable(reg);
453 regulator_disable(reg);
454 }
455 }
456 }
457
458 return 0;
459
460err:
461 mmc_slot(host).set_power = NULL;
462 mmc_slot(host).set_sleep = NULL;
463 return ret;
464}
465
466static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
467{
468 regulator_put(host->vcc);
469 regulator_put(host->vcc_aux);
470 mmc_slot(host).set_power = NULL;
471 mmc_slot(host).set_sleep = NULL;
472}
473
b702b106
AH		 474static inline int omap_hsmmc_have_reg(void)
475{
476 return 1;
477}
478
479#else
480
481static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
482{
483 return -EINVAL;
484}
485
486static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
487{
488}
489
490static inline int omap_hsmmc_have_reg(void)
491{
492 return 0;
493}
494
495#endif
496
497static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
498{
499 int ret;
500
501 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
b702b106
AH		 502 if (pdata->slots[0].cover)
503 pdata->slots[0].get_cover_state =
504 omap_hsmmc_get_cover_state;
505 else
506 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
507 pdata->slots[0].card_detect_irq =
508 gpio_to_irq(pdata->slots[0].switch_pin);
509 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
510 if (ret)
511 return ret;
512 ret = gpio_direction_input(pdata->slots[0].switch_pin);
513 if (ret)
514 goto err_free_sp;
515 } else
516 pdata->slots[0].switch_pin = -EINVAL;
517
518 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
519 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
520 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
521 if (ret)
522 goto err_free_cd;
523 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
524 if (ret)
525 goto err_free_wp;
526 } else
527 pdata->slots[0].gpio_wp = -EINVAL;
528
529 return 0;
530
531err_free_wp:
532 gpio_free(pdata->slots[0].gpio_wp);
533err_free_cd:
534 if (gpio_is_valid(pdata->slots[0].switch_pin))
535err_free_sp:
536 gpio_free(pdata->slots[0].switch_pin);
537 return ret;
538}
539
540static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
541{
542 if (gpio_is_valid(pdata->slots[0].gpio_wp))
543 gpio_free(pdata->slots[0].gpio_wp);
544 if (gpio_is_valid(pdata->slots[0].switch_pin))
545 gpio_free(pdata->slots[0].switch_pin);
546}
547
a45c6cb8
MC		 548/*
549 * Stop clock to the card
550 */
70a3341a 551static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
a45c6cb8
MC		 552{
553 OMAP_HSMMC_WRITE(host->base, SYSCTL,
554 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
555 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
556 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
557}
558
93caf8e6
AH		 559static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
560 struct mmc_command *cmd)
b417577d
AH		 561{
562 unsigned int irq_mask;
563
564 if (host->use_dma)
565 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
566 else
567 irq_mask = INT_EN_MASK;
568
93caf8e6
AH		 569 /* Disable timeout for erases */
570 if (cmd->opcode == MMC_ERASE)
571 irq_mask &= ~DTO_ENABLE;
572
b417577d
AH		 573 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
574 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
575 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
576}
577
578static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
579{
580 OMAP_HSMMC_WRITE(host->base, ISE, 0);
581 OMAP_HSMMC_WRITE(host->base, IE, 0);
582 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
583}
584
11dd62a7
DK		 585#ifdef CONFIG_PM
586
587/*
588 * Restore the MMC host context, if it was lost as result of a
589 * power state change.
590 */
70a3341a 591static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 592{
593 struct mmc_ios *ios = &host->mmc->ios;
594 struct omap_mmc_platform_data *pdata = host->pdata;
595 int context_loss = 0;
596 u32 hctl, capa, con;
597 u16 dsor = 0;
598 unsigned long timeout;
599
600 if (pdata->get_context_loss_count) {
601 context_loss = pdata->get_context_loss_count(host->dev);
602 if (context_loss < 0)
603 return 1;
604 }
605
606 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
607 context_loss == host->context_loss ? "not " : "");
608 if (host->context_loss == context_loss)
609 return 1;
610
611 /* Wait for hardware reset */
612 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
613 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
614 && time_before(jiffies, timeout))
615 ;
616
617 /* Do software reset */
618 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
619 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
620 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
621 && time_before(jiffies, timeout))
622 ;
623
624 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
625 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
626
627 if (host->id == OMAP_MMC1_DEVID) {
628 if (host->power_mode != MMC_POWER_OFF &&
629 (1 << ios->vdd) <= MMC_VDD_23_24)
630 hctl = SDVS18;
631 else
632 hctl = SDVS30;
633 capa = VS30 | VS18;
634 } else {
635 hctl = SDVS18;
636 capa = VS18;
637 }
638
639 OMAP_HSMMC_WRITE(host->base, HCTL,
640 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
641
642 OMAP_HSMMC_WRITE(host->base, CAPA,
643 OMAP_HSMMC_READ(host->base, CAPA) | capa);
644
645 OMAP_HSMMC_WRITE(host->base, HCTL,
646 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
647
648 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
649 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
650 && time_before(jiffies, timeout))
651 ;
652
b417577d 653 omap_hsmmc_disable_irq(host);
11dd62a7
DK		 654
655 /* Do not initialize card-specific things if the power is off */
656 if (host->power_mode == MMC_POWER_OFF)
657 goto out;
658
659 con = OMAP_HSMMC_READ(host->base, CON);
660 switch (ios->bus_width) {
661 case MMC_BUS_WIDTH_8:
662 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
663 break;
664 case MMC_BUS_WIDTH_4:
665 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
666 OMAP_HSMMC_WRITE(host->base, HCTL,
667 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
668 break;
669 case MMC_BUS_WIDTH_1:
670 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
671 OMAP_HSMMC_WRITE(host->base, HCTL,
672 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
673 break;
674 }
675
676 if (ios->clock) {
677 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
678 if (dsor < 1)
679 dsor = 1;
680
681 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
682 dsor++;
683
684 if (dsor > 250)
685 dsor = 250;
686 }
687
688 OMAP_HSMMC_WRITE(host->base, SYSCTL,
689 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
690 OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
691 OMAP_HSMMC_WRITE(host->base, SYSCTL,
692 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
693
694 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
695 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
696 && time_before(jiffies, timeout))
697 ;
698
699 OMAP_HSMMC_WRITE(host->base, SYSCTL,
700 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
701
702 con = OMAP_HSMMC_READ(host->base, CON);
703 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
704 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
705 else
706 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
707out:
708 host->context_loss = context_loss;
709
710 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
711 return 0;
712}
713
714/*
715 * Save the MMC host context (store the number of power state changes so far).
716 */
70a3341a 717static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 718{
719 struct omap_mmc_platform_data *pdata = host->pdata;
720 int context_loss;
721
722 if (pdata->get_context_loss_count) {
723 context_loss = pdata->get_context_loss_count(host->dev);
724 if (context_loss < 0)
725 return;
726 host->context_loss = context_loss;
727 }
728}
729
730#else
731
70a3341a 732static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 733{
734 return 0;
735}
736
70a3341a 737static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 738{
739}
740
741#endif
742
a45c6cb8
MC		 743/*
744 * Send init stream sequence to card
745 * before sending IDLE command
746 */
70a3341a 747static void send_init_stream(struct omap_hsmmc_host *host)
a45c6cb8
MC		 748{
749 int reg = 0;
750 unsigned long timeout;
751
b62f6228
AH		 752 if (host->protect_card)
753 return;
754
a45c6cb8 755 disable_irq(host->irq);
b417577d
AH		 756
757 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8
MC		 758 OMAP_HSMMC_WRITE(host->base, CON,
759 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
760 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
761
762 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
763 while ((reg != CC) && time_before(jiffies, timeout))
764 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
765
766 OMAP_HSMMC_WRITE(host->base, CON,
767 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
c653a6d4
AH		 768
769 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
770 OMAP_HSMMC_READ(host->base, STAT);
771
a45c6cb8
MC		 772 enable_irq(host->irq);
773}
774
775static inline
70a3341a 776int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
a45c6cb8
MC		 777{
778 int r = 1;
779
191d1f1d
DK		 780 if (mmc_slot(host).get_cover_state)
781 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
a45c6cb8
MC		 782 return r;
783}
784
785static ssize_t
70a3341a 786omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 787 char *buf)
788{
789 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 790 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 791
70a3341a
DK		 792 return sprintf(buf, "%s\n",
793 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
a45c6cb8
MC		 794}
795
70a3341a 796static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
a45c6cb8
MC		 797
798static ssize_t
70a3341a 799omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 800 char *buf)
801{
802 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 803 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 804
191d1f1d 805 return sprintf(buf, "%s\n", mmc_slot(host).name);
a45c6cb8
MC		 806}
807
70a3341a 808static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
a45c6cb8
MC		 809
810/*
811 * Configure the response type and send the cmd.
812 */
813static void
70a3341a 814omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
a45c6cb8
MC		 815 struct mmc_data *data)
816{
817 int cmdreg = 0, resptype = 0, cmdtype = 0;
818
819 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
820 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
821 host->cmd = cmd;
822
93caf8e6 823 omap_hsmmc_enable_irq(host, cmd);
a45c6cb8 824
4a694dc9 825 host->response_busy = 0;
a45c6cb8
MC		 826 if (cmd->flags & MMC_RSP_PRESENT) {
827 if (cmd->flags & MMC_RSP_136)
828 resptype = 1;
4a694dc9
AH		 829 else if (cmd->flags & MMC_RSP_BUSY) {
830 resptype = 3;
831 host->response_busy = 1;
832 } else
a45c6cb8
MC		 833 resptype = 2;
834 }
835
836 /*
837 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
838 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
839 * a val of 0x3, rest 0x0.
840 */
841 if (cmd == host->mrq->stop)
842 cmdtype = 0x3;
843
844 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
845
846 if (data) {
847 cmdreg |= DP_SELECT | MSBS | BCE;
848 if (data->flags & MMC_DATA_READ)
849 cmdreg |= DDIR;
850 else
851 cmdreg &= ~(DDIR);
852 }
853
854 if (host->use_dma)
855 cmdreg |= DMA_EN;
856
b417577d 857 host->req_in_progress = 1;
4dffd7a2 858
a45c6cb8
MC		 859 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
860 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
861}
862
0ccd76d4 863static int
70a3341a 864omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
0ccd76d4
JY		 865{
866 if (data->flags & MMC_DATA_WRITE)
867 return DMA_TO_DEVICE;
868 else
869 return DMA_FROM_DEVICE;
870}
871
b417577d
AH		 872static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
873{
874 int dma_ch;
875
876 spin_lock(&host->irq_lock);
877 host->req_in_progress = 0;
878 dma_ch = host->dma_ch;
879 spin_unlock(&host->irq_lock);
880
881 omap_hsmmc_disable_irq(host);
882 /* Do not complete the request if DMA is still in progress */
883 if (mrq->data && host->use_dma && dma_ch != -1)
884 return;
885 host->mrq = NULL;
886 mmc_request_done(host->mmc, mrq);
887}
888
a45c6cb8
MC		 889/*
890 * Notify the transfer complete to MMC core
891 */
892static void
70a3341a 893omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
a45c6cb8 894{
4a694dc9
AH		 895 if (!data) {
896 struct mmc_request *mrq = host->mrq;
897
23050103
AH		 898 /* TC before CC from CMD6 - don't know why, but it happens */
899 if (host->cmd && host->cmd->opcode == 6 &&
900 host->response_busy) {
901 host->response_busy = 0;
902 return;
903 }
904
b417577d 905 omap_hsmmc_request_done(host, mrq);
4a694dc9
AH		 906 return;
907 }
908
a45c6cb8
MC		 909 host->data = NULL;
910
a45c6cb8
MC		 911 if (!data->error)
912 data->bytes_xfered += data->blocks * (data->blksz);
913 else
914 data->bytes_xfered = 0;
915
916 if (!data->stop) {
b417577d 917 omap_hsmmc_request_done(host, data->mrq);
a45c6cb8
MC		 918 return;
919 }
70a3341a 920 omap_hsmmc_start_command(host, data->stop, NULL);
a45c6cb8
MC		 921}
922
923/*
924 * Notify the core about command completion
925 */
926static void
70a3341a 927omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
a45c6cb8
MC		 928{
929 host->cmd = NULL;
930
931 if (cmd->flags & MMC_RSP_PRESENT) {
932 if (cmd->flags & MMC_RSP_136) {
933 /* response type 2 */
934 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
935 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
936 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
937 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
938 } else {
939 /* response types 1, 1b, 3, 4, 5, 6 */
940 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
941 }
942 }
b417577d
AH		 943 if ((host->data == NULL && !host->response_busy) || cmd->error)
944 omap_hsmmc_request_done(host, cmd->mrq);
a45c6cb8
MC		 945}
946
947/*
948 * DMA clean up for command errors
949 */
70a3341a 950static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
a45c6cb8 951{
b417577d
AH		 952 int dma_ch;
953
82788ff5 954 host->data->error = errno;
a45c6cb8 955
b417577d
AH		 956 spin_lock(&host->irq_lock);
957 dma_ch = host->dma_ch;
958 host->dma_ch = -1;
959 spin_unlock(&host->irq_lock);
960
961 if (host->use_dma && dma_ch != -1) {
a45c6cb8 962 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
70a3341a 963 omap_hsmmc_get_dma_dir(host, host->data));
b417577d 964 omap_free_dma(dma_ch);
a45c6cb8
MC		 965 }
966 host->data = NULL;
a45c6cb8
MC		 967}
968
969/*
970 * Readable error output
971 */
972#ifdef CONFIG_MMC_DEBUG
70a3341a 973static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status)
a45c6cb8
MC		 974{
975 /* --- means reserved bit without definition at documentation */
70a3341a 976 static const char *omap_hsmmc_status_bits[] = {
a45c6cb8
MC		 977 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
978 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
979 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
980 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
981 };
982 char res[256];
983 char *buf = res;
984 int len, i;
985
986 len = sprintf(buf, "MMC IRQ 0x%x :", status);
987 buf += len;
988
70a3341a 989 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
a45c6cb8 990 if (status & (1 << i)) {
70a3341a 991 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
a45c6cb8
MC		 992 buf += len;
993 }
994
995 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
996}
997#endif /* CONFIG_MMC_DEBUG */
998
3ebf74b1
JP		 999/*
1000 * MMC controller internal state machines reset
1001 *
1002 * Used to reset command or data internal state machines, using respectively
1003 * SRC or SRD bit of SYSCTL register
1004 * Can be called from interrupt context
1005 */
70a3341a
DK		 1006static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1007 unsigned long bit)
3ebf74b1
JP		 1008{
1009 unsigned long i = 0;
1010 unsigned long limit = (loops_per_jiffy *
1011 msecs_to_jiffies(MMC_TIMEOUT_MS));
1012
1013 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1014 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1015
07ad64b6
MC		 1016 /*
1017 * OMAP4 ES2 and greater has an updated reset logic.
1018 * Monitor a 0->1 transition first
1019 */
1020 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
b432b4b3 1021 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
07ad64b6
MC		 1022 && (i++ < limit))
1023 cpu_relax();
1024 }
1025 i = 0;
1026
3ebf74b1
JP		 1027 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1028 (i++ < limit))
1029 cpu_relax();
1030
1031 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1032 dev_err(mmc_dev(host->mmc),
1033 "Timeout waiting on controller reset in %s\n",
1034 __func__);
1035}
a45c6cb8 1036
b417577d 1037static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
a45c6cb8 1038{
a45c6cb8 1039 struct mmc_data *data;
b417577d
AH		 1040 int end_cmd = 0, end_trans = 0;
1041
1042 if (!host->req_in_progress) {
1043 do {
1044 OMAP_HSMMC_WRITE(host->base, STAT, status);
1045 /* Flush posted write */
1046 status = OMAP_HSMMC_READ(host->base, STAT);
1047 } while (status & INT_EN_MASK);
1048 return;
a45c6cb8
MC		 1049 }
1050
1051 data = host->data;
a45c6cb8
MC		 1052 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1053
1054 if (status & ERR) {
1055#ifdef CONFIG_MMC_DEBUG
70a3341a 1056 omap_hsmmc_report_irq(host, status);
a45c6cb8
MC		 1057#endif
1058 if ((status & CMD_TIMEOUT) ||
1059 (status & CMD_CRC)) {
1060 if (host->cmd) {
1061 if (status & CMD_TIMEOUT) {
70a3341a
DK		 1062 omap_hsmmc_reset_controller_fsm(host,
1063 SRC);
a45c6cb8
MC		 1064 host->cmd->error = -ETIMEDOUT;
1065 } else {
1066 host->cmd->error = -EILSEQ;
1067 }
1068 end_cmd = 1;
1069 }
4a694dc9
AH		 1070 if (host->data || host->response_busy) {
1071 if (host->data)
70a3341a
DK		 1072 omap_hsmmc_dma_cleanup(host,
1073 -ETIMEDOUT);
4a694dc9 1074 host->response_busy = 0;
70a3341a 1075 omap_hsmmc_reset_controller_fsm(host, SRD);
c232f457 1076 }
a45c6cb8
MC		 1077 }
1078 if ((status & DATA_TIMEOUT) ||
1079 (status & DATA_CRC)) {
4a694dc9
AH		 1080 if (host->data || host->response_busy) {
1081 int err = (status & DATA_TIMEOUT) ?
1082 -ETIMEDOUT : -EILSEQ;
1083
1084 if (host->data)
70a3341a 1085 omap_hsmmc_dma_cleanup(host, err);
a45c6cb8 1086 else
4a694dc9
AH		 1087 host->mrq->cmd->error = err;
1088 host->response_busy = 0;
70a3341a 1089 omap_hsmmc_reset_controller_fsm(host, SRD);
a45c6cb8
MC		 1090 end_trans = 1;
1091 }
1092 }
1093 if (status & CARD_ERR) {
1094 dev_dbg(mmc_dev(host->mmc),
1095 "Ignoring card err CMD%d\n", host->cmd->opcode);
1096 if (host->cmd)
1097 end_cmd = 1;
1098 if (host->data)
1099 end_trans = 1;
1100 }
1101 }
1102
1103 OMAP_HSMMC_WRITE(host->base, STAT, status);
1104
a8fe29d8 1105 if (end_cmd || ((status & CC) && host->cmd))
70a3341a 1106 omap_hsmmc_cmd_done(host, host->cmd);
0a40e647 1107 if ((end_trans || (status & TC)) && host->mrq)
70a3341a 1108 omap_hsmmc_xfer_done(host, data);
b417577d 1109}
a45c6cb8 1110
b417577d
AH		 1111/*
1112 * MMC controller IRQ handler
1113 */
1114static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1115{
1116 struct omap_hsmmc_host *host = dev_id;
1117 int status;
1118
1119 status = OMAP_HSMMC_READ(host->base, STAT);
1120 do {
1121 omap_hsmmc_do_irq(host, status);
1122 /* Flush posted write */
1123 status = OMAP_HSMMC_READ(host->base, STAT);
1124 } while (status & INT_EN_MASK);
4dffd7a2 1125
a45c6cb8
MC		 1126 return IRQ_HANDLED;
1127}
1128
70a3341a 1129static void set_sd_bus_power(struct omap_hsmmc_host *host)
e13bb300
AH		 1130{
1131 unsigned long i;
1132
1133 OMAP_HSMMC_WRITE(host->base, HCTL,
1134 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1135 for (i = 0; i < loops_per_jiffy; i++) {
1136 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1137 break;
1138 cpu_relax();
1139 }
1140}
1141
a45c6cb8 1142/*
eb250826
DB		 1143 * Switch MMC interface voltage ... only relevant for MMC1.
1144 *
1145 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1146 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1147 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8 1148 */
70a3341a 1149static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
a45c6cb8
MC		 1150{
1151 u32 reg_val = 0;
1152 int ret;
1153
1154 /* Disable the clocks */
1155 clk_disable(host->fclk);
1156 clk_disable(host->iclk);
2bec0893
AH		 1157 if (host->got_dbclk)
1158 clk_disable(host->dbclk);
a45c6cb8
MC		 1159
1160 /* Turn the power off */
1161 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
a45c6cb8
MC		 1162
1163 /* Turn the power ON with given VDD 1.8 or 3.0v */
2bec0893
AH		 1164 if (!ret)
1165 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1166 vdd);
1167 clk_enable(host->iclk);
1168 clk_enable(host->fclk);
1169 if (host->got_dbclk)
1170 clk_enable(host->dbclk);
1171
a45c6cb8
MC		 1172 if (ret != 0)
1173 goto err;
1174
a45c6cb8
MC		 1175 OMAP_HSMMC_WRITE(host->base, HCTL,
1176 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1177 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 1178
a45c6cb8
MC		 1179 /*
1180 * If a MMC dual voltage card is detected, the set_ios fn calls
1181 * this fn with VDD bit set for 1.8V. Upon card removal from the
70a3341a 1182 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
a45c6cb8 1183 *
eb250826
DB		 1184 * Cope with a bit of slop in the range ... per data sheets:
1185 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1186 * but recommended values are 1.71V to 1.89V
1187 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1188 * but recommended values are 2.7V to 3.3V
1189 *
1190 * Board setup code shouldn't permit anything very out-of-range.
1191 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1192 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 1193 */
eb250826 1194 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 1195 reg_val |= SDVS18;
eb250826
DB		 1196 else
1197 reg_val |= SDVS30;
a45c6cb8
MC		 1198
1199 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 1200 set_sd_bus_power(host);
a45c6cb8
MC		 1201
1202 return 0;
1203err:
1204 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1205 return ret;
1206}
1207
b62f6228
AH		 1208/* Protect the card while the cover is open */
1209static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1210{
1211 if (!mmc_slot(host).get_cover_state)
1212 return;
1213
1214 host->reqs_blocked = 0;
1215 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1216 if (host->protect_card) {
1217 printk(KERN_INFO "%s: cover is closed, "
1218 "card is now accessible\n",
1219 mmc_hostname(host->mmc));
1220 host->protect_card = 0;
1221 }
1222 } else {
1223 if (!host->protect_card) {
1224 printk(KERN_INFO "%s: cover is open, "
1225 "card is now inaccessible\n",
1226 mmc_hostname(host->mmc));
1227 host->protect_card = 1;
1228 }
1229 }
1230}
1231
a45c6cb8
MC		 1232/*
1233 * Work Item to notify the core about card insertion/removal
1234 */
70a3341a 1235static void omap_hsmmc_detect(struct work_struct *work)
a45c6cb8 1236{
70a3341a
DK		 1237 struct omap_hsmmc_host *host =
1238 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
249d0fa9 1239 struct omap_mmc_slot_data *slot = &mmc_slot(host);
a6b2240d
AH		 1240 int carddetect;
1241
1242 if (host->suspended)
1243 return;
1244
1245 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
249d0fa9 1246
191d1f1d 1247 if (slot->card_detect)
db0fefc5 1248 carddetect = slot->card_detect(host->dev, host->slot_id);
b62f6228
AH		 1249 else {
1250 omap_hsmmc_protect_card(host);
a6b2240d 1251 carddetect = -ENOSYS;
b62f6228 1252 }
a45c6cb8 1253
cdeebadd 1254 if (carddetect)
a45c6cb8 1255 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
cdeebadd 1256 else
a45c6cb8 1257 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
a45c6cb8
MC		 1258}
1259
1260/*
1261 * ISR for handling card insertion and removal
1262 */
70a3341a 1263static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
a45c6cb8 1264{
70a3341a 1265 struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
a45c6cb8 1266
a6b2240d
AH		 1267 if (host->suspended)
1268 return IRQ_HANDLED;
a45c6cb8
MC		 1269 schedule_work(&host->mmc_carddetect_work);
1270
1271 return IRQ_HANDLED;
1272}
1273
70a3341a 1274static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1275 struct mmc_data *data)
1276{
1277 int sync_dev;
1278
f3e2f1dd
GI		 1279 if (data->flags & MMC_DATA_WRITE)
1280 sync_dev = host->dma_line_tx;
1281 else
1282 sync_dev = host->dma_line_rx;
0ccd76d4
JY		 1283 return sync_dev;
1284}
1285
70a3341a 1286static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1287 struct mmc_data *data,
1288 struct scatterlist *sgl)
1289{
1290 int blksz, nblk, dma_ch;
1291
1292 dma_ch = host->dma_ch;
1293 if (data->flags & MMC_DATA_WRITE) {
1294 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1295 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1296 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1297 sg_dma_address(sgl), 0, 0);
1298 } else {
1299 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
191d1f1d 1300 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
0ccd76d4
JY		 1301 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1302 sg_dma_address(sgl), 0, 0);
1303 }
1304
1305 blksz = host->data->blksz;
1306 nblk = sg_dma_len(sgl) / blksz;
1307
1308 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1309 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
70a3341a 1310 omap_hsmmc_get_dma_sync_dev(host, data),
0ccd76d4
JY		 1311 !(data->flags & MMC_DATA_WRITE));
1312
1313 omap_start_dma(dma_ch);
1314}
1315
a45c6cb8
MC		 1316/*
1317 * DMA call back function
1318 */
b417577d 1319static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
a45c6cb8 1320{
b417577d
AH		 1321 struct omap_hsmmc_host *host = cb_data;
1322 struct mmc_data *data = host->mrq->data;
1323 int dma_ch, req_in_progress;
a45c6cb8 1324
f3584e5e
V		 1325 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1326 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1327 ch_status);
1328 return;
1329 }
a45c6cb8 1330
b417577d
AH		 1331 spin_lock(&host->irq_lock);
1332 if (host->dma_ch < 0) {
1333 spin_unlock(&host->irq_lock);
a45c6cb8 1334 return;
b417577d 1335 }
a45c6cb8 1336
0ccd76d4
JY		 1337 host->dma_sg_idx++;
1338 if (host->dma_sg_idx < host->dma_len) {
1339 /* Fire up the next transfer. */
b417577d
AH		 1340 omap_hsmmc_config_dma_params(host, data,
1341 data->sg + host->dma_sg_idx);
1342 spin_unlock(&host->irq_lock);
0ccd76d4
JY		 1343 return;
1344 }
1345
b417577d
AH		 1346 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
1347 omap_hsmmc_get_dma_dir(host, data));
1348
1349 req_in_progress = host->req_in_progress;
1350 dma_ch = host->dma_ch;
a45c6cb8 1351 host->dma_ch = -1;
b417577d
AH		 1352 spin_unlock(&host->irq_lock);
1353
1354 omap_free_dma(dma_ch);
1355
1356 /* If DMA has finished after TC, complete the request */
1357 if (!req_in_progress) {
1358 struct mmc_request *mrq = host->mrq;
1359
1360 host->mrq = NULL;
1361 mmc_request_done(host->mmc, mrq);
1362 }
a45c6cb8
MC		 1363}
1364
a45c6cb8
MC		 1365/*
1366 * Routine to configure and start DMA for the MMC card
1367 */
70a3341a
DK		 1368static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1369 struct mmc_request *req)
a45c6cb8 1370{
b417577d 1371 int dma_ch = 0, ret = 0, i;
a45c6cb8
MC		 1372 struct mmc_data *data = req->data;
1373
0ccd76d4 1374 /* Sanity check: all the SG entries must be aligned by block size. */
a3f406f8 1375 for (i = 0; i < data->sg_len; i++) {
0ccd76d4
JY		 1376 struct scatterlist *sgl;
1377
1378 sgl = data->sg + i;
1379 if (sgl->length % data->blksz)
1380 return -EINVAL;
1381 }
1382 if ((data->blksz % 4) != 0)
1383 /* REVISIT: The MMC buffer increments only when MSB is written.
1384 * Return error for blksz which is non multiple of four.
1385 */
1386 return -EINVAL;
1387
b417577d 1388 BUG_ON(host->dma_ch != -1);
a45c6cb8 1389
70a3341a
DK		 1390 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1391 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
a45c6cb8 1392 if (ret != 0) {
0ccd76d4 1393 dev_err(mmc_dev(host->mmc),
a45c6cb8
MC		 1394 "%s: omap_request_dma() failed with %d\n",
1395 mmc_hostname(host->mmc), ret);
1396 return ret;
1397 }
1398
1399 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
70a3341a 1400 data->sg_len, omap_hsmmc_get_dma_dir(host, data));
a45c6cb8 1401 host->dma_ch = dma_ch;
0ccd76d4 1402 host->dma_sg_idx = 0;
a45c6cb8 1403
70a3341a 1404 omap_hsmmc_config_dma_params(host, data, data->sg);
a45c6cb8 1405
a45c6cb8
MC		 1406 return 0;
1407}
1408
70a3341a 1409static void set_data_timeout(struct omap_hsmmc_host *host,
e2bf08d6
AH		 1410 unsigned int timeout_ns,
1411 unsigned int timeout_clks)
a45c6cb8
MC		 1412{
1413 unsigned int timeout, cycle_ns;
1414 uint32_t reg, clkd, dto = 0;
1415
1416 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1417 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1418 if (clkd == 0)
1419 clkd = 1;
1420
1421 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
e2bf08d6
AH		 1422 timeout = timeout_ns / cycle_ns;
1423 timeout += timeout_clks;
a45c6cb8
MC		 1424 if (timeout) {
1425 while ((timeout & 0x80000000) == 0) {
1426 dto += 1;
1427 timeout <<= 1;
1428 }
1429 dto = 31 - dto;
1430 timeout <<= 1;
1431 if (timeout && dto)
1432 dto += 1;
1433 if (dto >= 13)
1434 dto -= 13;
1435 else
1436 dto = 0;
1437 if (dto > 14)
1438 dto = 14;
1439 }
1440
1441 reg &= ~DTO_MASK;
1442 reg |= dto << DTO_SHIFT;
1443 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1444}
1445
1446/*
1447 * Configure block length for MMC/SD cards and initiate the transfer.
1448 */
1449static int
70a3341a 1450omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
a45c6cb8
MC		 1451{
1452 int ret;
1453 host->data = req->data;
1454
1455 if (req->data == NULL) {
a45c6cb8 1456 OMAP_HSMMC_WRITE(host->base, BLK, 0);
e2bf08d6
AH		 1457 /*
1458 * Set an arbitrary 100ms data timeout for commands with
1459 * busy signal.
1460 */
1461 if (req->cmd->flags & MMC_RSP_BUSY)
1462 set_data_timeout(host, 100000000U, 0);
a45c6cb8
MC		 1463 return 0;
1464 }
1465
1466 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1467 | (req->data->blocks << 16));
e2bf08d6 1468 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
a45c6cb8 1469
a45c6cb8 1470 if (host->use_dma) {
70a3341a 1471 ret = omap_hsmmc_start_dma_transfer(host, req);
a45c6cb8
MC		 1472 if (ret != 0) {
1473 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1474 return ret;
1475 }
1476 }
1477 return 0;
1478}
1479
1480/*
1481 * Request function. for read/write operation
1482 */
70a3341a 1483static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
a45c6cb8 1484{
70a3341a 1485 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3f406f8 1486 int err;
a45c6cb8 1487
b417577d
AH		 1488 BUG_ON(host->req_in_progress);
1489 BUG_ON(host->dma_ch != -1);
1490 if (host->protect_card) {
1491 if (host->reqs_blocked < 3) {
1492 /*
1493 * Ensure the controller is left in a consistent
1494 * state by resetting the command and data state
1495 * machines.
1496 */
1497 omap_hsmmc_reset_controller_fsm(host, SRD);
1498 omap_hsmmc_reset_controller_fsm(host, SRC);
1499 host->reqs_blocked += 1;
1500 }
1501 req->cmd->error = -EBADF;
1502 if (req->data)
1503 req->data->error = -EBADF;
1504 req->cmd->retries = 0;
1505 mmc_request_done(mmc, req);
1506 return;
1507 } else if (host->reqs_blocked)
1508 host->reqs_blocked = 0;
a45c6cb8
MC		 1509 WARN_ON(host->mrq != NULL);
1510 host->mrq = req;
70a3341a 1511 err = omap_hsmmc_prepare_data(host, req);
a3f406f8
JL		 1512 if (err) {
1513 req->cmd->error = err;
1514 if (req->data)
1515 req->data->error = err;
1516 host->mrq = NULL;
1517 mmc_request_done(mmc, req);
1518 return;
1519 }
1520
70a3341a 1521 omap_hsmmc_start_command(host, req->cmd, req->data);
a45c6cb8
MC		 1522}
1523
a45c6cb8 1524/* Routine to configure clock values. Exposed API to core */
70a3341a 1525static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
a45c6cb8 1526{
70a3341a 1527 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8
MC		 1528 u16 dsor = 0;
1529 unsigned long regval;
1530 unsigned long timeout;
73153010 1531 u32 con;
a3621465 1532 int do_send_init_stream = 0;
a45c6cb8 1533
5e2ea617
AH		 1534 mmc_host_enable(host->mmc);
1535
a3621465
AH		 1536 if (ios->power_mode != host->power_mode) {
1537 switch (ios->power_mode) {
1538 case MMC_POWER_OFF:
1539 mmc_slot(host).set_power(host->dev, host->slot_id,
1540 0, 0);
623821f7 1541 host->vdd = 0;
a3621465
AH		 1542 break;
1543 case MMC_POWER_UP:
1544 mmc_slot(host).set_power(host->dev, host->slot_id,
1545 1, ios->vdd);
623821f7 1546 host->vdd = ios->vdd;
a3621465
AH		 1547 break;
1548 case MMC_POWER_ON:
1549 do_send_init_stream = 1;
1550 break;
1551 }
1552 host->power_mode = ios->power_mode;
a45c6cb8
MC		 1553 }
1554
dd498eff
DK		 1555 /* FIXME: set registers based only on changes to ios */
1556
73153010 1557 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 1558 switch (mmc->ios.bus_width) {
73153010
JL		 1559 case MMC_BUS_WIDTH_8:
1560 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1561 break;
a45c6cb8 1562 case MMC_BUS_WIDTH_4:
73153010 1563 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 1564 OMAP_HSMMC_WRITE(host->base, HCTL,
1565 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1566 break;
1567 case MMC_BUS_WIDTH_1:
73153010 1568 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 1569 OMAP_HSMMC_WRITE(host->base, HCTL,
1570 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1571 break;
1572 }
1573
4621d5f8 1574 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
eb250826
DB		 1575 /* Only MMC1 can interface at 3V without some flavor
1576 * of external transceiver; but they all handle 1.8V.
1577 */
a45c6cb8
MC		 1578 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1579 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1580 /*
1581 * The mmc_select_voltage fn of the core does
1582 * not seem to set the power_mode to
1583 * MMC_POWER_UP upon recalculating the voltage.
1584 * vdd 1.8v.
1585 */
70a3341a
DK		 1586 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1587 dev_dbg(mmc_dev(host->mmc),
a45c6cb8
MC		 1588 "Switch operation failed\n");
1589 }
1590 }
1591
1592 if (ios->clock) {
1593 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1594 if (dsor < 1)
1595 dsor = 1;
1596
1597 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1598 dsor++;
1599
1600 if (dsor > 250)
1601 dsor = 250;
1602 }
70a3341a 1603 omap_hsmmc_stop_clock(host);
a45c6cb8
MC		 1604 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1605 regval = regval & ~(CLKD_MASK);
1606 regval = regval | (dsor << 6) | (DTO << 16);
1607 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1608 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1609 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1610
1611 /* Wait till the ICS bit is set */
1612 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
11dd62a7 1613 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
a45c6cb8
MC		 1614 && time_before(jiffies, timeout))
1615 msleep(1);
1616
1617 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1618 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1619
a3621465 1620 if (do_send_init_stream)
a45c6cb8
MC		 1621 send_init_stream(host);
1622
abb28e73 1623 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 1624 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
abb28e73
DK		 1625 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1626 else
1627 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
5e2ea617 1628
dd498eff
DK		 1629 if (host->power_mode == MMC_POWER_OFF)
1630 mmc_host_disable(host->mmc);
1631 else
1632 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 1633}
1634
1635static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1636{
70a3341a 1637 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1638
191d1f1d 1639 if (!mmc_slot(host).card_detect)
a45c6cb8 1640 return -ENOSYS;
db0fefc5 1641 return mmc_slot(host).card_detect(host->dev, host->slot_id);
a45c6cb8
MC		 1642}
1643
1644static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1645{
70a3341a 1646 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1647
191d1f1d 1648 if (!mmc_slot(host).get_ro)
a45c6cb8 1649 return -ENOSYS;
191d1f1d 1650 return mmc_slot(host).get_ro(host->dev, 0);
a45c6cb8
MC		 1651}
1652
4816858c
GI		 1653static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1654{
1655 struct omap_hsmmc_host *host = mmc_priv(mmc);
1656
1657 if (mmc_slot(host).init_card)
1658 mmc_slot(host).init_card(card);
1659}
1660
70a3341a 1661static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1b331e69
KK		 1662{
1663 u32 hctl, capa, value;
1664
1665 /* Only MMC1 supports 3.0V */
4621d5f8 1666 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1b331e69
KK		 1667 hctl = SDVS30;
1668 capa = VS30 | VS18;
1669 } else {
1670 hctl = SDVS18;
1671 capa = VS18;
1672 }
1673
1674 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1675 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1676
1677 value = OMAP_HSMMC_READ(host->base, CAPA);
1678 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1679
1680 /* Set the controller to AUTO IDLE mode */
1681 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1682 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1683
1684 /* Set SD bus power bit */
e13bb300 1685 set_sd_bus_power(host);
1b331e69
KK		 1686}
1687
dd498eff
DK		 1688/*
1689 * Dynamic power saving handling, FSM:
13189e78
JL		 1690 * ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF
1691 * ^___________| | |
1692 * |______________________|______________________|
dd498eff
DK		 1693 *
1694 * ENABLED: mmc host is fully functional
1695 * DISABLED: fclk is off
13189e78
JL		 1696 * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep
1697 * REGSLEEP: fclk is off, voltage regulator is asleep
1698 * OFF: fclk is off, voltage regulator is off
dd498eff
DK		 1699 *
1700 * Transition handlers return the timeout for the next state transition
1701 * or negative error.
1702 */
1703
13189e78 1704enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF};
dd498eff
DK		 1705
1706/* Handler for [ENABLED -> DISABLED] transition */
70a3341a 1707static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host)
dd498eff 1708{
70a3341a 1709 omap_hsmmc_context_save(host);
dd498eff
DK		 1710 clk_disable(host->fclk);
1711 host->dpm_state = DISABLED;
1712
1713 dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n");
1714
1715 if (host->power_mode == MMC_POWER_OFF)
1716 return 0;
1717
4380eea2 1718 return OMAP_MMC_SLEEP_TIMEOUT;
dd498eff
DK		 1719}
1720
13189e78 1721/* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */
70a3341a 1722static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host)
dd498eff 1723{
13189e78 1724 int err, new_state;
dd498eff
DK		 1725
1726 if (!mmc_try_claim_host(host->mmc))
1727 return 0;
1728
1729 clk_enable(host->fclk);
70a3341a 1730 omap_hsmmc_context_restore(host);
13189e78
JL		 1731 if (mmc_card_can_sleep(host->mmc)) {
1732 err = mmc_card_sleep(host->mmc);
1733 if (err < 0) {
1734 clk_disable(host->fclk);
1735 mmc_release_host(host->mmc);
1736 return err;
1737 }
1738 new_state = CARDSLEEP;
70a3341a 1739 } else {
13189e78 1740 new_state = REGSLEEP;
70a3341a 1741 }
13189e78
JL		 1742 if (mmc_slot(host).set_sleep)
1743 mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0,
1744 new_state == CARDSLEEP);
1745 /* FIXME: turn off bus power and perhaps interrupts too */
1746 clk_disable(host->fclk);
1747 host->dpm_state = new_state;
1748
1749 mmc_release_host(host->mmc);
1750
1751 dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n",
1752 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
dd498eff 1753
1df58db8
AH		 1754 if (mmc_slot(host).no_off)
1755 return 0;
1756
dd498eff
DK		 1757 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1758 mmc_slot(host).card_detect ||
1759 (mmc_slot(host).get_cover_state &&
13189e78 1760 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))
4380eea2 1761 return OMAP_MMC_OFF_TIMEOUT;
13189e78
JL		 1762
1763 return 0;
1764}
1765
1766/* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */
70a3341a 1767static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host)
13189e78
JL		 1768{
1769 if (!mmc_try_claim_host(host->mmc))
1770 return 0;
1771
1df58db8
AH		 1772 if (mmc_slot(host).no_off)
1773 return 0;
1774
13189e78
JL		 1775 if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1776 mmc_slot(host).card_detect ||
1777 (mmc_slot(host).get_cover_state &&
1778 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) {
1779 mmc_release_host(host->mmc);
1780 return 0;
623821f7 1781 }
dd498eff 1782
13189e78
JL		 1783 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1784 host->vdd = 0;
1785 host->power_mode = MMC_POWER_OFF;
dd498eff 1786
13189e78
JL		 1787 dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n",
1788 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
dd498eff 1789
13189e78 1790 host->dpm_state = OFF;
dd498eff
DK		 1791
1792 mmc_release_host(host->mmc);
1793
1794 return 0;
1795}
1796
1797/* Handler for [DISABLED -> ENABLED] transition */
70a3341a 1798static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host *host)
dd498eff
DK		 1799{
1800 int err;
1801
1802 err = clk_enable(host->fclk);
1803 if (err < 0)
1804 return err;
1805
70a3341a 1806 omap_hsmmc_context_restore(host);
dd498eff
DK		 1807 host->dpm_state = ENABLED;
1808
1809 dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n");
1810
1811 return 0;
1812}
1813
13189e78 1814/* Handler for [SLEEP -> ENABLED] transition */
70a3341a 1815static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host)
dd498eff 1816{
13189e78
JL		 1817 if (!mmc_try_claim_host(host->mmc))
1818 return 0;
dd498eff 1819
13189e78 1820 clk_enable(host->fclk);
70a3341a 1821 omap_hsmmc_context_restore(host);
13189e78
JL		 1822 if (mmc_slot(host).set_sleep)
1823 mmc_slot(host).set_sleep(host->dev, host->slot_id, 0,
1824 host->vdd, host->dpm_state == CARDSLEEP);
1825 if (mmc_card_can_sleep(host->mmc))
1826 mmc_card_awake(host->mmc);
1827
1828 dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n",
1829 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
dd498eff
DK		 1830
1831 host->dpm_state = ENABLED;
1832
13189e78 1833 mmc_release_host(host->mmc);
dd498eff
DK		 1834
1835 return 0;
1836}
1837
13189e78 1838/* Handler for [OFF -> ENABLED] transition */
70a3341a 1839static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host *host)
623821f7 1840{
623821f7 1841 clk_enable(host->fclk);
623821f7 1842
70a3341a
DK		 1843 omap_hsmmc_context_restore(host);
1844 omap_hsmmc_conf_bus_power(host);
13189e78 1845 mmc_power_restore_host(host->mmc);
623821f7
AH		 1846
1847 host->dpm_state = ENABLED;
1848
13189e78
JL		 1849 dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n");
1850
623821f7
AH		 1851 return 0;
1852}
1853
dd498eff
DK		 1854/*
1855 * Bring MMC host to ENABLED from any other PM state.
1856 */
70a3341a 1857static int omap_hsmmc_enable(struct mmc_host *mmc)
dd498eff 1858{
70a3341a 1859 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff
DK		 1860
1861 switch (host->dpm_state) {
1862 case DISABLED:
70a3341a 1863 return omap_hsmmc_disabled_to_enabled(host);
13189e78 1864 case CARDSLEEP:
623821f7 1865 case REGSLEEP:
70a3341a 1866 return omap_hsmmc_sleep_to_enabled(host);
dd498eff 1867 case OFF:
70a3341a 1868 return omap_hsmmc_off_to_enabled(host);
dd498eff
DK		 1869 default:
1870 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1871 return -EINVAL;
1872 }
1873}
1874
1875/*
1876 * Bring MMC host in PM state (one level deeper).
1877 */
70a3341a 1878static int omap_hsmmc_disable(struct mmc_host *mmc, int lazy)
dd498eff 1879{
70a3341a 1880 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff
DK		 1881
1882 switch (host->dpm_state) {
1883 case ENABLED: {
1884 int delay;
1885
70a3341a 1886 delay = omap_hsmmc_enabled_to_disabled(host);
dd498eff
DK		 1887 if (lazy || delay < 0)
1888 return delay;
1889 return 0;
1890 }
1891 case DISABLED:
70a3341a 1892 return omap_hsmmc_disabled_to_sleep(host);
13189e78
JL		 1893 case CARDSLEEP:
1894 case REGSLEEP:
70a3341a 1895 return omap_hsmmc_sleep_to_off(host);
dd498eff
DK		 1896 default:
1897 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1898 return -EINVAL;
1899 }
1900}
1901
70a3341a 1902static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
dd498eff 1903{
70a3341a 1904 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff
DK		 1905 int err;
1906
1907 err = clk_enable(host->fclk);
1908 if (err)
1909 return err;
1910 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
70a3341a 1911 omap_hsmmc_context_restore(host);
dd498eff
DK		 1912 return 0;
1913}
1914
70a3341a 1915static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
dd498eff 1916{
70a3341a 1917 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1918
70a3341a 1919 omap_hsmmc_context_save(host);
dd498eff
DK		 1920 clk_disable(host->fclk);
1921 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
1922 return 0;
1923}
1924
70a3341a
DK		 1925static const struct mmc_host_ops omap_hsmmc_ops = {
1926 .enable = omap_hsmmc_enable_fclk,
1927 .disable = omap_hsmmc_disable_fclk,
1928 .request = omap_hsmmc_request,
1929 .set_ios = omap_hsmmc_set_ios,
dd498eff
DK		 1930 .get_cd = omap_hsmmc_get_cd,
1931 .get_ro = omap_hsmmc_get_ro,
4816858c 1932 .init_card = omap_hsmmc_init_card,
dd498eff
DK		 1933 /* NYET -- enable_sdio_irq */
1934};
1935
70a3341a
DK		 1936static const struct mmc_host_ops omap_hsmmc_ps_ops = {
1937 .enable = omap_hsmmc_enable,
1938 .disable = omap_hsmmc_disable,
1939 .request = omap_hsmmc_request,
1940 .set_ios = omap_hsmmc_set_ios,
a45c6cb8
MC		 1941 .get_cd = omap_hsmmc_get_cd,
1942 .get_ro = omap_hsmmc_get_ro,
4816858c 1943 .init_card = omap_hsmmc_init_card,
a45c6cb8
MC		 1944 /* NYET -- enable_sdio_irq */
1945};
1946
d900f712
DK		 1947#ifdef CONFIG_DEBUG_FS
1948
70a3341a 1949static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
d900f712
DK		 1950{
1951 struct mmc_host *mmc = s->private;
70a3341a 1952 struct omap_hsmmc_host *host = mmc_priv(mmc);
11dd62a7
DK		 1953 int context_loss = 0;
1954
70a3341a
DK		 1955 if (host->pdata->get_context_loss_count)
1956 context_loss = host->pdata->get_context_loss_count(host->dev);
d900f712 1957
5e2ea617
AH		 1958 seq_printf(s, "mmc%d:\n"
1959 " enabled:\t%d\n"
dd498eff 1960 " dpm_state:\t%d\n"
5e2ea617 1961 " nesting_cnt:\t%d\n"
11dd62a7 1962 " ctx_loss:\t%d:%d\n"
5e2ea617 1963 "\nregs:\n",
dd498eff
DK		 1964 mmc->index, mmc->enabled ? 1 : 0,
1965 host->dpm_state, mmc->nesting_cnt,
11dd62a7 1966 host->context_loss, context_loss);
5e2ea617 1967
13189e78 1968 if (host->suspended || host->dpm_state == OFF) {
dd498eff
DK		 1969 seq_printf(s, "host suspended, can't read registers\n");
1970 return 0;
1971 }
1972
5e2ea617
AH		 1973 if (clk_enable(host->fclk) != 0) {
1974 seq_printf(s, "can't read the regs\n");
dd498eff 1975 return 0;
5e2ea617 1976 }
d900f712
DK		 1977
1978 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1979 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1980 seq_printf(s, "CON:\t\t0x%08x\n",
1981 OMAP_HSMMC_READ(host->base, CON));
1982 seq_printf(s, "HCTL:\t\t0x%08x\n",
1983 OMAP_HSMMC_READ(host->base, HCTL));
1984 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1985 OMAP_HSMMC_READ(host->base, SYSCTL));
1986 seq_printf(s, "IE:\t\t0x%08x\n",
1987 OMAP_HSMMC_READ(host->base, IE));
1988 seq_printf(s, "ISE:\t\t0x%08x\n",
1989 OMAP_HSMMC_READ(host->base, ISE));
1990 seq_printf(s, "CAPA:\t\t0x%08x\n",
1991 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617
AH		 1992
1993 clk_disable(host->fclk);
dd498eff 1994
d900f712
DK		 1995 return 0;
1996}
1997
70a3341a 1998static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
d900f712 1999{
70a3341a 2000 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
d900f712
DK		 2001}
2002
2003static const struct file_operations mmc_regs_fops = {
70a3341a 2004 .open = omap_hsmmc_regs_open,
d900f712
DK		 2005 .read = seq_read,
2006 .llseek = seq_lseek,
2007 .release = single_release,
2008};
2009
70a3341a 2010static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 2011{
2012 if (mmc->debugfs_root)
2013 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
2014 mmc, &mmc_regs_fops);
2015}
2016
2017#else
2018
70a3341a 2019static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 2020{
2021}
2022
2023#endif
2024
70a3341a 2025static int __init omap_hsmmc_probe(struct platform_device *pdev)
a45c6cb8
MC		 2026{
2027 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
2028 struct mmc_host *mmc;
70a3341a 2029 struct omap_hsmmc_host *host = NULL;
a45c6cb8 2030 struct resource *res;
db0fefc5 2031 int ret, irq;
a45c6cb8
MC		 2032
2033 if (pdata == NULL) {
2034 dev_err(&pdev->dev, "Platform Data is missing\n");
2035 return -ENXIO;
2036 }
2037
2038 if (pdata->nr_slots == 0) {
2039 dev_err(&pdev->dev, "No Slots\n");
2040 return -ENXIO;
2041 }
2042
2043 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2044 irq = platform_get_irq(pdev, 0);
2045 if (res == NULL || irq < 0)
2046 return -ENXIO;
2047
91a0b089 2048 res->start += pdata->reg_offset;
2049 res->end += pdata->reg_offset;
984b203a 2050 res = request_mem_region(res->start, resource_size(res), pdev->name);
a45c6cb8
MC		 2051 if (res == NULL)
2052 return -EBUSY;
2053
db0fefc5
AH		 2054 ret = omap_hsmmc_gpio_init(pdata);
2055 if (ret)
2056 goto err;
2057
70a3341a 2058 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
a45c6cb8
MC		 2059 if (!mmc) {
2060 ret = -ENOMEM;
db0fefc5 2061 goto err_alloc;
a45c6cb8
MC		 2062 }
2063
2064 host = mmc_priv(mmc);
2065 host->mmc = mmc;
2066 host->pdata = pdata;
2067 host->dev = &pdev->dev;
2068 host->use_dma = 1;
2069 host->dev->dma_mask = &pdata->dma_mask;
2070 host->dma_ch = -1;
2071 host->irq = irq;
2072 host->id = pdev->id;
2073 host->slot_id = 0;
2074 host->mapbase = res->start;
2075 host->base = ioremap(host->mapbase, SZ_4K);
6da20c89 2076 host->power_mode = MMC_POWER_OFF;
a45c6cb8
MC		 2077
2078 platform_set_drvdata(pdev, host);
70a3341a 2079 INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
a45c6cb8 2080
191d1f1d 2081 if (mmc_slot(host).power_saving)
70a3341a 2082 mmc->ops = &omap_hsmmc_ps_ops;
dd498eff 2083 else
70a3341a 2084 mmc->ops = &omap_hsmmc_ops;
dd498eff 2085
e0eb2424
AH		 2086 /*
2087 * If regulator_disable can only put vcc_aux to sleep then there is
2088 * no off state.
2089 */
2090 if (mmc_slot(host).vcc_aux_disable_is_sleep)
2091 mmc_slot(host).no_off = 1;
2092
a45c6cb8
MC		 2093 mmc->f_min = 400000;
2094 mmc->f_max = 52000000;
2095
4dffd7a2 2096 spin_lock_init(&host->irq_lock);
a45c6cb8 2097
6f7607cc 2098 host->iclk = clk_get(&pdev->dev, "ick");
a45c6cb8
MC		 2099 if (IS_ERR(host->iclk)) {
2100 ret = PTR_ERR(host->iclk);
2101 host->iclk = NULL;
2102 goto err1;
2103 }
6f7607cc 2104 host->fclk = clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 2105 if (IS_ERR(host->fclk)) {
2106 ret = PTR_ERR(host->fclk);
2107 host->fclk = NULL;
2108 clk_put(host->iclk);
2109 goto err1;
2110 }
2111
70a3341a 2112 omap_hsmmc_context_save(host);
11dd62a7 2113
5e2ea617 2114 mmc->caps |= MMC_CAP_DISABLE;
dd498eff
DK		 2115 mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT);
2116 /* we start off in DISABLED state */
2117 host->dpm_state = DISABLED;
2118
a05dcdb9 2119 if (clk_enable(host->iclk) != 0) {
a45c6cb8
MC		 2120 clk_put(host->iclk);
2121 clk_put(host->fclk);
2122 goto err1;
2123 }
2124
a05dcdb9
PW		 2125 if (mmc_host_enable(host->mmc) != 0) {
2126 clk_disable(host->iclk);
a45c6cb8
MC		 2127 clk_put(host->iclk);
2128 clk_put(host->fclk);
2129 goto err1;
2130 }
2131
2bec0893
AH		 2132 if (cpu_is_omap2430()) {
2133 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
2134 /*
2135 * MMC can still work without debounce clock.
2136 */
2137 if (IS_ERR(host->dbclk))
2138 dev_warn(mmc_dev(host->mmc),
2139 "Failed to get debounce clock\n");
a45c6cb8 2140 else
2bec0893
AH		 2141 host->got_dbclk = 1;
2142
2143 if (host->got_dbclk)
2144 if (clk_enable(host->dbclk) != 0)
2145 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
2146 " clk failed\n");
2147 }
a45c6cb8 2148
0ccd76d4
JY		 2149 /* Since we do only SG emulation, we can have as many segs
2150 * as we want. */
a36274e0 2151 mmc->max_segs = 1024;
0ccd76d4 2152
a45c6cb8
MC		 2153 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
2154 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
2155 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2156 mmc->max_seg_size = mmc->max_req_size;
2157
13189e78 2158 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
93caf8e6 2159 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
a45c6cb8 2160
3a63833e
SG		 2161 mmc->caps |= mmc_slot(host).caps;
2162 if (mmc->caps & MMC_CAP_8_BIT_DATA)
a45c6cb8
MC		 2163 mmc->caps |= MMC_CAP_4_BIT_DATA;
2164
191d1f1d 2165 if (mmc_slot(host).nonremovable)
23d99bb9
AH		 2166 mmc->caps |= MMC_CAP_NONREMOVABLE;
2167
70a3341a 2168 omap_hsmmc_conf_bus_power(host);
a45c6cb8 2169
f3e2f1dd
GI		 2170 /* Select DMA lines */
2171 switch (host->id) {
2172 case OMAP_MMC1_DEVID:
2173 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
2174 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
2175 break;
2176 case OMAP_MMC2_DEVID:
2177 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
2178 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
2179 break;
2180 case OMAP_MMC3_DEVID:
2181 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2182 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2183 break;
82cf818d 2184 case OMAP_MMC4_DEVID:
2185 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2186 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2187 break;
2188 case OMAP_MMC5_DEVID:
2189 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2190 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2191 break;
f3e2f1dd
GI		 2192 default:
2193 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2194 goto err_irq;
2195 }
a45c6cb8
MC		 2196
2197 /* Request IRQ for MMC operations */
70a3341a 2198 ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED,
a45c6cb8
MC		 2199 mmc_hostname(mmc), host);
2200 if (ret) {
2201 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2202 goto err_irq;
2203 }
2204
2205 if (pdata->init != NULL) {
2206 if (pdata->init(&pdev->dev) != 0) {
70a3341a
DK		 2207 dev_dbg(mmc_dev(host->mmc),
2208 "Unable to configure MMC IRQs\n");
a45c6cb8
MC		 2209 goto err_irq_cd_init;
2210 }
2211 }
db0fefc5 2212
b702b106 2213 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
db0fefc5
AH		 2214 ret = omap_hsmmc_reg_get(host);
2215 if (ret)
2216 goto err_reg;
2217 host->use_reg = 1;
2218 }
2219
b583f26d 2220 mmc->ocr_avail = mmc_slot(host).ocr_mask;
a45c6cb8
MC		 2221
2222 /* Request IRQ for card detect */
e1a55f5e 2223 if ((mmc_slot(host).card_detect_irq)) {
a45c6cb8 2224 ret = request_irq(mmc_slot(host).card_detect_irq,
70a3341a 2225 omap_hsmmc_cd_handler,
a45c6cb8
MC		 2226 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2227 | IRQF_DISABLED,
2228 mmc_hostname(mmc), host);
2229 if (ret) {
2230 dev_dbg(mmc_dev(host->mmc),
2231 "Unable to grab MMC CD IRQ\n");
2232 goto err_irq_cd;
2233 }
72f2e2c7 2234 pdata->suspend = omap_hsmmc_suspend_cdirq;
2235 pdata->resume = omap_hsmmc_resume_cdirq;
a45c6cb8
MC		 2236 }
2237
b417577d 2238 omap_hsmmc_disable_irq(host);
a45c6cb8 2239
5e2ea617
AH		 2240 mmc_host_lazy_disable(host->mmc);
2241
b62f6228
AH		 2242 omap_hsmmc_protect_card(host);
2243
a45c6cb8
MC		 2244 mmc_add_host(mmc);
2245
191d1f1d 2246 if (mmc_slot(host).name != NULL) {
a45c6cb8
MC		 2247 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2248 if (ret < 0)
2249 goto err_slot_name;
2250 }
191d1f1d 2251 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
a45c6cb8
MC		 2252 ret = device_create_file(&mmc->class_dev,
2253 &dev_attr_cover_switch);
2254 if (ret < 0)
db0fefc5 2255 goto err_slot_name;
a45c6cb8
MC		 2256 }
2257
70a3341a 2258 omap_hsmmc_debugfs(mmc);
d900f712 2259
a45c6cb8
MC		 2260 return 0;
2261
a45c6cb8
MC		 2262err_slot_name:
2263 mmc_remove_host(mmc);
a45c6cb8 2264 free_irq(mmc_slot(host).card_detect_irq, host);
db0fefc5
AH		 2265err_irq_cd:
2266 if (host->use_reg)
2267 omap_hsmmc_reg_put(host);
2268err_reg:
2269 if (host->pdata->cleanup)
2270 host->pdata->cleanup(&pdev->dev);
a45c6cb8
MC		 2271err_irq_cd_init:
2272 free_irq(host->irq, host);
2273err_irq:
5e2ea617 2274 mmc_host_disable(host->mmc);
a45c6cb8
MC		 2275 clk_disable(host->iclk);
2276 clk_put(host->fclk);
2277 clk_put(host->iclk);
2bec0893 2278 if (host->got_dbclk) {
a45c6cb8
MC		 2279 clk_disable(host->dbclk);
2280 clk_put(host->dbclk);
2281 }
a45c6cb8
MC		 2282err1:
2283 iounmap(host->base);
db0fefc5
AH		 2284 platform_set_drvdata(pdev, NULL);
2285 mmc_free_host(mmc);
2286err_alloc:
2287 omap_hsmmc_gpio_free(pdata);
a45c6cb8 2288err:
984b203a 2289 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 2290 return ret;
2291}
2292
70a3341a 2293static int omap_hsmmc_remove(struct platform_device *pdev)
a45c6cb8 2294{
70a3341a 2295 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2296 struct resource *res;
2297
2298 if (host) {
5e2ea617 2299 mmc_host_enable(host->mmc);
a45c6cb8 2300 mmc_remove_host(host->mmc);
db0fefc5
AH		 2301 if (host->use_reg)
2302 omap_hsmmc_reg_put(host);
a45c6cb8
MC		 2303 if (host->pdata->cleanup)
2304 host->pdata->cleanup(&pdev->dev);
2305 free_irq(host->irq, host);
2306 if (mmc_slot(host).card_detect_irq)
2307 free_irq(mmc_slot(host).card_detect_irq, host);
0d9ee5b2 2308 flush_work_sync(&host->mmc_carddetect_work);
a45c6cb8 2309
5e2ea617 2310 mmc_host_disable(host->mmc);
a45c6cb8
MC		 2311 clk_disable(host->iclk);
2312 clk_put(host->fclk);
2313 clk_put(host->iclk);
2bec0893 2314 if (host->got_dbclk) {
a45c6cb8
MC		 2315 clk_disable(host->dbclk);
2316 clk_put(host->dbclk);
2317 }
2318
2319 mmc_free_host(host->mmc);
2320 iounmap(host->base);
db0fefc5 2321 omap_hsmmc_gpio_free(pdev->dev.platform_data);
a45c6cb8
MC		 2322 }
2323
2324 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2325 if (res)
984b203a 2326 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 2327 platform_set_drvdata(pdev, NULL);
2328
2329 return 0;
2330}
2331
2332#ifdef CONFIG_PM
a791daa1 2333static int omap_hsmmc_suspend(struct device *dev)
a45c6cb8
MC		 2334{
2335 int ret = 0;
a791daa1 2336 struct platform_device *pdev = to_platform_device(dev);
70a3341a 2337 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2338
2339 if (host && host->suspended)
2340 return 0;
2341
2342 if (host) {
a6b2240d
AH		 2343 host->suspended = 1;
2344 if (host->pdata->suspend) {
2345 ret = host->pdata->suspend(&pdev->dev,
2346 host->slot_id);
2347 if (ret) {
2348 dev_dbg(mmc_dev(host->mmc),
2349 "Unable to handle MMC board"
2350 " level suspend\n");
2351 host->suspended = 0;
2352 return ret;
2353 }
2354 }
2355 cancel_work_sync(&host->mmc_carddetect_work);
1a13f8fa 2356 ret = mmc_suspend_host(host->mmc);
e7cb756f 2357 mmc_host_enable(host->mmc);
a45c6cb8 2358 if (ret == 0) {
b417577d 2359 omap_hsmmc_disable_irq(host);
0683af48 2360 OMAP_HSMMC_WRITE(host->base, HCTL,
191d1f1d 2361 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
5e2ea617 2362 mmc_host_disable(host->mmc);
a45c6cb8 2363 clk_disable(host->iclk);
2bec0893
AH		 2364 if (host->got_dbclk)
2365 clk_disable(host->dbclk);
a6b2240d
AH		 2366 } else {
2367 host->suspended = 0;
2368 if (host->pdata->resume) {
2369 ret = host->pdata->resume(&pdev->dev,
2370 host->slot_id);
2371 if (ret)
2372 dev_dbg(mmc_dev(host->mmc),
2373 "Unmask interrupt failed\n");
2374 }
5e2ea617 2375 mmc_host_disable(host->mmc);
a6b2240d 2376 }
a45c6cb8
MC		 2377
2378 }
2379 return ret;
2380}
2381
2382/* Routine to resume the MMC device */
a791daa1 2383static int omap_hsmmc_resume(struct device *dev)
a45c6cb8
MC		 2384{
2385 int ret = 0;
a791daa1 2386 struct platform_device *pdev = to_platform_device(dev);
70a3341a 2387 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2388
2389 if (host && !host->suspended)
2390 return 0;
2391
2392 if (host) {
a45c6cb8 2393 ret = clk_enable(host->iclk);
11dd62a7 2394 if (ret)
a45c6cb8 2395 goto clk_en_err;
a45c6cb8 2396
11dd62a7
DK		 2397 if (mmc_host_enable(host->mmc) != 0) {
2398 clk_disable(host->iclk);
2399 goto clk_en_err;
2400 }
2401
2bec0893
AH		 2402 if (host->got_dbclk)
2403 clk_enable(host->dbclk);
2404
70a3341a 2405 omap_hsmmc_conf_bus_power(host);
1b331e69 2406
a45c6cb8
MC		 2407 if (host->pdata->resume) {
2408 ret = host->pdata->resume(&pdev->dev, host->slot_id);
2409 if (ret)
2410 dev_dbg(mmc_dev(host->mmc),
2411 "Unmask interrupt failed\n");
2412 }
2413
b62f6228
AH		 2414 omap_hsmmc_protect_card(host);
2415
a45c6cb8
MC		 2416 /* Notify the core to resume the host */
2417 ret = mmc_resume_host(host->mmc);
2418 if (ret == 0)
2419 host->suspended = 0;
70a3341a 2420
5e2ea617 2421 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 2422 }
2423
2424 return ret;
2425
2426clk_en_err:
2427 dev_dbg(mmc_dev(host->mmc),
2428 "Failed to enable MMC clocks during resume\n");
2429 return ret;
2430}
2431
2432#else
70a3341a
DK		 2433#define omap_hsmmc_suspend NULL
2434#define omap_hsmmc_resume NULL
a45c6cb8
MC		 2435#endif
2436
a791daa1 2437static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
70a3341a
DK		 2438 .suspend = omap_hsmmc_suspend,
2439 .resume = omap_hsmmc_resume,
a791daa1
KH		 2440};
2441
2442static struct platform_driver omap_hsmmc_driver = {
2443 .remove = omap_hsmmc_remove,
a45c6cb8
MC		 2444 .driver = {
2445 .name = DRIVER_NAME,
2446 .owner = THIS_MODULE,
a791daa1 2447 .pm = &omap_hsmmc_dev_pm_ops,
a45c6cb8
MC		 2448 },
2449};
2450
70a3341a 2451static int __init omap_hsmmc_init(void)
a45c6cb8
MC		 2452{
2453 /* Register the MMC driver */
8753298a 2454 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
a45c6cb8
MC		 2455}
2456
70a3341a 2457static void __exit omap_hsmmc_cleanup(void)
a45c6cb8
MC		 2458{
2459 /* Unregister MMC driver */
70a3341a 2460 platform_driver_unregister(&omap_hsmmc_driver);
a45c6cb8
MC		 2461}
2462
70a3341a
DK		 2463module_init(omap_hsmmc_init);
2464module_exit(omap_hsmmc_cleanup);
a45c6cb8
MC		 2465
2466MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2467MODULE_LICENSE("GPL");
2468MODULE_ALIAS("platform:" DRIVER_NAME);
2469MODULE_AUTHOR("Texas Instruments Inc");
Linux kernel - Deliverables
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