Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/pxa.c - PXA MMCI driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2003 Russell King, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This hardware is really sick: | |
11 | * - No way to clear interrupts. | |
12 | * - Have to turn off the clock whenever we touch the device. | |
13 | * - Doesn't tell you how many data blocks were transferred. | |
14 | * Yuck! | |
15 | * | |
16 | * 1 and 3 byte data transfers not supported | |
17 | * max block length up to 1023 | |
18 | */ | |
1da177e4 LT |
19 | #include <linux/module.h> |
20 | #include <linux/init.h> | |
21 | #include <linux/ioport.h> | |
d052d1be | 22 | #include <linux/platform_device.h> |
1da177e4 LT |
23 | #include <linux/delay.h> |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/dma-mapping.h> | |
ebebd9b0 RK |
26 | #include <linux/clk.h> |
27 | #include <linux/err.h> | |
1da177e4 | 28 | #include <linux/mmc/host.h> |
05678a96 | 29 | #include <linux/io.h> |
8385f9cb | 30 | #include <linux/regulator/consumer.h> |
1da177e4 | 31 | |
1da177e4 LT |
32 | #include <asm/sizes.h> |
33 | ||
05678a96 | 34 | #include <mach/hardware.h> |
7ebc8d56 | 35 | #include <mach/dma.h> |
a09e64fb | 36 | #include <mach/mmc.h> |
1da177e4 LT |
37 | |
38 | #include "pxamci.h" | |
39 | ||
1da177e4 LT |
40 | #define DRIVER_NAME "pxa2xx-mci" |
41 | ||
42 | #define NR_SG 1 | |
d8cb70d1 | 43 | #define CLKRT_OFF (~0) |
1da177e4 LT |
44 | |
45 | struct pxamci_host { | |
46 | struct mmc_host *mmc; | |
47 | spinlock_t lock; | |
48 | struct resource *res; | |
49 | void __iomem *base; | |
ebebd9b0 RK |
50 | struct clk *clk; |
51 | unsigned long clkrate; | |
1da177e4 LT |
52 | int irq; |
53 | int dma; | |
54 | unsigned int clkrt; | |
55 | unsigned int cmdat; | |
56 | unsigned int imask; | |
57 | unsigned int power_mode; | |
58 | struct pxamci_platform_data *pdata; | |
59 | ||
60 | struct mmc_request *mrq; | |
61 | struct mmc_command *cmd; | |
62 | struct mmc_data *data; | |
63 | ||
64 | dma_addr_t sg_dma; | |
65 | struct pxa_dma_desc *sg_cpu; | |
66 | unsigned int dma_len; | |
67 | ||
68 | unsigned int dma_dir; | |
9a788c6b BW |
69 | unsigned int dma_drcmrrx; |
70 | unsigned int dma_drcmrtx; | |
8385f9cb DR |
71 | |
72 | struct regulator *vcc; | |
1da177e4 LT |
73 | }; |
74 | ||
8385f9cb DR |
75 | static inline void pxamci_init_ocr(struct pxamci_host *host) |
76 | { | |
77 | #ifdef CONFIG_REGULATOR | |
78 | host->vcc = regulator_get(mmc_dev(host->mmc), "vmmc"); | |
79 | ||
80 | if (IS_ERR(host->vcc)) | |
81 | host->vcc = NULL; | |
82 | else { | |
83 | host->mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vcc); | |
84 | if (host->pdata && host->pdata->ocr_mask) | |
85 | dev_warn(mmc_dev(host->mmc), | |
86 | "ocr_mask/setpower will not be used\n"); | |
87 | } | |
88 | #endif | |
89 | if (host->vcc == NULL) { | |
90 | /* fall-back to platform data */ | |
91 | host->mmc->ocr_avail = host->pdata ? | |
92 | host->pdata->ocr_mask : | |
93 | MMC_VDD_32_33 | MMC_VDD_33_34; | |
94 | } | |
95 | } | |
96 | ||
97 | static inline void pxamci_set_power(struct pxamci_host *host, unsigned int vdd) | |
98 | { | |
99 | #ifdef CONFIG_REGULATOR | |
100 | if (host->vcc) | |
101 | mmc_regulator_set_ocr(host->vcc, vdd); | |
102 | #endif | |
103 | if (!host->vcc && host->pdata && host->pdata->setpower) | |
104 | host->pdata->setpower(mmc_dev(host->mmc), vdd); | |
105 | } | |
106 | ||
1da177e4 LT |
107 | static void pxamci_stop_clock(struct pxamci_host *host) |
108 | { | |
109 | if (readl(host->base + MMC_STAT) & STAT_CLK_EN) { | |
110 | unsigned long timeout = 10000; | |
111 | unsigned int v; | |
112 | ||
113 | writel(STOP_CLOCK, host->base + MMC_STRPCL); | |
114 | ||
115 | do { | |
116 | v = readl(host->base + MMC_STAT); | |
117 | if (!(v & STAT_CLK_EN)) | |
118 | break; | |
119 | udelay(1); | |
120 | } while (timeout--); | |
121 | ||
122 | if (v & STAT_CLK_EN) | |
123 | dev_err(mmc_dev(host->mmc), "unable to stop clock\n"); | |
124 | } | |
125 | } | |
126 | ||
127 | static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask) | |
128 | { | |
129 | unsigned long flags; | |
130 | ||
131 | spin_lock_irqsave(&host->lock, flags); | |
132 | host->imask &= ~mask; | |
133 | writel(host->imask, host->base + MMC_I_MASK); | |
134 | spin_unlock_irqrestore(&host->lock, flags); | |
135 | } | |
136 | ||
137 | static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask) | |
138 | { | |
139 | unsigned long flags; | |
140 | ||
141 | spin_lock_irqsave(&host->lock, flags); | |
142 | host->imask |= mask; | |
143 | writel(host->imask, host->base + MMC_I_MASK); | |
144 | spin_unlock_irqrestore(&host->lock, flags); | |
145 | } | |
146 | ||
147 | static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data) | |
148 | { | |
149 | unsigned int nob = data->blocks; | |
3d63abe5 | 150 | unsigned long long clks; |
1da177e4 | 151 | unsigned int timeout; |
97f8571e | 152 | bool dalgn = 0; |
1da177e4 LT |
153 | u32 dcmd; |
154 | int i; | |
155 | ||
156 | host->data = data; | |
157 | ||
158 | if (data->flags & MMC_DATA_STREAM) | |
159 | nob = 0xffff; | |
160 | ||
161 | writel(nob, host->base + MMC_NOB); | |
2c171bf1 | 162 | writel(data->blksz, host->base + MMC_BLKLEN); |
1da177e4 | 163 | |
ebebd9b0 | 164 | clks = (unsigned long long)data->timeout_ns * host->clkrate; |
3d63abe5 RK |
165 | do_div(clks, 1000000000UL); |
166 | timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt); | |
1da177e4 LT |
167 | writel((timeout + 255) / 256, host->base + MMC_RDTO); |
168 | ||
169 | if (data->flags & MMC_DATA_READ) { | |
170 | host->dma_dir = DMA_FROM_DEVICE; | |
171 | dcmd = DCMD_INCTRGADDR | DCMD_FLOWTRG; | |
9a788c6b BW |
172 | DRCMR(host->dma_drcmrtx) = 0; |
173 | DRCMR(host->dma_drcmrrx) = host->dma | DRCMR_MAPVLD; | |
1da177e4 LT |
174 | } else { |
175 | host->dma_dir = DMA_TO_DEVICE; | |
176 | dcmd = DCMD_INCSRCADDR | DCMD_FLOWSRC; | |
9a788c6b BW |
177 | DRCMR(host->dma_drcmrrx) = 0; |
178 | DRCMR(host->dma_drcmrtx) = host->dma | DRCMR_MAPVLD; | |
1da177e4 LT |
179 | } |
180 | ||
181 | dcmd |= DCMD_BURST32 | DCMD_WIDTH1; | |
182 | ||
183 | host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, | |
184 | host->dma_dir); | |
185 | ||
186 | for (i = 0; i < host->dma_len; i++) { | |
c783837b NP |
187 | unsigned int length = sg_dma_len(&data->sg[i]); |
188 | host->sg_cpu[i].dcmd = dcmd | length; | |
189 | if (length & 31 && !(data->flags & MMC_DATA_READ)) | |
190 | host->sg_cpu[i].dcmd |= DCMD_ENDIRQEN; | |
97f8571e PZ |
191 | /* Not aligned to 8-byte boundary? */ |
192 | if (sg_dma_address(&data->sg[i]) & 0x7) | |
193 | dalgn = 1; | |
1da177e4 LT |
194 | if (data->flags & MMC_DATA_READ) { |
195 | host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO; | |
196 | host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]); | |
197 | } else { | |
198 | host->sg_cpu[i].dsadr = sg_dma_address(&data->sg[i]); | |
199 | host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO; | |
200 | } | |
1da177e4 LT |
201 | host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) * |
202 | sizeof(struct pxa_dma_desc); | |
203 | } | |
204 | host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP; | |
205 | wmb(); | |
206 | ||
97f8571e PZ |
207 | /* |
208 | * The PXA27x DMA controller encounters overhead when working with | |
209 | * unaligned (to 8-byte boundaries) data, so switch on byte alignment | |
210 | * mode only if we have unaligned data. | |
211 | */ | |
212 | if (dalgn) | |
213 | DALGN |= (1 << host->dma); | |
214 | else | |
4fe16897 | 215 | DALGN &= ~(1 << host->dma); |
1da177e4 | 216 | DDADR(host->dma) = host->sg_dma; |
b6018958 CB |
217 | |
218 | /* | |
219 | * workaround for erratum #91: | |
220 | * only start DMA now if we are doing a read, | |
221 | * otherwise we wait until CMD/RESP has finished | |
222 | * before starting DMA. | |
223 | */ | |
224 | if (!cpu_is_pxa27x() || data->flags & MMC_DATA_READ) | |
225 | DCSR(host->dma) = DCSR_RUN; | |
1da177e4 LT |
226 | } |
227 | ||
228 | static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat) | |
229 | { | |
230 | WARN_ON(host->cmd != NULL); | |
231 | host->cmd = cmd; | |
232 | ||
233 | if (cmd->flags & MMC_RSP_BUSY) | |
234 | cmdat |= CMDAT_BUSY; | |
235 | ||
e9225176 RK |
236 | #define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE)) |
237 | switch (RSP_TYPE(mmc_resp_type(cmd))) { | |
6f949909 | 238 | case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6, r7 */ |
1da177e4 LT |
239 | cmdat |= CMDAT_RESP_SHORT; |
240 | break; | |
e9225176 | 241 | case RSP_TYPE(MMC_RSP_R3): |
1da177e4 LT |
242 | cmdat |= CMDAT_RESP_R3; |
243 | break; | |
e9225176 | 244 | case RSP_TYPE(MMC_RSP_R2): |
1da177e4 LT |
245 | cmdat |= CMDAT_RESP_R2; |
246 | break; | |
247 | default: | |
248 | break; | |
249 | } | |
250 | ||
251 | writel(cmd->opcode, host->base + MMC_CMD); | |
252 | writel(cmd->arg >> 16, host->base + MMC_ARGH); | |
253 | writel(cmd->arg & 0xffff, host->base + MMC_ARGL); | |
254 | writel(cmdat, host->base + MMC_CMDAT); | |
255 | writel(host->clkrt, host->base + MMC_CLKRT); | |
256 | ||
257 | writel(START_CLOCK, host->base + MMC_STRPCL); | |
258 | ||
259 | pxamci_enable_irq(host, END_CMD_RES); | |
260 | } | |
261 | ||
262 | static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq) | |
263 | { | |
1da177e4 LT |
264 | host->mrq = NULL; |
265 | host->cmd = NULL; | |
266 | host->data = NULL; | |
267 | mmc_request_done(host->mmc, mrq); | |
268 | } | |
269 | ||
270 | static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat) | |
271 | { | |
272 | struct mmc_command *cmd = host->cmd; | |
273 | int i; | |
274 | u32 v; | |
275 | ||
276 | if (!cmd) | |
277 | return 0; | |
278 | ||
279 | host->cmd = NULL; | |
280 | ||
281 | /* | |
282 | * Did I mention this is Sick. We always need to | |
283 | * discard the upper 8 bits of the first 16-bit word. | |
284 | */ | |
285 | v = readl(host->base + MMC_RES) & 0xffff; | |
286 | for (i = 0; i < 4; i++) { | |
287 | u32 w1 = readl(host->base + MMC_RES) & 0xffff; | |
288 | u32 w2 = readl(host->base + MMC_RES) & 0xffff; | |
289 | cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8; | |
290 | v = w2; | |
291 | } | |
292 | ||
293 | if (stat & STAT_TIME_OUT_RESPONSE) { | |
17b0429d | 294 | cmd->error = -ETIMEDOUT; |
1da177e4 | 295 | } else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) { |
1da177e4 LT |
296 | /* |
297 | * workaround for erratum #42: | |
298 | * Intel PXA27x Family Processor Specification Update Rev 001 | |
90e07d9f NP |
299 | * A bogus CRC error can appear if the msb of a 136 bit |
300 | * response is a one. | |
1da177e4 | 301 | */ |
e10a854c CB |
302 | if (cpu_is_pxa27x() && |
303 | (cmd->flags & MMC_RSP_136 && cmd->resp[0] & 0x80000000)) | |
90e07d9f | 304 | pr_debug("ignoring CRC from command %d - *risky*\n", cmd->opcode); |
e10a854c CB |
305 | else |
306 | cmd->error = -EILSEQ; | |
1da177e4 LT |
307 | } |
308 | ||
309 | pxamci_disable_irq(host, END_CMD_RES); | |
17b0429d | 310 | if (host->data && !cmd->error) { |
1da177e4 | 311 | pxamci_enable_irq(host, DATA_TRAN_DONE); |
b6018958 CB |
312 | /* |
313 | * workaround for erratum #91, if doing write | |
314 | * enable DMA late | |
315 | */ | |
316 | if (cpu_is_pxa27x() && host->data->flags & MMC_DATA_WRITE) | |
317 | DCSR(host->dma) = DCSR_RUN; | |
1da177e4 LT |
318 | } else { |
319 | pxamci_finish_request(host, host->mrq); | |
320 | } | |
321 | ||
322 | return 1; | |
323 | } | |
324 | ||
325 | static int pxamci_data_done(struct pxamci_host *host, unsigned int stat) | |
326 | { | |
327 | struct mmc_data *data = host->data; | |
328 | ||
329 | if (!data) | |
330 | return 0; | |
331 | ||
332 | DCSR(host->dma) = 0; | |
c00a46ab | 333 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, |
1da177e4 LT |
334 | host->dma_dir); |
335 | ||
336 | if (stat & STAT_READ_TIME_OUT) | |
17b0429d | 337 | data->error = -ETIMEDOUT; |
1da177e4 | 338 | else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR)) |
17b0429d | 339 | data->error = -EILSEQ; |
1da177e4 LT |
340 | |
341 | /* | |
342 | * There appears to be a hardware design bug here. There seems to | |
343 | * be no way to find out how much data was transferred to the card. | |
344 | * This means that if there was an error on any block, we mark all | |
345 | * data blocks as being in error. | |
346 | */ | |
17b0429d | 347 | if (!data->error) |
2c171bf1 | 348 | data->bytes_xfered = data->blocks * data->blksz; |
1da177e4 LT |
349 | else |
350 | data->bytes_xfered = 0; | |
351 | ||
352 | pxamci_disable_irq(host, DATA_TRAN_DONE); | |
353 | ||
354 | host->data = NULL; | |
58741e8b | 355 | if (host->mrq->stop) { |
1da177e4 | 356 | pxamci_stop_clock(host); |
df456f47 | 357 | pxamci_start_cmd(host, host->mrq->stop, host->cmdat); |
1da177e4 LT |
358 | } else { |
359 | pxamci_finish_request(host, host->mrq); | |
360 | } | |
361 | ||
362 | return 1; | |
363 | } | |
364 | ||
7d12e780 | 365 | static irqreturn_t pxamci_irq(int irq, void *devid) |
1da177e4 LT |
366 | { |
367 | struct pxamci_host *host = devid; | |
368 | unsigned int ireg; | |
369 | int handled = 0; | |
370 | ||
81ab570f | 371 | ireg = readl(host->base + MMC_I_REG) & ~readl(host->base + MMC_I_MASK); |
1da177e4 | 372 | |
1da177e4 LT |
373 | if (ireg) { |
374 | unsigned stat = readl(host->base + MMC_STAT); | |
375 | ||
d78e9079 | 376 | pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat); |
1da177e4 LT |
377 | |
378 | if (ireg & END_CMD_RES) | |
379 | handled |= pxamci_cmd_done(host, stat); | |
380 | if (ireg & DATA_TRAN_DONE) | |
381 | handled |= pxamci_data_done(host, stat); | |
5d3ad4e8 BW |
382 | if (ireg & SDIO_INT) { |
383 | mmc_signal_sdio_irq(host->mmc); | |
384 | handled = 1; | |
385 | } | |
1da177e4 LT |
386 | } |
387 | ||
388 | return IRQ_RETVAL(handled); | |
389 | } | |
390 | ||
391 | static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
392 | { | |
393 | struct pxamci_host *host = mmc_priv(mmc); | |
394 | unsigned int cmdat; | |
395 | ||
396 | WARN_ON(host->mrq != NULL); | |
397 | ||
398 | host->mrq = mrq; | |
399 | ||
400 | pxamci_stop_clock(host); | |
401 | ||
402 | cmdat = host->cmdat; | |
403 | host->cmdat &= ~CMDAT_INIT; | |
404 | ||
405 | if (mrq->data) { | |
406 | pxamci_setup_data(host, mrq->data); | |
407 | ||
408 | cmdat &= ~CMDAT_BUSY; | |
409 | cmdat |= CMDAT_DATAEN | CMDAT_DMAEN; | |
410 | if (mrq->data->flags & MMC_DATA_WRITE) | |
411 | cmdat |= CMDAT_WRITE; | |
412 | ||
413 | if (mrq->data->flags & MMC_DATA_STREAM) | |
414 | cmdat |= CMDAT_STREAM; | |
415 | } | |
416 | ||
417 | pxamci_start_cmd(host, mrq->cmd, cmdat); | |
418 | } | |
419 | ||
e619524f RP |
420 | static int pxamci_get_ro(struct mmc_host *mmc) |
421 | { | |
422 | struct pxamci_host *host = mmc_priv(mmc); | |
423 | ||
424 | if (host->pdata && host->pdata->get_ro) | |
08f80bb5 AV |
425 | return !!host->pdata->get_ro(mmc_dev(mmc)); |
426 | /* | |
427 | * Board doesn't support read only detection; let the mmc core | |
428 | * decide what to do. | |
429 | */ | |
430 | return -ENOSYS; | |
e619524f RP |
431 | } |
432 | ||
1da177e4 LT |
433 | static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
434 | { | |
435 | struct pxamci_host *host = mmc_priv(mmc); | |
436 | ||
1da177e4 | 437 | if (ios->clock) { |
ebebd9b0 RK |
438 | unsigned long rate = host->clkrate; |
439 | unsigned int clk = rate / ios->clock; | |
440 | ||
d8cb70d1 RK |
441 | if (host->clkrt == CLKRT_OFF) |
442 | clk_enable(host->clk); | |
443 | ||
64eb036a BW |
444 | if (ios->clock == 26000000) { |
445 | /* to support 26MHz on pxa300/pxa310 */ | |
446 | host->clkrt = 7; | |
447 | } else { | |
448 | /* to handle (19.5MHz, 26MHz) */ | |
449 | if (!clk) | |
450 | clk = 1; | |
451 | ||
452 | /* | |
453 | * clk might result in a lower divisor than we | |
454 | * desire. check for that condition and adjust | |
455 | * as appropriate. | |
456 | */ | |
457 | if (rate / clk > ios->clock) | |
458 | clk <<= 1; | |
459 | host->clkrt = fls(clk) - 1; | |
460 | } | |
1da177e4 LT |
461 | |
462 | /* | |
463 | * we write clkrt on the next command | |
464 | */ | |
465 | } else { | |
466 | pxamci_stop_clock(host); | |
d8cb70d1 RK |
467 | if (host->clkrt != CLKRT_OFF) { |
468 | host->clkrt = CLKRT_OFF; | |
469 | clk_disable(host->clk); | |
470 | } | |
1da177e4 LT |
471 | } |
472 | ||
473 | if (host->power_mode != ios->power_mode) { | |
474 | host->power_mode = ios->power_mode; | |
475 | ||
8385f9cb | 476 | pxamci_set_power(host, ios->vdd); |
1da177e4 LT |
477 | |
478 | if (ios->power_mode == MMC_POWER_ON) | |
479 | host->cmdat |= CMDAT_INIT; | |
480 | } | |
481 | ||
df456f47 BW |
482 | if (ios->bus_width == MMC_BUS_WIDTH_4) |
483 | host->cmdat |= CMDAT_SD_4DAT; | |
484 | else | |
485 | host->cmdat &= ~CMDAT_SD_4DAT; | |
486 | ||
d78e9079 | 487 | pr_debug("PXAMCI: clkrt = %x cmdat = %x\n", |
c6563178 | 488 | host->clkrt, host->cmdat); |
1da177e4 LT |
489 | } |
490 | ||
5d3ad4e8 BW |
491 | static void pxamci_enable_sdio_irq(struct mmc_host *host, int enable) |
492 | { | |
493 | struct pxamci_host *pxa_host = mmc_priv(host); | |
494 | ||
495 | if (enable) | |
496 | pxamci_enable_irq(pxa_host, SDIO_INT); | |
497 | else | |
498 | pxamci_disable_irq(pxa_host, SDIO_INT); | |
499 | } | |
500 | ||
ab7aefd0 | 501 | static const struct mmc_host_ops pxamci_ops = { |
5d3ad4e8 BW |
502 | .request = pxamci_request, |
503 | .get_ro = pxamci_get_ro, | |
504 | .set_ios = pxamci_set_ios, | |
505 | .enable_sdio_irq = pxamci_enable_sdio_irq, | |
1da177e4 LT |
506 | }; |
507 | ||
7d12e780 | 508 | static void pxamci_dma_irq(int dma, void *devid) |
1da177e4 | 509 | { |
c783837b NP |
510 | struct pxamci_host *host = devid; |
511 | int dcsr = DCSR(dma); | |
512 | DCSR(dma) = dcsr & ~DCSR_STOPIRQEN; | |
513 | ||
514 | if (dcsr & DCSR_ENDINTR) { | |
515 | writel(BUF_PART_FULL, host->base + MMC_PRTBUF); | |
516 | } else { | |
517 | printk(KERN_ERR "%s: DMA error on channel %d (DCSR=%#x)\n", | |
518 | mmc_hostname(host->mmc), dma, dcsr); | |
519 | host->data->error = -EIO; | |
520 | pxamci_data_done(host, 0); | |
521 | } | |
1da177e4 LT |
522 | } |
523 | ||
7d12e780 | 524 | static irqreturn_t pxamci_detect_irq(int irq, void *devid) |
1da177e4 | 525 | { |
c26971cb RP |
526 | struct pxamci_host *host = mmc_priv(devid); |
527 | ||
528 | mmc_detect_change(devid, host->pdata->detect_delay); | |
1da177e4 LT |
529 | return IRQ_HANDLED; |
530 | } | |
531 | ||
3ae5eaec | 532 | static int pxamci_probe(struct platform_device *pdev) |
1da177e4 | 533 | { |
1da177e4 LT |
534 | struct mmc_host *mmc; |
535 | struct pxamci_host *host = NULL; | |
9a788c6b | 536 | struct resource *r, *dmarx, *dmatx; |
1da177e4 LT |
537 | int ret, irq; |
538 | ||
539 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
540 | irq = platform_get_irq(pdev, 0); | |
48944738 | 541 | if (!r || irq < 0) |
1da177e4 LT |
542 | return -ENXIO; |
543 | ||
544 | r = request_mem_region(r->start, SZ_4K, DRIVER_NAME); | |
545 | if (!r) | |
546 | return -EBUSY; | |
547 | ||
3ae5eaec | 548 | mmc = mmc_alloc_host(sizeof(struct pxamci_host), &pdev->dev); |
1da177e4 LT |
549 | if (!mmc) { |
550 | ret = -ENOMEM; | |
551 | goto out; | |
552 | } | |
553 | ||
554 | mmc->ops = &pxamci_ops; | |
1da177e4 LT |
555 | |
556 | /* | |
557 | * We can do SG-DMA, but we don't because we never know how much | |
558 | * data we successfully wrote to the card. | |
559 | */ | |
560 | mmc->max_phys_segs = NR_SG; | |
561 | ||
562 | /* | |
563 | * Our hardware DMA can handle a maximum of one page per SG entry. | |
564 | */ | |
565 | mmc->max_seg_size = PAGE_SIZE; | |
566 | ||
fe4a3c7a | 567 | /* |
fe2dc44e | 568 | * Block length register is only 10 bits before PXA27x. |
fe4a3c7a | 569 | */ |
0ffcbfd5 | 570 | mmc->max_blk_size = cpu_is_pxa25x() ? 1023 : 2048; |
fe4a3c7a | 571 | |
55db890a PO |
572 | /* |
573 | * Block count register is 16 bits. | |
574 | */ | |
575 | mmc->max_blk_count = 65535; | |
576 | ||
1da177e4 LT |
577 | host = mmc_priv(mmc); |
578 | host->mmc = mmc; | |
579 | host->dma = -1; | |
580 | host->pdata = pdev->dev.platform_data; | |
d8cb70d1 | 581 | host->clkrt = CLKRT_OFF; |
ebebd9b0 | 582 | |
e0d8b13a | 583 | host->clk = clk_get(&pdev->dev, NULL); |
ebebd9b0 RK |
584 | if (IS_ERR(host->clk)) { |
585 | ret = PTR_ERR(host->clk); | |
586 | host->clk = NULL; | |
587 | goto out; | |
588 | } | |
589 | ||
590 | host->clkrate = clk_get_rate(host->clk); | |
591 | ||
592 | /* | |
593 | * Calculate minimum clock rate, rounding up. | |
594 | */ | |
595 | mmc->f_min = (host->clkrate + 63) / 64; | |
64eb036a BW |
596 | mmc->f_max = (cpu_is_pxa300() || cpu_is_pxa310()) ? 26000000 |
597 | : host->clkrate; | |
ebebd9b0 | 598 | |
8385f9cb DR |
599 | pxamci_init_ocr(host); |
600 | ||
df456f47 | 601 | mmc->caps = 0; |
5d3ad4e8 | 602 | host->cmdat = 0; |
0ffcbfd5 | 603 | if (!cpu_is_pxa25x()) { |
5d3ad4e8 BW |
604 | mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; |
605 | host->cmdat |= CMDAT_SDIO_INT_EN; | |
64eb036a BW |
606 | if (cpu_is_pxa300() || cpu_is_pxa310()) |
607 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED | | |
608 | MMC_CAP_SD_HIGHSPEED; | |
5d3ad4e8 | 609 | } |
1da177e4 | 610 | |
3ae5eaec | 611 | host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL); |
1da177e4 LT |
612 | if (!host->sg_cpu) { |
613 | ret = -ENOMEM; | |
614 | goto out; | |
615 | } | |
616 | ||
617 | spin_lock_init(&host->lock); | |
618 | host->res = r; | |
619 | host->irq = irq; | |
620 | host->imask = MMC_I_MASK_ALL; | |
621 | ||
622 | host->base = ioremap(r->start, SZ_4K); | |
623 | if (!host->base) { | |
624 | ret = -ENOMEM; | |
625 | goto out; | |
626 | } | |
627 | ||
628 | /* | |
629 | * Ensure that the host controller is shut down, and setup | |
630 | * with our defaults. | |
631 | */ | |
632 | pxamci_stop_clock(host); | |
633 | writel(0, host->base + MMC_SPI); | |
634 | writel(64, host->base + MMC_RESTO); | |
635 | writel(host->imask, host->base + MMC_I_MASK); | |
636 | ||
637 | host->dma = pxa_request_dma(DRIVER_NAME, DMA_PRIO_LOW, | |
638 | pxamci_dma_irq, host); | |
639 | if (host->dma < 0) { | |
640 | ret = -EBUSY; | |
641 | goto out; | |
642 | } | |
643 | ||
644 | ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host); | |
645 | if (ret) | |
646 | goto out; | |
647 | ||
3ae5eaec | 648 | platform_set_drvdata(pdev, mmc); |
1da177e4 | 649 | |
9a788c6b BW |
650 | dmarx = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
651 | if (!dmarx) { | |
652 | ret = -ENXIO; | |
653 | goto out; | |
654 | } | |
655 | host->dma_drcmrrx = dmarx->start; | |
656 | ||
657 | dmatx = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
658 | if (!dmatx) { | |
659 | ret = -ENXIO; | |
660 | goto out; | |
661 | } | |
662 | host->dma_drcmrtx = dmatx->start; | |
663 | ||
1da177e4 | 664 | if (host->pdata && host->pdata->init) |
3ae5eaec | 665 | host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc); |
1da177e4 LT |
666 | |
667 | mmc_add_host(mmc); | |
668 | ||
669 | return 0; | |
670 | ||
671 | out: | |
672 | if (host) { | |
673 | if (host->dma >= 0) | |
674 | pxa_free_dma(host->dma); | |
675 | if (host->base) | |
676 | iounmap(host->base); | |
677 | if (host->sg_cpu) | |
3ae5eaec | 678 | dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); |
ebebd9b0 RK |
679 | if (host->clk) |
680 | clk_put(host->clk); | |
1da177e4 LT |
681 | } |
682 | if (mmc) | |
683 | mmc_free_host(mmc); | |
684 | release_resource(r); | |
685 | return ret; | |
686 | } | |
687 | ||
3ae5eaec | 688 | static int pxamci_remove(struct platform_device *pdev) |
1da177e4 | 689 | { |
3ae5eaec | 690 | struct mmc_host *mmc = platform_get_drvdata(pdev); |
1da177e4 | 691 | |
3ae5eaec | 692 | platform_set_drvdata(pdev, NULL); |
1da177e4 LT |
693 | |
694 | if (mmc) { | |
695 | struct pxamci_host *host = mmc_priv(mmc); | |
696 | ||
8385f9cb DR |
697 | if (host->vcc) |
698 | regulator_put(host->vcc); | |
699 | ||
1da177e4 | 700 | if (host->pdata && host->pdata->exit) |
3ae5eaec | 701 | host->pdata->exit(&pdev->dev, mmc); |
1da177e4 LT |
702 | |
703 | mmc_remove_host(mmc); | |
704 | ||
705 | pxamci_stop_clock(host); | |
706 | writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD| | |
707 | END_CMD_RES|PRG_DONE|DATA_TRAN_DONE, | |
708 | host->base + MMC_I_MASK); | |
709 | ||
9a788c6b BW |
710 | DRCMR(host->dma_drcmrrx) = 0; |
711 | DRCMR(host->dma_drcmrtx) = 0; | |
1da177e4 LT |
712 | |
713 | free_irq(host->irq, host); | |
714 | pxa_free_dma(host->dma); | |
715 | iounmap(host->base); | |
3ae5eaec | 716 | dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); |
1da177e4 | 717 | |
ebebd9b0 RK |
718 | clk_put(host->clk); |
719 | ||
1da177e4 LT |
720 | release_resource(host->res); |
721 | ||
722 | mmc_free_host(mmc); | |
723 | } | |
724 | return 0; | |
725 | } | |
726 | ||
727 | #ifdef CONFIG_PM | |
3ae5eaec | 728 | static int pxamci_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 | 729 | { |
3ae5eaec | 730 | struct mmc_host *mmc = platform_get_drvdata(dev); |
1da177e4 LT |
731 | int ret = 0; |
732 | ||
9480e307 | 733 | if (mmc) |
1da177e4 LT |
734 | ret = mmc_suspend_host(mmc, state); |
735 | ||
736 | return ret; | |
737 | } | |
738 | ||
3ae5eaec | 739 | static int pxamci_resume(struct platform_device *dev) |
1da177e4 | 740 | { |
3ae5eaec | 741 | struct mmc_host *mmc = platform_get_drvdata(dev); |
1da177e4 LT |
742 | int ret = 0; |
743 | ||
9480e307 | 744 | if (mmc) |
1da177e4 LT |
745 | ret = mmc_resume_host(mmc); |
746 | ||
747 | return ret; | |
748 | } | |
749 | #else | |
750 | #define pxamci_suspend NULL | |
751 | #define pxamci_resume NULL | |
752 | #endif | |
753 | ||
3ae5eaec | 754 | static struct platform_driver pxamci_driver = { |
1da177e4 LT |
755 | .probe = pxamci_probe, |
756 | .remove = pxamci_remove, | |
757 | .suspend = pxamci_suspend, | |
758 | .resume = pxamci_resume, | |
3ae5eaec RK |
759 | .driver = { |
760 | .name = DRIVER_NAME, | |
bc65c724 | 761 | .owner = THIS_MODULE, |
3ae5eaec | 762 | }, |
1da177e4 LT |
763 | }; |
764 | ||
765 | static int __init pxamci_init(void) | |
766 | { | |
3ae5eaec | 767 | return platform_driver_register(&pxamci_driver); |
1da177e4 LT |
768 | } |
769 | ||
770 | static void __exit pxamci_exit(void) | |
771 | { | |
3ae5eaec | 772 | platform_driver_unregister(&pxamci_driver); |
1da177e4 LT |
773 | } |
774 | ||
775 | module_init(pxamci_init); | |
776 | module_exit(pxamci_exit); | |
777 | ||
778 | MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver"); | |
779 | MODULE_LICENSE("GPL"); | |
bc65c724 | 780 | MODULE_ALIAS("platform:pxa2xx-mci"); |