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ff984e57 WW |
1 | /* Realtek PCI-Express SD/MMC Card Interface driver |
2 | * | |
62282180 | 3 | * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. |
ff984e57 WW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2, or (at your option) any | |
8 | * later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along | |
16 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
18 | * Author: | |
19 | * Wei WANG <wei_wang@realsil.com.cn> | |
ff984e57 WW |
20 | */ |
21 | ||
22 | #include <linux/module.h> | |
433e075c | 23 | #include <linux/slab.h> |
ff984e57 WW |
24 | #include <linux/highmem.h> |
25 | #include <linux/delay.h> | |
26 | #include <linux/platform_device.h> | |
6291e715 | 27 | #include <linux/workqueue.h> |
ff984e57 WW |
28 | #include <linux/mmc/host.h> |
29 | #include <linux/mmc/mmc.h> | |
30 | #include <linux/mmc/sd.h> | |
31 | #include <linux/mmc/card.h> | |
32 | #include <linux/mfd/rtsx_pci.h> | |
33 | #include <asm/unaligned.h> | |
34 | ||
ff984e57 WW |
35 | struct realtek_pci_sdmmc { |
36 | struct platform_device *pdev; | |
37 | struct rtsx_pcr *pcr; | |
38 | struct mmc_host *mmc; | |
39 | struct mmc_request *mrq; | |
6291e715 MC |
40 | struct workqueue_struct *workq; |
41 | #define SDMMC_WORKQ_NAME "rtsx_pci_sdmmc_workq" | |
98fcc576 | 42 | |
6291e715 | 43 | struct work_struct work; |
98fcc576 MC |
44 | struct mutex host_mutex; |
45 | ||
ff984e57 WW |
46 | u8 ssc_depth; |
47 | unsigned int clock; | |
48 | bool vpclk; | |
49 | bool double_clk; | |
50 | bool eject; | |
51 | bool initial_mode; | |
d88691be WW |
52 | int power_state; |
53 | #define SDMMC_POWER_ON 1 | |
54 | #define SDMMC_POWER_OFF 0 | |
6291e715 MC |
55 | |
56 | unsigned int sg_count; | |
57 | s32 cookie; | |
58 | unsigned int cookie_sg_count; | |
59 | bool using_cookie; | |
ff984e57 WW |
60 | }; |
61 | ||
62 | static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host) | |
63 | { | |
64 | return &(host->pdev->dev); | |
65 | } | |
66 | ||
67 | static inline void sd_clear_error(struct realtek_pci_sdmmc *host) | |
68 | { | |
69 | rtsx_pci_write_register(host->pcr, CARD_STOP, | |
70 | SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR); | |
71 | } | |
72 | ||
73 | #ifdef DEBUG | |
74 | static void sd_print_debug_regs(struct realtek_pci_sdmmc *host) | |
75 | { | |
76 | struct rtsx_pcr *pcr = host->pcr; | |
77 | u16 i; | |
78 | u8 *ptr; | |
79 | ||
80 | /* Print SD host internal registers */ | |
81 | rtsx_pci_init_cmd(pcr); | |
82 | for (i = 0xFDA0; i <= 0xFDAE; i++) | |
83 | rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0); | |
84 | for (i = 0xFD52; i <= 0xFD69; i++) | |
85 | rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0); | |
86 | rtsx_pci_send_cmd(pcr, 100); | |
87 | ||
88 | ptr = rtsx_pci_get_cmd_data(pcr); | |
89 | for (i = 0xFDA0; i <= 0xFDAE; i++) | |
90 | dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++)); | |
91 | for (i = 0xFD52; i <= 0xFD69; i++) | |
92 | dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++)); | |
93 | } | |
94 | #else | |
95 | #define sd_print_debug_regs(host) | |
96 | #endif /* DEBUG */ | |
97 | ||
6291e715 MC |
98 | /* |
99 | * sd_pre_dma_transfer - do dma_map_sg() or using cookie | |
100 | * | |
101 | * @pre: if called in pre_req() | |
102 | * return: | |
103 | * 0 - do dma_map_sg() | |
104 | * 1 - using cookie | |
105 | */ | |
106 | static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host, | |
107 | struct mmc_data *data, bool pre) | |
108 | { | |
109 | struct rtsx_pcr *pcr = host->pcr; | |
110 | int read = data->flags & MMC_DATA_READ; | |
111 | int count = 0; | |
112 | int using_cookie = 0; | |
113 | ||
114 | if (!pre && data->host_cookie && data->host_cookie != host->cookie) { | |
115 | dev_err(sdmmc_dev(host), | |
116 | "error: data->host_cookie = %d, host->cookie = %d\n", | |
117 | data->host_cookie, host->cookie); | |
118 | data->host_cookie = 0; | |
119 | } | |
120 | ||
121 | if (pre || data->host_cookie != host->cookie) { | |
122 | count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read); | |
123 | } else { | |
124 | count = host->cookie_sg_count; | |
125 | using_cookie = 1; | |
126 | } | |
127 | ||
128 | if (pre) { | |
129 | host->cookie_sg_count = count; | |
130 | if (++host->cookie < 0) | |
131 | host->cookie = 1; | |
132 | data->host_cookie = host->cookie; | |
133 | } else { | |
134 | host->sg_count = count; | |
135 | } | |
136 | ||
137 | return using_cookie; | |
138 | } | |
139 | ||
140 | static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, | |
141 | bool is_first_req) | |
142 | { | |
143 | struct realtek_pci_sdmmc *host = mmc_priv(mmc); | |
144 | struct mmc_data *data = mrq->data; | |
145 | ||
146 | if (data->host_cookie) { | |
147 | dev_err(sdmmc_dev(host), | |
148 | "error: reset data->host_cookie = %d\n", | |
149 | data->host_cookie); | |
150 | data->host_cookie = 0; | |
151 | } | |
152 | ||
153 | sd_pre_dma_transfer(host, data, true); | |
154 | dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count); | |
155 | } | |
156 | ||
157 | static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, | |
158 | int err) | |
159 | { | |
160 | struct realtek_pci_sdmmc *host = mmc_priv(mmc); | |
161 | struct rtsx_pcr *pcr = host->pcr; | |
162 | struct mmc_data *data = mrq->data; | |
163 | int read = data->flags & MMC_DATA_READ; | |
164 | ||
165 | rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read); | |
166 | data->host_cookie = 0; | |
167 | } | |
168 | ||
ff984e57 WW |
169 | static int sd_read_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt, |
170 | u8 *buf, int buf_len, int timeout) | |
171 | { | |
172 | struct rtsx_pcr *pcr = host->pcr; | |
173 | int err, i; | |
174 | u8 trans_mode; | |
175 | ||
176 | dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD%d\n", __func__, cmd[0] - 0x40); | |
177 | ||
178 | if (!buf) | |
179 | buf_len = 0; | |
180 | ||
181 | if ((cmd[0] & 0x3F) == MMC_SEND_TUNING_BLOCK) | |
182 | trans_mode = SD_TM_AUTO_TUNING; | |
183 | else | |
184 | trans_mode = SD_TM_NORMAL_READ; | |
185 | ||
186 | rtsx_pci_init_cmd(pcr); | |
187 | ||
188 | for (i = 0; i < 5; i++) | |
189 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0 + i, 0xFF, cmd[i]); | |
190 | ||
191 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt); | |
192 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, | |
193 | 0xFF, (u8)(byte_cnt >> 8)); | |
194 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1); | |
195 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0); | |
196 | ||
197 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, | |
198 | SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | | |
199 | SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6); | |
200 | if (trans_mode != SD_TM_AUTO_TUNING) | |
201 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, | |
202 | CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); | |
203 | ||
204 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, | |
205 | 0xFF, trans_mode | SD_TRANSFER_START); | |
206 | rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, | |
207 | SD_TRANSFER_END, SD_TRANSFER_END); | |
208 | ||
209 | err = rtsx_pci_send_cmd(pcr, timeout); | |
210 | if (err < 0) { | |
211 | sd_print_debug_regs(host); | |
212 | dev_dbg(sdmmc_dev(host), | |
213 | "rtsx_pci_send_cmd fail (err = %d)\n", err); | |
214 | return err; | |
215 | } | |
216 | ||
217 | if (buf && buf_len) { | |
218 | err = rtsx_pci_read_ppbuf(pcr, buf, buf_len); | |
219 | if (err < 0) { | |
220 | dev_dbg(sdmmc_dev(host), | |
221 | "rtsx_pci_read_ppbuf fail (err = %d)\n", err); | |
222 | return err; | |
223 | } | |
224 | } | |
225 | ||
226 | return 0; | |
227 | } | |
228 | ||
229 | static int sd_write_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt, | |
230 | u8 *buf, int buf_len, int timeout) | |
231 | { | |
232 | struct rtsx_pcr *pcr = host->pcr; | |
233 | int err, i; | |
234 | u8 trans_mode; | |
235 | ||
236 | if (!buf) | |
237 | buf_len = 0; | |
238 | ||
239 | if (buf && buf_len) { | |
240 | err = rtsx_pci_write_ppbuf(pcr, buf, buf_len); | |
241 | if (err < 0) { | |
242 | dev_dbg(sdmmc_dev(host), | |
243 | "rtsx_pci_write_ppbuf fail (err = %d)\n", err); | |
244 | return err; | |
245 | } | |
246 | } | |
247 | ||
248 | trans_mode = cmd ? SD_TM_AUTO_WRITE_2 : SD_TM_AUTO_WRITE_3; | |
249 | rtsx_pci_init_cmd(pcr); | |
250 | ||
251 | if (cmd) { | |
252 | dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d\n", __func__, | |
253 | cmd[0] - 0x40); | |
254 | ||
255 | for (i = 0; i < 5; i++) | |
256 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, | |
257 | SD_CMD0 + i, 0xFF, cmd[i]); | |
258 | } | |
259 | ||
260 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt); | |
261 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, | |
262 | 0xFF, (u8)(byte_cnt >> 8)); | |
263 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1); | |
264 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0); | |
265 | ||
266 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, | |
267 | SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | | |
268 | SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6); | |
269 | ||
270 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, | |
271 | trans_mode | SD_TRANSFER_START); | |
272 | rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, | |
273 | SD_TRANSFER_END, SD_TRANSFER_END); | |
274 | ||
275 | err = rtsx_pci_send_cmd(pcr, timeout); | |
276 | if (err < 0) { | |
277 | sd_print_debug_regs(host); | |
278 | dev_dbg(sdmmc_dev(host), | |
279 | "rtsx_pci_send_cmd fail (err = %d)\n", err); | |
280 | return err; | |
281 | } | |
282 | ||
283 | return 0; | |
284 | } | |
285 | ||
98fcc576 MC |
286 | static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host, |
287 | struct mmc_command *cmd) | |
ff984e57 WW |
288 | { |
289 | struct rtsx_pcr *pcr = host->pcr; | |
290 | u8 cmd_idx = (u8)cmd->opcode; | |
291 | u32 arg = cmd->arg; | |
292 | int err = 0; | |
293 | int timeout = 100; | |
294 | int i; | |
98fcc576 MC |
295 | u8 *ptr; |
296 | int stat_idx = 0; | |
ff984e57 WW |
297 | u8 rsp_type; |
298 | int rsp_len = 5; | |
98fcc576 | 299 | bool clock_toggled = false; |
ff984e57 WW |
300 | |
301 | dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", | |
302 | __func__, cmd_idx, arg); | |
303 | ||
304 | /* Response type: | |
305 | * R0 | |
306 | * R1, R5, R6, R7 | |
307 | * R1b | |
308 | * R2 | |
309 | * R3, R4 | |
310 | */ | |
311 | switch (mmc_resp_type(cmd)) { | |
312 | case MMC_RSP_NONE: | |
313 | rsp_type = SD_RSP_TYPE_R0; | |
314 | rsp_len = 0; | |
315 | break; | |
316 | case MMC_RSP_R1: | |
317 | rsp_type = SD_RSP_TYPE_R1; | |
318 | break; | |
5027251e MC |
319 | case MMC_RSP_R1 & ~MMC_RSP_CRC: |
320 | rsp_type = SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7; | |
321 | break; | |
ff984e57 WW |
322 | case MMC_RSP_R1B: |
323 | rsp_type = SD_RSP_TYPE_R1b; | |
324 | break; | |
325 | case MMC_RSP_R2: | |
326 | rsp_type = SD_RSP_TYPE_R2; | |
327 | rsp_len = 16; | |
328 | break; | |
329 | case MMC_RSP_R3: | |
330 | rsp_type = SD_RSP_TYPE_R3; | |
331 | break; | |
332 | default: | |
333 | dev_dbg(sdmmc_dev(host), "cmd->flag is not valid\n"); | |
334 | err = -EINVAL; | |
335 | goto out; | |
336 | } | |
337 | ||
338 | if (rsp_type == SD_RSP_TYPE_R1b) | |
339 | timeout = 3000; | |
340 | ||
341 | if (cmd->opcode == SD_SWITCH_VOLTAGE) { | |
342 | err = rtsx_pci_write_register(pcr, SD_BUS_STAT, | |
343 | 0xFF, SD_CLK_TOGGLE_EN); | |
344 | if (err < 0) | |
345 | goto out; | |
98fcc576 MC |
346 | |
347 | clock_toggled = true; | |
ff984e57 WW |
348 | } |
349 | ||
350 | rtsx_pci_init_cmd(pcr); | |
351 | ||
352 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | cmd_idx); | |
353 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD1, 0xFF, (u8)(arg >> 24)); | |
354 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD2, 0xFF, (u8)(arg >> 16)); | |
355 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD3, 0xFF, (u8)(arg >> 8)); | |
356 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD4, 0xFF, (u8)arg); | |
357 | ||
358 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type); | |
359 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, | |
360 | 0x01, PINGPONG_BUFFER); | |
361 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, | |
362 | 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START); | |
363 | rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, | |
364 | SD_TRANSFER_END | SD_STAT_IDLE, | |
365 | SD_TRANSFER_END | SD_STAT_IDLE); | |
366 | ||
367 | if (rsp_type == SD_RSP_TYPE_R2) { | |
368 | /* Read data from ping-pong buffer */ | |
369 | for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++) | |
370 | rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); | |
98fcc576 | 371 | stat_idx = 16; |
ff984e57 WW |
372 | } else if (rsp_type != SD_RSP_TYPE_R0) { |
373 | /* Read data from SD_CMDx registers */ | |
374 | for (i = SD_CMD0; i <= SD_CMD4; i++) | |
375 | rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); | |
98fcc576 | 376 | stat_idx = 5; |
ff984e57 WW |
377 | } |
378 | ||
379 | rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0); | |
380 | ||
98fcc576 MC |
381 | err = rtsx_pci_send_cmd(pcr, timeout); |
382 | if (err < 0) { | |
383 | sd_print_debug_regs(host); | |
384 | sd_clear_error(host); | |
385 | dev_dbg(sdmmc_dev(host), | |
386 | "rtsx_pci_send_cmd error (err = %d)\n", err); | |
ff984e57 WW |
387 | goto out; |
388 | } | |
389 | ||
390 | if (rsp_type == SD_RSP_TYPE_R0) { | |
391 | err = 0; | |
392 | goto out; | |
393 | } | |
394 | ||
395 | /* Eliminate returned value of CHECK_REG_CMD */ | |
396 | ptr = rtsx_pci_get_cmd_data(pcr) + 1; | |
397 | ||
398 | /* Check (Start,Transmission) bit of Response */ | |
399 | if ((ptr[0] & 0xC0) != 0) { | |
400 | err = -EILSEQ; | |
401 | dev_dbg(sdmmc_dev(host), "Invalid response bit\n"); | |
402 | goto out; | |
403 | } | |
404 | ||
405 | /* Check CRC7 */ | |
406 | if (!(rsp_type & SD_NO_CHECK_CRC7)) { | |
407 | if (ptr[stat_idx] & SD_CRC7_ERR) { | |
408 | err = -EILSEQ; | |
409 | dev_dbg(sdmmc_dev(host), "CRC7 error\n"); | |
410 | goto out; | |
411 | } | |
412 | } | |
413 | ||
414 | if (rsp_type == SD_RSP_TYPE_R2) { | |
d1419d50 RT |
415 | /* |
416 | * The controller offloads the last byte {CRC-7, end bit 1'b1} | |
417 | * of response type R2. Assign dummy CRC, 0, and end bit to the | |
418 | * byte(ptr[16], goes into the LSB of resp[3] later). | |
419 | */ | |
420 | ptr[16] = 1; | |
421 | ||
ff984e57 WW |
422 | for (i = 0; i < 4; i++) { |
423 | cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4); | |
424 | dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n", | |
425 | i, cmd->resp[i]); | |
426 | } | |
427 | } else { | |
428 | cmd->resp[0] = get_unaligned_be32(ptr + 1); | |
429 | dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n", | |
430 | cmd->resp[0]); | |
431 | } | |
432 | ||
433 | out: | |
434 | cmd->error = err; | |
1b8055b4 | 435 | |
98fcc576 MC |
436 | if (err && clock_toggled) |
437 | rtsx_pci_write_register(pcr, SD_BUS_STAT, | |
438 | SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); | |
ff984e57 WW |
439 | } |
440 | ||
98fcc576 | 441 | static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq) |
ff984e57 WW |
442 | { |
443 | struct rtsx_pcr *pcr = host->pcr; | |
444 | struct mmc_host *mmc = host->mmc; | |
445 | struct mmc_card *card = mmc->card; | |
446 | struct mmc_data *data = mrq->data; | |
71ef1ea4 | 447 | int uhs = mmc_card_uhs(card); |
98fcc576 | 448 | int read = (data->flags & MMC_DATA_READ) ? 1 : 0; |
ff984e57 WW |
449 | u8 cfg2, trans_mode; |
450 | int err; | |
451 | size_t data_len = data->blksz * data->blocks; | |
452 | ||
453 | if (read) { | |
454 | cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | | |
455 | SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0; | |
456 | trans_mode = SD_TM_AUTO_READ_3; | |
457 | } else { | |
458 | cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | | |
459 | SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0; | |
460 | trans_mode = SD_TM_AUTO_WRITE_3; | |
461 | } | |
462 | ||
463 | if (!uhs) | |
464 | cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; | |
465 | ||
466 | rtsx_pci_init_cmd(pcr); | |
467 | ||
468 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x00); | |
469 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 0x02); | |
470 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, | |
471 | 0xFF, (u8)data->blocks); | |
472 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, | |
473 | 0xFF, (u8)(data->blocks >> 8)); | |
ff984e57 WW |
474 | |
475 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, | |
476 | DMA_DONE_INT, DMA_DONE_INT); | |
477 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, | |
478 | 0xFF, (u8)(data_len >> 24)); | |
479 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, | |
480 | 0xFF, (u8)(data_len >> 16)); | |
481 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, | |
482 | 0xFF, (u8)(data_len >> 8)); | |
483 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); | |
484 | if (read) { | |
485 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, | |
486 | 0x03 | DMA_PACK_SIZE_MASK, | |
487 | DMA_DIR_FROM_CARD | DMA_EN | DMA_512); | |
488 | } else { | |
489 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, | |
490 | 0x03 | DMA_PACK_SIZE_MASK, | |
491 | DMA_DIR_TO_CARD | DMA_EN | DMA_512); | |
492 | } | |
493 | ||
494 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, | |
495 | 0x01, RING_BUFFER); | |
496 | ||
38d324df | 497 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2); |
ff984e57 WW |
498 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, |
499 | trans_mode | SD_TRANSFER_START); | |
500 | rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, | |
501 | SD_TRANSFER_END, SD_TRANSFER_END); | |
502 | ||
503 | rtsx_pci_send_cmd_no_wait(pcr); | |
504 | ||
6291e715 | 505 | err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, read, 10000); |
c42deffd | 506 | if (err < 0) { |
98fcc576 MC |
507 | sd_clear_error(host); |
508 | return err; | |
c42deffd MC |
509 | } |
510 | ||
98fcc576 | 511 | return 0; |
c42deffd MC |
512 | } |
513 | ||
ff984e57 WW |
514 | static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host) |
515 | { | |
516 | rtsx_pci_write_register(host->pcr, SD_CFG1, | |
517 | SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128); | |
518 | } | |
519 | ||
520 | static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host) | |
521 | { | |
522 | rtsx_pci_write_register(host->pcr, SD_CFG1, | |
523 | SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0); | |
524 | } | |
525 | ||
526 | static void sd_normal_rw(struct realtek_pci_sdmmc *host, | |
527 | struct mmc_request *mrq) | |
528 | { | |
529 | struct mmc_command *cmd = mrq->cmd; | |
530 | struct mmc_data *data = mrq->data; | |
531 | u8 _cmd[5], *buf; | |
532 | ||
533 | _cmd[0] = 0x40 | (u8)cmd->opcode; | |
534 | put_unaligned_be32(cmd->arg, (u32 *)(&_cmd[1])); | |
535 | ||
536 | buf = kzalloc(data->blksz, GFP_NOIO); | |
537 | if (!buf) { | |
538 | cmd->error = -ENOMEM; | |
539 | return; | |
540 | } | |
541 | ||
542 | if (data->flags & MMC_DATA_READ) { | |
543 | if (host->initial_mode) | |
544 | sd_disable_initial_mode(host); | |
545 | ||
546 | cmd->error = sd_read_data(host, _cmd, (u16)data->blksz, buf, | |
547 | data->blksz, 200); | |
548 | ||
549 | if (host->initial_mode) | |
550 | sd_enable_initial_mode(host); | |
551 | ||
552 | sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz); | |
553 | } else { | |
554 | sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz); | |
555 | ||
556 | cmd->error = sd_write_data(host, _cmd, (u16)data->blksz, buf, | |
557 | data->blksz, 200); | |
558 | } | |
559 | ||
560 | kfree(buf); | |
561 | } | |
562 | ||
84d72f9c WW |
563 | static int sd_change_phase(struct realtek_pci_sdmmc *host, |
564 | u8 sample_point, bool rx) | |
ff984e57 WW |
565 | { |
566 | struct rtsx_pcr *pcr = host->pcr; | |
567 | int err; | |
568 | ||
84d72f9c WW |
569 | dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n", |
570 | __func__, rx ? "RX" : "TX", sample_point); | |
ff984e57 WW |
571 | |
572 | rtsx_pci_init_cmd(pcr); | |
573 | ||
574 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK); | |
84d72f9c WW |
575 | if (rx) |
576 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, | |
577 | SD_VPRX_CTL, 0x1F, sample_point); | |
578 | else | |
579 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, | |
580 | SD_VPTX_CTL, 0x1F, sample_point); | |
ff984e57 WW |
581 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0); |
582 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, | |
583 | PHASE_NOT_RESET, PHASE_NOT_RESET); | |
584 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0); | |
585 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); | |
586 | ||
587 | err = rtsx_pci_send_cmd(pcr, 100); | |
588 | if (err < 0) | |
589 | return err; | |
590 | ||
591 | return 0; | |
592 | } | |
593 | ||
abcc6b29 | 594 | static inline u32 test_phase_bit(u32 phase_map, unsigned int bit) |
ff984e57 | 595 | { |
abcc6b29 MC |
596 | bit %= RTSX_PHASE_MAX; |
597 | return phase_map & (1 << bit); | |
598 | } | |
ff984e57 | 599 | |
abcc6b29 MC |
600 | static int sd_get_phase_len(u32 phase_map, unsigned int start_bit) |
601 | { | |
602 | int i; | |
ff984e57 | 603 | |
abcc6b29 MC |
604 | for (i = 0; i < RTSX_PHASE_MAX; i++) { |
605 | if (test_phase_bit(phase_map, start_bit + i) == 0) | |
606 | return i; | |
ff984e57 | 607 | } |
abcc6b29 MC |
608 | return RTSX_PHASE_MAX; |
609 | } | |
ff984e57 | 610 | |
abcc6b29 MC |
611 | static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map) |
612 | { | |
613 | int start = 0, len = 0; | |
614 | int start_final = 0, len_final = 0; | |
615 | u8 final_phase = 0xFF; | |
616 | ||
617 | if (phase_map == 0) { | |
618 | dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map); | |
619 | return final_phase; | |
ff984e57 WW |
620 | } |
621 | ||
abcc6b29 MC |
622 | while (start < RTSX_PHASE_MAX) { |
623 | len = sd_get_phase_len(phase_map, start); | |
624 | if (len_final < len) { | |
625 | start_final = start; | |
626 | len_final = len; | |
ff984e57 | 627 | } |
abcc6b29 | 628 | start += len ? len : 1; |
ff984e57 WW |
629 | } |
630 | ||
abcc6b29 MC |
631 | final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX; |
632 | dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n", | |
633 | phase_map, len_final, final_phase); | |
634 | ||
ff984e57 WW |
635 | return final_phase; |
636 | } | |
637 | ||
638 | static void sd_wait_data_idle(struct realtek_pci_sdmmc *host) | |
639 | { | |
640 | int err, i; | |
641 | u8 val = 0; | |
642 | ||
643 | for (i = 0; i < 100; i++) { | |
644 | err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val); | |
645 | if (val & SD_DATA_IDLE) | |
646 | return; | |
647 | ||
648 | udelay(100); | |
649 | } | |
650 | } | |
651 | ||
652 | static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host, | |
653 | u8 opcode, u8 sample_point) | |
654 | { | |
655 | int err; | |
656 | u8 cmd[5] = {0}; | |
657 | ||
84d72f9c | 658 | err = sd_change_phase(host, sample_point, true); |
ff984e57 WW |
659 | if (err < 0) |
660 | return err; | |
661 | ||
662 | cmd[0] = 0x40 | opcode; | |
663 | err = sd_read_data(host, cmd, 0x40, NULL, 0, 100); | |
664 | if (err < 0) { | |
665 | /* Wait till SD DATA IDLE */ | |
666 | sd_wait_data_idle(host); | |
667 | sd_clear_error(host); | |
668 | return err; | |
669 | } | |
670 | ||
671 | return 0; | |
672 | } | |
673 | ||
674 | static int sd_tuning_phase(struct realtek_pci_sdmmc *host, | |
675 | u8 opcode, u32 *phase_map) | |
676 | { | |
677 | int err, i; | |
678 | u32 raw_phase_map = 0; | |
679 | ||
abcc6b29 | 680 | for (i = 0; i < RTSX_PHASE_MAX; i++) { |
ff984e57 WW |
681 | err = sd_tuning_rx_cmd(host, opcode, (u8)i); |
682 | if (err == 0) | |
683 | raw_phase_map |= 1 << i; | |
684 | } | |
685 | ||
686 | if (phase_map) | |
687 | *phase_map = raw_phase_map; | |
688 | ||
689 | return 0; | |
690 | } | |
691 | ||
692 | static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode) | |
693 | { | |
694 | int err, i; | |
695 | u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map; | |
696 | u8 final_phase; | |
697 | ||
698 | for (i = 0; i < RX_TUNING_CNT; i++) { | |
699 | err = sd_tuning_phase(host, opcode, &(raw_phase_map[i])); | |
700 | if (err < 0) | |
701 | return err; | |
702 | ||
703 | if (raw_phase_map[i] == 0) | |
704 | break; | |
705 | } | |
706 | ||
707 | phase_map = 0xFFFFFFFF; | |
708 | for (i = 0; i < RX_TUNING_CNT; i++) { | |
709 | dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n", | |
710 | i, raw_phase_map[i]); | |
711 | phase_map &= raw_phase_map[i]; | |
712 | } | |
713 | dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map); | |
714 | ||
715 | if (phase_map) { | |
716 | final_phase = sd_search_final_phase(host, phase_map); | |
717 | if (final_phase == 0xFF) | |
718 | return -EINVAL; | |
719 | ||
84d72f9c | 720 | err = sd_change_phase(host, final_phase, true); |
ff984e57 WW |
721 | if (err < 0) |
722 | return err; | |
723 | } else { | |
724 | return -EINVAL; | |
725 | } | |
726 | ||
727 | return 0; | |
728 | } | |
729 | ||
6291e715 | 730 | static inline int sd_rw_cmd(struct mmc_command *cmd) |
ff984e57 | 731 | { |
6291e715 MC |
732 | return mmc_op_multi(cmd->opcode) || |
733 | (cmd->opcode == MMC_READ_SINGLE_BLOCK) || | |
734 | (cmd->opcode == MMC_WRITE_BLOCK); | |
735 | } | |
736 | ||
737 | static void sd_request(struct work_struct *work) | |
738 | { | |
739 | struct realtek_pci_sdmmc *host = container_of(work, | |
740 | struct realtek_pci_sdmmc, work); | |
ff984e57 | 741 | struct rtsx_pcr *pcr = host->pcr; |
6291e715 MC |
742 | |
743 | struct mmc_host *mmc = host->mmc; | |
744 | struct mmc_request *mrq = host->mrq; | |
ff984e57 WW |
745 | struct mmc_command *cmd = mrq->cmd; |
746 | struct mmc_data *data = mrq->data; | |
6291e715 | 747 | |
ff984e57 | 748 | unsigned int data_size = 0; |
c3481955 | 749 | int err; |
ff984e57 WW |
750 | |
751 | if (host->eject) { | |
752 | cmd->error = -ENOMEDIUM; | |
753 | goto finish; | |
754 | } | |
755 | ||
c3481955 WW |
756 | err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); |
757 | if (err) { | |
758 | cmd->error = err; | |
759 | goto finish; | |
760 | } | |
761 | ||
98fcc576 MC |
762 | mutex_lock(&pcr->pcr_mutex); |
763 | ||
ff984e57 WW |
764 | rtsx_pci_start_run(pcr); |
765 | ||
766 | rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth, | |
767 | host->initial_mode, host->double_clk, host->vpclk); | |
768 | rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL); | |
769 | rtsx_pci_write_register(pcr, CARD_SHARE_MODE, | |
770 | CARD_SHARE_MASK, CARD_SHARE_48_SD); | |
771 | ||
98fcc576 MC |
772 | mutex_lock(&host->host_mutex); |
773 | host->mrq = mrq; | |
774 | mutex_unlock(&host->host_mutex); | |
775 | ||
ff984e57 WW |
776 | if (mrq->data) |
777 | data_size = data->blocks * data->blksz; | |
778 | ||
6291e715 | 779 | if (!data_size || sd_rw_cmd(cmd)) { |
98fcc576 | 780 | sd_send_cmd_get_rsp(host, cmd); |
ff984e57 | 781 | |
98fcc576 MC |
782 | if (!cmd->error && data_size) { |
783 | sd_rw_multi(host, mrq); | |
6291e715 MC |
784 | if (!host->using_cookie) |
785 | sdmmc_post_req(host->mmc, host->mrq, 0); | |
98fcc576 MC |
786 | |
787 | if (mmc_op_multi(cmd->opcode) && mrq->stop) | |
788 | sd_send_cmd_get_rsp(host, mrq->stop); | |
789 | } | |
ff984e57 WW |
790 | } else { |
791 | sd_normal_rw(host, mrq); | |
792 | } | |
98fcc576 MC |
793 | |
794 | if (mrq->data) { | |
795 | if (cmd->error || data->error) | |
796 | data->bytes_xfered = 0; | |
797 | else | |
798 | data->bytes_xfered = data->blocks * data->blksz; | |
799 | } | |
800 | ||
801 | mutex_unlock(&pcr->pcr_mutex); | |
ff984e57 WW |
802 | |
803 | finish: | |
98fcc576 MC |
804 | if (cmd->error) |
805 | dev_dbg(sdmmc_dev(host), "cmd->error = %d\n", cmd->error); | |
806 | ||
807 | mutex_lock(&host->host_mutex); | |
808 | host->mrq = NULL; | |
809 | mutex_unlock(&host->host_mutex); | |
810 | ||
811 | mmc_request_done(mmc, mrq); | |
ff984e57 WW |
812 | } |
813 | ||
6291e715 MC |
814 | static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq) |
815 | { | |
816 | struct realtek_pci_sdmmc *host = mmc_priv(mmc); | |
817 | struct mmc_data *data = mrq->data; | |
818 | ||
819 | mutex_lock(&host->host_mutex); | |
820 | host->mrq = mrq; | |
821 | mutex_unlock(&host->host_mutex); | |
822 | ||
823 | if (sd_rw_cmd(mrq->cmd)) | |
824 | host->using_cookie = sd_pre_dma_transfer(host, data, false); | |
825 | ||
826 | queue_work(host->workq, &host->work); | |
827 | } | |
828 | ||
ff984e57 WW |
829 | static int sd_set_bus_width(struct realtek_pci_sdmmc *host, |
830 | unsigned char bus_width) | |
831 | { | |
832 | int err = 0; | |
833 | u8 width[] = { | |
834 | [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT, | |
835 | [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT, | |
836 | [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT, | |
837 | }; | |
838 | ||
839 | if (bus_width <= MMC_BUS_WIDTH_8) | |
840 | err = rtsx_pci_write_register(host->pcr, SD_CFG1, | |
841 | 0x03, width[bus_width]); | |
842 | ||
843 | return err; | |
844 | } | |
845 | ||
846 | static int sd_power_on(struct realtek_pci_sdmmc *host) | |
847 | { | |
848 | struct rtsx_pcr *pcr = host->pcr; | |
849 | int err; | |
850 | ||
d88691be WW |
851 | if (host->power_state == SDMMC_POWER_ON) |
852 | return 0; | |
853 | ||
ff984e57 WW |
854 | rtsx_pci_init_cmd(pcr); |
855 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL); | |
856 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE, | |
857 | CARD_SHARE_MASK, CARD_SHARE_48_SD); | |
858 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, | |
859 | SD_CLK_EN, SD_CLK_EN); | |
860 | err = rtsx_pci_send_cmd(pcr, 100); | |
861 | if (err < 0) | |
862 | return err; | |
863 | ||
864 | err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD); | |
865 | if (err < 0) | |
866 | return err; | |
867 | ||
868 | err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD); | |
869 | if (err < 0) | |
870 | return err; | |
871 | ||
872 | err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN); | |
873 | if (err < 0) | |
874 | return err; | |
875 | ||
d88691be | 876 | host->power_state = SDMMC_POWER_ON; |
ff984e57 WW |
877 | return 0; |
878 | } | |
879 | ||
880 | static int sd_power_off(struct realtek_pci_sdmmc *host) | |
881 | { | |
882 | struct rtsx_pcr *pcr = host->pcr; | |
883 | int err; | |
884 | ||
d88691be WW |
885 | host->power_state = SDMMC_POWER_OFF; |
886 | ||
ff984e57 WW |
887 | rtsx_pci_init_cmd(pcr); |
888 | ||
889 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0); | |
890 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0); | |
891 | ||
892 | err = rtsx_pci_send_cmd(pcr, 100); | |
893 | if (err < 0) | |
894 | return err; | |
895 | ||
896 | err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD); | |
897 | if (err < 0) | |
898 | return err; | |
899 | ||
900 | return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD); | |
901 | } | |
902 | ||
903 | static int sd_set_power_mode(struct realtek_pci_sdmmc *host, | |
904 | unsigned char power_mode) | |
905 | { | |
906 | int err; | |
907 | ||
908 | if (power_mode == MMC_POWER_OFF) | |
909 | err = sd_power_off(host); | |
910 | else | |
911 | err = sd_power_on(host); | |
912 | ||
913 | return err; | |
914 | } | |
915 | ||
84d72f9c | 916 | static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing) |
ff984e57 WW |
917 | { |
918 | struct rtsx_pcr *pcr = host->pcr; | |
919 | int err = 0; | |
920 | ||
ff984e57 WW |
921 | rtsx_pci_init_cmd(pcr); |
922 | ||
923 | switch (timing) { | |
924 | case MMC_TIMING_UHS_SDR104: | |
925 | case MMC_TIMING_UHS_SDR50: | |
926 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, | |
927 | 0x0C | SD_ASYNC_FIFO_NOT_RST, | |
928 | SD_30_MODE | SD_ASYNC_FIFO_NOT_RST); | |
929 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, | |
930 | CLK_LOW_FREQ, CLK_LOW_FREQ); | |
931 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, | |
932 | CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); | |
933 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); | |
934 | break; | |
935 | ||
1a0ae377 | 936 | case MMC_TIMING_MMC_DDR52: |
ff984e57 | 937 | case MMC_TIMING_UHS_DDR50: |
ff984e57 WW |
938 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, |
939 | 0x0C | SD_ASYNC_FIFO_NOT_RST, | |
940 | SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST); | |
941 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, | |
942 | CLK_LOW_FREQ, CLK_LOW_FREQ); | |
943 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, | |
944 | CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); | |
945 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); | |
946 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, | |
947 | DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT); | |
948 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, | |
949 | DDR_VAR_RX_DAT | DDR_VAR_RX_CMD, | |
950 | DDR_VAR_RX_DAT | DDR_VAR_RX_CMD); | |
951 | break; | |
952 | ||
953 | case MMC_TIMING_MMC_HS: | |
954 | case MMC_TIMING_SD_HS: | |
955 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, | |
956 | 0x0C, SD_20_MODE); | |
957 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, | |
958 | CLK_LOW_FREQ, CLK_LOW_FREQ); | |
959 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, | |
960 | CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); | |
961 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); | |
962 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, | |
963 | SD20_TX_SEL_MASK, SD20_TX_14_AHEAD); | |
964 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, | |
965 | SD20_RX_SEL_MASK, SD20_RX_14_DELAY); | |
966 | break; | |
967 | ||
968 | default: | |
969 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, | |
970 | SD_CFG1, 0x0C, SD_20_MODE); | |
971 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, | |
972 | CLK_LOW_FREQ, CLK_LOW_FREQ); | |
973 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, | |
974 | CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); | |
975 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); | |
976 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, | |
977 | SD_PUSH_POINT_CTL, 0xFF, 0); | |
978 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, | |
979 | SD20_RX_SEL_MASK, SD20_RX_POS_EDGE); | |
980 | break; | |
981 | } | |
982 | ||
983 | err = rtsx_pci_send_cmd(pcr, 100); | |
984 | ||
985 | return err; | |
986 | } | |
987 | ||
988 | static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
989 | { | |
990 | struct realtek_pci_sdmmc *host = mmc_priv(mmc); | |
991 | struct rtsx_pcr *pcr = host->pcr; | |
992 | ||
993 | if (host->eject) | |
994 | return; | |
995 | ||
c3481955 WW |
996 | if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD)) |
997 | return; | |
998 | ||
ff984e57 WW |
999 | mutex_lock(&pcr->pcr_mutex); |
1000 | ||
1001 | rtsx_pci_start_run(pcr); | |
1002 | ||
1003 | sd_set_bus_width(host, ios->bus_width); | |
1004 | sd_set_power_mode(host, ios->power_mode); | |
84d72f9c | 1005 | sd_set_timing(host, ios->timing); |
ff984e57 WW |
1006 | |
1007 | host->vpclk = false; | |
1008 | host->double_clk = true; | |
1009 | ||
1010 | switch (ios->timing) { | |
1011 | case MMC_TIMING_UHS_SDR104: | |
1012 | case MMC_TIMING_UHS_SDR50: | |
1013 | host->ssc_depth = RTSX_SSC_DEPTH_2M; | |
1014 | host->vpclk = true; | |
1015 | host->double_clk = false; | |
1016 | break; | |
1a0ae377 | 1017 | case MMC_TIMING_MMC_DDR52: |
ff984e57 WW |
1018 | case MMC_TIMING_UHS_DDR50: |
1019 | case MMC_TIMING_UHS_SDR25: | |
1020 | host->ssc_depth = RTSX_SSC_DEPTH_1M; | |
1021 | break; | |
1022 | default: | |
1023 | host->ssc_depth = RTSX_SSC_DEPTH_500K; | |
1024 | break; | |
1025 | } | |
1026 | ||
1027 | host->initial_mode = (ios->clock <= 1000000) ? true : false; | |
1028 | ||
1029 | host->clock = ios->clock; | |
1030 | rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth, | |
1031 | host->initial_mode, host->double_clk, host->vpclk); | |
1032 | ||
1033 | mutex_unlock(&pcr->pcr_mutex); | |
1034 | } | |
1035 | ||
1036 | static int sdmmc_get_ro(struct mmc_host *mmc) | |
1037 | { | |
1038 | struct realtek_pci_sdmmc *host = mmc_priv(mmc); | |
1039 | struct rtsx_pcr *pcr = host->pcr; | |
1040 | int ro = 0; | |
1041 | u32 val; | |
1042 | ||
1043 | if (host->eject) | |
1044 | return -ENOMEDIUM; | |
1045 | ||
1046 | mutex_lock(&pcr->pcr_mutex); | |
1047 | ||
1048 | rtsx_pci_start_run(pcr); | |
1049 | ||
1050 | /* Check SD mechanical write-protect switch */ | |
1051 | val = rtsx_pci_readl(pcr, RTSX_BIPR); | |
1052 | dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); | |
1053 | if (val & SD_WRITE_PROTECT) | |
1054 | ro = 1; | |
1055 | ||
1056 | mutex_unlock(&pcr->pcr_mutex); | |
1057 | ||
1058 | return ro; | |
1059 | } | |
1060 | ||
1061 | static int sdmmc_get_cd(struct mmc_host *mmc) | |
1062 | { | |
1063 | struct realtek_pci_sdmmc *host = mmc_priv(mmc); | |
1064 | struct rtsx_pcr *pcr = host->pcr; | |
1065 | int cd = 0; | |
1066 | u32 val; | |
1067 | ||
1068 | if (host->eject) | |
1069 | return -ENOMEDIUM; | |
1070 | ||
1071 | mutex_lock(&pcr->pcr_mutex); | |
1072 | ||
1073 | rtsx_pci_start_run(pcr); | |
1074 | ||
1075 | /* Check SD card detect */ | |
1076 | val = rtsx_pci_card_exist(pcr); | |
1077 | dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); | |
1078 | if (val & SD_EXIST) | |
1079 | cd = 1; | |
1080 | ||
1081 | mutex_unlock(&pcr->pcr_mutex); | |
1082 | ||
1083 | return cd; | |
1084 | } | |
1085 | ||
1086 | static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host) | |
1087 | { | |
1088 | struct rtsx_pcr *pcr = host->pcr; | |
1089 | int err; | |
1090 | u8 stat; | |
1091 | ||
1092 | /* Reference to Signal Voltage Switch Sequence in SD spec. | |
1093 | * Wait for a period of time so that the card can drive SD_CMD and | |
1094 | * SD_DAT[3:0] to low after sending back CMD11 response. | |
1095 | */ | |
1096 | mdelay(1); | |
1097 | ||
1098 | /* SD_CMD, SD_DAT[3:0] should be driven to low by card; | |
1099 | * If either one of SD_CMD,SD_DAT[3:0] is not low, | |
1100 | * abort the voltage switch sequence; | |
1101 | */ | |
1102 | err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); | |
1103 | if (err < 0) | |
1104 | return err; | |
1105 | ||
1106 | if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | | |
1107 | SD_DAT1_STATUS | SD_DAT0_STATUS)) | |
1108 | return -EINVAL; | |
1109 | ||
1110 | /* Stop toggle SD clock */ | |
1111 | err = rtsx_pci_write_register(pcr, SD_BUS_STAT, | |
1112 | 0xFF, SD_CLK_FORCE_STOP); | |
1113 | if (err < 0) | |
1114 | return err; | |
1115 | ||
1116 | return 0; | |
1117 | } | |
1118 | ||
1119 | static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host) | |
1120 | { | |
1121 | struct rtsx_pcr *pcr = host->pcr; | |
1122 | int err; | |
1123 | u8 stat, mask, val; | |
1124 | ||
1125 | /* Wait 1.8V output of voltage regulator in card stable */ | |
1126 | msleep(50); | |
1127 | ||
1128 | /* Toggle SD clock again */ | |
1129 | err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN); | |
1130 | if (err < 0) | |
1131 | return err; | |
1132 | ||
1133 | /* Wait for a period of time so that the card can drive | |
1134 | * SD_DAT[3:0] to high at 1.8V | |
1135 | */ | |
1136 | msleep(20); | |
1137 | ||
1138 | /* SD_CMD, SD_DAT[3:0] should be pulled high by host */ | |
1139 | err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); | |
1140 | if (err < 0) | |
1141 | return err; | |
1142 | ||
1143 | mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | | |
1144 | SD_DAT1_STATUS | SD_DAT0_STATUS; | |
1145 | val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | | |
1146 | SD_DAT1_STATUS | SD_DAT0_STATUS; | |
1147 | if ((stat & mask) != val) { | |
1148 | dev_dbg(sdmmc_dev(host), | |
1149 | "%s: SD_BUS_STAT = 0x%x\n", __func__, stat); | |
1150 | rtsx_pci_write_register(pcr, SD_BUS_STAT, | |
1151 | SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); | |
1152 | rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0); | |
1153 | return -EINVAL; | |
1154 | } | |
1155 | ||
1156 | return 0; | |
1157 | } | |
1158 | ||
ff984e57 WW |
1159 | static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) |
1160 | { | |
1161 | struct realtek_pci_sdmmc *host = mmc_priv(mmc); | |
1162 | struct rtsx_pcr *pcr = host->pcr; | |
1163 | int err = 0; | |
1164 | u8 voltage; | |
1165 | ||
1166 | dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n", | |
1167 | __func__, ios->signal_voltage); | |
1168 | ||
1169 | if (host->eject) | |
1170 | return -ENOMEDIUM; | |
1171 | ||
c3481955 WW |
1172 | err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); |
1173 | if (err) | |
1174 | return err; | |
1175 | ||
ff984e57 WW |
1176 | mutex_lock(&pcr->pcr_mutex); |
1177 | ||
1178 | rtsx_pci_start_run(pcr); | |
1179 | ||
1180 | if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) | |
ef85e736 | 1181 | voltage = OUTPUT_3V3; |
ff984e57 | 1182 | else |
ef85e736 | 1183 | voltage = OUTPUT_1V8; |
ff984e57 | 1184 | |
ef85e736 | 1185 | if (voltage == OUTPUT_1V8) { |
ff984e57 WW |
1186 | err = sd_wait_voltage_stable_1(host); |
1187 | if (err < 0) | |
1188 | goto out; | |
1189 | } | |
1190 | ||
ef85e736 | 1191 | err = rtsx_pci_switch_output_voltage(pcr, voltage); |
ff984e57 WW |
1192 | if (err < 0) |
1193 | goto out; | |
1194 | ||
ef85e736 | 1195 | if (voltage == OUTPUT_1V8) { |
ff984e57 WW |
1196 | err = sd_wait_voltage_stable_2(host); |
1197 | if (err < 0) | |
1198 | goto out; | |
1199 | } | |
1200 | ||
1b8055b4 | 1201 | out: |
ff984e57 WW |
1202 | /* Stop toggle SD clock in idle */ |
1203 | err = rtsx_pci_write_register(pcr, SD_BUS_STAT, | |
1204 | SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); | |
1205 | ||
ff984e57 WW |
1206 | mutex_unlock(&pcr->pcr_mutex); |
1207 | ||
1208 | return err; | |
1209 | } | |
1210 | ||
1211 | static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode) | |
1212 | { | |
1213 | struct realtek_pci_sdmmc *host = mmc_priv(mmc); | |
1214 | struct rtsx_pcr *pcr = host->pcr; | |
1215 | int err = 0; | |
1216 | ||
1217 | if (host->eject) | |
1218 | return -ENOMEDIUM; | |
1219 | ||
c3481955 WW |
1220 | err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); |
1221 | if (err) | |
1222 | return err; | |
1223 | ||
ff984e57 WW |
1224 | mutex_lock(&pcr->pcr_mutex); |
1225 | ||
1226 | rtsx_pci_start_run(pcr); | |
1227 | ||
84d72f9c WW |
1228 | /* Set initial TX phase */ |
1229 | switch (mmc->ios.timing) { | |
1230 | case MMC_TIMING_UHS_SDR104: | |
1231 | err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false); | |
1232 | break; | |
1233 | ||
1234 | case MMC_TIMING_UHS_SDR50: | |
1235 | err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false); | |
1236 | break; | |
1237 | ||
1238 | case MMC_TIMING_UHS_DDR50: | |
1239 | err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false); | |
1240 | break; | |
1241 | ||
1242 | default: | |
1243 | err = 0; | |
1244 | } | |
ff984e57 | 1245 | |
84d72f9c WW |
1246 | if (err) |
1247 | goto out; | |
1248 | ||
1249 | /* Tuning RX phase */ | |
1250 | if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) || | |
1251 | (mmc->ios.timing == MMC_TIMING_UHS_SDR50)) | |
1252 | err = sd_tuning_rx(host, opcode); | |
1253 | else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) | |
1254 | err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true); | |
1255 | ||
1256 | out: | |
ff984e57 WW |
1257 | mutex_unlock(&pcr->pcr_mutex); |
1258 | ||
1259 | return err; | |
1260 | } | |
1261 | ||
1262 | static const struct mmc_host_ops realtek_pci_sdmmc_ops = { | |
6291e715 MC |
1263 | .pre_req = sdmmc_pre_req, |
1264 | .post_req = sdmmc_post_req, | |
ff984e57 WW |
1265 | .request = sdmmc_request, |
1266 | .set_ios = sdmmc_set_ios, | |
1267 | .get_ro = sdmmc_get_ro, | |
1268 | .get_cd = sdmmc_get_cd, | |
1269 | .start_signal_voltage_switch = sdmmc_switch_voltage, | |
1270 | .execute_tuning = sdmmc_execute_tuning, | |
1271 | }; | |
1272 | ||
ff984e57 WW |
1273 | static void init_extra_caps(struct realtek_pci_sdmmc *host) |
1274 | { | |
1275 | struct mmc_host *mmc = host->mmc; | |
1276 | struct rtsx_pcr *pcr = host->pcr; | |
1277 | ||
1278 | dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps); | |
1279 | ||
1280 | if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50) | |
1281 | mmc->caps |= MMC_CAP_UHS_SDR50; | |
1282 | if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104) | |
1283 | mmc->caps |= MMC_CAP_UHS_SDR104; | |
1284 | if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50) | |
1285 | mmc->caps |= MMC_CAP_UHS_DDR50; | |
1286 | if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR) | |
1287 | mmc->caps |= MMC_CAP_1_8V_DDR; | |
1288 | if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT) | |
1289 | mmc->caps |= MMC_CAP_8_BIT_DATA; | |
1290 | } | |
1291 | ||
1292 | static void realtek_init_host(struct realtek_pci_sdmmc *host) | |
1293 | { | |
1294 | struct mmc_host *mmc = host->mmc; | |
1295 | ||
1296 | mmc->f_min = 250000; | |
1297 | mmc->f_max = 208000000; | |
1298 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; | |
1299 | mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | | |
1300 | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST | | |
1301 | MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; | |
1302 | mmc->max_current_330 = 400; | |
1303 | mmc->max_current_180 = 800; | |
1304 | mmc->ops = &realtek_pci_sdmmc_ops; | |
1305 | ||
1306 | init_extra_caps(host); | |
1307 | ||
1308 | mmc->max_segs = 256; | |
1309 | mmc->max_seg_size = 65536; | |
1310 | mmc->max_blk_size = 512; | |
1311 | mmc->max_blk_count = 65535; | |
1312 | mmc->max_req_size = 524288; | |
1313 | } | |
1314 | ||
1315 | static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev) | |
1316 | { | |
1317 | struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); | |
1318 | ||
1319 | mmc_detect_change(host->mmc, 0); | |
1320 | } | |
1321 | ||
1322 | static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev) | |
1323 | { | |
1324 | struct mmc_host *mmc; | |
1325 | struct realtek_pci_sdmmc *host; | |
1326 | struct rtsx_pcr *pcr; | |
1327 | struct pcr_handle *handle = pdev->dev.platform_data; | |
1328 | ||
1329 | if (!handle) | |
1330 | return -ENXIO; | |
1331 | ||
1332 | pcr = handle->pcr; | |
1333 | if (!pcr) | |
1334 | return -ENXIO; | |
1335 | ||
1336 | dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n"); | |
1337 | ||
1338 | mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); | |
1339 | if (!mmc) | |
1340 | return -ENOMEM; | |
1341 | ||
1342 | host = mmc_priv(mmc); | |
6291e715 MC |
1343 | host->workq = create_singlethread_workqueue(SDMMC_WORKQ_NAME); |
1344 | if (!host->workq) { | |
1345 | mmc_free_host(mmc); | |
1346 | return -ENOMEM; | |
1347 | } | |
ff984e57 WW |
1348 | host->pcr = pcr; |
1349 | host->mmc = mmc; | |
1350 | host->pdev = pdev; | |
d88691be | 1351 | host->power_state = SDMMC_POWER_OFF; |
6291e715 | 1352 | INIT_WORK(&host->work, sd_request); |
ff984e57 WW |
1353 | platform_set_drvdata(pdev, host); |
1354 | pcr->slots[RTSX_SD_CARD].p_dev = pdev; | |
1355 | pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event; | |
1356 | ||
98fcc576 | 1357 | mutex_init(&host->host_mutex); |
ff984e57 WW |
1358 | |
1359 | realtek_init_host(host); | |
1360 | ||
1361 | mmc_add_host(mmc); | |
1362 | ||
1363 | return 0; | |
1364 | } | |
1365 | ||
1366 | static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev) | |
1367 | { | |
1368 | struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); | |
1369 | struct rtsx_pcr *pcr; | |
1370 | struct mmc_host *mmc; | |
1371 | ||
1372 | if (!host) | |
1373 | return 0; | |
1374 | ||
1375 | pcr = host->pcr; | |
1376 | pcr->slots[RTSX_SD_CARD].p_dev = NULL; | |
1377 | pcr->slots[RTSX_SD_CARD].card_event = NULL; | |
1378 | mmc = host->mmc; | |
ff984e57 | 1379 | |
6291e715 MC |
1380 | cancel_work_sync(&host->work); |
1381 | ||
98fcc576 | 1382 | mutex_lock(&host->host_mutex); |
ff984e57 WW |
1383 | if (host->mrq) { |
1384 | dev_dbg(&(pdev->dev), | |
1385 | "%s: Controller removed during transfer\n", | |
1386 | mmc_hostname(mmc)); | |
1387 | ||
98fcc576 | 1388 | rtsx_pci_complete_unfinished_transfer(pcr); |
ff984e57 | 1389 | |
98fcc576 MC |
1390 | host->mrq->cmd->error = -ENOMEDIUM; |
1391 | if (host->mrq->stop) | |
1392 | host->mrq->stop->error = -ENOMEDIUM; | |
1393 | mmc_request_done(mmc, host->mrq); | |
ff984e57 | 1394 | } |
98fcc576 | 1395 | mutex_unlock(&host->host_mutex); |
ff984e57 WW |
1396 | |
1397 | mmc_remove_host(mmc); | |
640e09bc MC |
1398 | host->eject = true; |
1399 | ||
6291e715 MC |
1400 | flush_workqueue(host->workq); |
1401 | destroy_workqueue(host->workq); | |
1402 | host->workq = NULL; | |
1403 | ||
ff984e57 WW |
1404 | mmc_free_host(mmc); |
1405 | ||
ff984e57 WW |
1406 | dev_dbg(&(pdev->dev), |
1407 | ": Realtek PCI-E SDMMC controller has been removed\n"); | |
1408 | ||
1409 | return 0; | |
1410 | } | |
1411 | ||
1412 | static struct platform_device_id rtsx_pci_sdmmc_ids[] = { | |
1413 | { | |
1414 | .name = DRV_NAME_RTSX_PCI_SDMMC, | |
1415 | }, { | |
1416 | /* sentinel */ | |
1417 | } | |
1418 | }; | |
1419 | MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids); | |
1420 | ||
1421 | static struct platform_driver rtsx_pci_sdmmc_driver = { | |
1422 | .probe = rtsx_pci_sdmmc_drv_probe, | |
1423 | .remove = rtsx_pci_sdmmc_drv_remove, | |
1424 | .id_table = rtsx_pci_sdmmc_ids, | |
ff984e57 | 1425 | .driver = { |
ff984e57 WW |
1426 | .name = DRV_NAME_RTSX_PCI_SDMMC, |
1427 | }, | |
1428 | }; | |
1429 | module_platform_driver(rtsx_pci_sdmmc_driver); | |
1430 | ||
1431 | MODULE_LICENSE("GPL"); | |
1432 | MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>"); | |
1433 | MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver"); |